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comparison gcc/config/rs6000/rs6000.c @ 36:855418dad1a3

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gcc-4.4-20091020
author e075725
date Tue, 22 Dec 2009 21:19:31 +0900
parents a06113de4d67
children 77e2b8dfacca
comparison
equal deleted inserted replaced
19:58ad6c70ea60 36:855418dad1a3
3806 3806
3807 rtx 3807 rtx
3808 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, 3808 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3809 enum machine_mode mode) 3809 enum machine_mode mode)
3810 { 3810 {
3811 unsigned int extra = 0;
3812
3811 if (GET_CODE (x) == SYMBOL_REF) 3813 if (GET_CODE (x) == SYMBOL_REF)
3812 { 3814 {
3813 enum tls_model model = SYMBOL_REF_TLS_MODEL (x); 3815 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3814 if (model != 0) 3816 if (model != 0)
3815 return rs6000_legitimize_tls_address (x, model); 3817 return rs6000_legitimize_tls_address (x, model);
3816 } 3818 }
3817 3819
3820 switch (mode)
3821 {
3822 case DFmode:
3823 case DDmode:
3824 extra = 4;
3825 break;
3826 case DImode:
3827 if (!TARGET_POWERPC64)
3828 extra = 4;
3829 break;
3830 case TFmode:
3831 case TDmode:
3832 extra = 12;
3833 break;
3834 case TImode:
3835 extra = TARGET_POWERPC64 ? 8 : 12;
3836 break;
3837 default:
3838 break;
3839 }
3840
3818 if (GET_CODE (x) == PLUS 3841 if (GET_CODE (x) == PLUS
3819 && GET_CODE (XEXP (x, 0)) == REG 3842 && GET_CODE (XEXP (x, 0)) == REG
3820 && GET_CODE (XEXP (x, 1)) == CONST_INT 3843 && GET_CODE (XEXP (x, 1)) == CONST_INT
3821 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000 3844 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
3845 >= 0x10000 - extra)
3822 && !((TARGET_POWERPC64 3846 && !((TARGET_POWERPC64
3823 && (mode == DImode || mode == TImode) 3847 && (mode == DImode || mode == TImode)
3824 && (INTVAL (XEXP (x, 1)) & 3) != 0) 3848 && (INTVAL (XEXP (x, 1)) & 3) != 0)
3825 || SPE_VECTOR_MODE (mode) 3849 || SPE_VECTOR_MODE (mode)
3826 || ALTIVEC_VECTOR_MODE (mode) 3850 || ALTIVEC_VECTOR_MODE (mode)
3829 || mode == TDmode)))) 3853 || mode == TDmode))))
3830 { 3854 {
3831 HOST_WIDE_INT high_int, low_int; 3855 HOST_WIDE_INT high_int, low_int;
3832 rtx sum; 3856 rtx sum;
3833 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; 3857 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3858 if (low_int >= 0x8000 - extra)
3859 low_int = 0;
3834 high_int = INTVAL (XEXP (x, 1)) - low_int; 3860 high_int = INTVAL (XEXP (x, 1)) - low_int;
3835 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), 3861 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3836 GEN_INT (high_int)), 0); 3862 GEN_INT (high_int)), 0);
3837 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); 3863 return plus_constant (sum, low_int);
3838 } 3864 }
3839 else if (GET_CODE (x) == PLUS 3865 else if (GET_CODE (x) == PLUS
3840 && GET_CODE (XEXP (x, 0)) == REG 3866 && GET_CODE (XEXP (x, 0)) == REG
3841 && GET_CODE (XEXP (x, 1)) != CONST_INT 3867 && GET_CODE (XEXP (x, 1)) != CONST_INT
3842 && GET_MODE_NUNITS (mode) == 1 3868 && GET_MODE_NUNITS (mode) == 1
16788 common_mode_defined = 1; 16814 common_mode_defined = 1;
16789 } 16815 }
16790 16816
16791 if (! HAVE_prologue) 16817 if (! HAVE_prologue)
16792 { 16818 {
16819 rtx prologue;
16820
16793 start_sequence (); 16821 start_sequence ();
16794 16822
16795 /* A NOTE_INSN_DELETED is supposed to be at the start and end of 16823 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
16796 the "toplevel" insn chain. */ 16824 the "toplevel" insn chain. */
16797 emit_note (NOTE_INSN_DELETED); 16825 emit_note (NOTE_INSN_DELETED);
16807 INSN_ADDRESSES_NEW (insn, addr); 16835 INSN_ADDRESSES_NEW (insn, addr);
16808 addr += 4; 16836 addr += 4;
16809 } 16837 }
16810 } 16838 }
16811 16839
16840 prologue = get_insns ();
16841 end_sequence ();
16842
16812 if (TARGET_DEBUG_STACK) 16843 if (TARGET_DEBUG_STACK)
16813 debug_rtx_list (get_insns (), 100); 16844 debug_rtx_list (prologue, 100);
16814 final (get_insns (), file, FALSE); 16845
16815 end_sequence (); 16846 emit_insn_before_noloc (prologue, BB_HEAD (ENTRY_BLOCK_PTR->next_bb),
16847 ENTRY_BLOCK_PTR);
16816 } 16848 }
16817 16849
16818 rs6000_pic_labelno++; 16850 rs6000_pic_labelno++;
16819 } 16851 }
16820 16852