Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/s390/s390.md @ 36:855418dad1a3
gcc-4.4-20091020
author | e075725 |
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date | Tue, 22 Dec 2009 21:19:31 +0900 |
parents | 58ad6c70ea60 |
children | 3bfb6c00c1e0 |
comparison
equal
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inserted
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19:58ad6c70ea60 | 36:855418dad1a3 |
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200 ;; Instruction type attribute used for scheduling. | 200 ;; Instruction type attribute used for scheduling. |
201 | 201 |
202 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, | 202 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
203 cs,vs,store,sem,idiv, | 203 cs,vs,store,sem,idiv, |
204 imulhi,imulsi,imuldi, | 204 imulhi,imulsi,imuldi, |
205 branch,jsr,fsimptf,fsimpdf,fsimpsf, | 205 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
206 floadtf,floaddf,floadsf,fstoredf,fstoresf, | 206 floadtf,floaddf,floadsf,fstoredf,fstoresf, |
207 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | 207 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, |
208 ftoi,fsqrttf,fsqrtdf,fsqrtsf, | 208 ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
209 ftrunctf,ftruncdf, ftruncsd, ftruncdd, | 209 ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
210 itoftf, itofdf, itofsf, itofdd, itoftd, | 210 itoftf, itofdf, itofsf, itofdd, itoftd, |
1065 return which_alternative ? | 1065 return which_alternative ? |
1066 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | 1066 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; |
1067 else | 1067 else |
1068 return which_alternative ? | 1068 return which_alternative ? |
1069 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | 1069 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; |
1070 } | |
1071 [(set_attr "op_type" "RIE") | |
1072 (set_attr "type" "branch") | |
1073 (set_attr "z10prop" "z10_super_c,z10_super") | |
1074 (set (attr "length") | |
1075 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1076 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1077 ; 10 byte for clgr/jg | |
1078 | |
1079 ; And now the same two patterns as above but with a negated CC mask. | |
1080 | |
1081 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1082 ; The following instructions do a complementary access of their second | |
1083 ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1084 (define_insn "*icmp_and_br_signed_<mode>" | |
1085 [(set (pc) | |
1086 (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1087 [(match_operand:GPR 1 "register_operand" "d,d") | |
1088 (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1089 (pc) | |
1090 (label_ref (match_operand 3 "" "")))) | |
1091 (clobber (reg:CC CC_REGNUM))] | |
1092 "TARGET_Z10" | |
1093 { | |
1094 if (get_attr_length (insn) == 6) | |
1095 return which_alternative ? | |
1096 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1097 else | |
1098 return which_alternative ? | |
1099 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1100 } | |
1101 [(set_attr "op_type" "RIE") | |
1102 (set_attr "type" "branch") | |
1103 (set_attr "z10prop" "z10_super_c,z10_super") | |
1104 (set (attr "length") | |
1105 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1106 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1107 ; 10 byte for cgr/jg | |
1108 | |
1109 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1110 ; The following instructions do a complementary access of their second | |
1111 ; operand (z10 only): clrj, clgrj, clr, clgr | |
1112 (define_insn "*icmp_and_br_unsigned_<mode>" | |
1113 [(set (pc) | |
1114 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1115 [(match_operand:GPR 1 "register_operand" "d,d") | |
1116 (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1117 (pc) | |
1118 (label_ref (match_operand 3 "" "")))) | |
1119 (clobber (reg:CC CC_REGNUM))] | |
1120 "TARGET_Z10" | |
1121 { | |
1122 if (get_attr_length (insn) == 6) | |
1123 return which_alternative ? | |
1124 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1125 else | |
1126 return which_alternative ? | |
1127 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1070 } | 1128 } |
1071 [(set_attr "op_type" "RIE") | 1129 [(set_attr "op_type" "RIE") |
1072 (set_attr "type" "branch") | 1130 (set_attr "type" "branch") |
1073 (set_attr "z10prop" "z10_super_c,z10_super") | 1131 (set_attr "z10prop" "z10_super_c,z10_super") |
1074 (set (attr "length") | 1132 (set (attr "length") |
1468 [(set (match_dup 0) (match_dup 2))] | 1526 [(set (match_dup 0) (match_dup 2))] |
1469 "operands[2] = get_pool_constant (operands[1]);") | 1527 "operands[2] = get_pool_constant (operands[1]);") |
1470 | 1528 |
1471 (define_insn "*la_64" | 1529 (define_insn "*la_64" |
1472 [(set (match_operand:DI 0 "register_operand" "=d,d") | 1530 [(set (match_operand:DI 0 "register_operand" "=d,d") |
1473 (match_operand:QI 1 "address_operand" "U,W"))] | 1531 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
1474 "TARGET_64BIT" | 1532 "TARGET_64BIT" |
1475 "@ | 1533 "@ |
1476 la\t%0,%a1 | 1534 la\t%0,%a1 |
1477 lay\t%0,%a1" | 1535 lay\t%0,%a1" |
1478 [(set_attr "op_type" "RX,RXY") | 1536 [(set_attr "op_type" "RX,RXY") |
1651 [(set (match_dup 0) (match_dup 2))] | 1709 [(set (match_dup 0) (match_dup 2))] |
1652 "operands[2] = get_pool_constant (operands[1]);") | 1710 "operands[2] = get_pool_constant (operands[1]);") |
1653 | 1711 |
1654 (define_insn "*la_31" | 1712 (define_insn "*la_31" |
1655 [(set (match_operand:SI 0 "register_operand" "=d,d") | 1713 [(set (match_operand:SI 0 "register_operand" "=d,d") |
1656 (match_operand:QI 1 "address_operand" "U,W"))] | 1714 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
1657 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | 1715 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
1658 "@ | 1716 "@ |
1659 la\t%0,%a1 | 1717 la\t%0,%a1 |
1660 lay\t%0,%a1" | 1718 lay\t%0,%a1" |
1661 [(set_attr "op_type" "RX,RXY") | 1719 [(set_attr "op_type" "RX,RXY") |
1686 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] | 1744 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1687 "") | 1745 "") |
1688 | 1746 |
1689 (define_insn "*la_31_and" | 1747 (define_insn "*la_31_and" |
1690 [(set (match_operand:SI 0 "register_operand" "=d,d") | 1748 [(set (match_operand:SI 0 "register_operand" "=d,d") |
1691 (and:SI (match_operand:QI 1 "address_operand" "U,W") | 1749 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") |
1692 (const_int 2147483647)))] | 1750 (const_int 2147483647)))] |
1693 "!TARGET_64BIT" | 1751 "!TARGET_64BIT" |
1694 "@ | 1752 "@ |
1695 la\t%0,%a1 | 1753 la\t%0,%a1 |
1696 lay\t%0,%a1" | 1754 lay\t%0,%a1" |
1712 [(set_attr "op_type" "RX") | 1770 [(set_attr "op_type" "RX") |
1713 (set_attr "type" "la")]) | 1771 (set_attr "type" "la")]) |
1714 | 1772 |
1715 (define_insn "force_la_31" | 1773 (define_insn "force_la_31" |
1716 [(set (match_operand:SI 0 "register_operand" "=d,d") | 1774 [(set (match_operand:SI 0 "register_operand" "=d,d") |
1717 (match_operand:QI 1 "address_operand" "U,W")) | 1775 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) |
1718 (use (const_int 0))] | 1776 (use (const_int 0))] |
1719 "!TARGET_64BIT" | 1777 "!TARGET_64BIT" |
1720 "@ | 1778 "@ |
1721 la\t%0,%a1 | 1779 la\t%0,%a1 |
1722 lay\t%0,%a1" | 1780 lay\t%0,%a1" |
1907 lmg\t%0,%N0,%S1 | 1965 lmg\t%0,%N0,%S1 |
1908 stmg\t%1,%N1,%S0 | 1966 stmg\t%1,%N1,%S0 |
1909 # | 1967 # |
1910 #" | 1968 #" |
1911 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") | 1969 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
1912 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")]) | 1970 (set_attr "type" "fhex,fsimptf,*,*,lm,stm,*,*")]) |
1913 | 1971 |
1914 (define_insn "*mov<mode>_31" | 1972 (define_insn "*mov<mode>_31" |
1915 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") | 1973 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
1916 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | 1974 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] |
1917 "!TARGET_64BIT" | 1975 "!TARGET_64BIT" |
1919 lzxr\t%0 | 1977 lzxr\t%0 |
1920 lxr\t%0,%1 | 1978 lxr\t%0,%1 |
1921 # | 1979 # |
1922 #" | 1980 #" |
1923 [(set_attr "op_type" "RRE,RRE,*,*") | 1981 [(set_attr "op_type" "RRE,RRE,*,*") |
1924 (set_attr "type" "fsimptf,fsimptf,*,*")]) | 1982 (set_attr "type" "fhex,fsimptf,*,*")]) |
1925 | 1983 |
1926 ; TFmode in GPRs splitters | 1984 ; TFmode in GPRs splitters |
1927 | 1985 |
1928 (define_split | 1986 (define_split |
1929 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | 1987 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2027 stdy\t%1,%0 | 2085 stdy\t%1,%0 |
2028 lgr\t%0,%1 | 2086 lgr\t%0,%1 |
2029 lg\t%0,%1 | 2087 lg\t%0,%1 |
2030 stg\t%1,%0" | 2088 stg\t%1,%0" |
2031 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY") | 2089 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY") |
2032 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, | 2090 (set_attr "type" "fhex,floaddf,floaddf,floaddf,floaddf,floaddf, |
2033 fstoredf,fstoredf,lr,load,store") | 2091 fstoredf,fstoredf,lr,load,store") |
2034 (set_attr "z10prop" "*, | 2092 (set_attr "z10prop" "*, |
2035 *, | 2093 *, |
2036 *, | 2094 *, |
2037 *, | 2095 *, |
2057 stdy\t%1,%0 | 2115 stdy\t%1,%0 |
2058 lgr\t%0,%1 | 2116 lgr\t%0,%1 |
2059 lg\t%0,%1 | 2117 lg\t%0,%1 |
2060 stg\t%1,%0" | 2118 stg\t%1,%0" |
2061 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY") | 2119 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY") |
2062 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, | 2120 (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>, |
2063 fstore<mode>,fstore<mode>,lr,load,store") | 2121 fstore<mode>,fstore<mode>,lr,load,store") |
2064 (set_attr "z10prop" "*, | 2122 (set_attr "z10prop" "*, |
2065 *, | 2123 *, |
2066 *, | 2124 *, |
2067 *, | 2125 *, |
2089 stm\t%1,%N1,%S0 | 2147 stm\t%1,%N1,%S0 |
2090 stmy\t%1,%N1,%S0 | 2148 stmy\t%1,%N1,%S0 |
2091 # | 2149 # |
2092 #" | 2150 #" |
2093 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") | 2151 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2094 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, | 2152 (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>, |
2095 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")]) | 2153 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")]) |
2096 | 2154 |
2097 (define_split | 2155 (define_split |
2098 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | 2156 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2099 (match_operand:DD_DF 1 "general_operand" ""))] | 2157 (match_operand:DD_DF 1 "general_operand" ""))] |
2156 l\t%0,%1 | 2214 l\t%0,%1 |
2157 ly\t%0,%1 | 2215 ly\t%0,%1 |
2158 st\t%1,%0 | 2216 st\t%1,%0 |
2159 sty\t%1,%0" | 2217 sty\t%1,%0" |
2160 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY") | 2218 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY") |
2161 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, | 2219 (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>, |
2162 fstore<mode>,fstore<mode>,lr,load,load,store,store") | 2220 fstore<mode>,fstore<mode>,lr,load,load,store,store") |
2163 (set_attr "z10prop" "*, | 2221 (set_attr "z10prop" "*, |
2164 *, | 2222 *, |
2165 *, | 2223 *, |
2166 *, | 2224 *, |
7405 | 7463 |
7406 (define_insn "*cjump_long" | 7464 (define_insn "*cjump_long" |
7407 [(set (pc) | 7465 [(set (pc) |
7408 (if_then_else | 7466 (if_then_else |
7409 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | 7467 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
7410 (match_operand 0 "address_operand" "U") | 7468 (match_operand 0 "address_operand" "ZQZR") |
7411 (pc)))] | 7469 (pc)))] |
7412 "" | 7470 "" |
7413 { | 7471 { |
7414 if (get_attr_op_type (insn) == OP_TYPE_RR) | 7472 if (get_attr_op_type (insn) == OP_TYPE_RR) |
7415 return "b%C1r\t%0"; | 7473 return "b%C1r\t%0"; |
7469 (define_insn "*icjump_long" | 7527 (define_insn "*icjump_long" |
7470 [(set (pc) | 7528 [(set (pc) |
7471 (if_then_else | 7529 (if_then_else |
7472 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | 7530 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
7473 (pc) | 7531 (pc) |
7474 (match_operand 0 "address_operand" "U")))] | 7532 (match_operand 0 "address_operand" "ZQZR")))] |
7475 "" | 7533 "" |
7476 { | 7534 { |
7477 if (get_attr_op_type (insn) == OP_TYPE_RR) | 7535 if (get_attr_op_type (insn) == OP_TYPE_RR) |
7478 return "b%D1r\t%0"; | 7536 return "b%D1r\t%0"; |
7479 else | 7537 else |
7658 (define_insn "*doloop_si_long" | 7716 (define_insn "*doloop_si_long" |
7659 [(set (pc) | 7717 [(set (pc) |
7660 (if_then_else | 7718 (if_then_else |
7661 (ne (match_operand:SI 1 "register_operand" "d") | 7719 (ne (match_operand:SI 1 "register_operand" "d") |
7662 (const_int 1)) | 7720 (const_int 1)) |
7663 (match_operand 0 "address_operand" "U") | 7721 (match_operand 0 "address_operand" "ZQZR") |
7664 (pc))) | 7722 (pc))) |
7665 (set (match_operand:SI 2 "register_operand" "=1") | 7723 (set (match_operand:SI 2 "register_operand" "=1") |
7666 (plus:SI (match_dup 1) (const_int -1))) | 7724 (plus:SI (match_dup 1) (const_int -1))) |
7667 (clobber (match_scratch:SI 3 "=X")) | 7725 (clobber (match_scratch:SI 3 "=X")) |
7668 (clobber (reg:CC CC_REGNUM))] | 7726 (clobber (reg:CC CC_REGNUM))] |
7769 ; | 7827 ; |
7770 ; indirect-jump instruction pattern(s). | 7828 ; indirect-jump instruction pattern(s). |
7771 ; | 7829 ; |
7772 | 7830 |
7773 (define_insn "indirect_jump" | 7831 (define_insn "indirect_jump" |
7774 [(set (pc) (match_operand 0 "address_operand" "U"))] | 7832 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] |
7775 "" | 7833 "" |
7776 { | 7834 { |
7777 if (get_attr_op_type (insn) == OP_TYPE_RR) | 7835 if (get_attr_op_type (insn) == OP_TYPE_RR) |
7778 return "br\t%0"; | 7836 return "br\t%0"; |
7779 else | 7837 else |
7788 ; | 7846 ; |
7789 ; casesi instruction pattern(s). | 7847 ; casesi instruction pattern(s). |
7790 ; | 7848 ; |
7791 | 7849 |
7792 (define_insn "casesi_jump" | 7850 (define_insn "casesi_jump" |
7793 [(set (pc) (match_operand 0 "address_operand" "U")) | 7851 [(set (pc) (match_operand 0 "address_operand" "ZQZR")) |
7794 (use (label_ref (match_operand 1 "" "")))] | 7852 (use (label_ref (match_operand 1 "" "")))] |
7795 "" | 7853 "" |
7796 { | 7854 { |
7797 if (get_attr_op_type (insn) == OP_TYPE_RR) | 7855 if (get_attr_op_type (insn) == OP_TYPE_RR) |
7798 return "br\t%0"; | 7856 return "br\t%0"; |
8010 "brasl\t%2,%0" | 8068 "brasl\t%2,%0" |
8011 [(set_attr "op_type" "RIL") | 8069 [(set_attr "op_type" "RIL") |
8012 (set_attr "type" "jsr")]) | 8070 (set_attr "type" "jsr")]) |
8013 | 8071 |
8014 (define_insn "*basr" | 8072 (define_insn "*basr" |
8015 [(call (mem:QI (match_operand 0 "address_operand" "U")) | 8073 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) |
8016 (match_operand 1 "const_int_operand" "n")) | 8074 (match_operand 1 "const_int_operand" "n")) |
8017 (clobber (match_operand 2 "register_operand" "=r"))] | 8075 (clobber (match_operand 2 "register_operand" "=r"))] |
8018 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" | 8076 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
8019 { | 8077 { |
8020 if (get_attr_op_type (insn) == OP_TYPE_RR) | 8078 if (get_attr_op_type (insn) == OP_TYPE_RR) |
8068 [(set_attr "op_type" "RIL") | 8126 [(set_attr "op_type" "RIL") |
8069 (set_attr "type" "jsr")]) | 8127 (set_attr "type" "jsr")]) |
8070 | 8128 |
8071 (define_insn "*basr_r" | 8129 (define_insn "*basr_r" |
8072 [(set (match_operand 0 "" "") | 8130 [(set (match_operand 0 "" "") |
8073 (call (mem:QI (match_operand 1 "address_operand" "U")) | 8131 (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
8074 (match_operand 2 "const_int_operand" "n"))) | 8132 (match_operand 2 "const_int_operand" "n"))) |
8075 (clobber (match_operand 3 "register_operand" "=r"))] | 8133 (clobber (match_operand 3 "register_operand" "=r"))] |
8076 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" | 8134 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
8077 { | 8135 { |
8078 if (get_attr_op_type (insn) == OP_TYPE_RR) | 8136 if (get_attr_op_type (insn) == OP_TYPE_RR) |
8168 [(set_attr "op_type" "RIL") | 8226 [(set_attr "op_type" "RIL") |
8169 (set_attr "type" "jsr")]) | 8227 (set_attr "type" "jsr")]) |
8170 | 8228 |
8171 (define_insn "*basr_tls" | 8229 (define_insn "*basr_tls" |
8172 [(set (match_operand 0 "" "") | 8230 [(set (match_operand 0 "" "") |
8173 (call (mem:QI (match_operand 1 "address_operand" "U")) | 8231 (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
8174 (match_operand 2 "const_int_operand" "n"))) | 8232 (match_operand 2 "const_int_operand" "n"))) |
8175 (clobber (match_operand 3 "register_operand" "=r")) | 8233 (clobber (match_operand 3 "register_operand" "=r")) |
8176 (use (match_operand 4 "" ""))] | 8234 (use (match_operand 4 "" ""))] |
8177 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" | 8235 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
8178 { | 8236 { |
8718 ; | 8776 ; |
8719 ; Data prefetch patterns | 8777 ; Data prefetch patterns |
8720 ; | 8778 ; |
8721 | 8779 |
8722 (define_insn "prefetch" | 8780 (define_insn "prefetch" |
8723 [(prefetch (match_operand 0 "address_operand" "UW,X") | 8781 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") |
8724 (match_operand:SI 1 "const_int_operand" "n,n") | 8782 (match_operand:SI 1 "const_int_operand" " n,n") |
8725 (match_operand:SI 2 "const_int_operand" "n,n"))] | 8783 (match_operand:SI 2 "const_int_operand" " n,n"))] |
8726 "TARGET_Z10" | 8784 "TARGET_Z10" |
8727 { | 8785 { |
8728 if (larl_operand (operands[0], Pmode)) | 8786 switch (which_alternative) |
8729 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | 8787 { |
8730 | 8788 case 0: |
8731 if (s390_mem_constraint ("W", operands[0]) | 8789 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
8732 || s390_mem_constraint ("U", operands[0])) | 8790 case 1: |
8733 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; | 8791 if (larl_operand (operands[0], Pmode)) |
8734 | 8792 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; |
8735 /* This point might be reached if op0 is a larl operand with an | 8793 default: |
8736 uneven addend. In this case we simply omit issuing a prefetch | 8794 |
8737 instruction. */ | 8795 /* This might be reached for symbolic operands with an odd |
8738 | 8796 addend. We simply omit the prefetch for such rare cases. */ |
8739 return ""; | 8797 |
8798 return ""; | |
8799 } | |
8740 } | 8800 } |
8741 [(set_attr "type" "load,larl") | 8801 [(set_attr "type" "load,larl") |
8742 (set_attr "op_type" "RXY,RIL") | 8802 (set_attr "op_type" "RXY,RIL") |
8743 (set_attr "z10prop" "z10_super")]) | 8803 (set_attr "z10prop" "z10_super")]) |
8744 | 8804 |