Mercurial > hg > CbC > CbC_gcc
comparison gcc/combine.c @ 0:a06113de4d67
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author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
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date | Fri, 17 Jul 2009 14:47:48 +0900 |
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children | 3bfb6c00c1e0 |
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1 /* Optimize by combining instructions for GNU compiler. | |
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, | |
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 | |
4 Free Software Foundation, Inc. | |
5 | |
6 This file is part of GCC. | |
7 | |
8 GCC is free software; you can redistribute it and/or modify it under | |
9 the terms of the GNU General Public License as published by the Free | |
10 Software Foundation; either version 3, or (at your option) any later | |
11 version. | |
12 | |
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 for more details. | |
17 | |
18 You should have received a copy of the GNU General Public License | |
19 along with GCC; see the file COPYING3. If not see | |
20 <http://www.gnu.org/licenses/>. */ | |
21 | |
22 /* This module is essentially the "combiner" phase of the U. of Arizona | |
23 Portable Optimizer, but redone to work on our list-structured | |
24 representation for RTL instead of their string representation. | |
25 | |
26 The LOG_LINKS of each insn identify the most recent assignment | |
27 to each REG used in the insn. It is a list of previous insns, | |
28 each of which contains a SET for a REG that is used in this insn | |
29 and not used or set in between. LOG_LINKs never cross basic blocks. | |
30 They were set up by the preceding pass (lifetime analysis). | |
31 | |
32 We try to combine each pair of insns joined by a logical link. | |
33 We also try to combine triples of insns A, B and C when | |
34 C has a link back to B and B has a link back to A. | |
35 | |
36 LOG_LINKS does not have links for use of the CC0. They don't | |
37 need to, because the insn that sets the CC0 is always immediately | |
38 before the insn that tests it. So we always regard a branch | |
39 insn as having a logical link to the preceding insn. The same is true | |
40 for an insn explicitly using CC0. | |
41 | |
42 We check (with use_crosses_set_p) to avoid combining in such a way | |
43 as to move a computation to a place where its value would be different. | |
44 | |
45 Combination is done by mathematically substituting the previous | |
46 insn(s) values for the regs they set into the expressions in | |
47 the later insns that refer to these regs. If the result is a valid insn | |
48 for our target machine, according to the machine description, | |
49 we install it, delete the earlier insns, and update the data flow | |
50 information (LOG_LINKS and REG_NOTES) for what we did. | |
51 | |
52 There are a few exceptions where the dataflow information isn't | |
53 completely updated (however this is only a local issue since it is | |
54 regenerated before the next pass that uses it): | |
55 | |
56 - reg_live_length is not updated | |
57 - reg_n_refs is not adjusted in the rare case when a register is | |
58 no longer required in a computation | |
59 - there are extremely rare cases (see distribute_notes) when a | |
60 REG_DEAD note is lost | |
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be | |
62 removed because there is no way to know which register it was | |
63 linking | |
64 | |
65 To simplify substitution, we combine only when the earlier insn(s) | |
66 consist of only a single assignment. To simplify updating afterward, | |
67 we never combine when a subroutine call appears in the middle. | |
68 | |
69 Since we do not represent assignments to CC0 explicitly except when that | |
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses | |
71 the condition code for the insn that set the condition code. | |
72 Fortunately, these two insns must be consecutive. | |
73 Therefore, every JUMP_INSN is taken to have an implicit logical link | |
74 to the preceding insn. This is not quite right, since non-jumps can | |
75 also use the condition code; but in practice such insns would not | |
76 combine anyway. */ | |
77 | |
78 #include "config.h" | |
79 #include "system.h" | |
80 #include "coretypes.h" | |
81 #include "tm.h" | |
82 #include "rtl.h" | |
83 #include "tree.h" | |
84 #include "tm_p.h" | |
85 #include "flags.h" | |
86 #include "regs.h" | |
87 #include "hard-reg-set.h" | |
88 #include "basic-block.h" | |
89 #include "insn-config.h" | |
90 #include "function.h" | |
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ | |
92 #include "expr.h" | |
93 #include "insn-attr.h" | |
94 #include "recog.h" | |
95 #include "real.h" | |
96 #include "toplev.h" | |
97 #include "target.h" | |
98 #include "optabs.h" | |
99 #include "insn-codes.h" | |
100 #include "rtlhooks-def.h" | |
101 /* Include output.h for dump_file. */ | |
102 #include "output.h" | |
103 #include "params.h" | |
104 #include "timevar.h" | |
105 #include "tree-pass.h" | |
106 #include "df.h" | |
107 #include "cgraph.h" | |
108 | |
109 /* Number of attempts to combine instructions in this function. */ | |
110 | |
111 static int combine_attempts; | |
112 | |
113 /* Number of attempts that got as far as substitution in this function. */ | |
114 | |
115 static int combine_merges; | |
116 | |
117 /* Number of instructions combined with added SETs in this function. */ | |
118 | |
119 static int combine_extras; | |
120 | |
121 /* Number of instructions combined in this function. */ | |
122 | |
123 static int combine_successes; | |
124 | |
125 /* Totals over entire compilation. */ | |
126 | |
127 static int total_attempts, total_merges, total_extras, total_successes; | |
128 | |
129 /* combine_instructions may try to replace the right hand side of the | |
130 second instruction with the value of an associated REG_EQUAL note | |
131 before throwing it at try_combine. That is problematic when there | |
132 is a REG_DEAD note for a register used in the old right hand side | |
133 and can cause distribute_notes to do wrong things. This is the | |
134 second instruction if it has been so modified, null otherwise. */ | |
135 | |
136 static rtx i2mod; | |
137 | |
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */ | |
139 | |
140 static rtx i2mod_old_rhs; | |
141 | |
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */ | |
143 | |
144 static rtx i2mod_new_rhs; | |
145 | |
146 typedef struct reg_stat_struct { | |
147 /* Record last point of death of (hard or pseudo) register n. */ | |
148 rtx last_death; | |
149 | |
150 /* Record last point of modification of (hard or pseudo) register n. */ | |
151 rtx last_set; | |
152 | |
153 /* The next group of fields allows the recording of the last value assigned | |
154 to (hard or pseudo) register n. We use this information to see if an | |
155 operation being processed is redundant given a prior operation performed | |
156 on the register. For example, an `and' with a constant is redundant if | |
157 all the zero bits are already known to be turned off. | |
158 | |
159 We use an approach similar to that used by cse, but change it in the | |
160 following ways: | |
161 | |
162 (1) We do not want to reinitialize at each label. | |
163 (2) It is useful, but not critical, to know the actual value assigned | |
164 to a register. Often just its form is helpful. | |
165 | |
166 Therefore, we maintain the following fields: | |
167 | |
168 last_set_value the last value assigned | |
169 last_set_label records the value of label_tick when the | |
170 register was assigned | |
171 last_set_table_tick records the value of label_tick when a | |
172 value using the register is assigned | |
173 last_set_invalid set to nonzero when it is not valid | |
174 to use the value of this register in some | |
175 register's value | |
176 | |
177 To understand the usage of these tables, it is important to understand | |
178 the distinction between the value in last_set_value being valid and | |
179 the register being validly contained in some other expression in the | |
180 table. | |
181 | |
182 (The next two parameters are out of date). | |
183 | |
184 reg_stat[i].last_set_value is valid if it is nonzero, and either | |
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick. | |
186 | |
187 Register I may validly appear in any expression returned for the value | |
188 of another register if reg_n_sets[i] is 1. It may also appear in the | |
189 value for register J if reg_stat[j].last_set_invalid is zero, or | |
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label. | |
191 | |
192 If an expression is found in the table containing a register which may | |
193 not validly appear in an expression, the register is replaced by | |
194 something that won't match, (clobber (const_int 0)). */ | |
195 | |
196 /* Record last value assigned to (hard or pseudo) register n. */ | |
197 | |
198 rtx last_set_value; | |
199 | |
200 /* Record the value of label_tick when an expression involving register n | |
201 is placed in last_set_value. */ | |
202 | |
203 int last_set_table_tick; | |
204 | |
205 /* Record the value of label_tick when the value for register n is placed in | |
206 last_set_value. */ | |
207 | |
208 int last_set_label; | |
209 | |
210 /* These fields are maintained in parallel with last_set_value and are | |
211 used to store the mode in which the register was last set, the bits | |
212 that were known to be zero when it was last set, and the number of | |
213 sign bits copies it was known to have when it was last set. */ | |
214 | |
215 unsigned HOST_WIDE_INT last_set_nonzero_bits; | |
216 char last_set_sign_bit_copies; | |
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8; | |
218 | |
219 /* Set nonzero if references to register n in expressions should not be | |
220 used. last_set_invalid is set nonzero when this register is being | |
221 assigned to and last_set_table_tick == label_tick. */ | |
222 | |
223 char last_set_invalid; | |
224 | |
225 /* Some registers that are set more than once and used in more than one | |
226 basic block are nevertheless always set in similar ways. For example, | |
227 a QImode register may be loaded from memory in two places on a machine | |
228 where byte loads zero extend. | |
229 | |
230 We record in the following fields if a register has some leading bits | |
231 that are always equal to the sign bit, and what we know about the | |
232 nonzero bits of a register, specifically which bits are known to be | |
233 zero. | |
234 | |
235 If an entry is zero, it means that we don't know anything special. */ | |
236 | |
237 unsigned char sign_bit_copies; | |
238 | |
239 unsigned HOST_WIDE_INT nonzero_bits; | |
240 | |
241 /* Record the value of the label_tick when the last truncation | |
242 happened. The field truncated_to_mode is only valid if | |
243 truncation_label == label_tick. */ | |
244 | |
245 int truncation_label; | |
246 | |
247 /* Record the last truncation seen for this register. If truncation | |
248 is not a nop to this mode we might be able to save an explicit | |
249 truncation if we know that value already contains a truncated | |
250 value. */ | |
251 | |
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8; | |
253 } reg_stat_type; | |
254 | |
255 DEF_VEC_O(reg_stat_type); | |
256 DEF_VEC_ALLOC_O(reg_stat_type,heap); | |
257 | |
258 static VEC(reg_stat_type,heap) *reg_stat; | |
259 | |
260 /* Record the luid of the last insn that invalidated memory | |
261 (anything that writes memory, and subroutine calls, but not pushes). */ | |
262 | |
263 static int mem_last_set; | |
264 | |
265 /* Record the luid of the last CALL_INSN | |
266 so we can tell whether a potential combination crosses any calls. */ | |
267 | |
268 static int last_call_luid; | |
269 | |
270 /* When `subst' is called, this is the insn that is being modified | |
271 (by combining in a previous insn). The PATTERN of this insn | |
272 is still the old pattern partially modified and it should not be | |
273 looked at, but this may be used to examine the successors of the insn | |
274 to judge whether a simplification is valid. */ | |
275 | |
276 static rtx subst_insn; | |
277 | |
278 /* This is the lowest LUID that `subst' is currently dealing with. | |
279 get_last_value will not return a value if the register was set at or | |
280 after this LUID. If not for this mechanism, we could get confused if | |
281 I2 or I1 in try_combine were an insn that used the old value of a register | |
282 to obtain a new value. In that case, we might erroneously get the | |
283 new value of the register when we wanted the old one. */ | |
284 | |
285 static int subst_low_luid; | |
286 | |
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p | |
288 must consider all these registers to be always live. */ | |
289 | |
290 static HARD_REG_SET newpat_used_regs; | |
291 | |
292 /* This is an insn to which a LOG_LINKS entry has been added. If this | |
293 insn is the earlier than I2 or I3, combine should rescan starting at | |
294 that location. */ | |
295 | |
296 static rtx added_links_insn; | |
297 | |
298 /* Basic block in which we are performing combines. */ | |
299 static basic_block this_basic_block; | |
300 static bool optimize_this_for_speed_p; | |
301 | |
302 | |
303 /* Length of the currently allocated uid_insn_cost array. */ | |
304 | |
305 static int max_uid_known; | |
306 | |
307 /* The following array records the insn_rtx_cost for every insn | |
308 in the instruction stream. */ | |
309 | |
310 static int *uid_insn_cost; | |
311 | |
312 /* The following array records the LOG_LINKS for every insn in the | |
313 instruction stream as an INSN_LIST rtx. */ | |
314 | |
315 static rtx *uid_log_links; | |
316 | |
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)]) | |
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)]) | |
319 | |
320 /* Incremented for each basic block. */ | |
321 | |
322 static int label_tick; | |
323 | |
324 /* Reset to label_tick for each label. */ | |
325 | |
326 static int label_tick_ebb_start; | |
327 | |
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the | |
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ | |
330 | |
331 static enum machine_mode nonzero_bits_mode; | |
332 | |
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can | |
334 be safely used. It is zero while computing them and after combine has | |
335 completed. This former test prevents propagating values based on | |
336 previously set values, which can be incorrect if a variable is modified | |
337 in a loop. */ | |
338 | |
339 static int nonzero_sign_valid; | |
340 | |
341 | |
342 /* Record one modification to rtl structure | |
343 to be undone by storing old_contents into *where. */ | |
344 | |
345 struct undo | |
346 { | |
347 struct undo *next; | |
348 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind; | |
349 union { rtx r; int i; enum machine_mode m; } old_contents; | |
350 union { rtx *r; int *i; } where; | |
351 }; | |
352 | |
353 /* Record a bunch of changes to be undone, up to MAX_UNDO of them. | |
354 num_undo says how many are currently recorded. | |
355 | |
356 other_insn is nonzero if we have modified some other insn in the process | |
357 of working on subst_insn. It must be verified too. */ | |
358 | |
359 struct undobuf | |
360 { | |
361 struct undo *undos; | |
362 struct undo *frees; | |
363 rtx other_insn; | |
364 }; | |
365 | |
366 static struct undobuf undobuf; | |
367 | |
368 /* Number of times the pseudo being substituted for | |
369 was found and replaced. */ | |
370 | |
371 static int n_occurrences; | |
372 | |
373 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx, | |
374 enum machine_mode, | |
375 unsigned HOST_WIDE_INT, | |
376 unsigned HOST_WIDE_INT *); | |
377 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx, | |
378 enum machine_mode, | |
379 unsigned int, unsigned int *); | |
380 static void do_SUBST (rtx *, rtx); | |
381 static void do_SUBST_INT (int *, int); | |
382 static void init_reg_last (void); | |
383 static void setup_incoming_promotions (rtx); | |
384 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *); | |
385 static int cant_combine_insn_p (rtx); | |
386 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *); | |
387 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *); | |
388 static int contains_muldiv (rtx); | |
389 static rtx try_combine (rtx, rtx, rtx, int *); | |
390 static void undo_all (void); | |
391 static void undo_commit (void); | |
392 static rtx *find_split_point (rtx *, rtx); | |
393 static rtx subst (rtx, rtx, rtx, int, int); | |
394 static rtx combine_simplify_rtx (rtx, enum machine_mode, int); | |
395 static rtx simplify_if_then_else (rtx); | |
396 static rtx simplify_set (rtx); | |
397 static rtx simplify_logical (rtx); | |
398 static rtx expand_compound_operation (rtx); | |
399 static const_rtx expand_field_assignment (const_rtx); | |
400 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT, | |
401 rtx, unsigned HOST_WIDE_INT, int, int, int); | |
402 static rtx extract_left_shift (rtx, int); | |
403 static rtx make_compound_operation (rtx, enum rtx_code); | |
404 static int get_pos_from_mask (unsigned HOST_WIDE_INT, | |
405 unsigned HOST_WIDE_INT *); | |
406 static rtx canon_reg_for_combine (rtx, rtx); | |
407 static rtx force_to_mode (rtx, enum machine_mode, | |
408 unsigned HOST_WIDE_INT, int); | |
409 static rtx if_then_else_cond (rtx, rtx *, rtx *); | |
410 static rtx known_cond (rtx, enum rtx_code, rtx, rtx); | |
411 static int rtx_equal_for_field_assignment_p (rtx, rtx); | |
412 static rtx make_field_assignment (rtx); | |
413 static rtx apply_distributive_law (rtx); | |
414 static rtx distribute_and_simplify_rtx (rtx, int); | |
415 static rtx simplify_and_const_int_1 (enum machine_mode, rtx, | |
416 unsigned HOST_WIDE_INT); | |
417 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx, | |
418 unsigned HOST_WIDE_INT); | |
419 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code, | |
420 HOST_WIDE_INT, enum machine_mode, int *); | |
421 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int); | |
422 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx, | |
423 int); | |
424 static int recog_for_combine (rtx *, rtx, rtx *); | |
425 static rtx gen_lowpart_for_combine (enum machine_mode, rtx); | |
426 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *); | |
427 static void update_table_tick (rtx); | |
428 static void record_value_for_reg (rtx, rtx, rtx); | |
429 static void check_promoted_subreg (rtx, rtx); | |
430 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *); | |
431 static void record_dead_and_set_regs (rtx); | |
432 static int get_last_value_validate (rtx *, rtx, int, int); | |
433 static rtx get_last_value (const_rtx); | |
434 static int use_crosses_set_p (const_rtx, int); | |
435 static void reg_dead_at_p_1 (rtx, const_rtx, void *); | |
436 static int reg_dead_at_p (rtx, rtx); | |
437 static void move_deaths (rtx, rtx, int, rtx, rtx *); | |
438 static int reg_bitfield_target_p (rtx, rtx); | |
439 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx); | |
440 static void distribute_links (rtx); | |
441 static void mark_used_regs_combine (rtx); | |
442 static void record_promoted_value (rtx, rtx); | |
443 static int unmentioned_reg_p_1 (rtx *, void *); | |
444 static bool unmentioned_reg_p (rtx, rtx); | |
445 static int record_truncated_value (rtx *, void *); | |
446 static void record_truncated_values (rtx *, void *); | |
447 static bool reg_truncated_to_mode (enum machine_mode, const_rtx); | |
448 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx); | |
449 | |
450 | |
451 /* It is not safe to use ordinary gen_lowpart in combine. | |
452 See comments in gen_lowpart_for_combine. */ | |
453 #undef RTL_HOOKS_GEN_LOWPART | |
454 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine | |
455 | |
456 /* Our implementation of gen_lowpart never emits a new pseudo. */ | |
457 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT | |
458 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine | |
459 | |
460 #undef RTL_HOOKS_REG_NONZERO_REG_BITS | |
461 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine | |
462 | |
463 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES | |
464 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine | |
465 | |
466 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE | |
467 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode | |
468 | |
469 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER; | |
470 | |
471 | |
472 /* Try to split PATTERN found in INSN. This returns NULL_RTX if | |
473 PATTERN can not be split. Otherwise, it returns an insn sequence. | |
474 This is a wrapper around split_insns which ensures that the | |
475 reg_stat vector is made larger if the splitter creates a new | |
476 register. */ | |
477 | |
478 static rtx | |
479 combine_split_insns (rtx pattern, rtx insn) | |
480 { | |
481 rtx ret; | |
482 unsigned int nregs; | |
483 | |
484 ret = split_insns (pattern, insn); | |
485 nregs = max_reg_num (); | |
486 if (nregs > VEC_length (reg_stat_type, reg_stat)) | |
487 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs); | |
488 return ret; | |
489 } | |
490 | |
491 /* This is used by find_single_use to locate an rtx in LOC that | |
492 contains exactly one use of DEST, which is typically either a REG | |
493 or CC0. It returns a pointer to the innermost rtx expression | |
494 containing DEST. Appearances of DEST that are being used to | |
495 totally replace it are not counted. */ | |
496 | |
497 static rtx * | |
498 find_single_use_1 (rtx dest, rtx *loc) | |
499 { | |
500 rtx x = *loc; | |
501 enum rtx_code code = GET_CODE (x); | |
502 rtx *result = NULL; | |
503 rtx *this_result; | |
504 int i; | |
505 const char *fmt; | |
506 | |
507 switch (code) | |
508 { | |
509 case CONST_INT: | |
510 case CONST: | |
511 case LABEL_REF: | |
512 case SYMBOL_REF: | |
513 case CONST_DOUBLE: | |
514 case CONST_VECTOR: | |
515 case CLOBBER: | |
516 return 0; | |
517 | |
518 case SET: | |
519 /* If the destination is anything other than CC0, PC, a REG or a SUBREG | |
520 of a REG that occupies all of the REG, the insn uses DEST if | |
521 it is mentioned in the destination or the source. Otherwise, we | |
522 need just check the source. */ | |
523 if (GET_CODE (SET_DEST (x)) != CC0 | |
524 && GET_CODE (SET_DEST (x)) != PC | |
525 && !REG_P (SET_DEST (x)) | |
526 && ! (GET_CODE (SET_DEST (x)) == SUBREG | |
527 && REG_P (SUBREG_REG (SET_DEST (x))) | |
528 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
529 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
530 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) | |
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) | |
532 break; | |
533 | |
534 return find_single_use_1 (dest, &SET_SRC (x)); | |
535 | |
536 case MEM: | |
537 case SUBREG: | |
538 return find_single_use_1 (dest, &XEXP (x, 0)); | |
539 | |
540 default: | |
541 break; | |
542 } | |
543 | |
544 /* If it wasn't one of the common cases above, check each expression and | |
545 vector of this code. Look for a unique usage of DEST. */ | |
546 | |
547 fmt = GET_RTX_FORMAT (code); | |
548 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
549 { | |
550 if (fmt[i] == 'e') | |
551 { | |
552 if (dest == XEXP (x, i) | |
553 || (REG_P (dest) && REG_P (XEXP (x, i)) | |
554 && REGNO (dest) == REGNO (XEXP (x, i)))) | |
555 this_result = loc; | |
556 else | |
557 this_result = find_single_use_1 (dest, &XEXP (x, i)); | |
558 | |
559 if (result == NULL) | |
560 result = this_result; | |
561 else if (this_result) | |
562 /* Duplicate usage. */ | |
563 return NULL; | |
564 } | |
565 else if (fmt[i] == 'E') | |
566 { | |
567 int j; | |
568 | |
569 for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
570 { | |
571 if (XVECEXP (x, i, j) == dest | |
572 || (REG_P (dest) | |
573 && REG_P (XVECEXP (x, i, j)) | |
574 && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) | |
575 this_result = loc; | |
576 else | |
577 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); | |
578 | |
579 if (result == NULL) | |
580 result = this_result; | |
581 else if (this_result) | |
582 return NULL; | |
583 } | |
584 } | |
585 } | |
586 | |
587 return result; | |
588 } | |
589 | |
590 | |
591 /* See if DEST, produced in INSN, is used only a single time in the | |
592 sequel. If so, return a pointer to the innermost rtx expression in which | |
593 it is used. | |
594 | |
595 If PLOC is nonzero, *PLOC is set to the insn containing the single use. | |
596 | |
597 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't | |
598 care about REG_DEAD notes or LOG_LINKS. | |
599 | |
600 Otherwise, we find the single use by finding an insn that has a | |
601 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is | |
602 only referenced once in that insn, we know that it must be the first | |
603 and last insn referencing DEST. */ | |
604 | |
605 static rtx * | |
606 find_single_use (rtx dest, rtx insn, rtx *ploc) | |
607 { | |
608 rtx next; | |
609 rtx *result; | |
610 rtx link; | |
611 | |
612 #ifdef HAVE_cc0 | |
613 if (dest == cc0_rtx) | |
614 { | |
615 next = NEXT_INSN (insn); | |
616 if (next == 0 | |
617 || (!NONJUMP_INSN_P (next) && !JUMP_P (next))) | |
618 return 0; | |
619 | |
620 result = find_single_use_1 (dest, &PATTERN (next)); | |
621 if (result && ploc) | |
622 *ploc = next; | |
623 return result; | |
624 } | |
625 #endif | |
626 | |
627 if (!REG_P (dest)) | |
628 return 0; | |
629 | |
630 for (next = next_nonnote_insn (insn); | |
631 next != 0 && !LABEL_P (next); | |
632 next = next_nonnote_insn (next)) | |
633 if (INSN_P (next) && dead_or_set_p (next, dest)) | |
634 { | |
635 for (link = LOG_LINKS (next); link; link = XEXP (link, 1)) | |
636 if (XEXP (link, 0) == insn) | |
637 break; | |
638 | |
639 if (link) | |
640 { | |
641 result = find_single_use_1 (dest, &PATTERN (next)); | |
642 if (ploc) | |
643 *ploc = next; | |
644 return result; | |
645 } | |
646 } | |
647 | |
648 return 0; | |
649 } | |
650 | |
651 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some | |
652 insn. The substitution can be undone by undo_all. If INTO is already | |
653 set to NEWVAL, do not record this change. Because computing NEWVAL might | |
654 also call SUBST, we have to compute it before we put anything into | |
655 the undo table. */ | |
656 | |
657 static void | |
658 do_SUBST (rtx *into, rtx newval) | |
659 { | |
660 struct undo *buf; | |
661 rtx oldval = *into; | |
662 | |
663 if (oldval == newval) | |
664 return; | |
665 | |
666 /* We'd like to catch as many invalid transformations here as | |
667 possible. Unfortunately, there are way too many mode changes | |
668 that are perfectly valid, so we'd waste too much effort for | |
669 little gain doing the checks here. Focus on catching invalid | |
670 transformations involving integer constants. */ | |
671 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT | |
672 && GET_CODE (newval) == CONST_INT) | |
673 { | |
674 /* Sanity check that we're replacing oldval with a CONST_INT | |
675 that is a valid sign-extension for the original mode. */ | |
676 gcc_assert (INTVAL (newval) | |
677 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval))); | |
678 | |
679 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a | |
680 CONST_INT is not valid, because after the replacement, the | |
681 original mode would be gone. Unfortunately, we can't tell | |
682 when do_SUBST is called to replace the operand thereof, so we | |
683 perform this test on oldval instead, checking whether an | |
684 invalid replacement took place before we got here. */ | |
685 gcc_assert (!(GET_CODE (oldval) == SUBREG | |
686 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)); | |
687 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND | |
688 && GET_CODE (XEXP (oldval, 0)) == CONST_INT)); | |
689 } | |
690 | |
691 if (undobuf.frees) | |
692 buf = undobuf.frees, undobuf.frees = buf->next; | |
693 else | |
694 buf = XNEW (struct undo); | |
695 | |
696 buf->kind = UNDO_RTX; | |
697 buf->where.r = into; | |
698 buf->old_contents.r = oldval; | |
699 *into = newval; | |
700 | |
701 buf->next = undobuf.undos, undobuf.undos = buf; | |
702 } | |
703 | |
704 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL)) | |
705 | |
706 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution | |
707 for the value of a HOST_WIDE_INT value (including CONST_INT) is | |
708 not safe. */ | |
709 | |
710 static void | |
711 do_SUBST_INT (int *into, int newval) | |
712 { | |
713 struct undo *buf; | |
714 int oldval = *into; | |
715 | |
716 if (oldval == newval) | |
717 return; | |
718 | |
719 if (undobuf.frees) | |
720 buf = undobuf.frees, undobuf.frees = buf->next; | |
721 else | |
722 buf = XNEW (struct undo); | |
723 | |
724 buf->kind = UNDO_INT; | |
725 buf->where.i = into; | |
726 buf->old_contents.i = oldval; | |
727 *into = newval; | |
728 | |
729 buf->next = undobuf.undos, undobuf.undos = buf; | |
730 } | |
731 | |
732 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL)) | |
733 | |
734 /* Similar to SUBST, but just substitute the mode. This is used when | |
735 changing the mode of a pseudo-register, so that any other | |
736 references to the entry in the regno_reg_rtx array will change as | |
737 well. */ | |
738 | |
739 static void | |
740 do_SUBST_MODE (rtx *into, enum machine_mode newval) | |
741 { | |
742 struct undo *buf; | |
743 enum machine_mode oldval = GET_MODE (*into); | |
744 | |
745 if (oldval == newval) | |
746 return; | |
747 | |
748 if (undobuf.frees) | |
749 buf = undobuf.frees, undobuf.frees = buf->next; | |
750 else | |
751 buf = XNEW (struct undo); | |
752 | |
753 buf->kind = UNDO_MODE; | |
754 buf->where.r = into; | |
755 buf->old_contents.m = oldval; | |
756 adjust_reg_mode (*into, newval); | |
757 | |
758 buf->next = undobuf.undos, undobuf.undos = buf; | |
759 } | |
760 | |
761 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL)) | |
762 | |
763 /* Subroutine of try_combine. Determine whether the combine replacement | |
764 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to | |
765 insn_rtx_cost that the original instruction sequence I1, I2, I3 and | |
766 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX. | |
767 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This | |
768 function returns false, if the costs of all instructions can be | |
769 estimated, and the replacements are more expensive than the original | |
770 sequence. */ | |
771 | |
772 static bool | |
773 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat, | |
774 rtx newotherpat) | |
775 { | |
776 int i1_cost, i2_cost, i3_cost; | |
777 int new_i2_cost, new_i3_cost; | |
778 int old_cost, new_cost; | |
779 | |
780 /* Lookup the original insn_rtx_costs. */ | |
781 i2_cost = INSN_COST (i2); | |
782 i3_cost = INSN_COST (i3); | |
783 | |
784 if (i1) | |
785 { | |
786 i1_cost = INSN_COST (i1); | |
787 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0) | |
788 ? i1_cost + i2_cost + i3_cost : 0; | |
789 } | |
790 else | |
791 { | |
792 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0; | |
793 i1_cost = 0; | |
794 } | |
795 | |
796 /* Calculate the replacement insn_rtx_costs. */ | |
797 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p); | |
798 if (newi2pat) | |
799 { | |
800 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p); | |
801 new_cost = (new_i2_cost > 0 && new_i3_cost > 0) | |
802 ? new_i2_cost + new_i3_cost : 0; | |
803 } | |
804 else | |
805 { | |
806 new_cost = new_i3_cost; | |
807 new_i2_cost = 0; | |
808 } | |
809 | |
810 if (undobuf.other_insn) | |
811 { | |
812 int old_other_cost, new_other_cost; | |
813 | |
814 old_other_cost = INSN_COST (undobuf.other_insn); | |
815 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p); | |
816 if (old_other_cost > 0 && new_other_cost > 0) | |
817 { | |
818 old_cost += old_other_cost; | |
819 new_cost += new_other_cost; | |
820 } | |
821 else | |
822 old_cost = 0; | |
823 } | |
824 | |
825 /* Disallow this recombination if both new_cost and old_cost are | |
826 greater than zero, and new_cost is greater than old cost. */ | |
827 if (old_cost > 0 | |
828 && new_cost > old_cost) | |
829 { | |
830 if (dump_file) | |
831 { | |
832 if (i1) | |
833 { | |
834 fprintf (dump_file, | |
835 "rejecting combination of insns %d, %d and %d\n", | |
836 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); | |
837 fprintf (dump_file, "original costs %d + %d + %d = %d\n", | |
838 i1_cost, i2_cost, i3_cost, old_cost); | |
839 } | |
840 else | |
841 { | |
842 fprintf (dump_file, | |
843 "rejecting combination of insns %d and %d\n", | |
844 INSN_UID (i2), INSN_UID (i3)); | |
845 fprintf (dump_file, "original costs %d + %d = %d\n", | |
846 i2_cost, i3_cost, old_cost); | |
847 } | |
848 | |
849 if (newi2pat) | |
850 { | |
851 fprintf (dump_file, "replacement costs %d + %d = %d\n", | |
852 new_i2_cost, new_i3_cost, new_cost); | |
853 } | |
854 else | |
855 fprintf (dump_file, "replacement cost %d\n", new_cost); | |
856 } | |
857 | |
858 return false; | |
859 } | |
860 | |
861 /* Update the uid_insn_cost array with the replacement costs. */ | |
862 INSN_COST (i2) = new_i2_cost; | |
863 INSN_COST (i3) = new_i3_cost; | |
864 if (i1) | |
865 INSN_COST (i1) = 0; | |
866 | |
867 return true; | |
868 } | |
869 | |
870 | |
871 /* Delete any insns that copy a register to itself. */ | |
872 | |
873 static void | |
874 delete_noop_moves (void) | |
875 { | |
876 rtx insn, next; | |
877 basic_block bb; | |
878 | |
879 FOR_EACH_BB (bb) | |
880 { | |
881 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next) | |
882 { | |
883 next = NEXT_INSN (insn); | |
884 if (INSN_P (insn) && noop_move_p (insn)) | |
885 { | |
886 if (dump_file) | |
887 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn)); | |
888 | |
889 delete_insn_and_edges (insn); | |
890 } | |
891 } | |
892 } | |
893 } | |
894 | |
895 | |
896 /* Fill in log links field for all insns. */ | |
897 | |
898 static void | |
899 create_log_links (void) | |
900 { | |
901 basic_block bb; | |
902 rtx *next_use, insn; | |
903 df_ref *def_vec, *use_vec; | |
904 | |
905 next_use = XCNEWVEC (rtx, max_reg_num ()); | |
906 | |
907 /* Pass through each block from the end, recording the uses of each | |
908 register and establishing log links when def is encountered. | |
909 Note that we do not clear next_use array in order to save time, | |
910 so we have to test whether the use is in the same basic block as def. | |
911 | |
912 There are a few cases below when we do not consider the definition or | |
913 usage -- these are taken from original flow.c did. Don't ask me why it is | |
914 done this way; I don't know and if it works, I don't want to know. */ | |
915 | |
916 FOR_EACH_BB (bb) | |
917 { | |
918 FOR_BB_INSNS_REVERSE (bb, insn) | |
919 { | |
920 if (!INSN_P (insn)) | |
921 continue; | |
922 | |
923 /* Log links are created only once. */ | |
924 gcc_assert (!LOG_LINKS (insn)); | |
925 | |
926 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++) | |
927 { | |
928 df_ref def = *def_vec; | |
929 int regno = DF_REF_REGNO (def); | |
930 rtx use_insn; | |
931 | |
932 if (!next_use[regno]) | |
933 continue; | |
934 | |
935 /* Do not consider if it is pre/post modification in MEM. */ | |
936 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY) | |
937 continue; | |
938 | |
939 /* Do not make the log link for frame pointer. */ | |
940 if ((regno == FRAME_POINTER_REGNUM | |
941 && (! reload_completed || frame_pointer_needed)) | |
942 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
943 || (regno == HARD_FRAME_POINTER_REGNUM | |
944 && (! reload_completed || frame_pointer_needed)) | |
945 #endif | |
946 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
947 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) | |
948 #endif | |
949 ) | |
950 continue; | |
951 | |
952 use_insn = next_use[regno]; | |
953 if (BLOCK_FOR_INSN (use_insn) == bb) | |
954 { | |
955 /* flow.c claimed: | |
956 | |
957 We don't build a LOG_LINK for hard registers contained | |
958 in ASM_OPERANDs. If these registers get replaced, | |
959 we might wind up changing the semantics of the insn, | |
960 even if reload can make what appear to be valid | |
961 assignments later. */ | |
962 if (regno >= FIRST_PSEUDO_REGISTER | |
963 || asm_noperands (PATTERN (use_insn)) < 0) | |
964 { | |
965 /* Don't add duplicate links between instructions. */ | |
966 rtx links; | |
967 for (links = LOG_LINKS (use_insn); links; | |
968 links = XEXP (links, 1)) | |
969 if (insn == XEXP (links, 0)) | |
970 break; | |
971 | |
972 if (!links) | |
973 LOG_LINKS (use_insn) = | |
974 alloc_INSN_LIST (insn, LOG_LINKS (use_insn)); | |
975 } | |
976 } | |
977 next_use[regno] = NULL_RTX; | |
978 } | |
979 | |
980 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++) | |
981 { | |
982 df_ref use = *use_vec; | |
983 int regno = DF_REF_REGNO (use); | |
984 | |
985 /* Do not consider the usage of the stack pointer | |
986 by function call. */ | |
987 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE) | |
988 continue; | |
989 | |
990 next_use[regno] = insn; | |
991 } | |
992 } | |
993 } | |
994 | |
995 free (next_use); | |
996 } | |
997 | |
998 /* Clear LOG_LINKS fields of insns. */ | |
999 | |
1000 static void | |
1001 clear_log_links (void) | |
1002 { | |
1003 rtx insn; | |
1004 | |
1005 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
1006 if (INSN_P (insn)) | |
1007 free_INSN_LIST_list (&LOG_LINKS (insn)); | |
1008 } | |
1009 | |
1010 | |
1011 | |
1012 | |
1013 /* Main entry point for combiner. F is the first insn of the function. | |
1014 NREGS is the first unused pseudo-reg number. | |
1015 | |
1016 Return nonzero if the combiner has turned an indirect jump | |
1017 instruction into a direct jump. */ | |
1018 static int | |
1019 combine_instructions (rtx f, unsigned int nregs) | |
1020 { | |
1021 rtx insn, next; | |
1022 #ifdef HAVE_cc0 | |
1023 rtx prev; | |
1024 #endif | |
1025 rtx links, nextlinks; | |
1026 rtx first; | |
1027 | |
1028 int new_direct_jump_p = 0; | |
1029 | |
1030 for (first = f; first && !INSN_P (first); ) | |
1031 first = NEXT_INSN (first); | |
1032 if (!first) | |
1033 return 0; | |
1034 | |
1035 combine_attempts = 0; | |
1036 combine_merges = 0; | |
1037 combine_extras = 0; | |
1038 combine_successes = 0; | |
1039 | |
1040 rtl_hooks = combine_rtl_hooks; | |
1041 | |
1042 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs); | |
1043 | |
1044 init_recog_no_volatile (); | |
1045 | |
1046 /* Allocate array for insn info. */ | |
1047 max_uid_known = get_max_uid (); | |
1048 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1); | |
1049 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1); | |
1050 | |
1051 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); | |
1052 | |
1053 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause | |
1054 problems when, for example, we have j <<= 1 in a loop. */ | |
1055 | |
1056 nonzero_sign_valid = 0; | |
1057 | |
1058 /* Scan all SETs and see if we can deduce anything about what | |
1059 bits are known to be zero for some registers and how many copies | |
1060 of the sign bit are known to exist for those registers. | |
1061 | |
1062 Also set any known values so that we can use it while searching | |
1063 for what bits are known to be set. */ | |
1064 | |
1065 label_tick = label_tick_ebb_start = 1; | |
1066 | |
1067 setup_incoming_promotions (first); | |
1068 | |
1069 create_log_links (); | |
1070 FOR_EACH_BB (this_basic_block) | |
1071 { | |
1072 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block); | |
1073 last_call_luid = 0; | |
1074 mem_last_set = -1; | |
1075 label_tick++; | |
1076 FOR_BB_INSNS (this_basic_block, insn) | |
1077 if (INSN_P (insn) && BLOCK_FOR_INSN (insn)) | |
1078 { | |
1079 subst_low_luid = DF_INSN_LUID (insn); | |
1080 subst_insn = insn; | |
1081 | |
1082 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies, | |
1083 insn); | |
1084 record_dead_and_set_regs (insn); | |
1085 | |
1086 #ifdef AUTO_INC_DEC | |
1087 for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) | |
1088 if (REG_NOTE_KIND (links) == REG_INC) | |
1089 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX, | |
1090 insn); | |
1091 #endif | |
1092 | |
1093 /* Record the current insn_rtx_cost of this instruction. */ | |
1094 if (NONJUMP_INSN_P (insn)) | |
1095 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn), | |
1096 optimize_this_for_speed_p); | |
1097 if (dump_file) | |
1098 fprintf(dump_file, "insn_cost %d: %d\n", | |
1099 INSN_UID (insn), INSN_COST (insn)); | |
1100 } | |
1101 else if (LABEL_P (insn)) | |
1102 label_tick_ebb_start = label_tick; | |
1103 } | |
1104 | |
1105 nonzero_sign_valid = 1; | |
1106 | |
1107 /* Now scan all the insns in forward order. */ | |
1108 | |
1109 label_tick = label_tick_ebb_start = 1; | |
1110 init_reg_last (); | |
1111 setup_incoming_promotions (first); | |
1112 | |
1113 FOR_EACH_BB (this_basic_block) | |
1114 { | |
1115 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block); | |
1116 last_call_luid = 0; | |
1117 mem_last_set = -1; | |
1118 label_tick++; | |
1119 rtl_profile_for_bb (this_basic_block); | |
1120 for (insn = BB_HEAD (this_basic_block); | |
1121 insn != NEXT_INSN (BB_END (this_basic_block)); | |
1122 insn = next ? next : NEXT_INSN (insn)) | |
1123 { | |
1124 next = 0; | |
1125 if (INSN_P (insn)) | |
1126 { | |
1127 /* See if we know about function return values before this | |
1128 insn based upon SUBREG flags. */ | |
1129 check_promoted_subreg (insn, PATTERN (insn)); | |
1130 | |
1131 /* See if we can find hardregs and subreg of pseudos in | |
1132 narrower modes. This could help turning TRUNCATEs | |
1133 into SUBREGs. */ | |
1134 note_uses (&PATTERN (insn), record_truncated_values, NULL); | |
1135 | |
1136 /* Try this insn with each insn it links back to. */ | |
1137 | |
1138 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
1139 if ((next = try_combine (insn, XEXP (links, 0), | |
1140 NULL_RTX, &new_direct_jump_p)) != 0) | |
1141 goto retry; | |
1142 | |
1143 /* Try each sequence of three linked insns ending with this one. */ | |
1144 | |
1145 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
1146 { | |
1147 rtx link = XEXP (links, 0); | |
1148 | |
1149 /* If the linked insn has been replaced by a note, then there | |
1150 is no point in pursuing this chain any further. */ | |
1151 if (NOTE_P (link)) | |
1152 continue; | |
1153 | |
1154 for (nextlinks = LOG_LINKS (link); | |
1155 nextlinks; | |
1156 nextlinks = XEXP (nextlinks, 1)) | |
1157 if ((next = try_combine (insn, link, | |
1158 XEXP (nextlinks, 0), | |
1159 &new_direct_jump_p)) != 0) | |
1160 goto retry; | |
1161 } | |
1162 | |
1163 #ifdef HAVE_cc0 | |
1164 /* Try to combine a jump insn that uses CC0 | |
1165 with a preceding insn that sets CC0, and maybe with its | |
1166 logical predecessor as well. | |
1167 This is how we make decrement-and-branch insns. | |
1168 We need this special code because data flow connections | |
1169 via CC0 do not get entered in LOG_LINKS. */ | |
1170 | |
1171 if (JUMP_P (insn) | |
1172 && (prev = prev_nonnote_insn (insn)) != 0 | |
1173 && NONJUMP_INSN_P (prev) | |
1174 && sets_cc0_p (PATTERN (prev))) | |
1175 { | |
1176 if ((next = try_combine (insn, prev, | |
1177 NULL_RTX, &new_direct_jump_p)) != 0) | |
1178 goto retry; | |
1179 | |
1180 for (nextlinks = LOG_LINKS (prev); nextlinks; | |
1181 nextlinks = XEXP (nextlinks, 1)) | |
1182 if ((next = try_combine (insn, prev, | |
1183 XEXP (nextlinks, 0), | |
1184 &new_direct_jump_p)) != 0) | |
1185 goto retry; | |
1186 } | |
1187 | |
1188 /* Do the same for an insn that explicitly references CC0. */ | |
1189 if (NONJUMP_INSN_P (insn) | |
1190 && (prev = prev_nonnote_insn (insn)) != 0 | |
1191 && NONJUMP_INSN_P (prev) | |
1192 && sets_cc0_p (PATTERN (prev)) | |
1193 && GET_CODE (PATTERN (insn)) == SET | |
1194 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) | |
1195 { | |
1196 if ((next = try_combine (insn, prev, | |
1197 NULL_RTX, &new_direct_jump_p)) != 0) | |
1198 goto retry; | |
1199 | |
1200 for (nextlinks = LOG_LINKS (prev); nextlinks; | |
1201 nextlinks = XEXP (nextlinks, 1)) | |
1202 if ((next = try_combine (insn, prev, | |
1203 XEXP (nextlinks, 0), | |
1204 &new_direct_jump_p)) != 0) | |
1205 goto retry; | |
1206 } | |
1207 | |
1208 /* Finally, see if any of the insns that this insn links to | |
1209 explicitly references CC0. If so, try this insn, that insn, | |
1210 and its predecessor if it sets CC0. */ | |
1211 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
1212 if (NONJUMP_INSN_P (XEXP (links, 0)) | |
1213 && GET_CODE (PATTERN (XEXP (links, 0))) == SET | |
1214 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) | |
1215 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 | |
1216 && NONJUMP_INSN_P (prev) | |
1217 && sets_cc0_p (PATTERN (prev)) | |
1218 && (next = try_combine (insn, XEXP (links, 0), | |
1219 prev, &new_direct_jump_p)) != 0) | |
1220 goto retry; | |
1221 #endif | |
1222 | |
1223 /* Try combining an insn with two different insns whose results it | |
1224 uses. */ | |
1225 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
1226 for (nextlinks = XEXP (links, 1); nextlinks; | |
1227 nextlinks = XEXP (nextlinks, 1)) | |
1228 if ((next = try_combine (insn, XEXP (links, 0), | |
1229 XEXP (nextlinks, 0), | |
1230 &new_direct_jump_p)) != 0) | |
1231 goto retry; | |
1232 | |
1233 /* Try this insn with each REG_EQUAL note it links back to. */ | |
1234 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
1235 { | |
1236 rtx set, note; | |
1237 rtx temp = XEXP (links, 0); | |
1238 if ((set = single_set (temp)) != 0 | |
1239 && (note = find_reg_equal_equiv_note (temp)) != 0 | |
1240 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST | |
1241 /* Avoid using a register that may already been marked | |
1242 dead by an earlier instruction. */ | |
1243 && ! unmentioned_reg_p (note, SET_SRC (set)) | |
1244 && (GET_MODE (note) == VOIDmode | |
1245 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set))) | |
1246 : GET_MODE (SET_DEST (set)) == GET_MODE (note))) | |
1247 { | |
1248 /* Temporarily replace the set's source with the | |
1249 contents of the REG_EQUAL note. The insn will | |
1250 be deleted or recognized by try_combine. */ | |
1251 rtx orig = SET_SRC (set); | |
1252 SET_SRC (set) = note; | |
1253 i2mod = temp; | |
1254 i2mod_old_rhs = copy_rtx (orig); | |
1255 i2mod_new_rhs = copy_rtx (note); | |
1256 next = try_combine (insn, i2mod, NULL_RTX, | |
1257 &new_direct_jump_p); | |
1258 i2mod = NULL_RTX; | |
1259 if (next) | |
1260 goto retry; | |
1261 SET_SRC (set) = orig; | |
1262 } | |
1263 } | |
1264 | |
1265 if (!NOTE_P (insn)) | |
1266 record_dead_and_set_regs (insn); | |
1267 | |
1268 retry: | |
1269 ; | |
1270 } | |
1271 else if (LABEL_P (insn)) | |
1272 label_tick_ebb_start = label_tick; | |
1273 } | |
1274 } | |
1275 | |
1276 default_rtl_profile (); | |
1277 clear_log_links (); | |
1278 clear_bb_flags (); | |
1279 new_direct_jump_p |= purge_all_dead_edges (); | |
1280 delete_noop_moves (); | |
1281 | |
1282 /* Clean up. */ | |
1283 free (uid_log_links); | |
1284 free (uid_insn_cost); | |
1285 VEC_free (reg_stat_type, heap, reg_stat); | |
1286 | |
1287 { | |
1288 struct undo *undo, *next; | |
1289 for (undo = undobuf.frees; undo; undo = next) | |
1290 { | |
1291 next = undo->next; | |
1292 free (undo); | |
1293 } | |
1294 undobuf.frees = 0; | |
1295 } | |
1296 | |
1297 total_attempts += combine_attempts; | |
1298 total_merges += combine_merges; | |
1299 total_extras += combine_extras; | |
1300 total_successes += combine_successes; | |
1301 | |
1302 nonzero_sign_valid = 0; | |
1303 rtl_hooks = general_rtl_hooks; | |
1304 | |
1305 /* Make recognizer allow volatile MEMs again. */ | |
1306 init_recog (); | |
1307 | |
1308 return new_direct_jump_p; | |
1309 } | |
1310 | |
1311 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */ | |
1312 | |
1313 static void | |
1314 init_reg_last (void) | |
1315 { | |
1316 unsigned int i; | |
1317 reg_stat_type *p; | |
1318 | |
1319 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i) | |
1320 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies)); | |
1321 } | |
1322 | |
1323 /* Set up any promoted values for incoming argument registers. */ | |
1324 | |
1325 static void | |
1326 setup_incoming_promotions (rtx first) | |
1327 { | |
1328 tree arg; | |
1329 bool strictly_local = false; | |
1330 | |
1331 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl))) | |
1332 return; | |
1333 | |
1334 for (arg = DECL_ARGUMENTS (current_function_decl); arg; | |
1335 arg = TREE_CHAIN (arg)) | |
1336 { | |
1337 rtx reg = DECL_INCOMING_RTL (arg); | |
1338 int uns1, uns3; | |
1339 enum machine_mode mode1, mode2, mode3, mode4; | |
1340 | |
1341 /* Only continue if the incoming argument is in a register. */ | |
1342 if (!REG_P (reg)) | |
1343 continue; | |
1344 | |
1345 /* Determine, if possible, whether all call sites of the current | |
1346 function lie within the current compilation unit. (This does | |
1347 take into account the exporting of a function via taking its | |
1348 address, and so forth.) */ | |
1349 strictly_local = cgraph_local_info (current_function_decl)->local; | |
1350 | |
1351 /* The mode and signedness of the argument before any promotions happen | |
1352 (equal to the mode of the pseudo holding it at that stage). */ | |
1353 mode1 = TYPE_MODE (TREE_TYPE (arg)); | |
1354 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg)); | |
1355 | |
1356 /* The mode and signedness of the argument after any source language and | |
1357 TARGET_PROMOTE_PROTOTYPES-driven promotions. */ | |
1358 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg)); | |
1359 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg)); | |
1360 | |
1361 /* The mode and signedness of the argument as it is actually passed, | |
1362 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */ | |
1363 mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1); | |
1364 | |
1365 /* The mode of the register in which the argument is being passed. */ | |
1366 mode4 = GET_MODE (reg); | |
1367 | |
1368 /* Eliminate sign extensions in the callee when possible. Only | |
1369 do this when: | |
1370 (a) a mode promotion has occurred; | |
1371 (b) the mode of the register is the same as the mode of | |
1372 the argument as it is passed; and | |
1373 (c) the signedness does not change across any of the promotions; and | |
1374 (d) when no language-level promotions (which we cannot guarantee | |
1375 will have been done by an external caller) are necessary, | |
1376 unless we know that this function is only ever called from | |
1377 the current compilation unit -- all of whose call sites will | |
1378 do the mode1 --> mode2 promotion. */ | |
1379 if (mode1 != mode3 | |
1380 && mode3 == mode4 | |
1381 && uns1 == uns3 | |
1382 && (mode1 == mode2 || strictly_local)) | |
1383 { | |
1384 /* Record that the value was promoted from mode1 to mode3, | |
1385 so that any sign extension at the head of the current | |
1386 function may be eliminated. */ | |
1387 rtx x; | |
1388 x = gen_rtx_CLOBBER (mode1, const0_rtx); | |
1389 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x); | |
1390 record_value_for_reg (reg, first, x); | |
1391 } | |
1392 } | |
1393 } | |
1394 | |
1395 /* Called via note_stores. If X is a pseudo that is narrower than | |
1396 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. | |
1397 | |
1398 If we are setting only a portion of X and we can't figure out what | |
1399 portion, assume all bits will be used since we don't know what will | |
1400 be happening. | |
1401 | |
1402 Similarly, set how many bits of X are known to be copies of the sign bit | |
1403 at all locations in the function. This is the smallest number implied | |
1404 by any set of X. */ | |
1405 | |
1406 static void | |
1407 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data) | |
1408 { | |
1409 rtx insn = (rtx) data; | |
1410 unsigned int num; | |
1411 | |
1412 if (REG_P (x) | |
1413 && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
1414 /* If this register is undefined at the start of the file, we can't | |
1415 say what its contents were. */ | |
1416 && ! REGNO_REG_SET_P | |
1417 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)) | |
1418 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) | |
1419 { | |
1420 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x)); | |
1421 | |
1422 if (set == 0 || GET_CODE (set) == CLOBBER) | |
1423 { | |
1424 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); | |
1425 rsp->sign_bit_copies = 1; | |
1426 return; | |
1427 } | |
1428 | |
1429 /* If this register is being initialized using itself, and the | |
1430 register is uninitialized in this basic block, and there are | |
1431 no LOG_LINKS which set the register, then part of the | |
1432 register is uninitialized. In that case we can't assume | |
1433 anything about the number of nonzero bits. | |
1434 | |
1435 ??? We could do better if we checked this in | |
1436 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we | |
1437 could avoid making assumptions about the insn which initially | |
1438 sets the register, while still using the information in other | |
1439 insns. We would have to be careful to check every insn | |
1440 involved in the combination. */ | |
1441 | |
1442 if (insn | |
1443 && reg_referenced_p (x, PATTERN (insn)) | |
1444 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)), | |
1445 REGNO (x))) | |
1446 { | |
1447 rtx link; | |
1448 | |
1449 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
1450 { | |
1451 if (dead_or_set_p (XEXP (link, 0), x)) | |
1452 break; | |
1453 } | |
1454 if (!link) | |
1455 { | |
1456 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); | |
1457 rsp->sign_bit_copies = 1; | |
1458 return; | |
1459 } | |
1460 } | |
1461 | |
1462 /* If this is a complex assignment, see if we can convert it into a | |
1463 simple assignment. */ | |
1464 set = expand_field_assignment (set); | |
1465 | |
1466 /* If this is a simple assignment, or we have a paradoxical SUBREG, | |
1467 set what we know about X. */ | |
1468 | |
1469 if (SET_DEST (set) == x | |
1470 || (GET_CODE (SET_DEST (set)) == SUBREG | |
1471 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) | |
1472 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set))))) | |
1473 && SUBREG_REG (SET_DEST (set)) == x)) | |
1474 { | |
1475 rtx src = SET_SRC (set); | |
1476 | |
1477 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND | |
1478 /* If X is narrower than a word and SRC is a non-negative | |
1479 constant that would appear negative in the mode of X, | |
1480 sign-extend it for use in reg_stat[].nonzero_bits because some | |
1481 machines (maybe most) will actually do the sign-extension | |
1482 and this is the conservative approach. | |
1483 | |
1484 ??? For 2.5, try to tighten up the MD files in this regard | |
1485 instead of this kludge. */ | |
1486 | |
1487 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD | |
1488 && GET_CODE (src) == CONST_INT | |
1489 && INTVAL (src) > 0 | |
1490 && 0 != (INTVAL (src) | |
1491 & ((HOST_WIDE_INT) 1 | |
1492 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) | |
1493 src = GEN_INT (INTVAL (src) | |
1494 | ((HOST_WIDE_INT) (-1) | |
1495 << GET_MODE_BITSIZE (GET_MODE (x)))); | |
1496 #endif | |
1497 | |
1498 /* Don't call nonzero_bits if it cannot change anything. */ | |
1499 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0) | |
1500 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode); | |
1501 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); | |
1502 if (rsp->sign_bit_copies == 0 | |
1503 || rsp->sign_bit_copies > num) | |
1504 rsp->sign_bit_copies = num; | |
1505 } | |
1506 else | |
1507 { | |
1508 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); | |
1509 rsp->sign_bit_copies = 1; | |
1510 } | |
1511 } | |
1512 } | |
1513 | |
1514 /* See if INSN can be combined into I3. PRED and SUCC are optionally | |
1515 insns that were previously combined into I3 or that will be combined | |
1516 into the merger of INSN and I3. | |
1517 | |
1518 Return 0 if the combination is not allowed for any reason. | |
1519 | |
1520 If the combination is allowed, *PDEST will be set to the single | |
1521 destination of INSN and *PSRC to the single source, and this function | |
1522 will return 1. */ | |
1523 | |
1524 static int | |
1525 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ, | |
1526 rtx *pdest, rtx *psrc) | |
1527 { | |
1528 int i; | |
1529 const_rtx set = 0; | |
1530 rtx src, dest; | |
1531 rtx p; | |
1532 #ifdef AUTO_INC_DEC | |
1533 rtx link; | |
1534 #endif | |
1535 int all_adjacent = (succ ? (next_active_insn (insn) == succ | |
1536 && next_active_insn (succ) == i3) | |
1537 : next_active_insn (insn) == i3); | |
1538 | |
1539 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. | |
1540 or a PARALLEL consisting of such a SET and CLOBBERs. | |
1541 | |
1542 If INSN has CLOBBER parallel parts, ignore them for our processing. | |
1543 By definition, these happen during the execution of the insn. When it | |
1544 is merged with another insn, all bets are off. If they are, in fact, | |
1545 needed and aren't also supplied in I3, they may be added by | |
1546 recog_for_combine. Otherwise, it won't match. | |
1547 | |
1548 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED | |
1549 note. | |
1550 | |
1551 Get the source and destination of INSN. If more than one, can't | |
1552 combine. */ | |
1553 | |
1554 if (GET_CODE (PATTERN (insn)) == SET) | |
1555 set = PATTERN (insn); | |
1556 else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1557 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
1558 { | |
1559 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
1560 { | |
1561 rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
1562 rtx note; | |
1563 | |
1564 switch (GET_CODE (elt)) | |
1565 { | |
1566 /* This is important to combine floating point insns | |
1567 for the SH4 port. */ | |
1568 case USE: | |
1569 /* Combining an isolated USE doesn't make sense. | |
1570 We depend here on combinable_i3pat to reject them. */ | |
1571 /* The code below this loop only verifies that the inputs of | |
1572 the SET in INSN do not change. We call reg_set_between_p | |
1573 to verify that the REG in the USE does not change between | |
1574 I3 and INSN. | |
1575 If the USE in INSN was for a pseudo register, the matching | |
1576 insn pattern will likely match any register; combining this | |
1577 with any other USE would only be safe if we knew that the | |
1578 used registers have identical values, or if there was | |
1579 something to tell them apart, e.g. different modes. For | |
1580 now, we forgo such complicated tests and simply disallow | |
1581 combining of USES of pseudo registers with any other USE. */ | |
1582 if (REG_P (XEXP (elt, 0)) | |
1583 && GET_CODE (PATTERN (i3)) == PARALLEL) | |
1584 { | |
1585 rtx i3pat = PATTERN (i3); | |
1586 int i = XVECLEN (i3pat, 0) - 1; | |
1587 unsigned int regno = REGNO (XEXP (elt, 0)); | |
1588 | |
1589 do | |
1590 { | |
1591 rtx i3elt = XVECEXP (i3pat, 0, i); | |
1592 | |
1593 if (GET_CODE (i3elt) == USE | |
1594 && REG_P (XEXP (i3elt, 0)) | |
1595 && (REGNO (XEXP (i3elt, 0)) == regno | |
1596 ? reg_set_between_p (XEXP (elt, 0), | |
1597 PREV_INSN (insn), i3) | |
1598 : regno >= FIRST_PSEUDO_REGISTER)) | |
1599 return 0; | |
1600 } | |
1601 while (--i >= 0); | |
1602 } | |
1603 break; | |
1604 | |
1605 /* We can ignore CLOBBERs. */ | |
1606 case CLOBBER: | |
1607 break; | |
1608 | |
1609 case SET: | |
1610 /* Ignore SETs whose result isn't used but not those that | |
1611 have side-effects. */ | |
1612 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) | |
1613 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX)) | |
1614 || INTVAL (XEXP (note, 0)) <= 0) | |
1615 && ! side_effects_p (elt)) | |
1616 break; | |
1617 | |
1618 /* If we have already found a SET, this is a second one and | |
1619 so we cannot combine with this insn. */ | |
1620 if (set) | |
1621 return 0; | |
1622 | |
1623 set = elt; | |
1624 break; | |
1625 | |
1626 default: | |
1627 /* Anything else means we can't combine. */ | |
1628 return 0; | |
1629 } | |
1630 } | |
1631 | |
1632 if (set == 0 | |
1633 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, | |
1634 so don't do anything with it. */ | |
1635 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) | |
1636 return 0; | |
1637 } | |
1638 else | |
1639 return 0; | |
1640 | |
1641 if (set == 0) | |
1642 return 0; | |
1643 | |
1644 set = expand_field_assignment (set); | |
1645 src = SET_SRC (set), dest = SET_DEST (set); | |
1646 | |
1647 /* Don't eliminate a store in the stack pointer. */ | |
1648 if (dest == stack_pointer_rtx | |
1649 /* Don't combine with an insn that sets a register to itself if it has | |
1650 a REG_EQUAL note. This may be part of a LIBCALL sequence. */ | |
1651 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) | |
1652 /* Can't merge an ASM_OPERANDS. */ | |
1653 || GET_CODE (src) == ASM_OPERANDS | |
1654 /* Can't merge a function call. */ | |
1655 || GET_CODE (src) == CALL | |
1656 /* Don't eliminate a function call argument. */ | |
1657 || (CALL_P (i3) | |
1658 && (find_reg_fusage (i3, USE, dest) | |
1659 || (REG_P (dest) | |
1660 && REGNO (dest) < FIRST_PSEUDO_REGISTER | |
1661 && global_regs[REGNO (dest)]))) | |
1662 /* Don't substitute into an incremented register. */ | |
1663 || FIND_REG_INC_NOTE (i3, dest) | |
1664 || (succ && FIND_REG_INC_NOTE (succ, dest)) | |
1665 /* Don't substitute into a non-local goto, this confuses CFG. */ | |
1666 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
1667 /* Make sure that DEST is not used after SUCC but before I3. */ | |
1668 || (succ && ! all_adjacent | |
1669 && reg_used_between_p (dest, succ, i3)) | |
1670 /* Make sure that the value that is to be substituted for the register | |
1671 does not use any registers whose values alter in between. However, | |
1672 If the insns are adjacent, a use can't cross a set even though we | |
1673 think it might (this can happen for a sequence of insns each setting | |
1674 the same destination; last_set of that register might point to | |
1675 a NOTE). If INSN has a REG_EQUIV note, the register is always | |
1676 equivalent to the memory so the substitution is valid even if there | |
1677 are intervening stores. Also, don't move a volatile asm or | |
1678 UNSPEC_VOLATILE across any other insns. */ | |
1679 || (! all_adjacent | |
1680 && (((!MEM_P (src) | |
1681 || ! find_reg_note (insn, REG_EQUIV, src)) | |
1682 && use_crosses_set_p (src, DF_INSN_LUID (insn))) | |
1683 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) | |
1684 || GET_CODE (src) == UNSPEC_VOLATILE)) | |
1685 /* Don't combine across a CALL_INSN, because that would possibly | |
1686 change whether the life span of some REGs crosses calls or not, | |
1687 and it is a pain to update that information. | |
1688 Exception: if source is a constant, moving it later can't hurt. | |
1689 Accept that as a special case. */ | |
1690 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src))) | |
1691 return 0; | |
1692 | |
1693 /* DEST must either be a REG or CC0. */ | |
1694 if (REG_P (dest)) | |
1695 { | |
1696 /* If register alignment is being enforced for multi-word items in all | |
1697 cases except for parameters, it is possible to have a register copy | |
1698 insn referencing a hard register that is not allowed to contain the | |
1699 mode being copied and which would not be valid as an operand of most | |
1700 insns. Eliminate this problem by not combining with such an insn. | |
1701 | |
1702 Also, on some machines we don't want to extend the life of a hard | |
1703 register. */ | |
1704 | |
1705 if (REG_P (src) | |
1706 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER | |
1707 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) | |
1708 /* Don't extend the life of a hard register unless it is | |
1709 user variable (if we have few registers) or it can't | |
1710 fit into the desired register (meaning something special | |
1711 is going on). | |
1712 Also avoid substituting a return register into I3, because | |
1713 reload can't handle a conflict with constraints of other | |
1714 inputs. */ | |
1715 || (REGNO (src) < FIRST_PSEUDO_REGISTER | |
1716 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))))) | |
1717 return 0; | |
1718 } | |
1719 else if (GET_CODE (dest) != CC0) | |
1720 return 0; | |
1721 | |
1722 | |
1723 if (GET_CODE (PATTERN (i3)) == PARALLEL) | |
1724 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) | |
1725 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER) | |
1726 { | |
1727 /* Don't substitute for a register intended as a clobberable | |
1728 operand. */ | |
1729 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0); | |
1730 if (rtx_equal_p (reg, dest)) | |
1731 return 0; | |
1732 | |
1733 /* If the clobber represents an earlyclobber operand, we must not | |
1734 substitute an expression containing the clobbered register. | |
1735 As we do not analyze the constraint strings here, we have to | |
1736 make the conservative assumption. However, if the register is | |
1737 a fixed hard reg, the clobber cannot represent any operand; | |
1738 we leave it up to the machine description to either accept or | |
1739 reject use-and-clobber patterns. */ | |
1740 if (!REG_P (reg) | |
1741 || REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1742 || !fixed_regs[REGNO (reg)]) | |
1743 if (reg_overlap_mentioned_p (reg, src)) | |
1744 return 0; | |
1745 } | |
1746 | |
1747 /* If INSN contains anything volatile, or is an `asm' (whether volatile | |
1748 or not), reject, unless nothing volatile comes between it and I3 */ | |
1749 | |
1750 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) | |
1751 { | |
1752 /* Make sure succ doesn't contain a volatile reference. */ | |
1753 if (succ != 0 && volatile_refs_p (PATTERN (succ))) | |
1754 return 0; | |
1755 | |
1756 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) | |
1757 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p))) | |
1758 return 0; | |
1759 } | |
1760 | |
1761 /* If INSN is an asm, and DEST is a hard register, reject, since it has | |
1762 to be an explicit register variable, and was chosen for a reason. */ | |
1763 | |
1764 if (GET_CODE (src) == ASM_OPERANDS | |
1765 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER) | |
1766 return 0; | |
1767 | |
1768 /* If there are any volatile insns between INSN and I3, reject, because | |
1769 they might affect machine state. */ | |
1770 | |
1771 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) | |
1772 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p))) | |
1773 return 0; | |
1774 | |
1775 /* If INSN contains an autoincrement or autodecrement, make sure that | |
1776 register is not used between there and I3, and not already used in | |
1777 I3 either. Neither must it be used in PRED or SUCC, if they exist. | |
1778 Also insist that I3 not be a jump; if it were one | |
1779 and the incremented register were spilled, we would lose. */ | |
1780 | |
1781 #ifdef AUTO_INC_DEC | |
1782 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1783 if (REG_NOTE_KIND (link) == REG_INC | |
1784 && (JUMP_P (i3) | |
1785 || reg_used_between_p (XEXP (link, 0), insn, i3) | |
1786 || (pred != NULL_RTX | |
1787 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred))) | |
1788 || (succ != NULL_RTX | |
1789 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ))) | |
1790 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) | |
1791 return 0; | |
1792 #endif | |
1793 | |
1794 #ifdef HAVE_cc0 | |
1795 /* Don't combine an insn that follows a CC0-setting insn. | |
1796 An insn that uses CC0 must not be separated from the one that sets it. | |
1797 We do, however, allow I2 to follow a CC0-setting insn if that insn | |
1798 is passed as I1; in that case it will be deleted also. | |
1799 We also allow combining in this case if all the insns are adjacent | |
1800 because that would leave the two CC0 insns adjacent as well. | |
1801 It would be more logical to test whether CC0 occurs inside I1 or I2, | |
1802 but that would be much slower, and this ought to be equivalent. */ | |
1803 | |
1804 p = prev_nonnote_insn (insn); | |
1805 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p)) | |
1806 && ! all_adjacent) | |
1807 return 0; | |
1808 #endif | |
1809 | |
1810 /* If we get here, we have passed all the tests and the combination is | |
1811 to be allowed. */ | |
1812 | |
1813 *pdest = dest; | |
1814 *psrc = src; | |
1815 | |
1816 return 1; | |
1817 } | |
1818 | |
1819 /* LOC is the location within I3 that contains its pattern or the component | |
1820 of a PARALLEL of the pattern. We validate that it is valid for combining. | |
1821 | |
1822 One problem is if I3 modifies its output, as opposed to replacing it | |
1823 entirely, we can't allow the output to contain I2DEST or I1DEST as doing | |
1824 so would produce an insn that is not equivalent to the original insns. | |
1825 | |
1826 Consider: | |
1827 | |
1828 (set (reg:DI 101) (reg:DI 100)) | |
1829 (set (subreg:SI (reg:DI 101) 0) <foo>) | |
1830 | |
1831 This is NOT equivalent to: | |
1832 | |
1833 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) | |
1834 (set (reg:DI 101) (reg:DI 100))]) | |
1835 | |
1836 Not only does this modify 100 (in which case it might still be valid | |
1837 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. | |
1838 | |
1839 We can also run into a problem if I2 sets a register that I1 | |
1840 uses and I1 gets directly substituted into I3 (not via I2). In that | |
1841 case, we would be getting the wrong value of I2DEST into I3, so we | |
1842 must reject the combination. This case occurs when I2 and I1 both | |
1843 feed into I3, rather than when I1 feeds into I2, which feeds into I3. | |
1844 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source | |
1845 of a SET must prevent combination from occurring. | |
1846 | |
1847 Before doing the above check, we first try to expand a field assignment | |
1848 into a set of logical operations. | |
1849 | |
1850 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which | |
1851 we place a register that is both set and used within I3. If more than one | |
1852 such register is detected, we fail. | |
1853 | |
1854 Return 1 if the combination is valid, zero otherwise. */ | |
1855 | |
1856 static int | |
1857 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, | |
1858 int i1_not_in_src, rtx *pi3dest_killed) | |
1859 { | |
1860 rtx x = *loc; | |
1861 | |
1862 if (GET_CODE (x) == SET) | |
1863 { | |
1864 rtx set = x ; | |
1865 rtx dest = SET_DEST (set); | |
1866 rtx src = SET_SRC (set); | |
1867 rtx inner_dest = dest; | |
1868 rtx subdest; | |
1869 | |
1870 while (GET_CODE (inner_dest) == STRICT_LOW_PART | |
1871 || GET_CODE (inner_dest) == SUBREG | |
1872 || GET_CODE (inner_dest) == ZERO_EXTRACT) | |
1873 inner_dest = XEXP (inner_dest, 0); | |
1874 | |
1875 /* Check for the case where I3 modifies its output, as discussed | |
1876 above. We don't want to prevent pseudos from being combined | |
1877 into the address of a MEM, so only prevent the combination if | |
1878 i1 or i2 set the same MEM. */ | |
1879 if ((inner_dest != dest && | |
1880 (!MEM_P (inner_dest) | |
1881 || rtx_equal_p (i2dest, inner_dest) | |
1882 || (i1dest && rtx_equal_p (i1dest, inner_dest))) | |
1883 && (reg_overlap_mentioned_p (i2dest, inner_dest) | |
1884 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) | |
1885 | |
1886 /* This is the same test done in can_combine_p except we can't test | |
1887 all_adjacent; we don't have to, since this instruction will stay | |
1888 in place, thus we are not considering increasing the lifetime of | |
1889 INNER_DEST. | |
1890 | |
1891 Also, if this insn sets a function argument, combining it with | |
1892 something that might need a spill could clobber a previous | |
1893 function argument; the all_adjacent test in can_combine_p also | |
1894 checks this; here, we do a more specific test for this case. */ | |
1895 | |
1896 || (REG_P (inner_dest) | |
1897 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER | |
1898 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), | |
1899 GET_MODE (inner_dest)))) | |
1900 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) | |
1901 return 0; | |
1902 | |
1903 /* If DEST is used in I3, it is being killed in this insn, so | |
1904 record that for later. We have to consider paradoxical | |
1905 subregs here, since they kill the whole register, but we | |
1906 ignore partial subregs, STRICT_LOW_PART, etc. | |
1907 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the | |
1908 STACK_POINTER_REGNUM, since these are always considered to be | |
1909 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ | |
1910 subdest = dest; | |
1911 if (GET_CODE (subdest) == SUBREG | |
1912 && (GET_MODE_SIZE (GET_MODE (subdest)) | |
1913 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest))))) | |
1914 subdest = SUBREG_REG (subdest); | |
1915 if (pi3dest_killed | |
1916 && REG_P (subdest) | |
1917 && reg_referenced_p (subdest, PATTERN (i3)) | |
1918 && REGNO (subdest) != FRAME_POINTER_REGNUM | |
1919 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
1920 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM | |
1921 #endif | |
1922 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
1923 && (REGNO (subdest) != ARG_POINTER_REGNUM | |
1924 || ! fixed_regs [REGNO (subdest)]) | |
1925 #endif | |
1926 && REGNO (subdest) != STACK_POINTER_REGNUM) | |
1927 { | |
1928 if (*pi3dest_killed) | |
1929 return 0; | |
1930 | |
1931 *pi3dest_killed = subdest; | |
1932 } | |
1933 } | |
1934 | |
1935 else if (GET_CODE (x) == PARALLEL) | |
1936 { | |
1937 int i; | |
1938 | |
1939 for (i = 0; i < XVECLEN (x, 0); i++) | |
1940 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, | |
1941 i1_not_in_src, pi3dest_killed)) | |
1942 return 0; | |
1943 } | |
1944 | |
1945 return 1; | |
1946 } | |
1947 | |
1948 /* Return 1 if X is an arithmetic expression that contains a multiplication | |
1949 and division. We don't count multiplications by powers of two here. */ | |
1950 | |
1951 static int | |
1952 contains_muldiv (rtx x) | |
1953 { | |
1954 switch (GET_CODE (x)) | |
1955 { | |
1956 case MOD: case DIV: case UMOD: case UDIV: | |
1957 return 1; | |
1958 | |
1959 case MULT: | |
1960 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1961 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0); | |
1962 default: | |
1963 if (BINARY_P (x)) | |
1964 return contains_muldiv (XEXP (x, 0)) | |
1965 || contains_muldiv (XEXP (x, 1)); | |
1966 | |
1967 if (UNARY_P (x)) | |
1968 return contains_muldiv (XEXP (x, 0)); | |
1969 | |
1970 return 0; | |
1971 } | |
1972 } | |
1973 | |
1974 /* Determine whether INSN can be used in a combination. Return nonzero if | |
1975 not. This is used in try_combine to detect early some cases where we | |
1976 can't perform combinations. */ | |
1977 | |
1978 static int | |
1979 cant_combine_insn_p (rtx insn) | |
1980 { | |
1981 rtx set; | |
1982 rtx src, dest; | |
1983 | |
1984 /* If this isn't really an insn, we can't do anything. | |
1985 This can occur when flow deletes an insn that it has merged into an | |
1986 auto-increment address. */ | |
1987 if (! INSN_P (insn)) | |
1988 return 1; | |
1989 | |
1990 /* Never combine loads and stores involving hard regs that are likely | |
1991 to be spilled. The register allocator can usually handle such | |
1992 reg-reg moves by tying. If we allow the combiner to make | |
1993 substitutions of likely-spilled regs, reload might die. | |
1994 As an exception, we allow combinations involving fixed regs; these are | |
1995 not available to the register allocator so there's no risk involved. */ | |
1996 | |
1997 set = single_set (insn); | |
1998 if (! set) | |
1999 return 0; | |
2000 src = SET_SRC (set); | |
2001 dest = SET_DEST (set); | |
2002 if (GET_CODE (src) == SUBREG) | |
2003 src = SUBREG_REG (src); | |
2004 if (GET_CODE (dest) == SUBREG) | |
2005 dest = SUBREG_REG (dest); | |
2006 if (REG_P (src) && REG_P (dest) | |
2007 && ((REGNO (src) < FIRST_PSEUDO_REGISTER | |
2008 && ! fixed_regs[REGNO (src)] | |
2009 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src)))) | |
2010 || (REGNO (dest) < FIRST_PSEUDO_REGISTER | |
2011 && ! fixed_regs[REGNO (dest)] | |
2012 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest)))))) | |
2013 return 1; | |
2014 | |
2015 return 0; | |
2016 } | |
2017 | |
2018 struct likely_spilled_retval_info | |
2019 { | |
2020 unsigned regno, nregs; | |
2021 unsigned mask; | |
2022 }; | |
2023 | |
2024 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask | |
2025 hard registers that are known to be written to / clobbered in full. */ | |
2026 static void | |
2027 likely_spilled_retval_1 (rtx x, const_rtx set, void *data) | |
2028 { | |
2029 struct likely_spilled_retval_info *const info = | |
2030 (struct likely_spilled_retval_info *) data; | |
2031 unsigned regno, nregs; | |
2032 unsigned new_mask; | |
2033 | |
2034 if (!REG_P (XEXP (set, 0))) | |
2035 return; | |
2036 regno = REGNO (x); | |
2037 if (regno >= info->regno + info->nregs) | |
2038 return; | |
2039 nregs = hard_regno_nregs[regno][GET_MODE (x)]; | |
2040 if (regno + nregs <= info->regno) | |
2041 return; | |
2042 new_mask = (2U << (nregs - 1)) - 1; | |
2043 if (regno < info->regno) | |
2044 new_mask >>= info->regno - regno; | |
2045 else | |
2046 new_mask <<= regno - info->regno; | |
2047 info->mask &= ~new_mask; | |
2048 } | |
2049 | |
2050 /* Return nonzero iff part of the return value is live during INSN, and | |
2051 it is likely spilled. This can happen when more than one insn is needed | |
2052 to copy the return value, e.g. when we consider to combine into the | |
2053 second copy insn for a complex value. */ | |
2054 | |
2055 static int | |
2056 likely_spilled_retval_p (rtx insn) | |
2057 { | |
2058 rtx use = BB_END (this_basic_block); | |
2059 rtx reg, p; | |
2060 unsigned regno, nregs; | |
2061 /* We assume here that no machine mode needs more than | |
2062 32 hard registers when the value overlaps with a register | |
2063 for which FUNCTION_VALUE_REGNO_P is true. */ | |
2064 unsigned mask; | |
2065 struct likely_spilled_retval_info info; | |
2066 | |
2067 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use) | |
2068 return 0; | |
2069 reg = XEXP (PATTERN (use), 0); | |
2070 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg))) | |
2071 return 0; | |
2072 regno = REGNO (reg); | |
2073 nregs = hard_regno_nregs[regno][GET_MODE (reg)]; | |
2074 if (nregs == 1) | |
2075 return 0; | |
2076 mask = (2U << (nregs - 1)) - 1; | |
2077 | |
2078 /* Disregard parts of the return value that are set later. */ | |
2079 info.regno = regno; | |
2080 info.nregs = nregs; | |
2081 info.mask = mask; | |
2082 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p)) | |
2083 if (INSN_P (p)) | |
2084 note_stores (PATTERN (p), likely_spilled_retval_1, &info); | |
2085 mask = info.mask; | |
2086 | |
2087 /* Check if any of the (probably) live return value registers is | |
2088 likely spilled. */ | |
2089 nregs --; | |
2090 do | |
2091 { | |
2092 if ((mask & 1 << nregs) | |
2093 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs))) | |
2094 return 1; | |
2095 } while (nregs--); | |
2096 return 0; | |
2097 } | |
2098 | |
2099 /* Adjust INSN after we made a change to its destination. | |
2100 | |
2101 Changing the destination can invalidate notes that say something about | |
2102 the results of the insn and a LOG_LINK pointing to the insn. */ | |
2103 | |
2104 static void | |
2105 adjust_for_new_dest (rtx insn) | |
2106 { | |
2107 /* For notes, be conservative and simply remove them. */ | |
2108 remove_reg_equal_equiv_notes (insn); | |
2109 | |
2110 /* The new insn will have a destination that was previously the destination | |
2111 of an insn just above it. Call distribute_links to make a LOG_LINK from | |
2112 the next use of that destination. */ | |
2113 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX)); | |
2114 | |
2115 df_insn_rescan (insn); | |
2116 } | |
2117 | |
2118 /* Return TRUE if combine can reuse reg X in mode MODE. | |
2119 ADDED_SETS is nonzero if the original set is still required. */ | |
2120 static bool | |
2121 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode) | |
2122 { | |
2123 unsigned int regno; | |
2124 | |
2125 if (!REG_P(x)) | |
2126 return false; | |
2127 | |
2128 regno = REGNO (x); | |
2129 /* Allow hard registers if the new mode is legal, and occupies no more | |
2130 registers than the old mode. */ | |
2131 if (regno < FIRST_PSEUDO_REGISTER) | |
2132 return (HARD_REGNO_MODE_OK (regno, mode) | |
2133 && (hard_regno_nregs[regno][GET_MODE (x)] | |
2134 >= hard_regno_nregs[regno][mode])); | |
2135 | |
2136 /* Or a pseudo that is only used once. */ | |
2137 return (REG_N_SETS (regno) == 1 && !added_sets | |
2138 && !REG_USERVAR_P (x)); | |
2139 } | |
2140 | |
2141 | |
2142 /* Check whether X, the destination of a set, refers to part of | |
2143 the register specified by REG. */ | |
2144 | |
2145 static bool | |
2146 reg_subword_p (rtx x, rtx reg) | |
2147 { | |
2148 /* Check that reg is an integer mode register. */ | |
2149 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT) | |
2150 return false; | |
2151 | |
2152 if (GET_CODE (x) == STRICT_LOW_PART | |
2153 || GET_CODE (x) == ZERO_EXTRACT) | |
2154 x = XEXP (x, 0); | |
2155 | |
2156 return GET_CODE (x) == SUBREG | |
2157 && SUBREG_REG (x) == reg | |
2158 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT; | |
2159 } | |
2160 | |
2161 | |
2162 /* Try to combine the insns I1 and I2 into I3. | |
2163 Here I1 and I2 appear earlier than I3. | |
2164 I1 can be zero; then we combine just I2 into I3. | |
2165 | |
2166 If we are combining three insns and the resulting insn is not recognized, | |
2167 try splitting it into two insns. If that happens, I2 and I3 are retained | |
2168 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 | |
2169 are pseudo-deleted. | |
2170 | |
2171 Return 0 if the combination does not work. Then nothing is changed. | |
2172 If we did the combination, return the insn at which combine should | |
2173 resume scanning. | |
2174 | |
2175 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a | |
2176 new direct jump instruction. */ | |
2177 | |
2178 static rtx | |
2179 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p) | |
2180 { | |
2181 /* New patterns for I3 and I2, respectively. */ | |
2182 rtx newpat, newi2pat = 0; | |
2183 rtvec newpat_vec_with_clobbers = 0; | |
2184 int substed_i2 = 0, substed_i1 = 0; | |
2185 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ | |
2186 int added_sets_1, added_sets_2; | |
2187 /* Total number of SETs to put into I3. */ | |
2188 int total_sets; | |
2189 /* Nonzero if I2's body now appears in I3. */ | |
2190 int i2_is_used; | |
2191 /* INSN_CODEs for new I3, new I2, and user of condition code. */ | |
2192 int insn_code_number, i2_code_number = 0, other_code_number = 0; | |
2193 /* Contains I3 if the destination of I3 is used in its source, which means | |
2194 that the old life of I3 is being killed. If that usage is placed into | |
2195 I2 and not in I3, a REG_DEAD note must be made. */ | |
2196 rtx i3dest_killed = 0; | |
2197 /* SET_DEST and SET_SRC of I2 and I1. */ | |
2198 rtx i2dest, i2src, i1dest = 0, i1src = 0; | |
2199 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */ | |
2200 rtx i1pat = 0, i2pat = 0; | |
2201 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ | |
2202 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; | |
2203 int i2dest_killed = 0, i1dest_killed = 0; | |
2204 int i1_feeds_i3 = 0; | |
2205 /* Notes that must be added to REG_NOTES in I3 and I2. */ | |
2206 rtx new_i3_notes, new_i2_notes; | |
2207 /* Notes that we substituted I3 into I2 instead of the normal case. */ | |
2208 int i3_subst_into_i2 = 0; | |
2209 /* Notes that I1, I2 or I3 is a MULT operation. */ | |
2210 int have_mult = 0; | |
2211 int swap_i2i3 = 0; | |
2212 int changed_i3_dest = 0; | |
2213 | |
2214 int maxreg; | |
2215 rtx temp; | |
2216 rtx link; | |
2217 rtx other_pat = 0; | |
2218 rtx new_other_notes; | |
2219 int i; | |
2220 | |
2221 /* Exit early if one of the insns involved can't be used for | |
2222 combinations. */ | |
2223 if (cant_combine_insn_p (i3) | |
2224 || cant_combine_insn_p (i2) | |
2225 || (i1 && cant_combine_insn_p (i1)) | |
2226 || likely_spilled_retval_p (i3)) | |
2227 return 0; | |
2228 | |
2229 combine_attempts++; | |
2230 undobuf.other_insn = 0; | |
2231 | |
2232 /* Reset the hard register usage information. */ | |
2233 CLEAR_HARD_REG_SET (newpat_used_regs); | |
2234 | |
2235 /* If I1 and I2 both feed I3, they can be in any order. To simplify the | |
2236 code below, set I1 to be the earlier of the two insns. */ | |
2237 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2)) | |
2238 temp = i1, i1 = i2, i2 = temp; | |
2239 | |
2240 added_links_insn = 0; | |
2241 | |
2242 /* First check for one important special-case that the code below will | |
2243 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL | |
2244 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, | |
2245 we may be able to replace that destination with the destination of I3. | |
2246 This occurs in the common code where we compute both a quotient and | |
2247 remainder into a structure, in which case we want to do the computation | |
2248 directly into the structure to avoid register-register copies. | |
2249 | |
2250 Note that this case handles both multiple sets in I2 and also | |
2251 cases where I2 has a number of CLOBBER or PARALLELs. | |
2252 | |
2253 We make very conservative checks below and only try to handle the | |
2254 most common cases of this. For example, we only handle the case | |
2255 where I2 and I3 are adjacent to avoid making difficult register | |
2256 usage tests. */ | |
2257 | |
2258 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET | |
2259 && REG_P (SET_SRC (PATTERN (i3))) | |
2260 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER | |
2261 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) | |
2262 && GET_CODE (PATTERN (i2)) == PARALLEL | |
2263 && ! side_effects_p (SET_DEST (PATTERN (i3))) | |
2264 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code | |
2265 below would need to check what is inside (and reg_overlap_mentioned_p | |
2266 doesn't support those codes anyway). Don't allow those destinations; | |
2267 the resulting insn isn't likely to be recognized anyway. */ | |
2268 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT | |
2269 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART | |
2270 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), | |
2271 SET_DEST (PATTERN (i3))) | |
2272 && next_real_insn (i2) == i3) | |
2273 { | |
2274 rtx p2 = PATTERN (i2); | |
2275 | |
2276 /* Make sure that the destination of I3, | |
2277 which we are going to substitute into one output of I2, | |
2278 is not used within another output of I2. We must avoid making this: | |
2279 (parallel [(set (mem (reg 69)) ...) | |
2280 (set (reg 69) ...)]) | |
2281 which is not well-defined as to order of actions. | |
2282 (Besides, reload can't handle output reloads for this.) | |
2283 | |
2284 The problem can also happen if the dest of I3 is a memory ref, | |
2285 if another dest in I2 is an indirect memory ref. */ | |
2286 for (i = 0; i < XVECLEN (p2, 0); i++) | |
2287 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET | |
2288 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) | |
2289 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), | |
2290 SET_DEST (XVECEXP (p2, 0, i)))) | |
2291 break; | |
2292 | |
2293 if (i == XVECLEN (p2, 0)) | |
2294 for (i = 0; i < XVECLEN (p2, 0); i++) | |
2295 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET | |
2296 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) | |
2297 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) | |
2298 { | |
2299 combine_merges++; | |
2300 | |
2301 subst_insn = i3; | |
2302 subst_low_luid = DF_INSN_LUID (i2); | |
2303 | |
2304 added_sets_2 = added_sets_1 = 0; | |
2305 i2dest = SET_SRC (PATTERN (i3)); | |
2306 i2dest_killed = dead_or_set_p (i2, i2dest); | |
2307 | |
2308 /* Replace the dest in I2 with our dest and make the resulting | |
2309 insn the new pattern for I3. Then skip to where we | |
2310 validate the pattern. Everything was set up above. */ | |
2311 SUBST (SET_DEST (XVECEXP (p2, 0, i)), | |
2312 SET_DEST (PATTERN (i3))); | |
2313 | |
2314 newpat = p2; | |
2315 i3_subst_into_i2 = 1; | |
2316 goto validate_replacement; | |
2317 } | |
2318 } | |
2319 | |
2320 /* If I2 is setting a pseudo to a constant and I3 is setting some | |
2321 sub-part of it to another constant, merge them by making a new | |
2322 constant. */ | |
2323 if (i1 == 0 | |
2324 && (temp = single_set (i2)) != 0 | |
2325 && (GET_CODE (SET_SRC (temp)) == CONST_INT | |
2326 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE) | |
2327 && GET_CODE (PATTERN (i3)) == SET | |
2328 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT | |
2329 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE) | |
2330 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp))) | |
2331 { | |
2332 rtx dest = SET_DEST (PATTERN (i3)); | |
2333 int offset = -1; | |
2334 int width = 0; | |
2335 | |
2336 if (GET_CODE (dest) == ZERO_EXTRACT) | |
2337 { | |
2338 if (GET_CODE (XEXP (dest, 1)) == CONST_INT | |
2339 && GET_CODE (XEXP (dest, 2)) == CONST_INT) | |
2340 { | |
2341 width = INTVAL (XEXP (dest, 1)); | |
2342 offset = INTVAL (XEXP (dest, 2)); | |
2343 dest = XEXP (dest, 0); | |
2344 if (BITS_BIG_ENDIAN) | |
2345 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset; | |
2346 } | |
2347 } | |
2348 else | |
2349 { | |
2350 if (GET_CODE (dest) == STRICT_LOW_PART) | |
2351 dest = XEXP (dest, 0); | |
2352 width = GET_MODE_BITSIZE (GET_MODE (dest)); | |
2353 offset = 0; | |
2354 } | |
2355 | |
2356 if (offset >= 0) | |
2357 { | |
2358 /* If this is the low part, we're done. */ | |
2359 if (subreg_lowpart_p (dest)) | |
2360 ; | |
2361 /* Handle the case where inner is twice the size of outer. */ | |
2362 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp))) | |
2363 == 2 * GET_MODE_BITSIZE (GET_MODE (dest))) | |
2364 offset += GET_MODE_BITSIZE (GET_MODE (dest)); | |
2365 /* Otherwise give up for now. */ | |
2366 else | |
2367 offset = -1; | |
2368 } | |
2369 | |
2370 if (offset >= 0 | |
2371 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp))) | |
2372 <= HOST_BITS_PER_WIDE_INT * 2)) | |
2373 { | |
2374 HOST_WIDE_INT mhi, ohi, ihi; | |
2375 HOST_WIDE_INT mlo, olo, ilo; | |
2376 rtx inner = SET_SRC (PATTERN (i3)); | |
2377 rtx outer = SET_SRC (temp); | |
2378 | |
2379 if (GET_CODE (outer) == CONST_INT) | |
2380 { | |
2381 olo = INTVAL (outer); | |
2382 ohi = olo < 0 ? -1 : 0; | |
2383 } | |
2384 else | |
2385 { | |
2386 olo = CONST_DOUBLE_LOW (outer); | |
2387 ohi = CONST_DOUBLE_HIGH (outer); | |
2388 } | |
2389 | |
2390 if (GET_CODE (inner) == CONST_INT) | |
2391 { | |
2392 ilo = INTVAL (inner); | |
2393 ihi = ilo < 0 ? -1 : 0; | |
2394 } | |
2395 else | |
2396 { | |
2397 ilo = CONST_DOUBLE_LOW (inner); | |
2398 ihi = CONST_DOUBLE_HIGH (inner); | |
2399 } | |
2400 | |
2401 if (width < HOST_BITS_PER_WIDE_INT) | |
2402 { | |
2403 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1; | |
2404 mhi = 0; | |
2405 } | |
2406 else if (width < HOST_BITS_PER_WIDE_INT * 2) | |
2407 { | |
2408 mhi = ((unsigned HOST_WIDE_INT) 1 | |
2409 << (width - HOST_BITS_PER_WIDE_INT)) - 1; | |
2410 mlo = -1; | |
2411 } | |
2412 else | |
2413 { | |
2414 mlo = -1; | |
2415 mhi = -1; | |
2416 } | |
2417 | |
2418 ilo &= mlo; | |
2419 ihi &= mhi; | |
2420 | |
2421 if (offset >= HOST_BITS_PER_WIDE_INT) | |
2422 { | |
2423 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT); | |
2424 mlo = 0; | |
2425 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT); | |
2426 ilo = 0; | |
2427 } | |
2428 else if (offset > 0) | |
2429 { | |
2430 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo | |
2431 >> (HOST_BITS_PER_WIDE_INT - offset)); | |
2432 mlo = mlo << offset; | |
2433 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo | |
2434 >> (HOST_BITS_PER_WIDE_INT - offset)); | |
2435 ilo = ilo << offset; | |
2436 } | |
2437 | |
2438 olo = (olo & ~mlo) | ilo; | |
2439 ohi = (ohi & ~mhi) | ihi; | |
2440 | |
2441 combine_merges++; | |
2442 subst_insn = i3; | |
2443 subst_low_luid = DF_INSN_LUID (i2); | |
2444 added_sets_2 = added_sets_1 = 0; | |
2445 i2dest = SET_DEST (temp); | |
2446 i2dest_killed = dead_or_set_p (i2, i2dest); | |
2447 | |
2448 SUBST (SET_SRC (temp), | |
2449 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp)))); | |
2450 | |
2451 newpat = PATTERN (i2); | |
2452 goto validate_replacement; | |
2453 } | |
2454 } | |
2455 | |
2456 #ifndef HAVE_cc0 | |
2457 /* If we have no I1 and I2 looks like: | |
2458 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) | |
2459 (set Y OP)]) | |
2460 make up a dummy I1 that is | |
2461 (set Y OP) | |
2462 and change I2 to be | |
2463 (set (reg:CC X) (compare:CC Y (const_int 0))) | |
2464 | |
2465 (We can ignore any trailing CLOBBERs.) | |
2466 | |
2467 This undoes a previous combination and allows us to match a branch-and- | |
2468 decrement insn. */ | |
2469 | |
2470 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL | |
2471 && XVECLEN (PATTERN (i2), 0) >= 2 | |
2472 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET | |
2473 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) | |
2474 == MODE_CC) | |
2475 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE | |
2476 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx | |
2477 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET | |
2478 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) | |
2479 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), | |
2480 SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) | |
2481 { | |
2482 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) | |
2483 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) | |
2484 break; | |
2485 | |
2486 if (i == 1) | |
2487 { | |
2488 /* We make I1 with the same INSN_UID as I2. This gives it | |
2489 the same DF_INSN_LUID for value tracking. Our fake I1 will | |
2490 never appear in the insn stream so giving it the same INSN_UID | |
2491 as I2 will not cause a problem. */ | |
2492 | |
2493 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2, | |
2494 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2), | |
2495 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX); | |
2496 | |
2497 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); | |
2498 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), | |
2499 SET_DEST (PATTERN (i1))); | |
2500 } | |
2501 } | |
2502 #endif | |
2503 | |
2504 /* Verify that I2 and I1 are valid for combining. */ | |
2505 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src) | |
2506 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src))) | |
2507 { | |
2508 undo_all (); | |
2509 return 0; | |
2510 } | |
2511 | |
2512 /* Record whether I2DEST is used in I2SRC and similarly for the other | |
2513 cases. Knowing this will help in register status updating below. */ | |
2514 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); | |
2515 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); | |
2516 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); | |
2517 i2dest_killed = dead_or_set_p (i2, i2dest); | |
2518 i1dest_killed = i1 && dead_or_set_p (i1, i1dest); | |
2519 | |
2520 /* See if I1 directly feeds into I3. It does if I1DEST is not used | |
2521 in I2SRC. */ | |
2522 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); | |
2523 | |
2524 /* Ensure that I3's pattern can be the destination of combines. */ | |
2525 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, | |
2526 i1 && i2dest_in_i1src && i1_feeds_i3, | |
2527 &i3dest_killed)) | |
2528 { | |
2529 undo_all (); | |
2530 return 0; | |
2531 } | |
2532 | |
2533 /* See if any of the insns is a MULT operation. Unless one is, we will | |
2534 reject a combination that is, since it must be slower. Be conservative | |
2535 here. */ | |
2536 if (GET_CODE (i2src) == MULT | |
2537 || (i1 != 0 && GET_CODE (i1src) == MULT) | |
2538 || (GET_CODE (PATTERN (i3)) == SET | |
2539 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) | |
2540 have_mult = 1; | |
2541 | |
2542 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. | |
2543 We used to do this EXCEPT in one case: I3 has a post-inc in an | |
2544 output operand. However, that exception can give rise to insns like | |
2545 mov r3,(r3)+ | |
2546 which is a famous insn on the PDP-11 where the value of r3 used as the | |
2547 source was model-dependent. Avoid this sort of thing. */ | |
2548 | |
2549 #if 0 | |
2550 if (!(GET_CODE (PATTERN (i3)) == SET | |
2551 && REG_P (SET_SRC (PATTERN (i3))) | |
2552 && MEM_P (SET_DEST (PATTERN (i3))) | |
2553 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC | |
2554 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) | |
2555 /* It's not the exception. */ | |
2556 #endif | |
2557 #ifdef AUTO_INC_DEC | |
2558 for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) | |
2559 if (REG_NOTE_KIND (link) == REG_INC | |
2560 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) | |
2561 || (i1 != 0 | |
2562 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) | |
2563 { | |
2564 undo_all (); | |
2565 return 0; | |
2566 } | |
2567 #endif | |
2568 | |
2569 /* See if the SETs in I1 or I2 need to be kept around in the merged | |
2570 instruction: whenever the value set there is still needed past I3. | |
2571 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. | |
2572 | |
2573 For the SET in I1, we have two cases: If I1 and I2 independently | |
2574 feed into I3, the set in I1 needs to be kept around if I1DEST dies | |
2575 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set | |
2576 in I1 needs to be kept around unless I1DEST dies or is set in either | |
2577 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions | |
2578 I1DEST. If so, we know I1 feeds into I2. */ | |
2579 | |
2580 added_sets_2 = ! dead_or_set_p (i3, i2dest); | |
2581 | |
2582 added_sets_1 | |
2583 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) | |
2584 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); | |
2585 | |
2586 /* If the set in I2 needs to be kept around, we must make a copy of | |
2587 PATTERN (I2), so that when we substitute I1SRC for I1DEST in | |
2588 PATTERN (I2), we are only substituting for the original I1DEST, not into | |
2589 an already-substituted copy. This also prevents making self-referential | |
2590 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to | |
2591 I2DEST. */ | |
2592 | |
2593 if (added_sets_2) | |
2594 { | |
2595 if (GET_CODE (PATTERN (i2)) == PARALLEL) | |
2596 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src)); | |
2597 else | |
2598 i2pat = copy_rtx (PATTERN (i2)); | |
2599 } | |
2600 | |
2601 if (added_sets_1) | |
2602 { | |
2603 if (GET_CODE (PATTERN (i1)) == PARALLEL) | |
2604 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src)); | |
2605 else | |
2606 i1pat = copy_rtx (PATTERN (i1)); | |
2607 } | |
2608 | |
2609 combine_merges++; | |
2610 | |
2611 /* Substitute in the latest insn for the regs set by the earlier ones. */ | |
2612 | |
2613 maxreg = max_reg_num (); | |
2614 | |
2615 subst_insn = i3; | |
2616 | |
2617 #ifndef HAVE_cc0 | |
2618 /* Many machines that don't use CC0 have insns that can both perform an | |
2619 arithmetic operation and set the condition code. These operations will | |
2620 be represented as a PARALLEL with the first element of the vector | |
2621 being a COMPARE of an arithmetic operation with the constant zero. | |
2622 The second element of the vector will set some pseudo to the result | |
2623 of the same arithmetic operation. If we simplify the COMPARE, we won't | |
2624 match such a pattern and so will generate an extra insn. Here we test | |
2625 for this case, where both the comparison and the operation result are | |
2626 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with | |
2627 I2SRC. Later we will make the PARALLEL that contains I2. */ | |
2628 | |
2629 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET | |
2630 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE | |
2631 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx | |
2632 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) | |
2633 { | |
2634 #ifdef SELECT_CC_MODE | |
2635 rtx *cc_use; | |
2636 enum machine_mode compare_mode; | |
2637 #endif | |
2638 | |
2639 newpat = PATTERN (i3); | |
2640 SUBST (XEXP (SET_SRC (newpat), 0), i2src); | |
2641 | |
2642 i2_is_used = 1; | |
2643 | |
2644 #ifdef SELECT_CC_MODE | |
2645 /* See if a COMPARE with the operand we substituted in should be done | |
2646 with the mode that is currently being used. If not, do the same | |
2647 processing we do in `subst' for a SET; namely, if the destination | |
2648 is used only once, try to replace it with a register of the proper | |
2649 mode and also replace the COMPARE. */ | |
2650 if (undobuf.other_insn == 0 | |
2651 && (cc_use = find_single_use (SET_DEST (newpat), i3, | |
2652 &undobuf.other_insn)) | |
2653 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), | |
2654 i2src, const0_rtx)) | |
2655 != GET_MODE (SET_DEST (newpat)))) | |
2656 { | |
2657 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2, | |
2658 compare_mode)) | |
2659 { | |
2660 unsigned int regno = REGNO (SET_DEST (newpat)); | |
2661 rtx new_dest; | |
2662 | |
2663 if (regno < FIRST_PSEUDO_REGISTER) | |
2664 new_dest = gen_rtx_REG (compare_mode, regno); | |
2665 else | |
2666 { | |
2667 SUBST_MODE (regno_reg_rtx[regno], compare_mode); | |
2668 new_dest = regno_reg_rtx[regno]; | |
2669 } | |
2670 | |
2671 SUBST (SET_DEST (newpat), new_dest); | |
2672 SUBST (XEXP (*cc_use, 0), new_dest); | |
2673 SUBST (SET_SRC (newpat), | |
2674 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx)); | |
2675 } | |
2676 else | |
2677 undobuf.other_insn = 0; | |
2678 } | |
2679 #endif | |
2680 } | |
2681 else | |
2682 #endif | |
2683 { | |
2684 /* It is possible that the source of I2 or I1 may be performing | |
2685 an unneeded operation, such as a ZERO_EXTEND of something | |
2686 that is known to have the high part zero. Handle that case | |
2687 by letting subst look at the innermost one of them. | |
2688 | |
2689 Another way to do this would be to have a function that tries | |
2690 to simplify a single insn instead of merging two or more | |
2691 insns. We don't do this because of the potential of infinite | |
2692 loops and because of the potential extra memory required. | |
2693 However, doing it the way we are is a bit of a kludge and | |
2694 doesn't catch all cases. | |
2695 | |
2696 But only do this if -fexpensive-optimizations since it slows | |
2697 things down and doesn't usually win. | |
2698 | |
2699 This is not done in the COMPARE case above because the | |
2700 unmodified I2PAT is used in the PARALLEL and so a pattern | |
2701 with a modified I2SRC would not match. */ | |
2702 | |
2703 if (flag_expensive_optimizations) | |
2704 { | |
2705 /* Pass pc_rtx so no substitutions are done, just | |
2706 simplifications. */ | |
2707 if (i1) | |
2708 { | |
2709 subst_low_luid = DF_INSN_LUID (i1); | |
2710 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); | |
2711 } | |
2712 else | |
2713 { | |
2714 subst_low_luid = DF_INSN_LUID (i2); | |
2715 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); | |
2716 } | |
2717 } | |
2718 | |
2719 n_occurrences = 0; /* `subst' counts here */ | |
2720 | |
2721 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we | |
2722 need to make a unique copy of I2SRC each time we substitute it | |
2723 to avoid self-referential rtl. */ | |
2724 | |
2725 subst_low_luid = DF_INSN_LUID (i2); | |
2726 newpat = subst (PATTERN (i3), i2dest, i2src, 0, | |
2727 ! i1_feeds_i3 && i1dest_in_i1src); | |
2728 substed_i2 = 1; | |
2729 | |
2730 /* Record whether i2's body now appears within i3's body. */ | |
2731 i2_is_used = n_occurrences; | |
2732 } | |
2733 | |
2734 /* If we already got a failure, don't try to do more. Otherwise, | |
2735 try to substitute in I1 if we have it. */ | |
2736 | |
2737 if (i1 && GET_CODE (newpat) != CLOBBER) | |
2738 { | |
2739 /* Check that an autoincrement side-effect on I1 has not been lost. | |
2740 This happens if I1DEST is mentioned in I2 and dies there, and | |
2741 has disappeared from the new pattern. */ | |
2742 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 | |
2743 && !i1_feeds_i3 | |
2744 && dead_or_set_p (i2, i1dest) | |
2745 && !reg_overlap_mentioned_p (i1dest, newpat)) | |
2746 /* Before we can do this substitution, we must redo the test done | |
2747 above (see detailed comments there) that ensures that I1DEST | |
2748 isn't mentioned in any SETs in NEWPAT that are field assignments. */ | |
2749 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0)) | |
2750 { | |
2751 undo_all (); | |
2752 return 0; | |
2753 } | |
2754 | |
2755 n_occurrences = 0; | |
2756 subst_low_luid = DF_INSN_LUID (i1); | |
2757 newpat = subst (newpat, i1dest, i1src, 0, 0); | |
2758 substed_i1 = 1; | |
2759 } | |
2760 | |
2761 /* Fail if an autoincrement side-effect has been duplicated. Be careful | |
2762 to count all the ways that I2SRC and I1SRC can be used. */ | |
2763 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 | |
2764 && i2_is_used + added_sets_2 > 1) | |
2765 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 | |
2766 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) | |
2767 > 1)) | |
2768 /* Fail if we tried to make a new register. */ | |
2769 || max_reg_num () != maxreg | |
2770 /* Fail if we couldn't do something and have a CLOBBER. */ | |
2771 || GET_CODE (newpat) == CLOBBER | |
2772 /* Fail if this new pattern is a MULT and we didn't have one before | |
2773 at the outer level. */ | |
2774 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT | |
2775 && ! have_mult)) | |
2776 { | |
2777 undo_all (); | |
2778 return 0; | |
2779 } | |
2780 | |
2781 /* If the actions of the earlier insns must be kept | |
2782 in addition to substituting them into the latest one, | |
2783 we must make a new PARALLEL for the latest insn | |
2784 to hold additional the SETs. */ | |
2785 | |
2786 if (added_sets_1 || added_sets_2) | |
2787 { | |
2788 combine_extras++; | |
2789 | |
2790 if (GET_CODE (newpat) == PARALLEL) | |
2791 { | |
2792 rtvec old = XVEC (newpat, 0); | |
2793 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; | |
2794 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); | |
2795 memcpy (XVEC (newpat, 0)->elem, &old->elem[0], | |
2796 sizeof (old->elem[0]) * old->num_elem); | |
2797 } | |
2798 else | |
2799 { | |
2800 rtx old = newpat; | |
2801 total_sets = 1 + added_sets_1 + added_sets_2; | |
2802 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); | |
2803 XVECEXP (newpat, 0, 0) = old; | |
2804 } | |
2805 | |
2806 if (added_sets_1) | |
2807 XVECEXP (newpat, 0, --total_sets) = i1pat; | |
2808 | |
2809 if (added_sets_2) | |
2810 { | |
2811 /* If there is no I1, use I2's body as is. We used to also not do | |
2812 the subst call below if I2 was substituted into I3, | |
2813 but that could lose a simplification. */ | |
2814 if (i1 == 0) | |
2815 XVECEXP (newpat, 0, --total_sets) = i2pat; | |
2816 else | |
2817 /* See comment where i2pat is assigned. */ | |
2818 XVECEXP (newpat, 0, --total_sets) | |
2819 = subst (i2pat, i1dest, i1src, 0, 0); | |
2820 } | |
2821 } | |
2822 | |
2823 /* We come here when we are replacing a destination in I2 with the | |
2824 destination of I3. */ | |
2825 validate_replacement: | |
2826 | |
2827 /* Note which hard regs this insn has as inputs. */ | |
2828 mark_used_regs_combine (newpat); | |
2829 | |
2830 /* If recog_for_combine fails, it strips existing clobbers. If we'll | |
2831 consider splitting this pattern, we might need these clobbers. */ | |
2832 if (i1 && GET_CODE (newpat) == PARALLEL | |
2833 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER) | |
2834 { | |
2835 int len = XVECLEN (newpat, 0); | |
2836 | |
2837 newpat_vec_with_clobbers = rtvec_alloc (len); | |
2838 for (i = 0; i < len; i++) | |
2839 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i); | |
2840 } | |
2841 | |
2842 /* Is the result of combination a valid instruction? */ | |
2843 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
2844 | |
2845 /* If the result isn't valid, see if it is a PARALLEL of two SETs where | |
2846 the second SET's destination is a register that is unused and isn't | |
2847 marked as an instruction that might trap in an EH region. In that case, | |
2848 we just need the first SET. This can occur when simplifying a divmod | |
2849 insn. We *must* test for this case here because the code below that | |
2850 splits two independent SETs doesn't handle this case correctly when it | |
2851 updates the register status. | |
2852 | |
2853 It's pointless doing this if we originally had two sets, one from | |
2854 i3, and one from i2. Combining then splitting the parallel results | |
2855 in the original i2 again plus an invalid insn (which we delete). | |
2856 The net effect is only to move instructions around, which makes | |
2857 debug info less accurate. | |
2858 | |
2859 Also check the case where the first SET's destination is unused. | |
2860 That would not cause incorrect code, but does cause an unneeded | |
2861 insn to remain. */ | |
2862 | |
2863 if (insn_code_number < 0 | |
2864 && !(added_sets_2 && i1 == 0) | |
2865 && GET_CODE (newpat) == PARALLEL | |
2866 && XVECLEN (newpat, 0) == 2 | |
2867 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
2868 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
2869 && asm_noperands (newpat) < 0) | |
2870 { | |
2871 rtx set0 = XVECEXP (newpat, 0, 0); | |
2872 rtx set1 = XVECEXP (newpat, 0, 1); | |
2873 rtx note; | |
2874 | |
2875 if (((REG_P (SET_DEST (set1)) | |
2876 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1))) | |
2877 || (GET_CODE (SET_DEST (set1)) == SUBREG | |
2878 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1))))) | |
2879 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX)) | |
2880 || INTVAL (XEXP (note, 0)) <= 0) | |
2881 && ! side_effects_p (SET_SRC (set1))) | |
2882 { | |
2883 newpat = set0; | |
2884 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
2885 } | |
2886 | |
2887 else if (((REG_P (SET_DEST (set0)) | |
2888 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0))) | |
2889 || (GET_CODE (SET_DEST (set0)) == SUBREG | |
2890 && find_reg_note (i3, REG_UNUSED, | |
2891 SUBREG_REG (SET_DEST (set0))))) | |
2892 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX)) | |
2893 || INTVAL (XEXP (note, 0)) <= 0) | |
2894 && ! side_effects_p (SET_SRC (set0))) | |
2895 { | |
2896 newpat = set1; | |
2897 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
2898 | |
2899 if (insn_code_number >= 0) | |
2900 changed_i3_dest = 1; | |
2901 } | |
2902 } | |
2903 | |
2904 /* If we were combining three insns and the result is a simple SET | |
2905 with no ASM_OPERANDS that wasn't recognized, try to split it into two | |
2906 insns. There are two ways to do this. It can be split using a | |
2907 machine-specific method (like when you have an addition of a large | |
2908 constant) or by combine in the function find_split_point. */ | |
2909 | |
2910 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET | |
2911 && asm_noperands (newpat) < 0) | |
2912 { | |
2913 rtx parallel, m_split, *split; | |
2914 | |
2915 /* See if the MD file can split NEWPAT. If it can't, see if letting it | |
2916 use I2DEST as a scratch register will help. In the latter case, | |
2917 convert I2DEST to the mode of the source of NEWPAT if we can. */ | |
2918 | |
2919 m_split = combine_split_insns (newpat, i3); | |
2920 | |
2921 /* We can only use I2DEST as a scratch reg if it doesn't overlap any | |
2922 inputs of NEWPAT. */ | |
2923 | |
2924 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be | |
2925 possible to try that as a scratch reg. This would require adding | |
2926 more code to make it work though. */ | |
2927 | |
2928 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat)) | |
2929 { | |
2930 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat)); | |
2931 | |
2932 /* First try to split using the original register as a | |
2933 scratch register. */ | |
2934 parallel = gen_rtx_PARALLEL (VOIDmode, | |
2935 gen_rtvec (2, newpat, | |
2936 gen_rtx_CLOBBER (VOIDmode, | |
2937 i2dest))); | |
2938 m_split = combine_split_insns (parallel, i3); | |
2939 | |
2940 /* If that didn't work, try changing the mode of I2DEST if | |
2941 we can. */ | |
2942 if (m_split == 0 | |
2943 && new_mode != GET_MODE (i2dest) | |
2944 && new_mode != VOIDmode | |
2945 && can_change_dest_mode (i2dest, added_sets_2, new_mode)) | |
2946 { | |
2947 enum machine_mode old_mode = GET_MODE (i2dest); | |
2948 rtx ni2dest; | |
2949 | |
2950 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) | |
2951 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest)); | |
2952 else | |
2953 { | |
2954 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode); | |
2955 ni2dest = regno_reg_rtx[REGNO (i2dest)]; | |
2956 } | |
2957 | |
2958 parallel = (gen_rtx_PARALLEL | |
2959 (VOIDmode, | |
2960 gen_rtvec (2, newpat, | |
2961 gen_rtx_CLOBBER (VOIDmode, | |
2962 ni2dest)))); | |
2963 m_split = combine_split_insns (parallel, i3); | |
2964 | |
2965 if (m_split == 0 | |
2966 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) | |
2967 { | |
2968 struct undo *buf; | |
2969 | |
2970 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode); | |
2971 buf = undobuf.undos; | |
2972 undobuf.undos = buf->next; | |
2973 buf->next = undobuf.frees; | |
2974 undobuf.frees = buf; | |
2975 } | |
2976 } | |
2977 } | |
2978 | |
2979 /* If recog_for_combine has discarded clobbers, try to use them | |
2980 again for the split. */ | |
2981 if (m_split == 0 && newpat_vec_with_clobbers) | |
2982 { | |
2983 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers); | |
2984 m_split = combine_split_insns (parallel, i3); | |
2985 } | |
2986 | |
2987 if (m_split && NEXT_INSN (m_split) == NULL_RTX) | |
2988 { | |
2989 m_split = PATTERN (m_split); | |
2990 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes); | |
2991 if (insn_code_number >= 0) | |
2992 newpat = m_split; | |
2993 } | |
2994 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX | |
2995 && (next_real_insn (i2) == i3 | |
2996 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2)))) | |
2997 { | |
2998 rtx i2set, i3set; | |
2999 rtx newi3pat = PATTERN (NEXT_INSN (m_split)); | |
3000 newi2pat = PATTERN (m_split); | |
3001 | |
3002 i3set = single_set (NEXT_INSN (m_split)); | |
3003 i2set = single_set (m_split); | |
3004 | |
3005 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); | |
3006 | |
3007 /* If I2 or I3 has multiple SETs, we won't know how to track | |
3008 register status, so don't use these insns. If I2's destination | |
3009 is used between I2 and I3, we also can't use these insns. */ | |
3010 | |
3011 if (i2_code_number >= 0 && i2set && i3set | |
3012 && (next_real_insn (i2) == i3 | |
3013 || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) | |
3014 insn_code_number = recog_for_combine (&newi3pat, i3, | |
3015 &new_i3_notes); | |
3016 if (insn_code_number >= 0) | |
3017 newpat = newi3pat; | |
3018 | |
3019 /* It is possible that both insns now set the destination of I3. | |
3020 If so, we must show an extra use of it. */ | |
3021 | |
3022 if (insn_code_number >= 0) | |
3023 { | |
3024 rtx new_i3_dest = SET_DEST (i3set); | |
3025 rtx new_i2_dest = SET_DEST (i2set); | |
3026 | |
3027 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT | |
3028 || GET_CODE (new_i3_dest) == STRICT_LOW_PART | |
3029 || GET_CODE (new_i3_dest) == SUBREG) | |
3030 new_i3_dest = XEXP (new_i3_dest, 0); | |
3031 | |
3032 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT | |
3033 || GET_CODE (new_i2_dest) == STRICT_LOW_PART | |
3034 || GET_CODE (new_i2_dest) == SUBREG) | |
3035 new_i2_dest = XEXP (new_i2_dest, 0); | |
3036 | |
3037 if (REG_P (new_i3_dest) | |
3038 && REG_P (new_i2_dest) | |
3039 && REGNO (new_i3_dest) == REGNO (new_i2_dest)) | |
3040 INC_REG_N_SETS (REGNO (new_i2_dest), 1); | |
3041 } | |
3042 } | |
3043 | |
3044 /* If we can split it and use I2DEST, go ahead and see if that | |
3045 helps things be recognized. Verify that none of the registers | |
3046 are set between I2 and I3. */ | |
3047 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0 | |
3048 #ifdef HAVE_cc0 | |
3049 && REG_P (i2dest) | |
3050 #endif | |
3051 /* We need I2DEST in the proper mode. If it is a hard register | |
3052 or the only use of a pseudo, we can change its mode. | |
3053 Make sure we don't change a hard register to have a mode that | |
3054 isn't valid for it, or change the number of registers. */ | |
3055 && (GET_MODE (*split) == GET_MODE (i2dest) | |
3056 || GET_MODE (*split) == VOIDmode | |
3057 || can_change_dest_mode (i2dest, added_sets_2, | |
3058 GET_MODE (*split))) | |
3059 && (next_real_insn (i2) == i3 | |
3060 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2))) | |
3061 /* We can't overwrite I2DEST if its value is still used by | |
3062 NEWPAT. */ | |
3063 && ! reg_referenced_p (i2dest, newpat)) | |
3064 { | |
3065 rtx newdest = i2dest; | |
3066 enum rtx_code split_code = GET_CODE (*split); | |
3067 enum machine_mode split_mode = GET_MODE (*split); | |
3068 bool subst_done = false; | |
3069 newi2pat = NULL_RTX; | |
3070 | |
3071 /* Get NEWDEST as a register in the proper mode. We have already | |
3072 validated that we can do this. */ | |
3073 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) | |
3074 { | |
3075 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) | |
3076 newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); | |
3077 else | |
3078 { | |
3079 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode); | |
3080 newdest = regno_reg_rtx[REGNO (i2dest)]; | |
3081 } | |
3082 } | |
3083 | |
3084 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to | |
3085 an ASHIFT. This can occur if it was inside a PLUS and hence | |
3086 appeared to be a memory address. This is a kludge. */ | |
3087 if (split_code == MULT | |
3088 && GET_CODE (XEXP (*split, 1)) == CONST_INT | |
3089 && INTVAL (XEXP (*split, 1)) > 0 | |
3090 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) | |
3091 { | |
3092 SUBST (*split, gen_rtx_ASHIFT (split_mode, | |
3093 XEXP (*split, 0), GEN_INT (i))); | |
3094 /* Update split_code because we may not have a multiply | |
3095 anymore. */ | |
3096 split_code = GET_CODE (*split); | |
3097 } | |
3098 | |
3099 #ifdef INSN_SCHEDULING | |
3100 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should | |
3101 be written as a ZERO_EXTEND. */ | |
3102 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split))) | |
3103 { | |
3104 #ifdef LOAD_EXTEND_OP | |
3105 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's | |
3106 what it really is. */ | |
3107 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split))) | |
3108 == SIGN_EXTEND) | |
3109 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode, | |
3110 SUBREG_REG (*split))); | |
3111 else | |
3112 #endif | |
3113 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, | |
3114 SUBREG_REG (*split))); | |
3115 } | |
3116 #endif | |
3117 | |
3118 /* Attempt to split binary operators using arithmetic identities. */ | |
3119 if (BINARY_P (SET_SRC (newpat)) | |
3120 && split_mode == GET_MODE (SET_SRC (newpat)) | |
3121 && ! side_effects_p (SET_SRC (newpat))) | |
3122 { | |
3123 rtx setsrc = SET_SRC (newpat); | |
3124 enum machine_mode mode = GET_MODE (setsrc); | |
3125 enum rtx_code code = GET_CODE (setsrc); | |
3126 rtx src_op0 = XEXP (setsrc, 0); | |
3127 rtx src_op1 = XEXP (setsrc, 1); | |
3128 | |
3129 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */ | |
3130 if (rtx_equal_p (src_op0, src_op1)) | |
3131 { | |
3132 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0); | |
3133 SUBST (XEXP (setsrc, 0), newdest); | |
3134 SUBST (XEXP (setsrc, 1), newdest); | |
3135 subst_done = true; | |
3136 } | |
3137 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */ | |
3138 else if ((code == PLUS || code == MULT) | |
3139 && GET_CODE (src_op0) == code | |
3140 && GET_CODE (XEXP (src_op0, 0)) == code | |
3141 && (INTEGRAL_MODE_P (mode) | |
3142 || (FLOAT_MODE_P (mode) | |
3143 && flag_unsafe_math_optimizations))) | |
3144 { | |
3145 rtx p = XEXP (XEXP (src_op0, 0), 0); | |
3146 rtx q = XEXP (XEXP (src_op0, 0), 1); | |
3147 rtx r = XEXP (src_op0, 1); | |
3148 rtx s = src_op1; | |
3149 | |
3150 /* Split both "((X op Y) op X) op Y" and | |
3151 "((X op Y) op Y) op X" as "T op T" where T is | |
3152 "X op Y". */ | |
3153 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s)) | |
3154 || (rtx_equal_p (p,s) && rtx_equal_p (q,r))) | |
3155 { | |
3156 newi2pat = gen_rtx_SET (VOIDmode, newdest, | |
3157 XEXP (src_op0, 0)); | |
3158 SUBST (XEXP (setsrc, 0), newdest); | |
3159 SUBST (XEXP (setsrc, 1), newdest); | |
3160 subst_done = true; | |
3161 } | |
3162 /* Split "((X op X) op Y) op Y)" as "T op T" where | |
3163 T is "X op Y". */ | |
3164 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s)) | |
3165 { | |
3166 rtx tmp = simplify_gen_binary (code, mode, p, r); | |
3167 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp); | |
3168 SUBST (XEXP (setsrc, 0), newdest); | |
3169 SUBST (XEXP (setsrc, 1), newdest); | |
3170 subst_done = true; | |
3171 } | |
3172 } | |
3173 } | |
3174 | |
3175 if (!subst_done) | |
3176 { | |
3177 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split); | |
3178 SUBST (*split, newdest); | |
3179 } | |
3180 | |
3181 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); | |
3182 | |
3183 /* recog_for_combine might have added CLOBBERs to newi2pat. | |
3184 Make sure NEWPAT does not depend on the clobbered regs. */ | |
3185 if (GET_CODE (newi2pat) == PARALLEL) | |
3186 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) | |
3187 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) | |
3188 { | |
3189 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); | |
3190 if (reg_overlap_mentioned_p (reg, newpat)) | |
3191 { | |
3192 undo_all (); | |
3193 return 0; | |
3194 } | |
3195 } | |
3196 | |
3197 /* If the split point was a MULT and we didn't have one before, | |
3198 don't use one now. */ | |
3199 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) | |
3200 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
3201 } | |
3202 } | |
3203 | |
3204 /* Check for a case where we loaded from memory in a narrow mode and | |
3205 then sign extended it, but we need both registers. In that case, | |
3206 we have a PARALLEL with both loads from the same memory location. | |
3207 We can split this into a load from memory followed by a register-register | |
3208 copy. This saves at least one insn, more if register allocation can | |
3209 eliminate the copy. | |
3210 | |
3211 We cannot do this if the destination of the first assignment is a | |
3212 condition code register or cc0. We eliminate this case by making sure | |
3213 the SET_DEST and SET_SRC have the same mode. | |
3214 | |
3215 We cannot do this if the destination of the second assignment is | |
3216 a register that we have already assumed is zero-extended. Similarly | |
3217 for a SUBREG of such a register. */ | |
3218 | |
3219 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
3220 && GET_CODE (newpat) == PARALLEL | |
3221 && XVECLEN (newpat, 0) == 2 | |
3222 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
3223 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND | |
3224 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) | |
3225 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) | |
3226 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
3227 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
3228 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) | |
3229 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
3230 DF_INSN_LUID (i2)) | |
3231 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT | |
3232 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
3233 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)), | |
3234 (REG_P (temp) | |
3235 && VEC_index (reg_stat_type, reg_stat, | |
3236 REGNO (temp))->nonzero_bits != 0 | |
3237 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD | |
3238 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT | |
3239 && (VEC_index (reg_stat_type, reg_stat, | |
3240 REGNO (temp))->nonzero_bits | |
3241 != GET_MODE_MASK (word_mode)))) | |
3242 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG | |
3243 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), | |
3244 (REG_P (temp) | |
3245 && VEC_index (reg_stat_type, reg_stat, | |
3246 REGNO (temp))->nonzero_bits != 0 | |
3247 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD | |
3248 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT | |
3249 && (VEC_index (reg_stat_type, reg_stat, | |
3250 REGNO (temp))->nonzero_bits | |
3251 != GET_MODE_MASK (word_mode))))) | |
3252 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), | |
3253 SET_SRC (XVECEXP (newpat, 0, 1))) | |
3254 && ! find_reg_note (i3, REG_UNUSED, | |
3255 SET_DEST (XVECEXP (newpat, 0, 0)))) | |
3256 { | |
3257 rtx ni2dest; | |
3258 | |
3259 newi2pat = XVECEXP (newpat, 0, 0); | |
3260 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); | |
3261 newpat = XVECEXP (newpat, 0, 1); | |
3262 SUBST (SET_SRC (newpat), | |
3263 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest)); | |
3264 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); | |
3265 | |
3266 if (i2_code_number >= 0) | |
3267 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
3268 | |
3269 if (insn_code_number >= 0) | |
3270 swap_i2i3 = 1; | |
3271 } | |
3272 | |
3273 /* Similarly, check for a case where we have a PARALLEL of two independent | |
3274 SETs but we started with three insns. In this case, we can do the sets | |
3275 as two separate insns. This case occurs when some SET allows two | |
3276 other insns to combine, but the destination of that SET is still live. */ | |
3277 | |
3278 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
3279 && GET_CODE (newpat) == PARALLEL | |
3280 && XVECLEN (newpat, 0) == 2 | |
3281 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
3282 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT | |
3283 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART | |
3284 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
3285 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT | |
3286 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
3287 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
3288 DF_INSN_LUID (i2)) | |
3289 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), | |
3290 XVECEXP (newpat, 0, 0)) | |
3291 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), | |
3292 XVECEXP (newpat, 0, 1)) | |
3293 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) | |
3294 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))) | |
3295 #ifdef HAVE_cc0 | |
3296 /* We cannot split the parallel into two sets if both sets | |
3297 reference cc0. */ | |
3298 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)) | |
3299 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))) | |
3300 #endif | |
3301 ) | |
3302 { | |
3303 /* Normally, it doesn't matter which of the two is done first, | |
3304 but it does if one references cc0. In that case, it has to | |
3305 be first. */ | |
3306 #ifdef HAVE_cc0 | |
3307 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))) | |
3308 { | |
3309 newi2pat = XVECEXP (newpat, 0, 0); | |
3310 newpat = XVECEXP (newpat, 0, 1); | |
3311 } | |
3312 else | |
3313 #endif | |
3314 { | |
3315 newi2pat = XVECEXP (newpat, 0, 1); | |
3316 newpat = XVECEXP (newpat, 0, 0); | |
3317 } | |
3318 | |
3319 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); | |
3320 | |
3321 if (i2_code_number >= 0) | |
3322 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
3323 } | |
3324 | |
3325 /* If it still isn't recognized, fail and change things back the way they | |
3326 were. */ | |
3327 if ((insn_code_number < 0 | |
3328 /* Is the result a reasonable ASM_OPERANDS? */ | |
3329 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) | |
3330 { | |
3331 undo_all (); | |
3332 return 0; | |
3333 } | |
3334 | |
3335 /* If we had to change another insn, make sure it is valid also. */ | |
3336 if (undobuf.other_insn) | |
3337 { | |
3338 CLEAR_HARD_REG_SET (newpat_used_regs); | |
3339 | |
3340 other_pat = PATTERN (undobuf.other_insn); | |
3341 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, | |
3342 &new_other_notes); | |
3343 | |
3344 if (other_code_number < 0 && ! check_asm_operands (other_pat)) | |
3345 { | |
3346 undo_all (); | |
3347 return 0; | |
3348 } | |
3349 } | |
3350 | |
3351 #ifdef HAVE_cc0 | |
3352 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether | |
3353 they are adjacent to each other or not. */ | |
3354 { | |
3355 rtx p = prev_nonnote_insn (i3); | |
3356 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat | |
3357 && sets_cc0_p (newi2pat)) | |
3358 { | |
3359 undo_all (); | |
3360 return 0; | |
3361 } | |
3362 } | |
3363 #endif | |
3364 | |
3365 /* Only allow this combination if insn_rtx_costs reports that the | |
3366 replacement instructions are cheaper than the originals. */ | |
3367 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat)) | |
3368 { | |
3369 undo_all (); | |
3370 return 0; | |
3371 } | |
3372 | |
3373 /* If we will be able to accept this, we have made a | |
3374 change to the destination of I3. This requires us to | |
3375 do a few adjustments. */ | |
3376 | |
3377 if (changed_i3_dest) | |
3378 { | |
3379 PATTERN (i3) = newpat; | |
3380 adjust_for_new_dest (i3); | |
3381 } | |
3382 | |
3383 /* We now know that we can do this combination. Merge the insns and | |
3384 update the status of registers and LOG_LINKS. */ | |
3385 | |
3386 if (undobuf.other_insn) | |
3387 { | |
3388 rtx note, next; | |
3389 | |
3390 PATTERN (undobuf.other_insn) = other_pat; | |
3391 | |
3392 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they | |
3393 are still valid. Then add any non-duplicate notes added by | |
3394 recog_for_combine. */ | |
3395 for (note = REG_NOTES (undobuf.other_insn); note; note = next) | |
3396 { | |
3397 next = XEXP (note, 1); | |
3398 | |
3399 if (REG_NOTE_KIND (note) == REG_UNUSED | |
3400 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) | |
3401 remove_note (undobuf.other_insn, note); | |
3402 } | |
3403 | |
3404 distribute_notes (new_other_notes, undobuf.other_insn, | |
3405 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX); | |
3406 } | |
3407 | |
3408 if (swap_i2i3) | |
3409 { | |
3410 rtx insn; | |
3411 rtx link; | |
3412 rtx ni2dest; | |
3413 | |
3414 /* I3 now uses what used to be its destination and which is now | |
3415 I2's destination. This requires us to do a few adjustments. */ | |
3416 PATTERN (i3) = newpat; | |
3417 adjust_for_new_dest (i3); | |
3418 | |
3419 /* We need a LOG_LINK from I3 to I2. But we used to have one, | |
3420 so we still will. | |
3421 | |
3422 However, some later insn might be using I2's dest and have | |
3423 a LOG_LINK pointing at I3. We must remove this link. | |
3424 The simplest way to remove the link is to point it at I1, | |
3425 which we know will be a NOTE. */ | |
3426 | |
3427 /* newi2pat is usually a SET here; however, recog_for_combine might | |
3428 have added some clobbers. */ | |
3429 if (GET_CODE (newi2pat) == PARALLEL) | |
3430 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0)); | |
3431 else | |
3432 ni2dest = SET_DEST (newi2pat); | |
3433 | |
3434 for (insn = NEXT_INSN (i3); | |
3435 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR | |
3436 || insn != BB_HEAD (this_basic_block->next_bb)); | |
3437 insn = NEXT_INSN (insn)) | |
3438 { | |
3439 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn))) | |
3440 { | |
3441 for (link = LOG_LINKS (insn); link; | |
3442 link = XEXP (link, 1)) | |
3443 if (XEXP (link, 0) == i3) | |
3444 XEXP (link, 0) = i1; | |
3445 | |
3446 break; | |
3447 } | |
3448 } | |
3449 } | |
3450 | |
3451 { | |
3452 rtx i3notes, i2notes, i1notes = 0; | |
3453 rtx i3links, i2links, i1links = 0; | |
3454 rtx midnotes = 0; | |
3455 unsigned int regno; | |
3456 /* Compute which registers we expect to eliminate. newi2pat may be setting | |
3457 either i3dest or i2dest, so we must check it. Also, i1dest may be the | |
3458 same as i3dest, in which case newi2pat may be setting i1dest. */ | |
3459 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) | |
3460 || i2dest_in_i2src || i2dest_in_i1src | |
3461 || !i2dest_killed | |
3462 ? 0 : i2dest); | |
3463 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src | |
3464 || (newi2pat && reg_set_p (i1dest, newi2pat)) | |
3465 || !i1dest_killed | |
3466 ? 0 : i1dest); | |
3467 | |
3468 /* Get the old REG_NOTES and LOG_LINKS from all our insns and | |
3469 clear them. */ | |
3470 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); | |
3471 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); | |
3472 if (i1) | |
3473 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); | |
3474 | |
3475 /* Ensure that we do not have something that should not be shared but | |
3476 occurs multiple times in the new insns. Check this by first | |
3477 resetting all the `used' flags and then copying anything is shared. */ | |
3478 | |
3479 reset_used_flags (i3notes); | |
3480 reset_used_flags (i2notes); | |
3481 reset_used_flags (i1notes); | |
3482 reset_used_flags (newpat); | |
3483 reset_used_flags (newi2pat); | |
3484 if (undobuf.other_insn) | |
3485 reset_used_flags (PATTERN (undobuf.other_insn)); | |
3486 | |
3487 i3notes = copy_rtx_if_shared (i3notes); | |
3488 i2notes = copy_rtx_if_shared (i2notes); | |
3489 i1notes = copy_rtx_if_shared (i1notes); | |
3490 newpat = copy_rtx_if_shared (newpat); | |
3491 newi2pat = copy_rtx_if_shared (newi2pat); | |
3492 if (undobuf.other_insn) | |
3493 reset_used_flags (PATTERN (undobuf.other_insn)); | |
3494 | |
3495 INSN_CODE (i3) = insn_code_number; | |
3496 PATTERN (i3) = newpat; | |
3497 | |
3498 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3)) | |
3499 { | |
3500 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3); | |
3501 | |
3502 reset_used_flags (call_usage); | |
3503 call_usage = copy_rtx (call_usage); | |
3504 | |
3505 if (substed_i2) | |
3506 replace_rtx (call_usage, i2dest, i2src); | |
3507 | |
3508 if (substed_i1) | |
3509 replace_rtx (call_usage, i1dest, i1src); | |
3510 | |
3511 CALL_INSN_FUNCTION_USAGE (i3) = call_usage; | |
3512 } | |
3513 | |
3514 if (undobuf.other_insn) | |
3515 INSN_CODE (undobuf.other_insn) = other_code_number; | |
3516 | |
3517 /* We had one special case above where I2 had more than one set and | |
3518 we replaced a destination of one of those sets with the destination | |
3519 of I3. In that case, we have to update LOG_LINKS of insns later | |
3520 in this basic block. Note that this (expensive) case is rare. | |
3521 | |
3522 Also, in this case, we must pretend that all REG_NOTEs for I2 | |
3523 actually came from I3, so that REG_UNUSED notes from I2 will be | |
3524 properly handled. */ | |
3525 | |
3526 if (i3_subst_into_i2) | |
3527 { | |
3528 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) | |
3529 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET | |
3530 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER) | |
3531 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) | |
3532 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest | |
3533 && ! find_reg_note (i2, REG_UNUSED, | |
3534 SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) | |
3535 for (temp = NEXT_INSN (i2); | |
3536 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR | |
3537 || BB_HEAD (this_basic_block) != temp); | |
3538 temp = NEXT_INSN (temp)) | |
3539 if (temp != i3 && INSN_P (temp)) | |
3540 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1)) | |
3541 if (XEXP (link, 0) == i2) | |
3542 XEXP (link, 0) = i3; | |
3543 | |
3544 if (i3notes) | |
3545 { | |
3546 rtx link = i3notes; | |
3547 while (XEXP (link, 1)) | |
3548 link = XEXP (link, 1); | |
3549 XEXP (link, 1) = i2notes; | |
3550 } | |
3551 else | |
3552 i3notes = i2notes; | |
3553 i2notes = 0; | |
3554 } | |
3555 | |
3556 LOG_LINKS (i3) = 0; | |
3557 REG_NOTES (i3) = 0; | |
3558 LOG_LINKS (i2) = 0; | |
3559 REG_NOTES (i2) = 0; | |
3560 | |
3561 if (newi2pat) | |
3562 { | |
3563 INSN_CODE (i2) = i2_code_number; | |
3564 PATTERN (i2) = newi2pat; | |
3565 } | |
3566 else | |
3567 SET_INSN_DELETED (i2); | |
3568 | |
3569 if (i1) | |
3570 { | |
3571 LOG_LINKS (i1) = 0; | |
3572 REG_NOTES (i1) = 0; | |
3573 SET_INSN_DELETED (i1); | |
3574 } | |
3575 | |
3576 /* Get death notes for everything that is now used in either I3 or | |
3577 I2 and used to die in a previous insn. If we built two new | |
3578 patterns, move from I1 to I2 then I2 to I3 so that we get the | |
3579 proper movement on registers that I2 modifies. */ | |
3580 | |
3581 if (newi2pat) | |
3582 { | |
3583 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes); | |
3584 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes); | |
3585 } | |
3586 else | |
3587 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2), | |
3588 i3, &midnotes); | |
3589 | |
3590 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ | |
3591 if (i3notes) | |
3592 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX, | |
3593 elim_i2, elim_i1); | |
3594 if (i2notes) | |
3595 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX, | |
3596 elim_i2, elim_i1); | |
3597 if (i1notes) | |
3598 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX, | |
3599 elim_i2, elim_i1); | |
3600 if (midnotes) | |
3601 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, | |
3602 elim_i2, elim_i1); | |
3603 | |
3604 /* Distribute any notes added to I2 or I3 by recog_for_combine. We | |
3605 know these are REG_UNUSED and want them to go to the desired insn, | |
3606 so we always pass it as i3. */ | |
3607 | |
3608 if (newi2pat && new_i2_notes) | |
3609 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX); | |
3610 | |
3611 if (new_i3_notes) | |
3612 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX); | |
3613 | |
3614 /* If I3DEST was used in I3SRC, it really died in I3. We may need to | |
3615 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets | |
3616 I3DEST, the death must be somewhere before I2, not I3. If we passed I3 | |
3617 in that case, it might delete I2. Similarly for I2 and I1. | |
3618 Show an additional death due to the REG_DEAD note we make here. If | |
3619 we discard it in distribute_notes, we will decrement it again. */ | |
3620 | |
3621 if (i3dest_killed) | |
3622 { | |
3623 if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) | |
3624 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, | |
3625 NULL_RTX), | |
3626 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1); | |
3627 else | |
3628 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, | |
3629 NULL_RTX), | |
3630 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, | |
3631 elim_i2, elim_i1); | |
3632 } | |
3633 | |
3634 if (i2dest_in_i2src) | |
3635 { | |
3636 if (newi2pat && reg_set_p (i2dest, newi2pat)) | |
3637 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), | |
3638 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); | |
3639 else | |
3640 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), | |
3641 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, | |
3642 NULL_RTX, NULL_RTX); | |
3643 } | |
3644 | |
3645 if (i1dest_in_i1src) | |
3646 { | |
3647 if (newi2pat && reg_set_p (i1dest, newi2pat)) | |
3648 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), | |
3649 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); | |
3650 else | |
3651 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), | |
3652 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, | |
3653 NULL_RTX, NULL_RTX); | |
3654 } | |
3655 | |
3656 distribute_links (i3links); | |
3657 distribute_links (i2links); | |
3658 distribute_links (i1links); | |
3659 | |
3660 if (REG_P (i2dest)) | |
3661 { | |
3662 rtx link; | |
3663 rtx i2_insn = 0, i2_val = 0, set; | |
3664 | |
3665 /* The insn that used to set this register doesn't exist, and | |
3666 this life of the register may not exist either. See if one of | |
3667 I3's links points to an insn that sets I2DEST. If it does, | |
3668 that is now the last known value for I2DEST. If we don't update | |
3669 this and I2 set the register to a value that depended on its old | |
3670 contents, we will get confused. If this insn is used, thing | |
3671 will be set correctly in combine_instructions. */ | |
3672 | |
3673 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) | |
3674 if ((set = single_set (XEXP (link, 0))) != 0 | |
3675 && rtx_equal_p (i2dest, SET_DEST (set))) | |
3676 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set); | |
3677 | |
3678 record_value_for_reg (i2dest, i2_insn, i2_val); | |
3679 | |
3680 /* If the reg formerly set in I2 died only once and that was in I3, | |
3681 zero its use count so it won't make `reload' do any work. */ | |
3682 if (! added_sets_2 | |
3683 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) | |
3684 && ! i2dest_in_i2src) | |
3685 { | |
3686 regno = REGNO (i2dest); | |
3687 INC_REG_N_SETS (regno, -1); | |
3688 } | |
3689 } | |
3690 | |
3691 if (i1 && REG_P (i1dest)) | |
3692 { | |
3693 rtx link; | |
3694 rtx i1_insn = 0, i1_val = 0, set; | |
3695 | |
3696 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) | |
3697 if ((set = single_set (XEXP (link, 0))) != 0 | |
3698 && rtx_equal_p (i1dest, SET_DEST (set))) | |
3699 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set); | |
3700 | |
3701 record_value_for_reg (i1dest, i1_insn, i1_val); | |
3702 | |
3703 regno = REGNO (i1dest); | |
3704 if (! added_sets_1 && ! i1dest_in_i1src) | |
3705 INC_REG_N_SETS (regno, -1); | |
3706 } | |
3707 | |
3708 /* Update reg_stat[].nonzero_bits et al for any changes that may have | |
3709 been made to this insn. The order of | |
3710 set_nonzero_bits_and_sign_copies() is important. Because newi2pat | |
3711 can affect nonzero_bits of newpat */ | |
3712 if (newi2pat) | |
3713 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL); | |
3714 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL); | |
3715 | |
3716 /* Set new_direct_jump_p if a new return or simple jump instruction | |
3717 has been created. | |
3718 | |
3719 If I3 is now an unconditional jump, ensure that it has a | |
3720 BARRIER following it since it may have initially been a | |
3721 conditional jump. It may also be the last nonnote insn. */ | |
3722 | |
3723 if (returnjump_p (i3) || any_uncondjump_p (i3)) | |
3724 { | |
3725 *new_direct_jump_p = 1; | |
3726 mark_jump_label (PATTERN (i3), i3, 0); | |
3727 | |
3728 if ((temp = next_nonnote_insn (i3)) == NULL_RTX | |
3729 || !BARRIER_P (temp)) | |
3730 emit_barrier_after (i3); | |
3731 } | |
3732 | |
3733 if (undobuf.other_insn != NULL_RTX | |
3734 && (returnjump_p (undobuf.other_insn) | |
3735 || any_uncondjump_p (undobuf.other_insn))) | |
3736 { | |
3737 *new_direct_jump_p = 1; | |
3738 | |
3739 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX | |
3740 || !BARRIER_P (temp)) | |
3741 emit_barrier_after (undobuf.other_insn); | |
3742 } | |
3743 | |
3744 /* An NOOP jump does not need barrier, but it does need cleaning up | |
3745 of CFG. */ | |
3746 if (GET_CODE (newpat) == SET | |
3747 && SET_SRC (newpat) == pc_rtx | |
3748 && SET_DEST (newpat) == pc_rtx) | |
3749 *new_direct_jump_p = 1; | |
3750 } | |
3751 | |
3752 if (undobuf.other_insn != NULL_RTX) | |
3753 { | |
3754 if (dump_file) | |
3755 { | |
3756 fprintf (dump_file, "modifying other_insn "); | |
3757 dump_insn_slim (dump_file, undobuf.other_insn); | |
3758 } | |
3759 df_insn_rescan (undobuf.other_insn); | |
3760 } | |
3761 | |
3762 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED))) | |
3763 { | |
3764 if (dump_file) | |
3765 { | |
3766 fprintf (dump_file, "modifying insn i1 "); | |
3767 dump_insn_slim (dump_file, i1); | |
3768 } | |
3769 df_insn_rescan (i1); | |
3770 } | |
3771 | |
3772 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED))) | |
3773 { | |
3774 if (dump_file) | |
3775 { | |
3776 fprintf (dump_file, "modifying insn i2 "); | |
3777 dump_insn_slim (dump_file, i2); | |
3778 } | |
3779 df_insn_rescan (i2); | |
3780 } | |
3781 | |
3782 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED))) | |
3783 { | |
3784 if (dump_file) | |
3785 { | |
3786 fprintf (dump_file, "modifying insn i3 "); | |
3787 dump_insn_slim (dump_file, i3); | |
3788 } | |
3789 df_insn_rescan (i3); | |
3790 } | |
3791 | |
3792 combine_successes++; | |
3793 undo_commit (); | |
3794 | |
3795 if (added_links_insn | |
3796 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2)) | |
3797 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3)) | |
3798 return added_links_insn; | |
3799 else | |
3800 return newi2pat ? i2 : i3; | |
3801 } | |
3802 | |
3803 /* Undo all the modifications recorded in undobuf. */ | |
3804 | |
3805 static void | |
3806 undo_all (void) | |
3807 { | |
3808 struct undo *undo, *next; | |
3809 | |
3810 for (undo = undobuf.undos; undo; undo = next) | |
3811 { | |
3812 next = undo->next; | |
3813 switch (undo->kind) | |
3814 { | |
3815 case UNDO_RTX: | |
3816 *undo->where.r = undo->old_contents.r; | |
3817 break; | |
3818 case UNDO_INT: | |
3819 *undo->where.i = undo->old_contents.i; | |
3820 break; | |
3821 case UNDO_MODE: | |
3822 adjust_reg_mode (*undo->where.r, undo->old_contents.m); | |
3823 break; | |
3824 default: | |
3825 gcc_unreachable (); | |
3826 } | |
3827 | |
3828 undo->next = undobuf.frees; | |
3829 undobuf.frees = undo; | |
3830 } | |
3831 | |
3832 undobuf.undos = 0; | |
3833 } | |
3834 | |
3835 /* We've committed to accepting the changes we made. Move all | |
3836 of the undos to the free list. */ | |
3837 | |
3838 static void | |
3839 undo_commit (void) | |
3840 { | |
3841 struct undo *undo, *next; | |
3842 | |
3843 for (undo = undobuf.undos; undo; undo = next) | |
3844 { | |
3845 next = undo->next; | |
3846 undo->next = undobuf.frees; | |
3847 undobuf.frees = undo; | |
3848 } | |
3849 undobuf.undos = 0; | |
3850 } | |
3851 | |
3852 /* Find the innermost point within the rtx at LOC, possibly LOC itself, | |
3853 where we have an arithmetic expression and return that point. LOC will | |
3854 be inside INSN. | |
3855 | |
3856 try_combine will call this function to see if an insn can be split into | |
3857 two insns. */ | |
3858 | |
3859 static rtx * | |
3860 find_split_point (rtx *loc, rtx insn) | |
3861 { | |
3862 rtx x = *loc; | |
3863 enum rtx_code code = GET_CODE (x); | |
3864 rtx *split; | |
3865 unsigned HOST_WIDE_INT len = 0; | |
3866 HOST_WIDE_INT pos = 0; | |
3867 int unsignedp = 0; | |
3868 rtx inner = NULL_RTX; | |
3869 | |
3870 /* First special-case some codes. */ | |
3871 switch (code) | |
3872 { | |
3873 case SUBREG: | |
3874 #ifdef INSN_SCHEDULING | |
3875 /* If we are making a paradoxical SUBREG invalid, it becomes a split | |
3876 point. */ | |
3877 if (MEM_P (SUBREG_REG (x))) | |
3878 return loc; | |
3879 #endif | |
3880 return find_split_point (&SUBREG_REG (x), insn); | |
3881 | |
3882 case MEM: | |
3883 #ifdef HAVE_lo_sum | |
3884 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it | |
3885 using LO_SUM and HIGH. */ | |
3886 if (GET_CODE (XEXP (x, 0)) == CONST | |
3887 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
3888 { | |
3889 SUBST (XEXP (x, 0), | |
3890 gen_rtx_LO_SUM (Pmode, | |
3891 gen_rtx_HIGH (Pmode, XEXP (x, 0)), | |
3892 XEXP (x, 0))); | |
3893 return &XEXP (XEXP (x, 0), 0); | |
3894 } | |
3895 #endif | |
3896 | |
3897 /* If we have a PLUS whose second operand is a constant and the | |
3898 address is not valid, perhaps will can split it up using | |
3899 the machine-specific way to split large constants. We use | |
3900 the first pseudo-reg (one of the virtual regs) as a placeholder; | |
3901 it will not remain in the result. */ | |
3902 if (GET_CODE (XEXP (x, 0)) == PLUS | |
3903 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3904 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) | |
3905 { | |
3906 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
3907 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg, | |
3908 XEXP (x, 0)), | |
3909 subst_insn); | |
3910 | |
3911 /* This should have produced two insns, each of which sets our | |
3912 placeholder. If the source of the second is a valid address, | |
3913 we can make put both sources together and make a split point | |
3914 in the middle. */ | |
3915 | |
3916 if (seq | |
3917 && NEXT_INSN (seq) != NULL_RTX | |
3918 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX | |
3919 && NONJUMP_INSN_P (seq) | |
3920 && GET_CODE (PATTERN (seq)) == SET | |
3921 && SET_DEST (PATTERN (seq)) == reg | |
3922 && ! reg_mentioned_p (reg, | |
3923 SET_SRC (PATTERN (seq))) | |
3924 && NONJUMP_INSN_P (NEXT_INSN (seq)) | |
3925 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET | |
3926 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg | |
3927 && memory_address_p (GET_MODE (x), | |
3928 SET_SRC (PATTERN (NEXT_INSN (seq))))) | |
3929 { | |
3930 rtx src1 = SET_SRC (PATTERN (seq)); | |
3931 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq))); | |
3932 | |
3933 /* Replace the placeholder in SRC2 with SRC1. If we can | |
3934 find where in SRC2 it was placed, that can become our | |
3935 split point and we can replace this address with SRC2. | |
3936 Just try two obvious places. */ | |
3937 | |
3938 src2 = replace_rtx (src2, reg, src1); | |
3939 split = 0; | |
3940 if (XEXP (src2, 0) == src1) | |
3941 split = &XEXP (src2, 0); | |
3942 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' | |
3943 && XEXP (XEXP (src2, 0), 0) == src1) | |
3944 split = &XEXP (XEXP (src2, 0), 0); | |
3945 | |
3946 if (split) | |
3947 { | |
3948 SUBST (XEXP (x, 0), src2); | |
3949 return split; | |
3950 } | |
3951 } | |
3952 | |
3953 /* If that didn't work, perhaps the first operand is complex and | |
3954 needs to be computed separately, so make a split point there. | |
3955 This will occur on machines that just support REG + CONST | |
3956 and have a constant moved through some previous computation. */ | |
3957 | |
3958 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0)) | |
3959 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG | |
3960 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) | |
3961 return &XEXP (XEXP (x, 0), 0); | |
3962 } | |
3963 | |
3964 /* If we have a PLUS whose first operand is complex, try computing it | |
3965 separately by making a split there. */ | |
3966 if (GET_CODE (XEXP (x, 0)) == PLUS | |
3967 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)) | |
3968 && ! OBJECT_P (XEXP (XEXP (x, 0), 0)) | |
3969 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG | |
3970 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) | |
3971 return &XEXP (XEXP (x, 0), 0); | |
3972 break; | |
3973 | |
3974 case SET: | |
3975 #ifdef HAVE_cc0 | |
3976 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a | |
3977 ZERO_EXTRACT, the most likely reason why this doesn't match is that | |
3978 we need to put the operand into a register. So split at that | |
3979 point. */ | |
3980 | |
3981 if (SET_DEST (x) == cc0_rtx | |
3982 && GET_CODE (SET_SRC (x)) != COMPARE | |
3983 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT | |
3984 && !OBJECT_P (SET_SRC (x)) | |
3985 && ! (GET_CODE (SET_SRC (x)) == SUBREG | |
3986 && OBJECT_P (SUBREG_REG (SET_SRC (x))))) | |
3987 return &SET_SRC (x); | |
3988 #endif | |
3989 | |
3990 /* See if we can split SET_SRC as it stands. */ | |
3991 split = find_split_point (&SET_SRC (x), insn); | |
3992 if (split && split != &SET_SRC (x)) | |
3993 return split; | |
3994 | |
3995 /* See if we can split SET_DEST as it stands. */ | |
3996 split = find_split_point (&SET_DEST (x), insn); | |
3997 if (split && split != &SET_DEST (x)) | |
3998 return split; | |
3999 | |
4000 /* See if this is a bitfield assignment with everything constant. If | |
4001 so, this is an IOR of an AND, so split it into that. */ | |
4002 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
4003 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) | |
4004 <= HOST_BITS_PER_WIDE_INT) | |
4005 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT | |
4006 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT | |
4007 && GET_CODE (SET_SRC (x)) == CONST_INT | |
4008 && ((INTVAL (XEXP (SET_DEST (x), 1)) | |
4009 + INTVAL (XEXP (SET_DEST (x), 2))) | |
4010 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) | |
4011 && ! side_effects_p (XEXP (SET_DEST (x), 0))) | |
4012 { | |
4013 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2)); | |
4014 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1)); | |
4015 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)); | |
4016 rtx dest = XEXP (SET_DEST (x), 0); | |
4017 enum machine_mode mode = GET_MODE (dest); | |
4018 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1; | |
4019 rtx or_mask; | |
4020 | |
4021 if (BITS_BIG_ENDIAN) | |
4022 pos = GET_MODE_BITSIZE (mode) - len - pos; | |
4023 | |
4024 or_mask = gen_int_mode (src << pos, mode); | |
4025 if (src == mask) | |
4026 SUBST (SET_SRC (x), | |
4027 simplify_gen_binary (IOR, mode, dest, or_mask)); | |
4028 else | |
4029 { | |
4030 rtx negmask = gen_int_mode (~(mask << pos), mode); | |
4031 SUBST (SET_SRC (x), | |
4032 simplify_gen_binary (IOR, mode, | |
4033 simplify_gen_binary (AND, mode, | |
4034 dest, negmask), | |
4035 or_mask)); | |
4036 } | |
4037 | |
4038 SUBST (SET_DEST (x), dest); | |
4039 | |
4040 split = find_split_point (&SET_SRC (x), insn); | |
4041 if (split && split != &SET_SRC (x)) | |
4042 return split; | |
4043 } | |
4044 | |
4045 /* Otherwise, see if this is an operation that we can split into two. | |
4046 If so, try to split that. */ | |
4047 code = GET_CODE (SET_SRC (x)); | |
4048 | |
4049 switch (code) | |
4050 { | |
4051 case AND: | |
4052 /* If we are AND'ing with a large constant that is only a single | |
4053 bit and the result is only being used in a context where we | |
4054 need to know if it is zero or nonzero, replace it with a bit | |
4055 extraction. This will avoid the large constant, which might | |
4056 have taken more than one insn to make. If the constant were | |
4057 not a valid argument to the AND but took only one insn to make, | |
4058 this is no worse, but if it took more than one insn, it will | |
4059 be better. */ | |
4060 | |
4061 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
4062 && REG_P (XEXP (SET_SRC (x), 0)) | |
4063 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7 | |
4064 && REG_P (SET_DEST (x)) | |
4065 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0 | |
4066 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) | |
4067 && XEXP (*split, 0) == SET_DEST (x) | |
4068 && XEXP (*split, 1) == const0_rtx) | |
4069 { | |
4070 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), | |
4071 XEXP (SET_SRC (x), 0), | |
4072 pos, NULL_RTX, 1, 1, 0, 0); | |
4073 if (extraction != 0) | |
4074 { | |
4075 SUBST (SET_SRC (x), extraction); | |
4076 return find_split_point (loc, insn); | |
4077 } | |
4078 } | |
4079 break; | |
4080 | |
4081 case NE: | |
4082 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X | |
4083 is known to be on, this can be converted into a NEG of a shift. */ | |
4084 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx | |
4085 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) | |
4086 && 1 <= (pos = exact_log2 | |
4087 (nonzero_bits (XEXP (SET_SRC (x), 0), | |
4088 GET_MODE (XEXP (SET_SRC (x), 0)))))) | |
4089 { | |
4090 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); | |
4091 | |
4092 SUBST (SET_SRC (x), | |
4093 gen_rtx_NEG (mode, | |
4094 gen_rtx_LSHIFTRT (mode, | |
4095 XEXP (SET_SRC (x), 0), | |
4096 GEN_INT (pos)))); | |
4097 | |
4098 split = find_split_point (&SET_SRC (x), insn); | |
4099 if (split && split != &SET_SRC (x)) | |
4100 return split; | |
4101 } | |
4102 break; | |
4103 | |
4104 case SIGN_EXTEND: | |
4105 inner = XEXP (SET_SRC (x), 0); | |
4106 | |
4107 /* We can't optimize if either mode is a partial integer | |
4108 mode as we don't know how many bits are significant | |
4109 in those modes. */ | |
4110 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT | |
4111 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) | |
4112 break; | |
4113 | |
4114 pos = 0; | |
4115 len = GET_MODE_BITSIZE (GET_MODE (inner)); | |
4116 unsignedp = 0; | |
4117 break; | |
4118 | |
4119 case SIGN_EXTRACT: | |
4120 case ZERO_EXTRACT: | |
4121 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
4122 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) | |
4123 { | |
4124 inner = XEXP (SET_SRC (x), 0); | |
4125 len = INTVAL (XEXP (SET_SRC (x), 1)); | |
4126 pos = INTVAL (XEXP (SET_SRC (x), 2)); | |
4127 | |
4128 if (BITS_BIG_ENDIAN) | |
4129 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; | |
4130 unsignedp = (code == ZERO_EXTRACT); | |
4131 } | |
4132 break; | |
4133 | |
4134 default: | |
4135 break; | |
4136 } | |
4137 | |
4138 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) | |
4139 { | |
4140 enum machine_mode mode = GET_MODE (SET_SRC (x)); | |
4141 | |
4142 /* For unsigned, we have a choice of a shift followed by an | |
4143 AND or two shifts. Use two shifts for field sizes where the | |
4144 constant might be too large. We assume here that we can | |
4145 always at least get 8-bit constants in an AND insn, which is | |
4146 true for every current RISC. */ | |
4147 | |
4148 if (unsignedp && len <= 8) | |
4149 { | |
4150 SUBST (SET_SRC (x), | |
4151 gen_rtx_AND (mode, | |
4152 gen_rtx_LSHIFTRT | |
4153 (mode, gen_lowpart (mode, inner), | |
4154 GEN_INT (pos)), | |
4155 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1))); | |
4156 | |
4157 split = find_split_point (&SET_SRC (x), insn); | |
4158 if (split && split != &SET_SRC (x)) | |
4159 return split; | |
4160 } | |
4161 else | |
4162 { | |
4163 SUBST (SET_SRC (x), | |
4164 gen_rtx_fmt_ee | |
4165 (unsignedp ? LSHIFTRT : ASHIFTRT, mode, | |
4166 gen_rtx_ASHIFT (mode, | |
4167 gen_lowpart (mode, inner), | |
4168 GEN_INT (GET_MODE_BITSIZE (mode) | |
4169 - len - pos)), | |
4170 GEN_INT (GET_MODE_BITSIZE (mode) - len))); | |
4171 | |
4172 split = find_split_point (&SET_SRC (x), insn); | |
4173 if (split && split != &SET_SRC (x)) | |
4174 return split; | |
4175 } | |
4176 } | |
4177 | |
4178 /* See if this is a simple operation with a constant as the second | |
4179 operand. It might be that this constant is out of range and hence | |
4180 could be used as a split point. */ | |
4181 if (BINARY_P (SET_SRC (x)) | |
4182 && CONSTANT_P (XEXP (SET_SRC (x), 1)) | |
4183 && (OBJECT_P (XEXP (SET_SRC (x), 0)) | |
4184 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG | |
4185 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0)))))) | |
4186 return &XEXP (SET_SRC (x), 1); | |
4187 | |
4188 /* Finally, see if this is a simple operation with its first operand | |
4189 not in a register. The operation might require this operand in a | |
4190 register, so return it as a split point. We can always do this | |
4191 because if the first operand were another operation, we would have | |
4192 already found it as a split point. */ | |
4193 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x))) | |
4194 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) | |
4195 return &XEXP (SET_SRC (x), 0); | |
4196 | |
4197 return 0; | |
4198 | |
4199 case AND: | |
4200 case IOR: | |
4201 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, | |
4202 it is better to write this as (not (ior A B)) so we can split it. | |
4203 Similarly for IOR. */ | |
4204 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) | |
4205 { | |
4206 SUBST (*loc, | |
4207 gen_rtx_NOT (GET_MODE (x), | |
4208 gen_rtx_fmt_ee (code == IOR ? AND : IOR, | |
4209 GET_MODE (x), | |
4210 XEXP (XEXP (x, 0), 0), | |
4211 XEXP (XEXP (x, 1), 0)))); | |
4212 return find_split_point (loc, insn); | |
4213 } | |
4214 | |
4215 /* Many RISC machines have a large set of logical insns. If the | |
4216 second operand is a NOT, put it first so we will try to split the | |
4217 other operand first. */ | |
4218 if (GET_CODE (XEXP (x, 1)) == NOT) | |
4219 { | |
4220 rtx tem = XEXP (x, 0); | |
4221 SUBST (XEXP (x, 0), XEXP (x, 1)); | |
4222 SUBST (XEXP (x, 1), tem); | |
4223 } | |
4224 break; | |
4225 | |
4226 default: | |
4227 break; | |
4228 } | |
4229 | |
4230 /* Otherwise, select our actions depending on our rtx class. */ | |
4231 switch (GET_RTX_CLASS (code)) | |
4232 { | |
4233 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ | |
4234 case RTX_TERNARY: | |
4235 split = find_split_point (&XEXP (x, 2), insn); | |
4236 if (split) | |
4237 return split; | |
4238 /* ... fall through ... */ | |
4239 case RTX_BIN_ARITH: | |
4240 case RTX_COMM_ARITH: | |
4241 case RTX_COMPARE: | |
4242 case RTX_COMM_COMPARE: | |
4243 split = find_split_point (&XEXP (x, 1), insn); | |
4244 if (split) | |
4245 return split; | |
4246 /* ... fall through ... */ | |
4247 case RTX_UNARY: | |
4248 /* Some machines have (and (shift ...) ...) insns. If X is not | |
4249 an AND, but XEXP (X, 0) is, use it as our split point. */ | |
4250 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) | |
4251 return &XEXP (x, 0); | |
4252 | |
4253 split = find_split_point (&XEXP (x, 0), insn); | |
4254 if (split) | |
4255 return split; | |
4256 return loc; | |
4257 | |
4258 default: | |
4259 /* Otherwise, we don't have a split point. */ | |
4260 return 0; | |
4261 } | |
4262 } | |
4263 | |
4264 /* Throughout X, replace FROM with TO, and return the result. | |
4265 The result is TO if X is FROM; | |
4266 otherwise the result is X, but its contents may have been modified. | |
4267 If they were modified, a record was made in undobuf so that | |
4268 undo_all will (among other things) return X to its original state. | |
4269 | |
4270 If the number of changes necessary is too much to record to undo, | |
4271 the excess changes are not made, so the result is invalid. | |
4272 The changes already made can still be undone. | |
4273 undobuf.num_undo is incremented for such changes, so by testing that | |
4274 the caller can tell whether the result is valid. | |
4275 | |
4276 `n_occurrences' is incremented each time FROM is replaced. | |
4277 | |
4278 IN_DEST is nonzero if we are processing the SET_DEST of a SET. | |
4279 | |
4280 UNIQUE_COPY is nonzero if each substitution must be unique. We do this | |
4281 by copying if `n_occurrences' is nonzero. */ | |
4282 | |
4283 static rtx | |
4284 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy) | |
4285 { | |
4286 enum rtx_code code = GET_CODE (x); | |
4287 enum machine_mode op0_mode = VOIDmode; | |
4288 const char *fmt; | |
4289 int len, i; | |
4290 rtx new_rtx; | |
4291 | |
4292 /* Two expressions are equal if they are identical copies of a shared | |
4293 RTX or if they are both registers with the same register number | |
4294 and mode. */ | |
4295 | |
4296 #define COMBINE_RTX_EQUAL_P(X,Y) \ | |
4297 ((X) == (Y) \ | |
4298 || (REG_P (X) && REG_P (Y) \ | |
4299 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) | |
4300 | |
4301 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) | |
4302 { | |
4303 n_occurrences++; | |
4304 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); | |
4305 } | |
4306 | |
4307 /* If X and FROM are the same register but different modes, they | |
4308 will not have been seen as equal above. However, the log links code | |
4309 will make a LOG_LINKS entry for that case. If we do nothing, we | |
4310 will try to rerecognize our original insn and, when it succeeds, | |
4311 we will delete the feeding insn, which is incorrect. | |
4312 | |
4313 So force this insn not to match in this (rare) case. */ | |
4314 if (! in_dest && code == REG && REG_P (from) | |
4315 && reg_overlap_mentioned_p (x, from)) | |
4316 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); | |
4317 | |
4318 /* If this is an object, we are done unless it is a MEM or LO_SUM, both | |
4319 of which may contain things that can be combined. */ | |
4320 if (code != MEM && code != LO_SUM && OBJECT_P (x)) | |
4321 return x; | |
4322 | |
4323 /* It is possible to have a subexpression appear twice in the insn. | |
4324 Suppose that FROM is a register that appears within TO. | |
4325 Then, after that subexpression has been scanned once by `subst', | |
4326 the second time it is scanned, TO may be found. If we were | |
4327 to scan TO here, we would find FROM within it and create a | |
4328 self-referent rtl structure which is completely wrong. */ | |
4329 if (COMBINE_RTX_EQUAL_P (x, to)) | |
4330 return to; | |
4331 | |
4332 /* Parallel asm_operands need special attention because all of the | |
4333 inputs are shared across the arms. Furthermore, unsharing the | |
4334 rtl results in recognition failures. Failure to handle this case | |
4335 specially can result in circular rtl. | |
4336 | |
4337 Solve this by doing a normal pass across the first entry of the | |
4338 parallel, and only processing the SET_DESTs of the subsequent | |
4339 entries. Ug. */ | |
4340 | |
4341 if (code == PARALLEL | |
4342 && GET_CODE (XVECEXP (x, 0, 0)) == SET | |
4343 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) | |
4344 { | |
4345 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); | |
4346 | |
4347 /* If this substitution failed, this whole thing fails. */ | |
4348 if (GET_CODE (new_rtx) == CLOBBER | |
4349 && XEXP (new_rtx, 0) == const0_rtx) | |
4350 return new_rtx; | |
4351 | |
4352 SUBST (XVECEXP (x, 0, 0), new_rtx); | |
4353 | |
4354 for (i = XVECLEN (x, 0) - 1; i >= 1; i--) | |
4355 { | |
4356 rtx dest = SET_DEST (XVECEXP (x, 0, i)); | |
4357 | |
4358 if (!REG_P (dest) | |
4359 && GET_CODE (dest) != CC0 | |
4360 && GET_CODE (dest) != PC) | |
4361 { | |
4362 new_rtx = subst (dest, from, to, 0, unique_copy); | |
4363 | |
4364 /* If this substitution failed, this whole thing fails. */ | |
4365 if (GET_CODE (new_rtx) == CLOBBER | |
4366 && XEXP (new_rtx, 0) == const0_rtx) | |
4367 return new_rtx; | |
4368 | |
4369 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx); | |
4370 } | |
4371 } | |
4372 } | |
4373 else | |
4374 { | |
4375 len = GET_RTX_LENGTH (code); | |
4376 fmt = GET_RTX_FORMAT (code); | |
4377 | |
4378 /* We don't need to process a SET_DEST that is a register, CC0, | |
4379 or PC, so set up to skip this common case. All other cases | |
4380 where we want to suppress replacing something inside a | |
4381 SET_SRC are handled via the IN_DEST operand. */ | |
4382 if (code == SET | |
4383 && (REG_P (SET_DEST (x)) | |
4384 || GET_CODE (SET_DEST (x)) == CC0 | |
4385 || GET_CODE (SET_DEST (x)) == PC)) | |
4386 fmt = "ie"; | |
4387 | |
4388 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a | |
4389 constant. */ | |
4390 if (fmt[0] == 'e') | |
4391 op0_mode = GET_MODE (XEXP (x, 0)); | |
4392 | |
4393 for (i = 0; i < len; i++) | |
4394 { | |
4395 if (fmt[i] == 'E') | |
4396 { | |
4397 int j; | |
4398 for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4399 { | |
4400 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) | |
4401 { | |
4402 new_rtx = (unique_copy && n_occurrences | |
4403 ? copy_rtx (to) : to); | |
4404 n_occurrences++; | |
4405 } | |
4406 else | |
4407 { | |
4408 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, | |
4409 unique_copy); | |
4410 | |
4411 /* If this substitution failed, this whole thing | |
4412 fails. */ | |
4413 if (GET_CODE (new_rtx) == CLOBBER | |
4414 && XEXP (new_rtx, 0) == const0_rtx) | |
4415 return new_rtx; | |
4416 } | |
4417 | |
4418 SUBST (XVECEXP (x, i, j), new_rtx); | |
4419 } | |
4420 } | |
4421 else if (fmt[i] == 'e') | |
4422 { | |
4423 /* If this is a register being set, ignore it. */ | |
4424 new_rtx = XEXP (x, i); | |
4425 if (in_dest | |
4426 && i == 0 | |
4427 && (((code == SUBREG || code == ZERO_EXTRACT) | |
4428 && REG_P (new_rtx)) | |
4429 || code == STRICT_LOW_PART)) | |
4430 ; | |
4431 | |
4432 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) | |
4433 { | |
4434 /* In general, don't install a subreg involving two | |
4435 modes not tieable. It can worsen register | |
4436 allocation, and can even make invalid reload | |
4437 insns, since the reg inside may need to be copied | |
4438 from in the outside mode, and that may be invalid | |
4439 if it is an fp reg copied in integer mode. | |
4440 | |
4441 We allow two exceptions to this: It is valid if | |
4442 it is inside another SUBREG and the mode of that | |
4443 SUBREG and the mode of the inside of TO is | |
4444 tieable and it is valid if X is a SET that copies | |
4445 FROM to CC0. */ | |
4446 | |
4447 if (GET_CODE (to) == SUBREG | |
4448 && ! MODES_TIEABLE_P (GET_MODE (to), | |
4449 GET_MODE (SUBREG_REG (to))) | |
4450 && ! (code == SUBREG | |
4451 && MODES_TIEABLE_P (GET_MODE (x), | |
4452 GET_MODE (SUBREG_REG (to)))) | |
4453 #ifdef HAVE_cc0 | |
4454 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) | |
4455 #endif | |
4456 ) | |
4457 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); | |
4458 | |
4459 #ifdef CANNOT_CHANGE_MODE_CLASS | |
4460 if (code == SUBREG | |
4461 && REG_P (to) | |
4462 && REGNO (to) < FIRST_PSEUDO_REGISTER | |
4463 && REG_CANNOT_CHANGE_MODE_P (REGNO (to), | |
4464 GET_MODE (to), | |
4465 GET_MODE (x))) | |
4466 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); | |
4467 #endif | |
4468 | |
4469 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to); | |
4470 n_occurrences++; | |
4471 } | |
4472 else | |
4473 /* If we are in a SET_DEST, suppress most cases unless we | |
4474 have gone inside a MEM, in which case we want to | |
4475 simplify the address. We assume here that things that | |
4476 are actually part of the destination have their inner | |
4477 parts in the first expression. This is true for SUBREG, | |
4478 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only | |
4479 things aside from REG and MEM that should appear in a | |
4480 SET_DEST. */ | |
4481 new_rtx = subst (XEXP (x, i), from, to, | |
4482 (((in_dest | |
4483 && (code == SUBREG || code == STRICT_LOW_PART | |
4484 || code == ZERO_EXTRACT)) | |
4485 || code == SET) | |
4486 && i == 0), unique_copy); | |
4487 | |
4488 /* If we found that we will have to reject this combination, | |
4489 indicate that by returning the CLOBBER ourselves, rather than | |
4490 an expression containing it. This will speed things up as | |
4491 well as prevent accidents where two CLOBBERs are considered | |
4492 to be equal, thus producing an incorrect simplification. */ | |
4493 | |
4494 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx) | |
4495 return new_rtx; | |
4496 | |
4497 if (GET_CODE (x) == SUBREG | |
4498 && (GET_CODE (new_rtx) == CONST_INT | |
4499 || GET_CODE (new_rtx) == CONST_DOUBLE)) | |
4500 { | |
4501 enum machine_mode mode = GET_MODE (x); | |
4502 | |
4503 x = simplify_subreg (GET_MODE (x), new_rtx, | |
4504 GET_MODE (SUBREG_REG (x)), | |
4505 SUBREG_BYTE (x)); | |
4506 if (! x) | |
4507 x = gen_rtx_CLOBBER (mode, const0_rtx); | |
4508 } | |
4509 else if (GET_CODE (new_rtx) == CONST_INT | |
4510 && GET_CODE (x) == ZERO_EXTEND) | |
4511 { | |
4512 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), | |
4513 new_rtx, GET_MODE (XEXP (x, 0))); | |
4514 gcc_assert (x); | |
4515 } | |
4516 else | |
4517 SUBST (XEXP (x, i), new_rtx); | |
4518 } | |
4519 } | |
4520 } | |
4521 | |
4522 /* Check if we are loading something from the constant pool via float | |
4523 extension; in this case we would undo compress_float_constant | |
4524 optimization and degenerate constant load to an immediate value. */ | |
4525 if (GET_CODE (x) == FLOAT_EXTEND | |
4526 && MEM_P (XEXP (x, 0)) | |
4527 && MEM_READONLY_P (XEXP (x, 0))) | |
4528 { | |
4529 rtx tmp = avoid_constant_pool_reference (x); | |
4530 if (x != tmp) | |
4531 return x; | |
4532 } | |
4533 | |
4534 /* Try to simplify X. If the simplification changed the code, it is likely | |
4535 that further simplification will help, so loop, but limit the number | |
4536 of repetitions that will be performed. */ | |
4537 | |
4538 for (i = 0; i < 4; i++) | |
4539 { | |
4540 /* If X is sufficiently simple, don't bother trying to do anything | |
4541 with it. */ | |
4542 if (code != CONST_INT && code != REG && code != CLOBBER) | |
4543 x = combine_simplify_rtx (x, op0_mode, in_dest); | |
4544 | |
4545 if (GET_CODE (x) == code) | |
4546 break; | |
4547 | |
4548 code = GET_CODE (x); | |
4549 | |
4550 /* We no longer know the original mode of operand 0 since we | |
4551 have changed the form of X) */ | |
4552 op0_mode = VOIDmode; | |
4553 } | |
4554 | |
4555 return x; | |
4556 } | |
4557 | |
4558 /* Simplify X, a piece of RTL. We just operate on the expression at the | |
4559 outer level; call `subst' to simplify recursively. Return the new | |
4560 expression. | |
4561 | |
4562 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero | |
4563 if we are inside a SET_DEST. */ | |
4564 | |
4565 static rtx | |
4566 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest) | |
4567 { | |
4568 enum rtx_code code = GET_CODE (x); | |
4569 enum machine_mode mode = GET_MODE (x); | |
4570 rtx temp; | |
4571 int i; | |
4572 | |
4573 /* If this is a commutative operation, put a constant last and a complex | |
4574 expression first. We don't need to do this for comparisons here. */ | |
4575 if (COMMUTATIVE_ARITH_P (x) | |
4576 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) | |
4577 { | |
4578 temp = XEXP (x, 0); | |
4579 SUBST (XEXP (x, 0), XEXP (x, 1)); | |
4580 SUBST (XEXP (x, 1), temp); | |
4581 } | |
4582 | |
4583 /* If this is a simple operation applied to an IF_THEN_ELSE, try | |
4584 applying it to the arms of the IF_THEN_ELSE. This often simplifies | |
4585 things. Check for cases where both arms are testing the same | |
4586 condition. | |
4587 | |
4588 Don't do anything if all operands are very simple. */ | |
4589 | |
4590 if ((BINARY_P (x) | |
4591 && ((!OBJECT_P (XEXP (x, 0)) | |
4592 && ! (GET_CODE (XEXP (x, 0)) == SUBREG | |
4593 && OBJECT_P (SUBREG_REG (XEXP (x, 0))))) | |
4594 || (!OBJECT_P (XEXP (x, 1)) | |
4595 && ! (GET_CODE (XEXP (x, 1)) == SUBREG | |
4596 && OBJECT_P (SUBREG_REG (XEXP (x, 1))))))) | |
4597 || (UNARY_P (x) | |
4598 && (!OBJECT_P (XEXP (x, 0)) | |
4599 && ! (GET_CODE (XEXP (x, 0)) == SUBREG | |
4600 && OBJECT_P (SUBREG_REG (XEXP (x, 0))))))) | |
4601 { | |
4602 rtx cond, true_rtx, false_rtx; | |
4603 | |
4604 cond = if_then_else_cond (x, &true_rtx, &false_rtx); | |
4605 if (cond != 0 | |
4606 /* If everything is a comparison, what we have is highly unlikely | |
4607 to be simpler, so don't use it. */ | |
4608 && ! (COMPARISON_P (x) | |
4609 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))) | |
4610 { | |
4611 rtx cop1 = const0_rtx; | |
4612 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); | |
4613 | |
4614 if (cond_code == NE && COMPARISON_P (cond)) | |
4615 return x; | |
4616 | |
4617 /* Simplify the alternative arms; this may collapse the true and | |
4618 false arms to store-flag values. Be careful to use copy_rtx | |
4619 here since true_rtx or false_rtx might share RTL with x as a | |
4620 result of the if_then_else_cond call above. */ | |
4621 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0); | |
4622 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0); | |
4623 | |
4624 /* If true_rtx and false_rtx are not general_operands, an if_then_else | |
4625 is unlikely to be simpler. */ | |
4626 if (general_operand (true_rtx, VOIDmode) | |
4627 && general_operand (false_rtx, VOIDmode)) | |
4628 { | |
4629 enum rtx_code reversed; | |
4630 | |
4631 /* Restarting if we generate a store-flag expression will cause | |
4632 us to loop. Just drop through in this case. */ | |
4633 | |
4634 /* If the result values are STORE_FLAG_VALUE and zero, we can | |
4635 just make the comparison operation. */ | |
4636 if (true_rtx == const_true_rtx && false_rtx == const0_rtx) | |
4637 x = simplify_gen_relational (cond_code, mode, VOIDmode, | |
4638 cond, cop1); | |
4639 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx | |
4640 && ((reversed = reversed_comparison_code_parts | |
4641 (cond_code, cond, cop1, NULL)) | |
4642 != UNKNOWN)) | |
4643 x = simplify_gen_relational (reversed, mode, VOIDmode, | |
4644 cond, cop1); | |
4645 | |
4646 /* Likewise, we can make the negate of a comparison operation | |
4647 if the result values are - STORE_FLAG_VALUE and zero. */ | |
4648 else if (GET_CODE (true_rtx) == CONST_INT | |
4649 && INTVAL (true_rtx) == - STORE_FLAG_VALUE | |
4650 && false_rtx == const0_rtx) | |
4651 x = simplify_gen_unary (NEG, mode, | |
4652 simplify_gen_relational (cond_code, | |
4653 mode, VOIDmode, | |
4654 cond, cop1), | |
4655 mode); | |
4656 else if (GET_CODE (false_rtx) == CONST_INT | |
4657 && INTVAL (false_rtx) == - STORE_FLAG_VALUE | |
4658 && true_rtx == const0_rtx | |
4659 && ((reversed = reversed_comparison_code_parts | |
4660 (cond_code, cond, cop1, NULL)) | |
4661 != UNKNOWN)) | |
4662 x = simplify_gen_unary (NEG, mode, | |
4663 simplify_gen_relational (reversed, | |
4664 mode, VOIDmode, | |
4665 cond, cop1), | |
4666 mode); | |
4667 else | |
4668 return gen_rtx_IF_THEN_ELSE (mode, | |
4669 simplify_gen_relational (cond_code, | |
4670 mode, | |
4671 VOIDmode, | |
4672 cond, | |
4673 cop1), | |
4674 true_rtx, false_rtx); | |
4675 | |
4676 code = GET_CODE (x); | |
4677 op0_mode = VOIDmode; | |
4678 } | |
4679 } | |
4680 } | |
4681 | |
4682 /* Try to fold this expression in case we have constants that weren't | |
4683 present before. */ | |
4684 temp = 0; | |
4685 switch (GET_RTX_CLASS (code)) | |
4686 { | |
4687 case RTX_UNARY: | |
4688 if (op0_mode == VOIDmode) | |
4689 op0_mode = GET_MODE (XEXP (x, 0)); | |
4690 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); | |
4691 break; | |
4692 case RTX_COMPARE: | |
4693 case RTX_COMM_COMPARE: | |
4694 { | |
4695 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); | |
4696 if (cmp_mode == VOIDmode) | |
4697 { | |
4698 cmp_mode = GET_MODE (XEXP (x, 1)); | |
4699 if (cmp_mode == VOIDmode) | |
4700 cmp_mode = op0_mode; | |
4701 } | |
4702 temp = simplify_relational_operation (code, mode, cmp_mode, | |
4703 XEXP (x, 0), XEXP (x, 1)); | |
4704 } | |
4705 break; | |
4706 case RTX_COMM_ARITH: | |
4707 case RTX_BIN_ARITH: | |
4708 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); | |
4709 break; | |
4710 case RTX_BITFIELD_OPS: | |
4711 case RTX_TERNARY: | |
4712 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), | |
4713 XEXP (x, 1), XEXP (x, 2)); | |
4714 break; | |
4715 default: | |
4716 break; | |
4717 } | |
4718 | |
4719 if (temp) | |
4720 { | |
4721 x = temp; | |
4722 code = GET_CODE (temp); | |
4723 op0_mode = VOIDmode; | |
4724 mode = GET_MODE (temp); | |
4725 } | |
4726 | |
4727 /* First see if we can apply the inverse distributive law. */ | |
4728 if (code == PLUS || code == MINUS | |
4729 || code == AND || code == IOR || code == XOR) | |
4730 { | |
4731 x = apply_distributive_law (x); | |
4732 code = GET_CODE (x); | |
4733 op0_mode = VOIDmode; | |
4734 } | |
4735 | |
4736 /* If CODE is an associative operation not otherwise handled, see if we | |
4737 can associate some operands. This can win if they are constants or | |
4738 if they are logically related (i.e. (a & b) & a). */ | |
4739 if ((code == PLUS || code == MINUS || code == MULT || code == DIV | |
4740 || code == AND || code == IOR || code == XOR | |
4741 || code == SMAX || code == SMIN || code == UMAX || code == UMIN) | |
4742 && ((INTEGRAL_MODE_P (mode) && code != DIV) | |
4743 || (flag_associative_math && FLOAT_MODE_P (mode)))) | |
4744 { | |
4745 if (GET_CODE (XEXP (x, 0)) == code) | |
4746 { | |
4747 rtx other = XEXP (XEXP (x, 0), 0); | |
4748 rtx inner_op0 = XEXP (XEXP (x, 0), 1); | |
4749 rtx inner_op1 = XEXP (x, 1); | |
4750 rtx inner; | |
4751 | |
4752 /* Make sure we pass the constant operand if any as the second | |
4753 one if this is a commutative operation. */ | |
4754 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x)) | |
4755 { | |
4756 rtx tem = inner_op0; | |
4757 inner_op0 = inner_op1; | |
4758 inner_op1 = tem; | |
4759 } | |
4760 inner = simplify_binary_operation (code == MINUS ? PLUS | |
4761 : code == DIV ? MULT | |
4762 : code, | |
4763 mode, inner_op0, inner_op1); | |
4764 | |
4765 /* For commutative operations, try the other pair if that one | |
4766 didn't simplify. */ | |
4767 if (inner == 0 && COMMUTATIVE_ARITH_P (x)) | |
4768 { | |
4769 other = XEXP (XEXP (x, 0), 1); | |
4770 inner = simplify_binary_operation (code, mode, | |
4771 XEXP (XEXP (x, 0), 0), | |
4772 XEXP (x, 1)); | |
4773 } | |
4774 | |
4775 if (inner) | |
4776 return simplify_gen_binary (code, mode, other, inner); | |
4777 } | |
4778 } | |
4779 | |
4780 /* A little bit of algebraic simplification here. */ | |
4781 switch (code) | |
4782 { | |
4783 case MEM: | |
4784 /* Ensure that our address has any ASHIFTs converted to MULT in case | |
4785 address-recognizing predicates are called later. */ | |
4786 temp = make_compound_operation (XEXP (x, 0), MEM); | |
4787 SUBST (XEXP (x, 0), temp); | |
4788 break; | |
4789 | |
4790 case SUBREG: | |
4791 if (op0_mode == VOIDmode) | |
4792 op0_mode = GET_MODE (SUBREG_REG (x)); | |
4793 | |
4794 /* See if this can be moved to simplify_subreg. */ | |
4795 if (CONSTANT_P (SUBREG_REG (x)) | |
4796 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x) | |
4797 /* Don't call gen_lowpart if the inner mode | |
4798 is VOIDmode and we cannot simplify it, as SUBREG without | |
4799 inner mode is invalid. */ | |
4800 && (GET_MODE (SUBREG_REG (x)) != VOIDmode | |
4801 || gen_lowpart_common (mode, SUBREG_REG (x)))) | |
4802 return gen_lowpart (mode, SUBREG_REG (x)); | |
4803 | |
4804 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC) | |
4805 break; | |
4806 { | |
4807 rtx temp; | |
4808 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode, | |
4809 SUBREG_BYTE (x)); | |
4810 if (temp) | |
4811 return temp; | |
4812 } | |
4813 | |
4814 /* Don't change the mode of the MEM if that would change the meaning | |
4815 of the address. */ | |
4816 if (MEM_P (SUBREG_REG (x)) | |
4817 && (MEM_VOLATILE_P (SUBREG_REG (x)) | |
4818 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0)))) | |
4819 return gen_rtx_CLOBBER (mode, const0_rtx); | |
4820 | |
4821 /* Note that we cannot do any narrowing for non-constants since | |
4822 we might have been counting on using the fact that some bits were | |
4823 zero. We now do this in the SET. */ | |
4824 | |
4825 break; | |
4826 | |
4827 case NEG: | |
4828 temp = expand_compound_operation (XEXP (x, 0)); | |
4829 | |
4830 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be | |
4831 replaced by (lshiftrt X C). This will convert | |
4832 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ | |
4833 | |
4834 if (GET_CODE (temp) == ASHIFTRT | |
4835 && GET_CODE (XEXP (temp, 1)) == CONST_INT | |
4836 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) | |
4837 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0), | |
4838 INTVAL (XEXP (temp, 1))); | |
4839 | |
4840 /* If X has only a single bit that might be nonzero, say, bit I, convert | |
4841 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of | |
4842 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to | |
4843 (sign_extract X 1 Y). But only do this if TEMP isn't a register | |
4844 or a SUBREG of one since we'd be making the expression more | |
4845 complex if it was just a register. */ | |
4846 | |
4847 if (!REG_P (temp) | |
4848 && ! (GET_CODE (temp) == SUBREG | |
4849 && REG_P (SUBREG_REG (temp))) | |
4850 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) | |
4851 { | |
4852 rtx temp1 = simplify_shift_const | |
4853 (NULL_RTX, ASHIFTRT, mode, | |
4854 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, | |
4855 GET_MODE_BITSIZE (mode) - 1 - i), | |
4856 GET_MODE_BITSIZE (mode) - 1 - i); | |
4857 | |
4858 /* If all we did was surround TEMP with the two shifts, we | |
4859 haven't improved anything, so don't use it. Otherwise, | |
4860 we are better off with TEMP1. */ | |
4861 if (GET_CODE (temp1) != ASHIFTRT | |
4862 || GET_CODE (XEXP (temp1, 0)) != ASHIFT | |
4863 || XEXP (XEXP (temp1, 0), 0) != temp) | |
4864 return temp1; | |
4865 } | |
4866 break; | |
4867 | |
4868 case TRUNCATE: | |
4869 /* We can't handle truncation to a partial integer mode here | |
4870 because we don't know the real bitsize of the partial | |
4871 integer mode. */ | |
4872 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
4873 break; | |
4874 | |
4875 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
4876 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
4877 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))) | |
4878 SUBST (XEXP (x, 0), | |
4879 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), | |
4880 GET_MODE_MASK (mode), 0)); | |
4881 | |
4882 /* Similarly to what we do in simplify-rtx.c, a truncate of a register | |
4883 whose value is a comparison can be replaced with a subreg if | |
4884 STORE_FLAG_VALUE permits. */ | |
4885 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
4886 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0 | |
4887 && (temp = get_last_value (XEXP (x, 0))) | |
4888 && COMPARISON_P (temp)) | |
4889 return gen_lowpart (mode, XEXP (x, 0)); | |
4890 break; | |
4891 | |
4892 #ifdef HAVE_cc0 | |
4893 case COMPARE: | |
4894 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't | |
4895 using cc0, in which case we want to leave it as a COMPARE | |
4896 so we can distinguish it from a register-register-copy. */ | |
4897 if (XEXP (x, 1) == const0_rtx) | |
4898 return XEXP (x, 0); | |
4899 | |
4900 /* x - 0 is the same as x unless x's mode has signed zeros and | |
4901 allows rounding towards -infinity. Under those conditions, | |
4902 0 - 0 is -0. */ | |
4903 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0))) | |
4904 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0)))) | |
4905 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) | |
4906 return XEXP (x, 0); | |
4907 break; | |
4908 #endif | |
4909 | |
4910 case CONST: | |
4911 /* (const (const X)) can become (const X). Do it this way rather than | |
4912 returning the inner CONST since CONST can be shared with a | |
4913 REG_EQUAL note. */ | |
4914 if (GET_CODE (XEXP (x, 0)) == CONST) | |
4915 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4916 break; | |
4917 | |
4918 #ifdef HAVE_lo_sum | |
4919 case LO_SUM: | |
4920 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we | |
4921 can add in an offset. find_split_point will split this address up | |
4922 again if it doesn't match. */ | |
4923 if (GET_CODE (XEXP (x, 0)) == HIGH | |
4924 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) | |
4925 return XEXP (x, 1); | |
4926 break; | |
4927 #endif | |
4928 | |
4929 case PLUS: | |
4930 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) | |
4931 when c is (const_int (pow2 + 1) / 2) is a sign extension of a | |
4932 bit-field and can be replaced by either a sign_extend or a | |
4933 sign_extract. The `and' may be a zero_extend and the two | |
4934 <c>, -<c> constants may be reversed. */ | |
4935 if (GET_CODE (XEXP (x, 0)) == XOR | |
4936 && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4937 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
4938 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1)) | |
4939 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 | |
4940 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) | |
4941 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
4942 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND | |
4943 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
4944 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) | |
4945 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1)) | |
4946 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND | |
4947 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) | |
4948 == (unsigned int) i + 1)))) | |
4949 return simplify_shift_const | |
4950 (NULL_RTX, ASHIFTRT, mode, | |
4951 simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
4952 XEXP (XEXP (XEXP (x, 0), 0), 0), | |
4953 GET_MODE_BITSIZE (mode) - (i + 1)), | |
4954 GET_MODE_BITSIZE (mode) - (i + 1)); | |
4955 | |
4956 /* If only the low-order bit of X is possibly nonzero, (plus x -1) | |
4957 can become (ashiftrt (ashift (xor x 1) C) C) where C is | |
4958 the bitsize of the mode - 1. This allows simplification of | |
4959 "a = (b & 8) == 0;" */ | |
4960 if (XEXP (x, 1) == constm1_rtx | |
4961 && !REG_P (XEXP (x, 0)) | |
4962 && ! (GET_CODE (XEXP (x, 0)) == SUBREG | |
4963 && REG_P (SUBREG_REG (XEXP (x, 0)))) | |
4964 && nonzero_bits (XEXP (x, 0), mode) == 1) | |
4965 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, | |
4966 simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
4967 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx), | |
4968 GET_MODE_BITSIZE (mode) - 1), | |
4969 GET_MODE_BITSIZE (mode) - 1); | |
4970 | |
4971 /* If we are adding two things that have no bits in common, convert | |
4972 the addition into an IOR. This will often be further simplified, | |
4973 for example in cases like ((a & 1) + (a & 2)), which can | |
4974 become a & 3. */ | |
4975 | |
4976 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
4977 && (nonzero_bits (XEXP (x, 0), mode) | |
4978 & nonzero_bits (XEXP (x, 1), mode)) == 0) | |
4979 { | |
4980 /* Try to simplify the expression further. */ | |
4981 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); | |
4982 temp = combine_simplify_rtx (tor, mode, in_dest); | |
4983 | |
4984 /* If we could, great. If not, do not go ahead with the IOR | |
4985 replacement, since PLUS appears in many special purpose | |
4986 address arithmetic instructions. */ | |
4987 if (GET_CODE (temp) != CLOBBER && temp != tor) | |
4988 return temp; | |
4989 } | |
4990 break; | |
4991 | |
4992 case MINUS: | |
4993 /* (minus <foo> (and <foo> (const_int -pow2))) becomes | |
4994 (and <foo> (const_int pow2-1)) */ | |
4995 if (GET_CODE (XEXP (x, 1)) == AND | |
4996 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
4997 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 | |
4998 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) | |
4999 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), | |
5000 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1); | |
5001 break; | |
5002 | |
5003 case MULT: | |
5004 /* If we have (mult (plus A B) C), apply the distributive law and then | |
5005 the inverse distributive law to see if things simplify. This | |
5006 occurs mostly in addresses, often when unrolling loops. */ | |
5007 | |
5008 if (GET_CODE (XEXP (x, 0)) == PLUS) | |
5009 { | |
5010 rtx result = distribute_and_simplify_rtx (x, 0); | |
5011 if (result) | |
5012 return result; | |
5013 } | |
5014 | |
5015 /* Try simplify a*(b/c) as (a*b)/c. */ | |
5016 if (FLOAT_MODE_P (mode) && flag_associative_math | |
5017 && GET_CODE (XEXP (x, 0)) == DIV) | |
5018 { | |
5019 rtx tem = simplify_binary_operation (MULT, mode, | |
5020 XEXP (XEXP (x, 0), 0), | |
5021 XEXP (x, 1)); | |
5022 if (tem) | |
5023 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1)); | |
5024 } | |
5025 break; | |
5026 | |
5027 case UDIV: | |
5028 /* If this is a divide by a power of two, treat it as a shift if | |
5029 its first operand is a shift. */ | |
5030 if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5031 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 | |
5032 && (GET_CODE (XEXP (x, 0)) == ASHIFT | |
5033 || GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
5034 || GET_CODE (XEXP (x, 0)) == ASHIFTRT | |
5035 || GET_CODE (XEXP (x, 0)) == ROTATE | |
5036 || GET_CODE (XEXP (x, 0)) == ROTATERT)) | |
5037 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); | |
5038 break; | |
5039 | |
5040 case EQ: case NE: | |
5041 case GT: case GTU: case GE: case GEU: | |
5042 case LT: case LTU: case LE: case LEU: | |
5043 case UNEQ: case LTGT: | |
5044 case UNGT: case UNGE: | |
5045 case UNLT: case UNLE: | |
5046 case UNORDERED: case ORDERED: | |
5047 /* If the first operand is a condition code, we can't do anything | |
5048 with it. */ | |
5049 if (GET_CODE (XEXP (x, 0)) == COMPARE | |
5050 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC | |
5051 && ! CC0_P (XEXP (x, 0)))) | |
5052 { | |
5053 rtx op0 = XEXP (x, 0); | |
5054 rtx op1 = XEXP (x, 1); | |
5055 enum rtx_code new_code; | |
5056 | |
5057 if (GET_CODE (op0) == COMPARE) | |
5058 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
5059 | |
5060 /* Simplify our comparison, if possible. */ | |
5061 new_code = simplify_comparison (code, &op0, &op1); | |
5062 | |
5063 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X | |
5064 if only the low-order bit is possibly nonzero in X (such as when | |
5065 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to | |
5066 (xor X 1) or (minus 1 X); we use the former. Finally, if X is | |
5067 known to be either 0 or -1, NE becomes a NEG and EQ becomes | |
5068 (plus X 1). | |
5069 | |
5070 Remove any ZERO_EXTRACT we made when thinking this was a | |
5071 comparison. It may now be simpler to use, e.g., an AND. If a | |
5072 ZERO_EXTRACT is indeed appropriate, it will be placed back by | |
5073 the call to make_compound_operation in the SET case. */ | |
5074 | |
5075 if (STORE_FLAG_VALUE == 1 | |
5076 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
5077 && op1 == const0_rtx | |
5078 && mode == GET_MODE (op0) | |
5079 && nonzero_bits (op0, mode) == 1) | |
5080 return gen_lowpart (mode, | |
5081 expand_compound_operation (op0)); | |
5082 | |
5083 else if (STORE_FLAG_VALUE == 1 | |
5084 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
5085 && op1 == const0_rtx | |
5086 && mode == GET_MODE (op0) | |
5087 && (num_sign_bit_copies (op0, mode) | |
5088 == GET_MODE_BITSIZE (mode))) | |
5089 { | |
5090 op0 = expand_compound_operation (op0); | |
5091 return simplify_gen_unary (NEG, mode, | |
5092 gen_lowpart (mode, op0), | |
5093 mode); | |
5094 } | |
5095 | |
5096 else if (STORE_FLAG_VALUE == 1 | |
5097 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5098 && op1 == const0_rtx | |
5099 && mode == GET_MODE (op0) | |
5100 && nonzero_bits (op0, mode) == 1) | |
5101 { | |
5102 op0 = expand_compound_operation (op0); | |
5103 return simplify_gen_binary (XOR, mode, | |
5104 gen_lowpart (mode, op0), | |
5105 const1_rtx); | |
5106 } | |
5107 | |
5108 else if (STORE_FLAG_VALUE == 1 | |
5109 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5110 && op1 == const0_rtx | |
5111 && mode == GET_MODE (op0) | |
5112 && (num_sign_bit_copies (op0, mode) | |
5113 == GET_MODE_BITSIZE (mode))) | |
5114 { | |
5115 op0 = expand_compound_operation (op0); | |
5116 return plus_constant (gen_lowpart (mode, op0), 1); | |
5117 } | |
5118 | |
5119 /* If STORE_FLAG_VALUE is -1, we have cases similar to | |
5120 those above. */ | |
5121 if (STORE_FLAG_VALUE == -1 | |
5122 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
5123 && op1 == const0_rtx | |
5124 && (num_sign_bit_copies (op0, mode) | |
5125 == GET_MODE_BITSIZE (mode))) | |
5126 return gen_lowpart (mode, | |
5127 expand_compound_operation (op0)); | |
5128 | |
5129 else if (STORE_FLAG_VALUE == -1 | |
5130 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
5131 && op1 == const0_rtx | |
5132 && mode == GET_MODE (op0) | |
5133 && nonzero_bits (op0, mode) == 1) | |
5134 { | |
5135 op0 = expand_compound_operation (op0); | |
5136 return simplify_gen_unary (NEG, mode, | |
5137 gen_lowpart (mode, op0), | |
5138 mode); | |
5139 } | |
5140 | |
5141 else if (STORE_FLAG_VALUE == -1 | |
5142 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5143 && op1 == const0_rtx | |
5144 && mode == GET_MODE (op0) | |
5145 && (num_sign_bit_copies (op0, mode) | |
5146 == GET_MODE_BITSIZE (mode))) | |
5147 { | |
5148 op0 = expand_compound_operation (op0); | |
5149 return simplify_gen_unary (NOT, mode, | |
5150 gen_lowpart (mode, op0), | |
5151 mode); | |
5152 } | |
5153 | |
5154 /* If X is 0/1, (eq X 0) is X-1. */ | |
5155 else if (STORE_FLAG_VALUE == -1 | |
5156 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5157 && op1 == const0_rtx | |
5158 && mode == GET_MODE (op0) | |
5159 && nonzero_bits (op0, mode) == 1) | |
5160 { | |
5161 op0 = expand_compound_operation (op0); | |
5162 return plus_constant (gen_lowpart (mode, op0), -1); | |
5163 } | |
5164 | |
5165 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just | |
5166 one bit that might be nonzero, we can convert (ne x 0) to | |
5167 (ashift x c) where C puts the bit in the sign bit. Remove any | |
5168 AND with STORE_FLAG_VALUE when we are done, since we are only | |
5169 going to test the sign bit. */ | |
5170 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
5171 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5172 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) | |
5173 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) | |
5174 && op1 == const0_rtx | |
5175 && mode == GET_MODE (op0) | |
5176 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) | |
5177 { | |
5178 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
5179 expand_compound_operation (op0), | |
5180 GET_MODE_BITSIZE (mode) - 1 - i); | |
5181 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) | |
5182 return XEXP (x, 0); | |
5183 else | |
5184 return x; | |
5185 } | |
5186 | |
5187 /* If the code changed, return a whole new comparison. */ | |
5188 if (new_code != code) | |
5189 return gen_rtx_fmt_ee (new_code, mode, op0, op1); | |
5190 | |
5191 /* Otherwise, keep this operation, but maybe change its operands. | |
5192 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ | |
5193 SUBST (XEXP (x, 0), op0); | |
5194 SUBST (XEXP (x, 1), op1); | |
5195 } | |
5196 break; | |
5197 | |
5198 case IF_THEN_ELSE: | |
5199 return simplify_if_then_else (x); | |
5200 | |
5201 case ZERO_EXTRACT: | |
5202 case SIGN_EXTRACT: | |
5203 case ZERO_EXTEND: | |
5204 case SIGN_EXTEND: | |
5205 /* If we are processing SET_DEST, we are done. */ | |
5206 if (in_dest) | |
5207 return x; | |
5208 | |
5209 return expand_compound_operation (x); | |
5210 | |
5211 case SET: | |
5212 return simplify_set (x); | |
5213 | |
5214 case AND: | |
5215 case IOR: | |
5216 return simplify_logical (x); | |
5217 | |
5218 case ASHIFT: | |
5219 case LSHIFTRT: | |
5220 case ASHIFTRT: | |
5221 case ROTATE: | |
5222 case ROTATERT: | |
5223 /* If this is a shift by a constant amount, simplify it. */ | |
5224 if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5225 return simplify_shift_const (x, code, mode, XEXP (x, 0), | |
5226 INTVAL (XEXP (x, 1))); | |
5227 | |
5228 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1))) | |
5229 SUBST (XEXP (x, 1), | |
5230 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)), | |
5231 ((HOST_WIDE_INT) 1 | |
5232 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) | |
5233 - 1, | |
5234 0)); | |
5235 break; | |
5236 | |
5237 default: | |
5238 break; | |
5239 } | |
5240 | |
5241 return x; | |
5242 } | |
5243 | |
5244 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ | |
5245 | |
5246 static rtx | |
5247 simplify_if_then_else (rtx x) | |
5248 { | |
5249 enum machine_mode mode = GET_MODE (x); | |
5250 rtx cond = XEXP (x, 0); | |
5251 rtx true_rtx = XEXP (x, 1); | |
5252 rtx false_rtx = XEXP (x, 2); | |
5253 enum rtx_code true_code = GET_CODE (cond); | |
5254 int comparison_p = COMPARISON_P (cond); | |
5255 rtx temp; | |
5256 int i; | |
5257 enum rtx_code false_code; | |
5258 rtx reversed; | |
5259 | |
5260 /* Simplify storing of the truth value. */ | |
5261 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) | |
5262 return simplify_gen_relational (true_code, mode, VOIDmode, | |
5263 XEXP (cond, 0), XEXP (cond, 1)); | |
5264 | |
5265 /* Also when the truth value has to be reversed. */ | |
5266 if (comparison_p | |
5267 && true_rtx == const0_rtx && false_rtx == const_true_rtx | |
5268 && (reversed = reversed_comparison (cond, mode))) | |
5269 return reversed; | |
5270 | |
5271 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used | |
5272 in it is being compared against certain values. Get the true and false | |
5273 comparisons and see if that says anything about the value of each arm. */ | |
5274 | |
5275 if (comparison_p | |
5276 && ((false_code = reversed_comparison_code (cond, NULL)) | |
5277 != UNKNOWN) | |
5278 && REG_P (XEXP (cond, 0))) | |
5279 { | |
5280 HOST_WIDE_INT nzb; | |
5281 rtx from = XEXP (cond, 0); | |
5282 rtx true_val = XEXP (cond, 1); | |
5283 rtx false_val = true_val; | |
5284 int swapped = 0; | |
5285 | |
5286 /* If FALSE_CODE is EQ, swap the codes and arms. */ | |
5287 | |
5288 if (false_code == EQ) | |
5289 { | |
5290 swapped = 1, true_code = EQ, false_code = NE; | |
5291 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; | |
5292 } | |
5293 | |
5294 /* If we are comparing against zero and the expression being tested has | |
5295 only a single bit that might be nonzero, that is its value when it is | |
5296 not equal to zero. Similarly if it is known to be -1 or 0. */ | |
5297 | |
5298 if (true_code == EQ && true_val == const0_rtx | |
5299 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) | |
5300 { | |
5301 false_code = EQ; | |
5302 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from))); | |
5303 } | |
5304 else if (true_code == EQ && true_val == const0_rtx | |
5305 && (num_sign_bit_copies (from, GET_MODE (from)) | |
5306 == GET_MODE_BITSIZE (GET_MODE (from)))) | |
5307 { | |
5308 false_code = EQ; | |
5309 false_val = constm1_rtx; | |
5310 } | |
5311 | |
5312 /* Now simplify an arm if we know the value of the register in the | |
5313 branch and it is used in the arm. Be careful due to the potential | |
5314 of locally-shared RTL. */ | |
5315 | |
5316 if (reg_mentioned_p (from, true_rtx)) | |
5317 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, | |
5318 from, true_val), | |
5319 pc_rtx, pc_rtx, 0, 0); | |
5320 if (reg_mentioned_p (from, false_rtx)) | |
5321 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, | |
5322 from, false_val), | |
5323 pc_rtx, pc_rtx, 0, 0); | |
5324 | |
5325 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); | |
5326 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); | |
5327 | |
5328 true_rtx = XEXP (x, 1); | |
5329 false_rtx = XEXP (x, 2); | |
5330 true_code = GET_CODE (cond); | |
5331 } | |
5332 | |
5333 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be | |
5334 reversed, do so to avoid needing two sets of patterns for | |
5335 subtract-and-branch insns. Similarly if we have a constant in the true | |
5336 arm, the false arm is the same as the first operand of the comparison, or | |
5337 the false arm is more complicated than the true arm. */ | |
5338 | |
5339 if (comparison_p | |
5340 && reversed_comparison_code (cond, NULL) != UNKNOWN | |
5341 && (true_rtx == pc_rtx | |
5342 || (CONSTANT_P (true_rtx) | |
5343 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx) | |
5344 || true_rtx == const0_rtx | |
5345 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx)) | |
5346 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx)) | |
5347 && !OBJECT_P (false_rtx)) | |
5348 || reg_mentioned_p (true_rtx, false_rtx) | |
5349 || rtx_equal_p (false_rtx, XEXP (cond, 0)))) | |
5350 { | |
5351 true_code = reversed_comparison_code (cond, NULL); | |
5352 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond))); | |
5353 SUBST (XEXP (x, 1), false_rtx); | |
5354 SUBST (XEXP (x, 2), true_rtx); | |
5355 | |
5356 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; | |
5357 cond = XEXP (x, 0); | |
5358 | |
5359 /* It is possible that the conditional has been simplified out. */ | |
5360 true_code = GET_CODE (cond); | |
5361 comparison_p = COMPARISON_P (cond); | |
5362 } | |
5363 | |
5364 /* If the two arms are identical, we don't need the comparison. */ | |
5365 | |
5366 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond)) | |
5367 return true_rtx; | |
5368 | |
5369 /* Convert a == b ? b : a to "a". */ | |
5370 if (true_code == EQ && ! side_effects_p (cond) | |
5371 && !HONOR_NANS (mode) | |
5372 && rtx_equal_p (XEXP (cond, 0), false_rtx) | |
5373 && rtx_equal_p (XEXP (cond, 1), true_rtx)) | |
5374 return false_rtx; | |
5375 else if (true_code == NE && ! side_effects_p (cond) | |
5376 && !HONOR_NANS (mode) | |
5377 && rtx_equal_p (XEXP (cond, 0), true_rtx) | |
5378 && rtx_equal_p (XEXP (cond, 1), false_rtx)) | |
5379 return true_rtx; | |
5380 | |
5381 /* Look for cases where we have (abs x) or (neg (abs X)). */ | |
5382 | |
5383 if (GET_MODE_CLASS (mode) == MODE_INT | |
5384 && comparison_p | |
5385 && XEXP (cond, 1) == const0_rtx | |
5386 && GET_CODE (false_rtx) == NEG | |
5387 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0)) | |
5388 && rtx_equal_p (true_rtx, XEXP (cond, 0)) | |
5389 && ! side_effects_p (true_rtx)) | |
5390 switch (true_code) | |
5391 { | |
5392 case GT: | |
5393 case GE: | |
5394 return simplify_gen_unary (ABS, mode, true_rtx, mode); | |
5395 case LT: | |
5396 case LE: | |
5397 return | |
5398 simplify_gen_unary (NEG, mode, | |
5399 simplify_gen_unary (ABS, mode, true_rtx, mode), | |
5400 mode); | |
5401 default: | |
5402 break; | |
5403 } | |
5404 | |
5405 /* Look for MIN or MAX. */ | |
5406 | |
5407 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) | |
5408 && comparison_p | |
5409 && rtx_equal_p (XEXP (cond, 0), true_rtx) | |
5410 && rtx_equal_p (XEXP (cond, 1), false_rtx) | |
5411 && ! side_effects_p (cond)) | |
5412 switch (true_code) | |
5413 { | |
5414 case GE: | |
5415 case GT: | |
5416 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx); | |
5417 case LE: | |
5418 case LT: | |
5419 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx); | |
5420 case GEU: | |
5421 case GTU: | |
5422 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx); | |
5423 case LEU: | |
5424 case LTU: | |
5425 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx); | |
5426 default: | |
5427 break; | |
5428 } | |
5429 | |
5430 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its | |
5431 second operand is zero, this can be done as (OP Z (mult COND C2)) where | |
5432 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or | |
5433 SIGN_EXTEND as long as Z is already extended (so we don't destroy it). | |
5434 We can do this kind of thing in some cases when STORE_FLAG_VALUE is | |
5435 neither 1 or -1, but it isn't worth checking for. */ | |
5436 | |
5437 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
5438 && comparison_p | |
5439 && GET_MODE_CLASS (mode) == MODE_INT | |
5440 && ! side_effects_p (x)) | |
5441 { | |
5442 rtx t = make_compound_operation (true_rtx, SET); | |
5443 rtx f = make_compound_operation (false_rtx, SET); | |
5444 rtx cond_op0 = XEXP (cond, 0); | |
5445 rtx cond_op1 = XEXP (cond, 1); | |
5446 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN; | |
5447 enum machine_mode m = mode; | |
5448 rtx z = 0, c1 = NULL_RTX; | |
5449 | |
5450 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS | |
5451 || GET_CODE (t) == IOR || GET_CODE (t) == XOR | |
5452 || GET_CODE (t) == ASHIFT | |
5453 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) | |
5454 && rtx_equal_p (XEXP (t, 0), f)) | |
5455 c1 = XEXP (t, 1), op = GET_CODE (t), z = f; | |
5456 | |
5457 /* If an identity-zero op is commutative, check whether there | |
5458 would be a match if we swapped the operands. */ | |
5459 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR | |
5460 || GET_CODE (t) == XOR) | |
5461 && rtx_equal_p (XEXP (t, 1), f)) | |
5462 c1 = XEXP (t, 0), op = GET_CODE (t), z = f; | |
5463 else if (GET_CODE (t) == SIGN_EXTEND | |
5464 && (GET_CODE (XEXP (t, 0)) == PLUS | |
5465 || GET_CODE (XEXP (t, 0)) == MINUS | |
5466 || GET_CODE (XEXP (t, 0)) == IOR | |
5467 || GET_CODE (XEXP (t, 0)) == XOR | |
5468 || GET_CODE (XEXP (t, 0)) == ASHIFT | |
5469 || GET_CODE (XEXP (t, 0)) == LSHIFTRT | |
5470 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) | |
5471 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG | |
5472 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) | |
5473 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) | |
5474 && (num_sign_bit_copies (f, GET_MODE (f)) | |
5475 > (unsigned int) | |
5476 (GET_MODE_BITSIZE (mode) | |
5477 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0)))))) | |
5478 { | |
5479 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); | |
5480 extend_op = SIGN_EXTEND; | |
5481 m = GET_MODE (XEXP (t, 0)); | |
5482 } | |
5483 else if (GET_CODE (t) == SIGN_EXTEND | |
5484 && (GET_CODE (XEXP (t, 0)) == PLUS | |
5485 || GET_CODE (XEXP (t, 0)) == IOR | |
5486 || GET_CODE (XEXP (t, 0)) == XOR) | |
5487 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG | |
5488 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) | |
5489 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) | |
5490 && (num_sign_bit_copies (f, GET_MODE (f)) | |
5491 > (unsigned int) | |
5492 (GET_MODE_BITSIZE (mode) | |
5493 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1)))))) | |
5494 { | |
5495 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); | |
5496 extend_op = SIGN_EXTEND; | |
5497 m = GET_MODE (XEXP (t, 0)); | |
5498 } | |
5499 else if (GET_CODE (t) == ZERO_EXTEND | |
5500 && (GET_CODE (XEXP (t, 0)) == PLUS | |
5501 || GET_CODE (XEXP (t, 0)) == MINUS | |
5502 || GET_CODE (XEXP (t, 0)) == IOR | |
5503 || GET_CODE (XEXP (t, 0)) == XOR | |
5504 || GET_CODE (XEXP (t, 0)) == ASHIFT | |
5505 || GET_CODE (XEXP (t, 0)) == LSHIFTRT | |
5506 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) | |
5507 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG | |
5508 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5509 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) | |
5510 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) | |
5511 && ((nonzero_bits (f, GET_MODE (f)) | |
5512 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) | |
5513 == 0)) | |
5514 { | |
5515 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); | |
5516 extend_op = ZERO_EXTEND; | |
5517 m = GET_MODE (XEXP (t, 0)); | |
5518 } | |
5519 else if (GET_CODE (t) == ZERO_EXTEND | |
5520 && (GET_CODE (XEXP (t, 0)) == PLUS | |
5521 || GET_CODE (XEXP (t, 0)) == IOR | |
5522 || GET_CODE (XEXP (t, 0)) == XOR) | |
5523 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG | |
5524 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5525 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) | |
5526 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) | |
5527 && ((nonzero_bits (f, GET_MODE (f)) | |
5528 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) | |
5529 == 0)) | |
5530 { | |
5531 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); | |
5532 extend_op = ZERO_EXTEND; | |
5533 m = GET_MODE (XEXP (t, 0)); | |
5534 } | |
5535 | |
5536 if (z) | |
5537 { | |
5538 temp = subst (simplify_gen_relational (true_code, m, VOIDmode, | |
5539 cond_op0, cond_op1), | |
5540 pc_rtx, pc_rtx, 0, 0); | |
5541 temp = simplify_gen_binary (MULT, m, temp, | |
5542 simplify_gen_binary (MULT, m, c1, | |
5543 const_true_rtx)); | |
5544 temp = subst (temp, pc_rtx, pc_rtx, 0, 0); | |
5545 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); | |
5546 | |
5547 if (extend_op != UNKNOWN) | |
5548 temp = simplify_gen_unary (extend_op, mode, temp, m); | |
5549 | |
5550 return temp; | |
5551 } | |
5552 } | |
5553 | |
5554 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or | |
5555 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the | |
5556 negation of a single bit, we can convert this operation to a shift. We | |
5557 can actually do this more generally, but it doesn't seem worth it. */ | |
5558 | |
5559 if (true_code == NE && XEXP (cond, 1) == const0_rtx | |
5560 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT | |
5561 && ((1 == nonzero_bits (XEXP (cond, 0), mode) | |
5562 && (i = exact_log2 (INTVAL (true_rtx))) >= 0) | |
5563 || ((num_sign_bit_copies (XEXP (cond, 0), mode) | |
5564 == GET_MODE_BITSIZE (mode)) | |
5565 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0))) | |
5566 return | |
5567 simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
5568 gen_lowpart (mode, XEXP (cond, 0)), i); | |
5569 | |
5570 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */ | |
5571 if (true_code == NE && XEXP (cond, 1) == const0_rtx | |
5572 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT | |
5573 && GET_MODE (XEXP (cond, 0)) == mode | |
5574 && (INTVAL (true_rtx) & GET_MODE_MASK (mode)) | |
5575 == nonzero_bits (XEXP (cond, 0), mode) | |
5576 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0) | |
5577 return XEXP (cond, 0); | |
5578 | |
5579 return x; | |
5580 } | |
5581 | |
5582 /* Simplify X, a SET expression. Return the new expression. */ | |
5583 | |
5584 static rtx | |
5585 simplify_set (rtx x) | |
5586 { | |
5587 rtx src = SET_SRC (x); | |
5588 rtx dest = SET_DEST (x); | |
5589 enum machine_mode mode | |
5590 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); | |
5591 rtx other_insn; | |
5592 rtx *cc_use; | |
5593 | |
5594 /* (set (pc) (return)) gets written as (return). */ | |
5595 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN) | |
5596 return src; | |
5597 | |
5598 /* Now that we know for sure which bits of SRC we are using, see if we can | |
5599 simplify the expression for the object knowing that we only need the | |
5600 low-order bits. */ | |
5601 | |
5602 if (GET_MODE_CLASS (mode) == MODE_INT | |
5603 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
5604 { | |
5605 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0); | |
5606 SUBST (SET_SRC (x), src); | |
5607 } | |
5608 | |
5609 /* If we are setting CC0 or if the source is a COMPARE, look for the use of | |
5610 the comparison result and try to simplify it unless we already have used | |
5611 undobuf.other_insn. */ | |
5612 if ((GET_MODE_CLASS (mode) == MODE_CC | |
5613 || GET_CODE (src) == COMPARE | |
5614 || CC0_P (dest)) | |
5615 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 | |
5616 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) | |
5617 && COMPARISON_P (*cc_use) | |
5618 && rtx_equal_p (XEXP (*cc_use, 0), dest)) | |
5619 { | |
5620 enum rtx_code old_code = GET_CODE (*cc_use); | |
5621 enum rtx_code new_code; | |
5622 rtx op0, op1, tmp; | |
5623 int other_changed = 0; | |
5624 enum machine_mode compare_mode = GET_MODE (dest); | |
5625 | |
5626 if (GET_CODE (src) == COMPARE) | |
5627 op0 = XEXP (src, 0), op1 = XEXP (src, 1); | |
5628 else | |
5629 op0 = src, op1 = CONST0_RTX (GET_MODE (src)); | |
5630 | |
5631 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode, | |
5632 op0, op1); | |
5633 if (!tmp) | |
5634 new_code = old_code; | |
5635 else if (!CONSTANT_P (tmp)) | |
5636 { | |
5637 new_code = GET_CODE (tmp); | |
5638 op0 = XEXP (tmp, 0); | |
5639 op1 = XEXP (tmp, 1); | |
5640 } | |
5641 else | |
5642 { | |
5643 rtx pat = PATTERN (other_insn); | |
5644 undobuf.other_insn = other_insn; | |
5645 SUBST (*cc_use, tmp); | |
5646 | |
5647 /* Attempt to simplify CC user. */ | |
5648 if (GET_CODE (pat) == SET) | |
5649 { | |
5650 rtx new_rtx = simplify_rtx (SET_SRC (pat)); | |
5651 if (new_rtx != NULL_RTX) | |
5652 SUBST (SET_SRC (pat), new_rtx); | |
5653 } | |
5654 | |
5655 /* Convert X into a no-op move. */ | |
5656 SUBST (SET_DEST (x), pc_rtx); | |
5657 SUBST (SET_SRC (x), pc_rtx); | |
5658 return x; | |
5659 } | |
5660 | |
5661 /* Simplify our comparison, if possible. */ | |
5662 new_code = simplify_comparison (new_code, &op0, &op1); | |
5663 | |
5664 #ifdef SELECT_CC_MODE | |
5665 /* If this machine has CC modes other than CCmode, check to see if we | |
5666 need to use a different CC mode here. */ | |
5667 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) | |
5668 compare_mode = GET_MODE (op0); | |
5669 else | |
5670 compare_mode = SELECT_CC_MODE (new_code, op0, op1); | |
5671 | |
5672 #ifndef HAVE_cc0 | |
5673 /* If the mode changed, we have to change SET_DEST, the mode in the | |
5674 compare, and the mode in the place SET_DEST is used. If SET_DEST is | |
5675 a hard register, just build new versions with the proper mode. If it | |
5676 is a pseudo, we lose unless it is only time we set the pseudo, in | |
5677 which case we can safely change its mode. */ | |
5678 if (compare_mode != GET_MODE (dest)) | |
5679 { | |
5680 if (can_change_dest_mode (dest, 0, compare_mode)) | |
5681 { | |
5682 unsigned int regno = REGNO (dest); | |
5683 rtx new_dest; | |
5684 | |
5685 if (regno < FIRST_PSEUDO_REGISTER) | |
5686 new_dest = gen_rtx_REG (compare_mode, regno); | |
5687 else | |
5688 { | |
5689 SUBST_MODE (regno_reg_rtx[regno], compare_mode); | |
5690 new_dest = regno_reg_rtx[regno]; | |
5691 } | |
5692 | |
5693 SUBST (SET_DEST (x), new_dest); | |
5694 SUBST (XEXP (*cc_use, 0), new_dest); | |
5695 other_changed = 1; | |
5696 | |
5697 dest = new_dest; | |
5698 } | |
5699 } | |
5700 #endif /* cc0 */ | |
5701 #endif /* SELECT_CC_MODE */ | |
5702 | |
5703 /* If the code changed, we have to build a new comparison in | |
5704 undobuf.other_insn. */ | |
5705 if (new_code != old_code) | |
5706 { | |
5707 int other_changed_previously = other_changed; | |
5708 unsigned HOST_WIDE_INT mask; | |
5709 rtx old_cc_use = *cc_use; | |
5710 | |
5711 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use), | |
5712 dest, const0_rtx)); | |
5713 other_changed = 1; | |
5714 | |
5715 /* If the only change we made was to change an EQ into an NE or | |
5716 vice versa, OP0 has only one bit that might be nonzero, and OP1 | |
5717 is zero, check if changing the user of the condition code will | |
5718 produce a valid insn. If it won't, we can keep the original code | |
5719 in that insn by surrounding our operation with an XOR. */ | |
5720 | |
5721 if (((old_code == NE && new_code == EQ) | |
5722 || (old_code == EQ && new_code == NE)) | |
5723 && ! other_changed_previously && op1 == const0_rtx | |
5724 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT | |
5725 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) | |
5726 { | |
5727 rtx pat = PATTERN (other_insn), note = 0; | |
5728 | |
5729 if ((recog_for_combine (&pat, other_insn, ¬e) < 0 | |
5730 && ! check_asm_operands (pat))) | |
5731 { | |
5732 *cc_use = old_cc_use; | |
5733 other_changed = 0; | |
5734 | |
5735 op0 = simplify_gen_binary (XOR, GET_MODE (op0), | |
5736 op0, GEN_INT (mask)); | |
5737 } | |
5738 } | |
5739 } | |
5740 | |
5741 if (other_changed) | |
5742 undobuf.other_insn = other_insn; | |
5743 | |
5744 #ifdef HAVE_cc0 | |
5745 /* If we are now comparing against zero, change our source if | |
5746 needed. If we do not use cc0, we always have a COMPARE. */ | |
5747 if (op1 == const0_rtx && dest == cc0_rtx) | |
5748 { | |
5749 SUBST (SET_SRC (x), op0); | |
5750 src = op0; | |
5751 } | |
5752 else | |
5753 #endif | |
5754 | |
5755 /* Otherwise, if we didn't previously have a COMPARE in the | |
5756 correct mode, we need one. */ | |
5757 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) | |
5758 { | |
5759 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); | |
5760 src = SET_SRC (x); | |
5761 } | |
5762 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx) | |
5763 { | |
5764 SUBST (SET_SRC (x), op0); | |
5765 src = SET_SRC (x); | |
5766 } | |
5767 /* Otherwise, update the COMPARE if needed. */ | |
5768 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1) | |
5769 { | |
5770 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); | |
5771 src = SET_SRC (x); | |
5772 } | |
5773 } | |
5774 else | |
5775 { | |
5776 /* Get SET_SRC in a form where we have placed back any | |
5777 compound expressions. Then do the checks below. */ | |
5778 src = make_compound_operation (src, SET); | |
5779 SUBST (SET_SRC (x), src); | |
5780 } | |
5781 | |
5782 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, | |
5783 and X being a REG or (subreg (reg)), we may be able to convert this to | |
5784 (set (subreg:m2 x) (op)). | |
5785 | |
5786 We can always do this if M1 is narrower than M2 because that means that | |
5787 we only care about the low bits of the result. | |
5788 | |
5789 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot | |
5790 perform a narrower operation than requested since the high-order bits will | |
5791 be undefined. On machine where it is defined, this transformation is safe | |
5792 as long as M1 and M2 have the same number of words. */ | |
5793 | |
5794 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) | |
5795 && !OBJECT_P (SUBREG_REG (src)) | |
5796 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) | |
5797 / UNITS_PER_WORD) | |
5798 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) | |
5799 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
5800 #ifndef WORD_REGISTER_OPERATIONS | |
5801 && (GET_MODE_SIZE (GET_MODE (src)) | |
5802 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) | |
5803 #endif | |
5804 #ifdef CANNOT_CHANGE_MODE_CLASS | |
5805 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER | |
5806 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest), | |
5807 GET_MODE (SUBREG_REG (src)), | |
5808 GET_MODE (src))) | |
5809 #endif | |
5810 && (REG_P (dest) | |
5811 || (GET_CODE (dest) == SUBREG | |
5812 && REG_P (SUBREG_REG (dest))))) | |
5813 { | |
5814 SUBST (SET_DEST (x), | |
5815 gen_lowpart (GET_MODE (SUBREG_REG (src)), | |
5816 dest)); | |
5817 SUBST (SET_SRC (x), SUBREG_REG (src)); | |
5818 | |
5819 src = SET_SRC (x), dest = SET_DEST (x); | |
5820 } | |
5821 | |
5822 #ifdef HAVE_cc0 | |
5823 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg | |
5824 in SRC. */ | |
5825 if (dest == cc0_rtx | |
5826 && GET_CODE (src) == SUBREG | |
5827 && subreg_lowpart_p (src) | |
5828 && (GET_MODE_BITSIZE (GET_MODE (src)) | |
5829 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src))))) | |
5830 { | |
5831 rtx inner = SUBREG_REG (src); | |
5832 enum machine_mode inner_mode = GET_MODE (inner); | |
5833 | |
5834 /* Here we make sure that we don't have a sign bit on. */ | |
5835 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT | |
5836 && (nonzero_bits (inner, inner_mode) | |
5837 < ((unsigned HOST_WIDE_INT) 1 | |
5838 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1)))) | |
5839 { | |
5840 SUBST (SET_SRC (x), inner); | |
5841 src = SET_SRC (x); | |
5842 } | |
5843 } | |
5844 #endif | |
5845 | |
5846 #ifdef LOAD_EXTEND_OP | |
5847 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this | |
5848 would require a paradoxical subreg. Replace the subreg with a | |
5849 zero_extend to avoid the reload that would otherwise be required. */ | |
5850 | |
5851 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) | |
5852 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src))) | |
5853 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN | |
5854 && SUBREG_BYTE (src) == 0 | |
5855 && (GET_MODE_SIZE (GET_MODE (src)) | |
5856 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) | |
5857 && MEM_P (SUBREG_REG (src))) | |
5858 { | |
5859 SUBST (SET_SRC (x), | |
5860 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), | |
5861 GET_MODE (src), SUBREG_REG (src))); | |
5862 | |
5863 src = SET_SRC (x); | |
5864 } | |
5865 #endif | |
5866 | |
5867 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we | |
5868 are comparing an item known to be 0 or -1 against 0, use a logical | |
5869 operation instead. Check for one of the arms being an IOR of the other | |
5870 arm with some value. We compute three terms to be IOR'ed together. In | |
5871 practice, at most two will be nonzero. Then we do the IOR's. */ | |
5872 | |
5873 if (GET_CODE (dest) != PC | |
5874 && GET_CODE (src) == IF_THEN_ELSE | |
5875 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT | |
5876 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) | |
5877 && XEXP (XEXP (src, 0), 1) == const0_rtx | |
5878 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) | |
5879 #ifdef HAVE_conditional_move | |
5880 && ! can_conditionally_move_p (GET_MODE (src)) | |
5881 #endif | |
5882 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), | |
5883 GET_MODE (XEXP (XEXP (src, 0), 0))) | |
5884 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0)))) | |
5885 && ! side_effects_p (src)) | |
5886 { | |
5887 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE | |
5888 ? XEXP (src, 1) : XEXP (src, 2)); | |
5889 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE | |
5890 ? XEXP (src, 2) : XEXP (src, 1)); | |
5891 rtx term1 = const0_rtx, term2, term3; | |
5892 | |
5893 if (GET_CODE (true_rtx) == IOR | |
5894 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx)) | |
5895 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx; | |
5896 else if (GET_CODE (true_rtx) == IOR | |
5897 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx)) | |
5898 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx; | |
5899 else if (GET_CODE (false_rtx) == IOR | |
5900 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx)) | |
5901 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx; | |
5902 else if (GET_CODE (false_rtx) == IOR | |
5903 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx)) | |
5904 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx; | |
5905 | |
5906 term2 = simplify_gen_binary (AND, GET_MODE (src), | |
5907 XEXP (XEXP (src, 0), 0), true_rtx); | |
5908 term3 = simplify_gen_binary (AND, GET_MODE (src), | |
5909 simplify_gen_unary (NOT, GET_MODE (src), | |
5910 XEXP (XEXP (src, 0), 0), | |
5911 GET_MODE (src)), | |
5912 false_rtx); | |
5913 | |
5914 SUBST (SET_SRC (x), | |
5915 simplify_gen_binary (IOR, GET_MODE (src), | |
5916 simplify_gen_binary (IOR, GET_MODE (src), | |
5917 term1, term2), | |
5918 term3)); | |
5919 | |
5920 src = SET_SRC (x); | |
5921 } | |
5922 | |
5923 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this | |
5924 whole thing fail. */ | |
5925 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) | |
5926 return src; | |
5927 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) | |
5928 return dest; | |
5929 else | |
5930 /* Convert this into a field assignment operation, if possible. */ | |
5931 return make_field_assignment (x); | |
5932 } | |
5933 | |
5934 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified | |
5935 result. */ | |
5936 | |
5937 static rtx | |
5938 simplify_logical (rtx x) | |
5939 { | |
5940 enum machine_mode mode = GET_MODE (x); | |
5941 rtx op0 = XEXP (x, 0); | |
5942 rtx op1 = XEXP (x, 1); | |
5943 | |
5944 switch (GET_CODE (x)) | |
5945 { | |
5946 case AND: | |
5947 /* We can call simplify_and_const_int only if we don't lose | |
5948 any (sign) bits when converting INTVAL (op1) to | |
5949 "unsigned HOST_WIDE_INT". */ | |
5950 if (GET_CODE (op1) == CONST_INT | |
5951 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5952 || INTVAL (op1) > 0)) | |
5953 { | |
5954 x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); | |
5955 if (GET_CODE (x) != AND) | |
5956 return x; | |
5957 | |
5958 op0 = XEXP (x, 0); | |
5959 op1 = XEXP (x, 1); | |
5960 } | |
5961 | |
5962 /* If we have any of (and (ior A B) C) or (and (xor A B) C), | |
5963 apply the distributive law and then the inverse distributive | |
5964 law to see if things simplify. */ | |
5965 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) | |
5966 { | |
5967 rtx result = distribute_and_simplify_rtx (x, 0); | |
5968 if (result) | |
5969 return result; | |
5970 } | |
5971 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) | |
5972 { | |
5973 rtx result = distribute_and_simplify_rtx (x, 1); | |
5974 if (result) | |
5975 return result; | |
5976 } | |
5977 break; | |
5978 | |
5979 case IOR: | |
5980 /* If we have (ior (and A B) C), apply the distributive law and then | |
5981 the inverse distributive law to see if things simplify. */ | |
5982 | |
5983 if (GET_CODE (op0) == AND) | |
5984 { | |
5985 rtx result = distribute_and_simplify_rtx (x, 0); | |
5986 if (result) | |
5987 return result; | |
5988 } | |
5989 | |
5990 if (GET_CODE (op1) == AND) | |
5991 { | |
5992 rtx result = distribute_and_simplify_rtx (x, 1); | |
5993 if (result) | |
5994 return result; | |
5995 } | |
5996 break; | |
5997 | |
5998 default: | |
5999 gcc_unreachable (); | |
6000 } | |
6001 | |
6002 return x; | |
6003 } | |
6004 | |
6005 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound | |
6006 operations" because they can be replaced with two more basic operations. | |
6007 ZERO_EXTEND is also considered "compound" because it can be replaced with | |
6008 an AND operation, which is simpler, though only one operation. | |
6009 | |
6010 The function expand_compound_operation is called with an rtx expression | |
6011 and will convert it to the appropriate shifts and AND operations, | |
6012 simplifying at each stage. | |
6013 | |
6014 The function make_compound_operation is called to convert an expression | |
6015 consisting of shifts and ANDs into the equivalent compound expression. | |
6016 It is the inverse of this function, loosely speaking. */ | |
6017 | |
6018 static rtx | |
6019 expand_compound_operation (rtx x) | |
6020 { | |
6021 unsigned HOST_WIDE_INT pos = 0, len; | |
6022 int unsignedp = 0; | |
6023 unsigned int modewidth; | |
6024 rtx tem; | |
6025 | |
6026 switch (GET_CODE (x)) | |
6027 { | |
6028 case ZERO_EXTEND: | |
6029 unsignedp = 1; | |
6030 case SIGN_EXTEND: | |
6031 /* We can't necessarily use a const_int for a multiword mode; | |
6032 it depends on implicitly extending the value. | |
6033 Since we don't know the right way to extend it, | |
6034 we can't tell whether the implicit way is right. | |
6035 | |
6036 Even for a mode that is no wider than a const_int, | |
6037 we can't win, because we need to sign extend one of its bits through | |
6038 the rest of it, and we don't know which bit. */ | |
6039 if (GET_CODE (XEXP (x, 0)) == CONST_INT) | |
6040 return x; | |
6041 | |
6042 /* Return if (subreg:MODE FROM 0) is not a safe replacement for | |
6043 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM | |
6044 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be | |
6045 reloaded. If not for that, MEM's would very rarely be safe. | |
6046 | |
6047 Reject MODEs bigger than a word, because we might not be able | |
6048 to reference a two-register group starting with an arbitrary register | |
6049 (and currently gen_lowpart might crash for a SUBREG). */ | |
6050 | |
6051 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) | |
6052 return x; | |
6053 | |
6054 /* Reject MODEs that aren't scalar integers because turning vector | |
6055 or complex modes into shifts causes problems. */ | |
6056 | |
6057 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) | |
6058 return x; | |
6059 | |
6060 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); | |
6061 /* If the inner object has VOIDmode (the only way this can happen | |
6062 is if it is an ASM_OPERANDS), we can't do anything since we don't | |
6063 know how much masking to do. */ | |
6064 if (len == 0) | |
6065 return x; | |
6066 | |
6067 break; | |
6068 | |
6069 case ZERO_EXTRACT: | |
6070 unsignedp = 1; | |
6071 | |
6072 /* ... fall through ... */ | |
6073 | |
6074 case SIGN_EXTRACT: | |
6075 /* If the operand is a CLOBBER, just return it. */ | |
6076 if (GET_CODE (XEXP (x, 0)) == CLOBBER) | |
6077 return XEXP (x, 0); | |
6078 | |
6079 if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
6080 || GET_CODE (XEXP (x, 2)) != CONST_INT | |
6081 || GET_MODE (XEXP (x, 0)) == VOIDmode) | |
6082 return x; | |
6083 | |
6084 /* Reject MODEs that aren't scalar integers because turning vector | |
6085 or complex modes into shifts causes problems. */ | |
6086 | |
6087 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) | |
6088 return x; | |
6089 | |
6090 len = INTVAL (XEXP (x, 1)); | |
6091 pos = INTVAL (XEXP (x, 2)); | |
6092 | |
6093 /* This should stay within the object being extracted, fail otherwise. */ | |
6094 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) | |
6095 return x; | |
6096 | |
6097 if (BITS_BIG_ENDIAN) | |
6098 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; | |
6099 | |
6100 break; | |
6101 | |
6102 default: | |
6103 return x; | |
6104 } | |
6105 /* Convert sign extension to zero extension, if we know that the high | |
6106 bit is not set, as this is easier to optimize. It will be converted | |
6107 back to cheaper alternative in make_extraction. */ | |
6108 if (GET_CODE (x) == SIGN_EXTEND | |
6109 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
6110 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
6111 & ~(((unsigned HOST_WIDE_INT) | |
6112 GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) | |
6113 >> 1)) | |
6114 == 0))) | |
6115 { | |
6116 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0)); | |
6117 rtx temp2 = expand_compound_operation (temp); | |
6118 | |
6119 /* Make sure this is a profitable operation. */ | |
6120 if (rtx_cost (x, SET, optimize_this_for_speed_p) | |
6121 > rtx_cost (temp2, SET, optimize_this_for_speed_p)) | |
6122 return temp2; | |
6123 else if (rtx_cost (x, SET, optimize_this_for_speed_p) | |
6124 > rtx_cost (temp, SET, optimize_this_for_speed_p)) | |
6125 return temp; | |
6126 else | |
6127 return x; | |
6128 } | |
6129 | |
6130 /* We can optimize some special cases of ZERO_EXTEND. */ | |
6131 if (GET_CODE (x) == ZERO_EXTEND) | |
6132 { | |
6133 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we | |
6134 know that the last value didn't have any inappropriate bits | |
6135 set. */ | |
6136 if (GET_CODE (XEXP (x, 0)) == TRUNCATE | |
6137 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) | |
6138 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
6139 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) | |
6140 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) | |
6141 return XEXP (XEXP (x, 0), 0); | |
6142 | |
6143 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ | |
6144 if (GET_CODE (XEXP (x, 0)) == SUBREG | |
6145 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) | |
6146 && subreg_lowpart_p (XEXP (x, 0)) | |
6147 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
6148 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) | |
6149 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) | |
6150 return SUBREG_REG (XEXP (x, 0)); | |
6151 | |
6152 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo | |
6153 is a comparison and STORE_FLAG_VALUE permits. This is like | |
6154 the first case, but it works even when GET_MODE (x) is larger | |
6155 than HOST_WIDE_INT. */ | |
6156 if (GET_CODE (XEXP (x, 0)) == TRUNCATE | |
6157 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) | |
6158 && COMPARISON_P (XEXP (XEXP (x, 0), 0)) | |
6159 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) | |
6160 <= HOST_BITS_PER_WIDE_INT) | |
6161 && ((HOST_WIDE_INT) STORE_FLAG_VALUE | |
6162 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) | |
6163 return XEXP (XEXP (x, 0), 0); | |
6164 | |
6165 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ | |
6166 if (GET_CODE (XEXP (x, 0)) == SUBREG | |
6167 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) | |
6168 && subreg_lowpart_p (XEXP (x, 0)) | |
6169 && COMPARISON_P (SUBREG_REG (XEXP (x, 0))) | |
6170 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) | |
6171 <= HOST_BITS_PER_WIDE_INT) | |
6172 && ((HOST_WIDE_INT) STORE_FLAG_VALUE | |
6173 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) | |
6174 return SUBREG_REG (XEXP (x, 0)); | |
6175 | |
6176 } | |
6177 | |
6178 /* If we reach here, we want to return a pair of shifts. The inner | |
6179 shift is a left shift of BITSIZE - POS - LEN bits. The outer | |
6180 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or | |
6181 logical depending on the value of UNSIGNEDP. | |
6182 | |
6183 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be | |
6184 converted into an AND of a shift. | |
6185 | |
6186 We must check for the case where the left shift would have a negative | |
6187 count. This can happen in a case like (x >> 31) & 255 on machines | |
6188 that can't shift by a constant. On those machines, we would first | |
6189 combine the shift with the AND to produce a variable-position | |
6190 extraction. Then the constant of 31 would be substituted in to produce | |
6191 a such a position. */ | |
6192 | |
6193 modewidth = GET_MODE_BITSIZE (GET_MODE (x)); | |
6194 if (modewidth + len >= pos) | |
6195 { | |
6196 enum machine_mode mode = GET_MODE (x); | |
6197 tem = gen_lowpart (mode, XEXP (x, 0)); | |
6198 if (!tem || GET_CODE (tem) == CLOBBER) | |
6199 return x; | |
6200 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
6201 tem, modewidth - pos - len); | |
6202 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, | |
6203 mode, tem, modewidth - len); | |
6204 } | |
6205 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) | |
6206 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), | |
6207 simplify_shift_const (NULL_RTX, LSHIFTRT, | |
6208 GET_MODE (x), | |
6209 XEXP (x, 0), pos), | |
6210 ((HOST_WIDE_INT) 1 << len) - 1); | |
6211 else | |
6212 /* Any other cases we can't handle. */ | |
6213 return x; | |
6214 | |
6215 /* If we couldn't do this for some reason, return the original | |
6216 expression. */ | |
6217 if (GET_CODE (tem) == CLOBBER) | |
6218 return x; | |
6219 | |
6220 return tem; | |
6221 } | |
6222 | |
6223 /* X is a SET which contains an assignment of one object into | |
6224 a part of another (such as a bit-field assignment, STRICT_LOW_PART, | |
6225 or certain SUBREGS). If possible, convert it into a series of | |
6226 logical operations. | |
6227 | |
6228 We half-heartedly support variable positions, but do not at all | |
6229 support variable lengths. */ | |
6230 | |
6231 static const_rtx | |
6232 expand_field_assignment (const_rtx x) | |
6233 { | |
6234 rtx inner; | |
6235 rtx pos; /* Always counts from low bit. */ | |
6236 int len; | |
6237 rtx mask, cleared, masked; | |
6238 enum machine_mode compute_mode; | |
6239 | |
6240 /* Loop until we find something we can't simplify. */ | |
6241 while (1) | |
6242 { | |
6243 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART | |
6244 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) | |
6245 { | |
6246 inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); | |
6247 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); | |
6248 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0))); | |
6249 } | |
6250 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
6251 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) | |
6252 { | |
6253 inner = XEXP (SET_DEST (x), 0); | |
6254 len = INTVAL (XEXP (SET_DEST (x), 1)); | |
6255 pos = XEXP (SET_DEST (x), 2); | |
6256 | |
6257 /* A constant position should stay within the width of INNER. */ | |
6258 if (GET_CODE (pos) == CONST_INT | |
6259 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) | |
6260 break; | |
6261 | |
6262 if (BITS_BIG_ENDIAN) | |
6263 { | |
6264 if (GET_CODE (pos) == CONST_INT) | |
6265 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len | |
6266 - INTVAL (pos)); | |
6267 else if (GET_CODE (pos) == MINUS | |
6268 && GET_CODE (XEXP (pos, 1)) == CONST_INT | |
6269 && (INTVAL (XEXP (pos, 1)) | |
6270 == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) | |
6271 /* If position is ADJUST - X, new position is X. */ | |
6272 pos = XEXP (pos, 0); | |
6273 else | |
6274 pos = simplify_gen_binary (MINUS, GET_MODE (pos), | |
6275 GEN_INT (GET_MODE_BITSIZE ( | |
6276 GET_MODE (inner)) | |
6277 - len), | |
6278 pos); | |
6279 } | |
6280 } | |
6281 | |
6282 /* A SUBREG between two modes that occupy the same numbers of words | |
6283 can be done by moving the SUBREG to the source. */ | |
6284 else if (GET_CODE (SET_DEST (x)) == SUBREG | |
6285 /* We need SUBREGs to compute nonzero_bits properly. */ | |
6286 && nonzero_sign_valid | |
6287 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) | |
6288 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
6289 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
6290 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) | |
6291 { | |
6292 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)), | |
6293 gen_lowpart | |
6294 (GET_MODE (SUBREG_REG (SET_DEST (x))), | |
6295 SET_SRC (x))); | |
6296 continue; | |
6297 } | |
6298 else | |
6299 break; | |
6300 | |
6301 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) | |
6302 inner = SUBREG_REG (inner); | |
6303 | |
6304 compute_mode = GET_MODE (inner); | |
6305 | |
6306 /* Don't attempt bitwise arithmetic on non scalar integer modes. */ | |
6307 if (! SCALAR_INT_MODE_P (compute_mode)) | |
6308 { | |
6309 enum machine_mode imode; | |
6310 | |
6311 /* Don't do anything for vector or complex integral types. */ | |
6312 if (! FLOAT_MODE_P (compute_mode)) | |
6313 break; | |
6314 | |
6315 /* Try to find an integral mode to pun with. */ | |
6316 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); | |
6317 if (imode == BLKmode) | |
6318 break; | |
6319 | |
6320 compute_mode = imode; | |
6321 inner = gen_lowpart (imode, inner); | |
6322 } | |
6323 | |
6324 /* Compute a mask of LEN bits, if we can do this on the host machine. */ | |
6325 if (len >= HOST_BITS_PER_WIDE_INT) | |
6326 break; | |
6327 | |
6328 /* Now compute the equivalent expression. Make a copy of INNER | |
6329 for the SET_DEST in case it is a MEM into which we will substitute; | |
6330 we don't want shared RTL in that case. */ | |
6331 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1); | |
6332 cleared = simplify_gen_binary (AND, compute_mode, | |
6333 simplify_gen_unary (NOT, compute_mode, | |
6334 simplify_gen_binary (ASHIFT, | |
6335 compute_mode, | |
6336 mask, pos), | |
6337 compute_mode), | |
6338 inner); | |
6339 masked = simplify_gen_binary (ASHIFT, compute_mode, | |
6340 simplify_gen_binary ( | |
6341 AND, compute_mode, | |
6342 gen_lowpart (compute_mode, SET_SRC (x)), | |
6343 mask), | |
6344 pos); | |
6345 | |
6346 x = gen_rtx_SET (VOIDmode, copy_rtx (inner), | |
6347 simplify_gen_binary (IOR, compute_mode, | |
6348 cleared, masked)); | |
6349 } | |
6350 | |
6351 return x; | |
6352 } | |
6353 | |
6354 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, | |
6355 it is an RTX that represents a variable starting position; otherwise, | |
6356 POS is the (constant) starting bit position (counted from the LSB). | |
6357 | |
6358 UNSIGNEDP is nonzero for an unsigned reference and zero for a | |
6359 signed reference. | |
6360 | |
6361 IN_DEST is nonzero if this is a reference in the destination of a | |
6362 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero, | |
6363 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will | |
6364 be used. | |
6365 | |
6366 IN_COMPARE is nonzero if we are in a COMPARE. This means that a | |
6367 ZERO_EXTRACT should be built even for bits starting at bit 0. | |
6368 | |
6369 MODE is the desired mode of the result (if IN_DEST == 0). | |
6370 | |
6371 The result is an RTX for the extraction or NULL_RTX if the target | |
6372 can't handle it. */ | |
6373 | |
6374 static rtx | |
6375 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos, | |
6376 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp, | |
6377 int in_dest, int in_compare) | |
6378 { | |
6379 /* This mode describes the size of the storage area | |
6380 to fetch the overall value from. Within that, we | |
6381 ignore the POS lowest bits, etc. */ | |
6382 enum machine_mode is_mode = GET_MODE (inner); | |
6383 enum machine_mode inner_mode; | |
6384 enum machine_mode wanted_inner_mode; | |
6385 enum machine_mode wanted_inner_reg_mode = word_mode; | |
6386 enum machine_mode pos_mode = word_mode; | |
6387 enum machine_mode extraction_mode = word_mode; | |
6388 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); | |
6389 rtx new_rtx = 0; | |
6390 rtx orig_pos_rtx = pos_rtx; | |
6391 HOST_WIDE_INT orig_pos; | |
6392 | |
6393 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) | |
6394 { | |
6395 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), | |
6396 consider just the QI as the memory to extract from. | |
6397 The subreg adds or removes high bits; its mode is | |
6398 irrelevant to the meaning of this extraction, | |
6399 since POS and LEN count from the lsb. */ | |
6400 if (MEM_P (SUBREG_REG (inner))) | |
6401 is_mode = GET_MODE (SUBREG_REG (inner)); | |
6402 inner = SUBREG_REG (inner); | |
6403 } | |
6404 else if (GET_CODE (inner) == ASHIFT | |
6405 && GET_CODE (XEXP (inner, 1)) == CONST_INT | |
6406 && pos_rtx == 0 && pos == 0 | |
6407 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1))) | |
6408 { | |
6409 /* We're extracting the least significant bits of an rtx | |
6410 (ashift X (const_int C)), where LEN > C. Extract the | |
6411 least significant (LEN - C) bits of X, giving an rtx | |
6412 whose mode is MODE, then shift it left C times. */ | |
6413 new_rtx = make_extraction (mode, XEXP (inner, 0), | |
6414 0, 0, len - INTVAL (XEXP (inner, 1)), | |
6415 unsignedp, in_dest, in_compare); | |
6416 if (new_rtx != 0) | |
6417 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1)); | |
6418 } | |
6419 | |
6420 inner_mode = GET_MODE (inner); | |
6421 | |
6422 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) | |
6423 pos = INTVAL (pos_rtx), pos_rtx = 0; | |
6424 | |
6425 /* See if this can be done without an extraction. We never can if the | |
6426 width of the field is not the same as that of some integer mode. For | |
6427 registers, we can only avoid the extraction if the position is at the | |
6428 low-order bit and this is either not in the destination or we have the | |
6429 appropriate STRICT_LOW_PART operation available. | |
6430 | |
6431 For MEM, we can avoid an extract if the field starts on an appropriate | |
6432 boundary and we can change the mode of the memory reference. */ | |
6433 | |
6434 if (tmode != BLKmode | |
6435 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 | |
6436 && !MEM_P (inner) | |
6437 && (inner_mode == tmode | |
6438 || !REG_P (inner) | |
6439 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode), | |
6440 GET_MODE_BITSIZE (inner_mode)) | |
6441 || reg_truncated_to_mode (tmode, inner)) | |
6442 && (! in_dest | |
6443 || (REG_P (inner) | |
6444 && have_insn_for (STRICT_LOW_PART, tmode)))) | |
6445 || (MEM_P (inner) && pos_rtx == 0 | |
6446 && (pos | |
6447 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) | |
6448 : BITS_PER_UNIT)) == 0 | |
6449 /* We can't do this if we are widening INNER_MODE (it | |
6450 may not be aligned, for one thing). */ | |
6451 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) | |
6452 && (inner_mode == tmode | |
6453 || (! mode_dependent_address_p (XEXP (inner, 0)) | |
6454 && ! MEM_VOLATILE_P (inner)))))) | |
6455 { | |
6456 /* If INNER is a MEM, make a new MEM that encompasses just the desired | |
6457 field. If the original and current mode are the same, we need not | |
6458 adjust the offset. Otherwise, we do if bytes big endian. | |
6459 | |
6460 If INNER is not a MEM, get a piece consisting of just the field | |
6461 of interest (in this case POS % BITS_PER_WORD must be 0). */ | |
6462 | |
6463 if (MEM_P (inner)) | |
6464 { | |
6465 HOST_WIDE_INT offset; | |
6466 | |
6467 /* POS counts from lsb, but make OFFSET count in memory order. */ | |
6468 if (BYTES_BIG_ENDIAN) | |
6469 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT; | |
6470 else | |
6471 offset = pos / BITS_PER_UNIT; | |
6472 | |
6473 new_rtx = adjust_address_nv (inner, tmode, offset); | |
6474 } | |
6475 else if (REG_P (inner)) | |
6476 { | |
6477 if (tmode != inner_mode) | |
6478 { | |
6479 /* We can't call gen_lowpart in a DEST since we | |
6480 always want a SUBREG (see below) and it would sometimes | |
6481 return a new hard register. */ | |
6482 if (pos || in_dest) | |
6483 { | |
6484 HOST_WIDE_INT final_word = pos / BITS_PER_WORD; | |
6485 | |
6486 if (WORDS_BIG_ENDIAN | |
6487 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD) | |
6488 final_word = ((GET_MODE_SIZE (inner_mode) | |
6489 - GET_MODE_SIZE (tmode)) | |
6490 / UNITS_PER_WORD) - final_word; | |
6491 | |
6492 final_word *= UNITS_PER_WORD; | |
6493 if (BYTES_BIG_ENDIAN && | |
6494 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode)) | |
6495 final_word += (GET_MODE_SIZE (inner_mode) | |
6496 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD; | |
6497 | |
6498 /* Avoid creating invalid subregs, for example when | |
6499 simplifying (x>>32)&255. */ | |
6500 if (!validate_subreg (tmode, inner_mode, inner, final_word)) | |
6501 return NULL_RTX; | |
6502 | |
6503 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word); | |
6504 } | |
6505 else | |
6506 new_rtx = gen_lowpart (tmode, inner); | |
6507 } | |
6508 else | |
6509 new_rtx = inner; | |
6510 } | |
6511 else | |
6512 new_rtx = force_to_mode (inner, tmode, | |
6513 len >= HOST_BITS_PER_WIDE_INT | |
6514 ? ~(unsigned HOST_WIDE_INT) 0 | |
6515 : ((unsigned HOST_WIDE_INT) 1 << len) - 1, | |
6516 0); | |
6517 | |
6518 /* If this extraction is going into the destination of a SET, | |
6519 make a STRICT_LOW_PART unless we made a MEM. */ | |
6520 | |
6521 if (in_dest) | |
6522 return (MEM_P (new_rtx) ? new_rtx | |
6523 : (GET_CODE (new_rtx) != SUBREG | |
6524 ? gen_rtx_CLOBBER (tmode, const0_rtx) | |
6525 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx))); | |
6526 | |
6527 if (mode == tmode) | |
6528 return new_rtx; | |
6529 | |
6530 if (GET_CODE (new_rtx) == CONST_INT) | |
6531 return gen_int_mode (INTVAL (new_rtx), mode); | |
6532 | |
6533 /* If we know that no extraneous bits are set, and that the high | |
6534 bit is not set, convert the extraction to the cheaper of | |
6535 sign and zero extension, that are equivalent in these cases. */ | |
6536 if (flag_expensive_optimizations | |
6537 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT | |
6538 && ((nonzero_bits (new_rtx, tmode) | |
6539 & ~(((unsigned HOST_WIDE_INT) | |
6540 GET_MODE_MASK (tmode)) | |
6541 >> 1)) | |
6542 == 0))) | |
6543 { | |
6544 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx); | |
6545 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx); | |
6546 | |
6547 /* Prefer ZERO_EXTENSION, since it gives more information to | |
6548 backends. */ | |
6549 if (rtx_cost (temp, SET, optimize_this_for_speed_p) | |
6550 <= rtx_cost (temp1, SET, optimize_this_for_speed_p)) | |
6551 return temp; | |
6552 return temp1; | |
6553 } | |
6554 | |
6555 /* Otherwise, sign- or zero-extend unless we already are in the | |
6556 proper mode. */ | |
6557 | |
6558 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, | |
6559 mode, new_rtx)); | |
6560 } | |
6561 | |
6562 /* Unless this is a COMPARE or we have a funny memory reference, | |
6563 don't do anything with zero-extending field extracts starting at | |
6564 the low-order bit since they are simple AND operations. */ | |
6565 if (pos_rtx == 0 && pos == 0 && ! in_dest | |
6566 && ! in_compare && unsignedp) | |
6567 return 0; | |
6568 | |
6569 /* Unless INNER is not MEM, reject this if we would be spanning bytes or | |
6570 if the position is not a constant and the length is not 1. In all | |
6571 other cases, we would only be going outside our object in cases when | |
6572 an original shift would have been undefined. */ | |
6573 if (MEM_P (inner) | |
6574 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode)) | |
6575 || (pos_rtx != 0 && len != 1))) | |
6576 return 0; | |
6577 | |
6578 /* Get the mode to use should INNER not be a MEM, the mode for the position, | |
6579 and the mode for the result. */ | |
6580 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE) | |
6581 { | |
6582 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0); | |
6583 pos_mode = mode_for_extraction (EP_insv, 2); | |
6584 extraction_mode = mode_for_extraction (EP_insv, 3); | |
6585 } | |
6586 | |
6587 if (! in_dest && unsignedp | |
6588 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE) | |
6589 { | |
6590 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1); | |
6591 pos_mode = mode_for_extraction (EP_extzv, 3); | |
6592 extraction_mode = mode_for_extraction (EP_extzv, 0); | |
6593 } | |
6594 | |
6595 if (! in_dest && ! unsignedp | |
6596 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE) | |
6597 { | |
6598 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1); | |
6599 pos_mode = mode_for_extraction (EP_extv, 3); | |
6600 extraction_mode = mode_for_extraction (EP_extv, 0); | |
6601 } | |
6602 | |
6603 /* Never narrow an object, since that might not be safe. */ | |
6604 | |
6605 if (mode != VOIDmode | |
6606 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) | |
6607 extraction_mode = mode; | |
6608 | |
6609 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode | |
6610 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) | |
6611 pos_mode = GET_MODE (pos_rtx); | |
6612 | |
6613 /* If this is not from memory, the desired mode is the preferred mode | |
6614 for an extraction pattern's first input operand, or word_mode if there | |
6615 is none. */ | |
6616 if (!MEM_P (inner)) | |
6617 wanted_inner_mode = wanted_inner_reg_mode; | |
6618 else | |
6619 { | |
6620 /* Be careful not to go beyond the extracted object and maintain the | |
6621 natural alignment of the memory. */ | |
6622 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT); | |
6623 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len | |
6624 > GET_MODE_BITSIZE (wanted_inner_mode)) | |
6625 { | |
6626 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode); | |
6627 gcc_assert (wanted_inner_mode != VOIDmode); | |
6628 } | |
6629 | |
6630 /* If we have to change the mode of memory and cannot, the desired mode | |
6631 is EXTRACTION_MODE. */ | |
6632 if (inner_mode != wanted_inner_mode | |
6633 && (mode_dependent_address_p (XEXP (inner, 0)) | |
6634 || MEM_VOLATILE_P (inner) | |
6635 || pos_rtx)) | |
6636 wanted_inner_mode = extraction_mode; | |
6637 } | |
6638 | |
6639 orig_pos = pos; | |
6640 | |
6641 if (BITS_BIG_ENDIAN) | |
6642 { | |
6643 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to | |
6644 BITS_BIG_ENDIAN style. If position is constant, compute new | |
6645 position. Otherwise, build subtraction. | |
6646 Note that POS is relative to the mode of the original argument. | |
6647 If it's a MEM we need to recompute POS relative to that. | |
6648 However, if we're extracting from (or inserting into) a register, | |
6649 we want to recompute POS relative to wanted_inner_mode. */ | |
6650 int width = (MEM_P (inner) | |
6651 ? GET_MODE_BITSIZE (is_mode) | |
6652 : GET_MODE_BITSIZE (wanted_inner_mode)); | |
6653 | |
6654 if (pos_rtx == 0) | |
6655 pos = width - len - pos; | |
6656 else | |
6657 pos_rtx | |
6658 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx); | |
6659 /* POS may be less than 0 now, but we check for that below. | |
6660 Note that it can only be less than 0 if !MEM_P (inner). */ | |
6661 } | |
6662 | |
6663 /* If INNER has a wider mode, and this is a constant extraction, try to | |
6664 make it smaller and adjust the byte to point to the byte containing | |
6665 the value. */ | |
6666 if (wanted_inner_mode != VOIDmode | |
6667 && inner_mode != wanted_inner_mode | |
6668 && ! pos_rtx | |
6669 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) | |
6670 && MEM_P (inner) | |
6671 && ! mode_dependent_address_p (XEXP (inner, 0)) | |
6672 && ! MEM_VOLATILE_P (inner)) | |
6673 { | |
6674 int offset = 0; | |
6675 | |
6676 /* The computations below will be correct if the machine is big | |
6677 endian in both bits and bytes or little endian in bits and bytes. | |
6678 If it is mixed, we must adjust. */ | |
6679 | |
6680 /* If bytes are big endian and we had a paradoxical SUBREG, we must | |
6681 adjust OFFSET to compensate. */ | |
6682 if (BYTES_BIG_ENDIAN | |
6683 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) | |
6684 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); | |
6685 | |
6686 /* We can now move to the desired byte. */ | |
6687 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode)) | |
6688 * GET_MODE_SIZE (wanted_inner_mode); | |
6689 pos %= GET_MODE_BITSIZE (wanted_inner_mode); | |
6690 | |
6691 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN | |
6692 && is_mode != wanted_inner_mode) | |
6693 offset = (GET_MODE_SIZE (is_mode) | |
6694 - GET_MODE_SIZE (wanted_inner_mode) - offset); | |
6695 | |
6696 inner = adjust_address_nv (inner, wanted_inner_mode, offset); | |
6697 } | |
6698 | |
6699 /* If INNER is not memory, we can always get it into the proper mode. If we | |
6700 are changing its mode, POS must be a constant and smaller than the size | |
6701 of the new mode. */ | |
6702 else if (!MEM_P (inner)) | |
6703 { | |
6704 if (GET_MODE (inner) != wanted_inner_mode | |
6705 && (pos_rtx != 0 | |
6706 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) | |
6707 return 0; | |
6708 | |
6709 if (orig_pos < 0) | |
6710 return 0; | |
6711 | |
6712 inner = force_to_mode (inner, wanted_inner_mode, | |
6713 pos_rtx | |
6714 || len + orig_pos >= HOST_BITS_PER_WIDE_INT | |
6715 ? ~(unsigned HOST_WIDE_INT) 0 | |
6716 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1) | |
6717 << orig_pos), | |
6718 0); | |
6719 } | |
6720 | |
6721 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we | |
6722 have to zero extend. Otherwise, we can just use a SUBREG. */ | |
6723 if (pos_rtx != 0 | |
6724 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) | |
6725 { | |
6726 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx); | |
6727 | |
6728 /* If we know that no extraneous bits are set, and that the high | |
6729 bit is not set, convert extraction to cheaper one - either | |
6730 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these | |
6731 cases. */ | |
6732 if (flag_expensive_optimizations | |
6733 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT | |
6734 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx)) | |
6735 & ~(((unsigned HOST_WIDE_INT) | |
6736 GET_MODE_MASK (GET_MODE (pos_rtx))) | |
6737 >> 1)) | |
6738 == 0))) | |
6739 { | |
6740 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx); | |
6741 | |
6742 /* Prefer ZERO_EXTENSION, since it gives more information to | |
6743 backends. */ | |
6744 if (rtx_cost (temp1, SET, optimize_this_for_speed_p) | |
6745 < rtx_cost (temp, SET, optimize_this_for_speed_p)) | |
6746 temp = temp1; | |
6747 } | |
6748 pos_rtx = temp; | |
6749 } | |
6750 else if (pos_rtx != 0 | |
6751 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) | |
6752 pos_rtx = gen_lowpart (pos_mode, pos_rtx); | |
6753 | |
6754 /* Make POS_RTX unless we already have it and it is correct. If we don't | |
6755 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must | |
6756 be a CONST_INT. */ | |
6757 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) | |
6758 pos_rtx = orig_pos_rtx; | |
6759 | |
6760 else if (pos_rtx == 0) | |
6761 pos_rtx = GEN_INT (pos); | |
6762 | |
6763 /* Make the required operation. See if we can use existing rtx. */ | |
6764 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, | |
6765 extraction_mode, inner, GEN_INT (len), pos_rtx); | |
6766 if (! in_dest) | |
6767 new_rtx = gen_lowpart (mode, new_rtx); | |
6768 | |
6769 return new_rtx; | |
6770 } | |
6771 | |
6772 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted | |
6773 with any other operations in X. Return X without that shift if so. */ | |
6774 | |
6775 static rtx | |
6776 extract_left_shift (rtx x, int count) | |
6777 { | |
6778 enum rtx_code code = GET_CODE (x); | |
6779 enum machine_mode mode = GET_MODE (x); | |
6780 rtx tem; | |
6781 | |
6782 switch (code) | |
6783 { | |
6784 case ASHIFT: | |
6785 /* This is the shift itself. If it is wide enough, we will return | |
6786 either the value being shifted if the shift count is equal to | |
6787 COUNT or a shift for the difference. */ | |
6788 if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6789 && INTVAL (XEXP (x, 1)) >= count) | |
6790 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), | |
6791 INTVAL (XEXP (x, 1)) - count); | |
6792 break; | |
6793 | |
6794 case NEG: case NOT: | |
6795 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) | |
6796 return simplify_gen_unary (code, mode, tem, mode); | |
6797 | |
6798 break; | |
6799 | |
6800 case PLUS: case IOR: case XOR: case AND: | |
6801 /* If we can safely shift this constant and we find the inner shift, | |
6802 make a new operation. */ | |
6803 if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6804 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0 | |
6805 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) | |
6806 return simplify_gen_binary (code, mode, tem, | |
6807 GEN_INT (INTVAL (XEXP (x, 1)) >> count)); | |
6808 | |
6809 break; | |
6810 | |
6811 default: | |
6812 break; | |
6813 } | |
6814 | |
6815 return 0; | |
6816 } | |
6817 | |
6818 /* Look at the expression rooted at X. Look for expressions | |
6819 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. | |
6820 Form these expressions. | |
6821 | |
6822 Return the new rtx, usually just X. | |
6823 | |
6824 Also, for machines like the VAX that don't have logical shift insns, | |
6825 try to convert logical to arithmetic shift operations in cases where | |
6826 they are equivalent. This undoes the canonicalizations to logical | |
6827 shifts done elsewhere. | |
6828 | |
6829 We try, as much as possible, to re-use rtl expressions to save memory. | |
6830 | |
6831 IN_CODE says what kind of expression we are processing. Normally, it is | |
6832 SET. In a memory address (inside a MEM, PLUS or minus, the latter two | |
6833 being kludges), it is MEM. When processing the arguments of a comparison | |
6834 or a COMPARE against zero, it is COMPARE. */ | |
6835 | |
6836 static rtx | |
6837 make_compound_operation (rtx x, enum rtx_code in_code) | |
6838 { | |
6839 enum rtx_code code = GET_CODE (x); | |
6840 enum machine_mode mode = GET_MODE (x); | |
6841 int mode_width = GET_MODE_BITSIZE (mode); | |
6842 rtx rhs, lhs; | |
6843 enum rtx_code next_code; | |
6844 int i, j; | |
6845 rtx new_rtx = 0; | |
6846 rtx tem; | |
6847 const char *fmt; | |
6848 | |
6849 /* Select the code to be used in recursive calls. Once we are inside an | |
6850 address, we stay there. If we have a comparison, set to COMPARE, | |
6851 but once inside, go back to our default of SET. */ | |
6852 | |
6853 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM | |
6854 : ((code == COMPARE || COMPARISON_P (x)) | |
6855 && XEXP (x, 1) == const0_rtx) ? COMPARE | |
6856 : in_code == COMPARE ? SET : in_code); | |
6857 | |
6858 /* Process depending on the code of this operation. If NEW is set | |
6859 nonzero, it will be returned. */ | |
6860 | |
6861 switch (code) | |
6862 { | |
6863 case ASHIFT: | |
6864 /* Convert shifts by constants into multiplications if inside | |
6865 an address. */ | |
6866 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT | |
6867 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT | |
6868 && INTVAL (XEXP (x, 1)) >= 0) | |
6869 { | |
6870 new_rtx = make_compound_operation (XEXP (x, 0), next_code); | |
6871 new_rtx = gen_rtx_MULT (mode, new_rtx, | |
6872 GEN_INT ((HOST_WIDE_INT) 1 | |
6873 << INTVAL (XEXP (x, 1)))); | |
6874 } | |
6875 break; | |
6876 | |
6877 case AND: | |
6878 /* If the second operand is not a constant, we can't do anything | |
6879 with it. */ | |
6880 if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
6881 break; | |
6882 | |
6883 /* If the constant is a power of two minus one and the first operand | |
6884 is a logical right shift, make an extraction. */ | |
6885 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
6886 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
6887 { | |
6888 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); | |
6889 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1, | |
6890 0, in_code == COMPARE); | |
6891 } | |
6892 | |
6893 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ | |
6894 else if (GET_CODE (XEXP (x, 0)) == SUBREG | |
6895 && subreg_lowpart_p (XEXP (x, 0)) | |
6896 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT | |
6897 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
6898 { | |
6899 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), | |
6900 next_code); | |
6901 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0, | |
6902 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, | |
6903 0, in_code == COMPARE); | |
6904 } | |
6905 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ | |
6906 else if ((GET_CODE (XEXP (x, 0)) == XOR | |
6907 || GET_CODE (XEXP (x, 0)) == IOR) | |
6908 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT | |
6909 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT | |
6910 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
6911 { | |
6912 /* Apply the distributive law, and then try to make extractions. */ | |
6913 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode, | |
6914 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), | |
6915 XEXP (x, 1)), | |
6916 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), | |
6917 XEXP (x, 1))); | |
6918 new_rtx = make_compound_operation (new_rtx, in_code); | |
6919 } | |
6920 | |
6921 /* If we are have (and (rotate X C) M) and C is larger than the number | |
6922 of bits in M, this is an extraction. */ | |
6923 | |
6924 else if (GET_CODE (XEXP (x, 0)) == ROTATE | |
6925 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
6926 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 | |
6927 && i <= INTVAL (XEXP (XEXP (x, 0), 1))) | |
6928 { | |
6929 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); | |
6930 new_rtx = make_extraction (mode, new_rtx, | |
6931 (GET_MODE_BITSIZE (mode) | |
6932 - INTVAL (XEXP (XEXP (x, 0), 1))), | |
6933 NULL_RTX, i, 1, 0, in_code == COMPARE); | |
6934 } | |
6935 | |
6936 /* On machines without logical shifts, if the operand of the AND is | |
6937 a logical shift and our mask turns off all the propagated sign | |
6938 bits, we can replace the logical shift with an arithmetic shift. */ | |
6939 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
6940 && !have_insn_for (LSHIFTRT, mode) | |
6941 && have_insn_for (ASHIFTRT, mode) | |
6942 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
6943 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
6944 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT | |
6945 && mode_width <= HOST_BITS_PER_WIDE_INT) | |
6946 { | |
6947 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); | |
6948 | |
6949 mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); | |
6950 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) | |
6951 SUBST (XEXP (x, 0), | |
6952 gen_rtx_ASHIFTRT (mode, | |
6953 make_compound_operation | |
6954 (XEXP (XEXP (x, 0), 0), next_code), | |
6955 XEXP (XEXP (x, 0), 1))); | |
6956 } | |
6957 | |
6958 /* If the constant is one less than a power of two, this might be | |
6959 representable by an extraction even if no shift is present. | |
6960 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless | |
6961 we are in a COMPARE. */ | |
6962 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
6963 new_rtx = make_extraction (mode, | |
6964 make_compound_operation (XEXP (x, 0), | |
6965 next_code), | |
6966 0, NULL_RTX, i, 1, 0, in_code == COMPARE); | |
6967 | |
6968 /* If we are in a comparison and this is an AND with a power of two, | |
6969 convert this into the appropriate bit extract. */ | |
6970 else if (in_code == COMPARE | |
6971 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) | |
6972 new_rtx = make_extraction (mode, | |
6973 make_compound_operation (XEXP (x, 0), | |
6974 next_code), | |
6975 i, NULL_RTX, 1, 1, 0, 1); | |
6976 | |
6977 break; | |
6978 | |
6979 case LSHIFTRT: | |
6980 /* If the sign bit is known to be zero, replace this with an | |
6981 arithmetic shift. */ | |
6982 if (have_insn_for (ASHIFTRT, mode) | |
6983 && ! have_insn_for (LSHIFTRT, mode) | |
6984 && mode_width <= HOST_BITS_PER_WIDE_INT | |
6985 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) | |
6986 { | |
6987 new_rtx = gen_rtx_ASHIFTRT (mode, | |
6988 make_compound_operation (XEXP (x, 0), | |
6989 next_code), | |
6990 XEXP (x, 1)); | |
6991 break; | |
6992 } | |
6993 | |
6994 /* ... fall through ... */ | |
6995 | |
6996 case ASHIFTRT: | |
6997 lhs = XEXP (x, 0); | |
6998 rhs = XEXP (x, 1); | |
6999 | |
7000 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, | |
7001 this is a SIGN_EXTRACT. */ | |
7002 if (GET_CODE (rhs) == CONST_INT | |
7003 && GET_CODE (lhs) == ASHIFT | |
7004 && GET_CODE (XEXP (lhs, 1)) == CONST_INT | |
7005 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)) | |
7006 && INTVAL (rhs) < mode_width) | |
7007 { | |
7008 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code); | |
7009 new_rtx = make_extraction (mode, new_rtx, | |
7010 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), | |
7011 NULL_RTX, mode_width - INTVAL (rhs), | |
7012 code == LSHIFTRT, 0, in_code == COMPARE); | |
7013 break; | |
7014 } | |
7015 | |
7016 /* See if we have operations between an ASHIFTRT and an ASHIFT. | |
7017 If so, try to merge the shifts into a SIGN_EXTEND. We could | |
7018 also do this for some cases of SIGN_EXTRACT, but it doesn't | |
7019 seem worth the effort; the case checked for occurs on Alpha. */ | |
7020 | |
7021 if (!OBJECT_P (lhs) | |
7022 && ! (GET_CODE (lhs) == SUBREG | |
7023 && (OBJECT_P (SUBREG_REG (lhs)))) | |
7024 && GET_CODE (rhs) == CONST_INT | |
7025 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT | |
7026 && INTVAL (rhs) < mode_width | |
7027 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0) | |
7028 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code), | |
7029 0, NULL_RTX, mode_width - INTVAL (rhs), | |
7030 code == LSHIFTRT, 0, in_code == COMPARE); | |
7031 | |
7032 break; | |
7033 | |
7034 case SUBREG: | |
7035 /* Call ourselves recursively on the inner expression. If we are | |
7036 narrowing the object and it has a different RTL code from | |
7037 what it originally did, do this SUBREG as a force_to_mode. */ | |
7038 | |
7039 tem = make_compound_operation (SUBREG_REG (x), in_code); | |
7040 | |
7041 { | |
7042 rtx simplified; | |
7043 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem), | |
7044 SUBREG_BYTE (x)); | |
7045 | |
7046 if (simplified) | |
7047 tem = simplified; | |
7048 | |
7049 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x)) | |
7050 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem)) | |
7051 && subreg_lowpart_p (x)) | |
7052 { | |
7053 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, | |
7054 0); | |
7055 | |
7056 /* If we have something other than a SUBREG, we might have | |
7057 done an expansion, so rerun ourselves. */ | |
7058 if (GET_CODE (newer) != SUBREG) | |
7059 newer = make_compound_operation (newer, in_code); | |
7060 | |
7061 return newer; | |
7062 } | |
7063 | |
7064 if (simplified) | |
7065 return tem; | |
7066 } | |
7067 break; | |
7068 | |
7069 default: | |
7070 break; | |
7071 } | |
7072 | |
7073 if (new_rtx) | |
7074 { | |
7075 x = gen_lowpart (mode, new_rtx); | |
7076 code = GET_CODE (x); | |
7077 } | |
7078 | |
7079 /* Now recursively process each operand of this operation. */ | |
7080 fmt = GET_RTX_FORMAT (code); | |
7081 for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
7082 if (fmt[i] == 'e') | |
7083 { | |
7084 new_rtx = make_compound_operation (XEXP (x, i), next_code); | |
7085 SUBST (XEXP (x, i), new_rtx); | |
7086 } | |
7087 else if (fmt[i] == 'E') | |
7088 for (j = 0; j < XVECLEN (x, i); j++) | |
7089 { | |
7090 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code); | |
7091 SUBST (XVECEXP (x, i, j), new_rtx); | |
7092 } | |
7093 | |
7094 /* If this is a commutative operation, the changes to the operands | |
7095 may have made it noncanonical. */ | |
7096 if (COMMUTATIVE_ARITH_P (x) | |
7097 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) | |
7098 { | |
7099 tem = XEXP (x, 0); | |
7100 SUBST (XEXP (x, 0), XEXP (x, 1)); | |
7101 SUBST (XEXP (x, 1), tem); | |
7102 } | |
7103 | |
7104 return x; | |
7105 } | |
7106 | |
7107 /* Given M see if it is a value that would select a field of bits | |
7108 within an item, but not the entire word. Return -1 if not. | |
7109 Otherwise, return the starting position of the field, where 0 is the | |
7110 low-order bit. | |
7111 | |
7112 *PLEN is set to the length of the field. */ | |
7113 | |
7114 static int | |
7115 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen) | |
7116 { | |
7117 /* Get the bit number of the first 1 bit from the right, -1 if none. */ | |
7118 int pos = exact_log2 (m & -m); | |
7119 int len = 0; | |
7120 | |
7121 if (pos >= 0) | |
7122 /* Now shift off the low-order zero bits and see if we have a | |
7123 power of two minus 1. */ | |
7124 len = exact_log2 ((m >> pos) + 1); | |
7125 | |
7126 if (len <= 0) | |
7127 pos = -1; | |
7128 | |
7129 *plen = len; | |
7130 return pos; | |
7131 } | |
7132 | |
7133 /* If X refers to a register that equals REG in value, replace these | |
7134 references with REG. */ | |
7135 static rtx | |
7136 canon_reg_for_combine (rtx x, rtx reg) | |
7137 { | |
7138 rtx op0, op1, op2; | |
7139 const char *fmt; | |
7140 int i; | |
7141 bool copied; | |
7142 | |
7143 enum rtx_code code = GET_CODE (x); | |
7144 switch (GET_RTX_CLASS (code)) | |
7145 { | |
7146 case RTX_UNARY: | |
7147 op0 = canon_reg_for_combine (XEXP (x, 0), reg); | |
7148 if (op0 != XEXP (x, 0)) | |
7149 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0, | |
7150 GET_MODE (reg)); | |
7151 break; | |
7152 | |
7153 case RTX_BIN_ARITH: | |
7154 case RTX_COMM_ARITH: | |
7155 op0 = canon_reg_for_combine (XEXP (x, 0), reg); | |
7156 op1 = canon_reg_for_combine (XEXP (x, 1), reg); | |
7157 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
7158 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1); | |
7159 break; | |
7160 | |
7161 case RTX_COMPARE: | |
7162 case RTX_COMM_COMPARE: | |
7163 op0 = canon_reg_for_combine (XEXP (x, 0), reg); | |
7164 op1 = canon_reg_for_combine (XEXP (x, 1), reg); | |
7165 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
7166 return simplify_gen_relational (GET_CODE (x), GET_MODE (x), | |
7167 GET_MODE (op0), op0, op1); | |
7168 break; | |
7169 | |
7170 case RTX_TERNARY: | |
7171 case RTX_BITFIELD_OPS: | |
7172 op0 = canon_reg_for_combine (XEXP (x, 0), reg); | |
7173 op1 = canon_reg_for_combine (XEXP (x, 1), reg); | |
7174 op2 = canon_reg_for_combine (XEXP (x, 2), reg); | |
7175 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2)) | |
7176 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x), | |
7177 GET_MODE (op0), op0, op1, op2); | |
7178 | |
7179 case RTX_OBJ: | |
7180 if (REG_P (x)) | |
7181 { | |
7182 if (rtx_equal_p (get_last_value (reg), x) | |
7183 || rtx_equal_p (reg, get_last_value (x))) | |
7184 return reg; | |
7185 else | |
7186 break; | |
7187 } | |
7188 | |
7189 /* fall through */ | |
7190 | |
7191 default: | |
7192 fmt = GET_RTX_FORMAT (code); | |
7193 copied = false; | |
7194 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7195 if (fmt[i] == 'e') | |
7196 { | |
7197 rtx op = canon_reg_for_combine (XEXP (x, i), reg); | |
7198 if (op != XEXP (x, i)) | |
7199 { | |
7200 if (!copied) | |
7201 { | |
7202 copied = true; | |
7203 x = copy_rtx (x); | |
7204 } | |
7205 XEXP (x, i) = op; | |
7206 } | |
7207 } | |
7208 else if (fmt[i] == 'E') | |
7209 { | |
7210 int j; | |
7211 for (j = 0; j < XVECLEN (x, i); j++) | |
7212 { | |
7213 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg); | |
7214 if (op != XVECEXP (x, i, j)) | |
7215 { | |
7216 if (!copied) | |
7217 { | |
7218 copied = true; | |
7219 x = copy_rtx (x); | |
7220 } | |
7221 XVECEXP (x, i, j) = op; | |
7222 } | |
7223 } | |
7224 } | |
7225 | |
7226 break; | |
7227 } | |
7228 | |
7229 return x; | |
7230 } | |
7231 | |
7232 /* Return X converted to MODE. If the value is already truncated to | |
7233 MODE we can just return a subreg even though in the general case we | |
7234 would need an explicit truncation. */ | |
7235 | |
7236 static rtx | |
7237 gen_lowpart_or_truncate (enum machine_mode mode, rtx x) | |
7238 { | |
7239 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode) | |
7240 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
7241 GET_MODE_BITSIZE (GET_MODE (x))) | |
7242 || (REG_P (x) && reg_truncated_to_mode (mode, x))) | |
7243 return gen_lowpart (mode, x); | |
7244 else | |
7245 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x)); | |
7246 } | |
7247 | |
7248 /* See if X can be simplified knowing that we will only refer to it in | |
7249 MODE and will only refer to those bits that are nonzero in MASK. | |
7250 If other bits are being computed or if masking operations are done | |
7251 that select a superset of the bits in MASK, they can sometimes be | |
7252 ignored. | |
7253 | |
7254 Return a possibly simplified expression, but always convert X to | |
7255 MODE. If X is a CONST_INT, AND the CONST_INT with MASK. | |
7256 | |
7257 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK | |
7258 are all off in X. This is used when X will be complemented, by either | |
7259 NOT, NEG, or XOR. */ | |
7260 | |
7261 static rtx | |
7262 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask, | |
7263 int just_select) | |
7264 { | |
7265 enum rtx_code code = GET_CODE (x); | |
7266 int next_select = just_select || code == XOR || code == NOT || code == NEG; | |
7267 enum machine_mode op_mode; | |
7268 unsigned HOST_WIDE_INT fuller_mask, nonzero; | |
7269 rtx op0, op1, temp; | |
7270 | |
7271 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the | |
7272 code below will do the wrong thing since the mode of such an | |
7273 expression is VOIDmode. | |
7274 | |
7275 Also do nothing if X is a CLOBBER; this can happen if X was | |
7276 the return value from a call to gen_lowpart. */ | |
7277 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) | |
7278 return x; | |
7279 | |
7280 /* We want to perform the operation is its present mode unless we know | |
7281 that the operation is valid in MODE, in which case we do the operation | |
7282 in MODE. */ | |
7283 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) | |
7284 && have_insn_for (code, mode)) | |
7285 ? mode : GET_MODE (x)); | |
7286 | |
7287 /* It is not valid to do a right-shift in a narrower mode | |
7288 than the one it came in with. */ | |
7289 if ((code == LSHIFTRT || code == ASHIFTRT) | |
7290 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x))) | |
7291 op_mode = GET_MODE (x); | |
7292 | |
7293 /* Truncate MASK to fit OP_MODE. */ | |
7294 if (op_mode) | |
7295 mask &= GET_MODE_MASK (op_mode); | |
7296 | |
7297 /* When we have an arithmetic operation, or a shift whose count we | |
7298 do not know, we need to assume that all bits up to the highest-order | |
7299 bit in MASK will be needed. This is how we form such a mask. */ | |
7300 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) | |
7301 fuller_mask = ~(unsigned HOST_WIDE_INT) 0; | |
7302 else | |
7303 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) | |
7304 - 1); | |
7305 | |
7306 /* Determine what bits of X are guaranteed to be (non)zero. */ | |
7307 nonzero = nonzero_bits (x, mode); | |
7308 | |
7309 /* If none of the bits in X are needed, return a zero. */ | |
7310 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x)) | |
7311 x = const0_rtx; | |
7312 | |
7313 /* If X is a CONST_INT, return a new one. Do this here since the | |
7314 test below will fail. */ | |
7315 if (GET_CODE (x) == CONST_INT) | |
7316 { | |
7317 if (SCALAR_INT_MODE_P (mode)) | |
7318 return gen_int_mode (INTVAL (x) & mask, mode); | |
7319 else | |
7320 { | |
7321 x = GEN_INT (INTVAL (x) & mask); | |
7322 return gen_lowpart_common (mode, x); | |
7323 } | |
7324 } | |
7325 | |
7326 /* If X is narrower than MODE and we want all the bits in X's mode, just | |
7327 get X in the proper mode. */ | |
7328 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) | |
7329 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0) | |
7330 return gen_lowpart (mode, x); | |
7331 | |
7332 /* The arithmetic simplifications here do the wrong thing on vector modes. */ | |
7333 if (VECTOR_MODE_P (mode) || VECTOR_MODE_P (GET_MODE (x))) | |
7334 return gen_lowpart (mode, x); | |
7335 | |
7336 switch (code) | |
7337 { | |
7338 case CLOBBER: | |
7339 /* If X is a (clobber (const_int)), return it since we know we are | |
7340 generating something that won't match. */ | |
7341 return x; | |
7342 | |
7343 case SIGN_EXTEND: | |
7344 case ZERO_EXTEND: | |
7345 case ZERO_EXTRACT: | |
7346 case SIGN_EXTRACT: | |
7347 x = expand_compound_operation (x); | |
7348 if (GET_CODE (x) != code) | |
7349 return force_to_mode (x, mode, mask, next_select); | |
7350 break; | |
7351 | |
7352 case SUBREG: | |
7353 if (subreg_lowpart_p (x) | |
7354 /* We can ignore the effect of this SUBREG if it narrows the mode or | |
7355 if the constant masks to zero all the bits the mode doesn't | |
7356 have. */ | |
7357 && ((GET_MODE_SIZE (GET_MODE (x)) | |
7358 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
7359 || (0 == (mask | |
7360 & GET_MODE_MASK (GET_MODE (x)) | |
7361 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) | |
7362 return force_to_mode (SUBREG_REG (x), mode, mask, next_select); | |
7363 break; | |
7364 | |
7365 case AND: | |
7366 /* If this is an AND with a constant, convert it into an AND | |
7367 whose constant is the AND of that constant with MASK. If it | |
7368 remains an AND of MASK, delete it since it is redundant. */ | |
7369 | |
7370 if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7371 { | |
7372 x = simplify_and_const_int (x, op_mode, XEXP (x, 0), | |
7373 mask & INTVAL (XEXP (x, 1))); | |
7374 | |
7375 /* If X is still an AND, see if it is an AND with a mask that | |
7376 is just some low-order bits. If so, and it is MASK, we don't | |
7377 need it. */ | |
7378 | |
7379 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT | |
7380 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x))) | |
7381 == mask)) | |
7382 x = XEXP (x, 0); | |
7383 | |
7384 /* If it remains an AND, try making another AND with the bits | |
7385 in the mode mask that aren't in MASK turned on. If the | |
7386 constant in the AND is wide enough, this might make a | |
7387 cheaper constant. */ | |
7388 | |
7389 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT | |
7390 && GET_MODE_MASK (GET_MODE (x)) != mask | |
7391 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) | |
7392 { | |
7393 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1)) | |
7394 | (GET_MODE_MASK (GET_MODE (x)) & ~mask)); | |
7395 int width = GET_MODE_BITSIZE (GET_MODE (x)); | |
7396 rtx y; | |
7397 | |
7398 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative | |
7399 number, sign extend it. */ | |
7400 if (width > 0 && width < HOST_BITS_PER_WIDE_INT | |
7401 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
7402 cval |= (HOST_WIDE_INT) -1 << width; | |
7403 | |
7404 y = simplify_gen_binary (AND, GET_MODE (x), | |
7405 XEXP (x, 0), GEN_INT (cval)); | |
7406 if (rtx_cost (y, SET, optimize_this_for_speed_p) | |
7407 < rtx_cost (x, SET, optimize_this_for_speed_p)) | |
7408 x = y; | |
7409 } | |
7410 | |
7411 break; | |
7412 } | |
7413 | |
7414 goto binop; | |
7415 | |
7416 case PLUS: | |
7417 /* In (and (plus FOO C1) M), if M is a mask that just turns off | |
7418 low-order bits (as in an alignment operation) and FOO is already | |
7419 aligned to that boundary, mask C1 to that boundary as well. | |
7420 This may eliminate that PLUS and, later, the AND. */ | |
7421 | |
7422 { | |
7423 unsigned int width = GET_MODE_BITSIZE (mode); | |
7424 unsigned HOST_WIDE_INT smask = mask; | |
7425 | |
7426 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative | |
7427 number, sign extend it. */ | |
7428 | |
7429 if (width < HOST_BITS_PER_WIDE_INT | |
7430 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
7431 smask |= (HOST_WIDE_INT) -1 << width; | |
7432 | |
7433 if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7434 && exact_log2 (- smask) >= 0 | |
7435 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0 | |
7436 && (INTVAL (XEXP (x, 1)) & ~smask) != 0) | |
7437 return force_to_mode (plus_constant (XEXP (x, 0), | |
7438 (INTVAL (XEXP (x, 1)) & smask)), | |
7439 mode, smask, next_select); | |
7440 } | |
7441 | |
7442 /* ... fall through ... */ | |
7443 | |
7444 case MULT: | |
7445 /* For PLUS, MINUS and MULT, we need any bits less significant than the | |
7446 most significant bit in MASK since carries from those bits will | |
7447 affect the bits we are interested in. */ | |
7448 mask = fuller_mask; | |
7449 goto binop; | |
7450 | |
7451 case MINUS: | |
7452 /* If X is (minus C Y) where C's least set bit is larger than any bit | |
7453 in the mask, then we may replace with (neg Y). */ | |
7454 if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
7455 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0)) | |
7456 & -INTVAL (XEXP (x, 0)))) | |
7457 > mask)) | |
7458 { | |
7459 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1), | |
7460 GET_MODE (x)); | |
7461 return force_to_mode (x, mode, mask, next_select); | |
7462 } | |
7463 | |
7464 /* Similarly, if C contains every bit in the fuller_mask, then we may | |
7465 replace with (not Y). */ | |
7466 if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
7467 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask) | |
7468 == INTVAL (XEXP (x, 0)))) | |
7469 { | |
7470 x = simplify_gen_unary (NOT, GET_MODE (x), | |
7471 XEXP (x, 1), GET_MODE (x)); | |
7472 return force_to_mode (x, mode, mask, next_select); | |
7473 } | |
7474 | |
7475 mask = fuller_mask; | |
7476 goto binop; | |
7477 | |
7478 case IOR: | |
7479 case XOR: | |
7480 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and | |
7481 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) | |
7482 operation which may be a bitfield extraction. Ensure that the | |
7483 constant we form is not wider than the mode of X. */ | |
7484 | |
7485 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
7486 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
7487 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
7488 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT | |
7489 && GET_CODE (XEXP (x, 1)) == CONST_INT | |
7490 && ((INTVAL (XEXP (XEXP (x, 0), 1)) | |
7491 + floor_log2 (INTVAL (XEXP (x, 1)))) | |
7492 < GET_MODE_BITSIZE (GET_MODE (x))) | |
7493 && (INTVAL (XEXP (x, 1)) | |
7494 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) | |
7495 { | |
7496 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask) | |
7497 << INTVAL (XEXP (XEXP (x, 0), 1))); | |
7498 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x), | |
7499 XEXP (XEXP (x, 0), 0), temp); | |
7500 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp, | |
7501 XEXP (XEXP (x, 0), 1)); | |
7502 return force_to_mode (x, mode, mask, next_select); | |
7503 } | |
7504 | |
7505 binop: | |
7506 /* For most binary operations, just propagate into the operation and | |
7507 change the mode if we have an operation of that mode. */ | |
7508 | |
7509 op0 = gen_lowpart_or_truncate (op_mode, | |
7510 force_to_mode (XEXP (x, 0), mode, mask, | |
7511 next_select)); | |
7512 op1 = gen_lowpart_or_truncate (op_mode, | |
7513 force_to_mode (XEXP (x, 1), mode, mask, | |
7514 next_select)); | |
7515 | |
7516 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
7517 x = simplify_gen_binary (code, op_mode, op0, op1); | |
7518 break; | |
7519 | |
7520 case ASHIFT: | |
7521 /* For left shifts, do the same, but just for the first operand. | |
7522 However, we cannot do anything with shifts where we cannot | |
7523 guarantee that the counts are smaller than the size of the mode | |
7524 because such a count will have a different meaning in a | |
7525 wider mode. */ | |
7526 | |
7527 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7528 && INTVAL (XEXP (x, 1)) >= 0 | |
7529 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode)) | |
7530 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode | |
7531 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) | |
7532 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))) | |
7533 break; | |
7534 | |
7535 /* If the shift count is a constant and we can do arithmetic in | |
7536 the mode of the shift, refine which bits we need. Otherwise, use the | |
7537 conservative form of the mask. */ | |
7538 if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7539 && INTVAL (XEXP (x, 1)) >= 0 | |
7540 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode) | |
7541 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) | |
7542 mask >>= INTVAL (XEXP (x, 1)); | |
7543 else | |
7544 mask = fuller_mask; | |
7545 | |
7546 op0 = gen_lowpart_or_truncate (op_mode, | |
7547 force_to_mode (XEXP (x, 0), op_mode, | |
7548 mask, next_select)); | |
7549 | |
7550 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) | |
7551 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1)); | |
7552 break; | |
7553 | |
7554 case LSHIFTRT: | |
7555 /* Here we can only do something if the shift count is a constant, | |
7556 this shift constant is valid for the host, and we can do arithmetic | |
7557 in OP_MODE. */ | |
7558 | |
7559 if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7560 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT | |
7561 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) | |
7562 { | |
7563 rtx inner = XEXP (x, 0); | |
7564 unsigned HOST_WIDE_INT inner_mask; | |
7565 | |
7566 /* Select the mask of the bits we need for the shift operand. */ | |
7567 inner_mask = mask << INTVAL (XEXP (x, 1)); | |
7568 | |
7569 /* We can only change the mode of the shift if we can do arithmetic | |
7570 in the mode of the shift and INNER_MASK is no wider than the | |
7571 width of X's mode. */ | |
7572 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0) | |
7573 op_mode = GET_MODE (x); | |
7574 | |
7575 inner = force_to_mode (inner, op_mode, inner_mask, next_select); | |
7576 | |
7577 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) | |
7578 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); | |
7579 } | |
7580 | |
7581 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the | |
7582 shift and AND produces only copies of the sign bit (C2 is one less | |
7583 than a power of two), we can do this with just a shift. */ | |
7584 | |
7585 if (GET_CODE (x) == LSHIFTRT | |
7586 && GET_CODE (XEXP (x, 1)) == CONST_INT | |
7587 /* The shift puts one of the sign bit copies in the least significant | |
7588 bit. */ | |
7589 && ((INTVAL (XEXP (x, 1)) | |
7590 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) | |
7591 >= GET_MODE_BITSIZE (GET_MODE (x))) | |
7592 && exact_log2 (mask + 1) >= 0 | |
7593 /* Number of bits left after the shift must be more than the mask | |
7594 needs. */ | |
7595 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1)) | |
7596 <= GET_MODE_BITSIZE (GET_MODE (x))) | |
7597 /* Must be more sign bit copies than the mask needs. */ | |
7598 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
7599 >= exact_log2 (mask + 1))) | |
7600 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), | |
7601 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x)) | |
7602 - exact_log2 (mask + 1))); | |
7603 | |
7604 goto shiftrt; | |
7605 | |
7606 case ASHIFTRT: | |
7607 /* If we are just looking for the sign bit, we don't need this shift at | |
7608 all, even if it has a variable count. */ | |
7609 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
7610 && (mask == ((unsigned HOST_WIDE_INT) 1 | |
7611 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) | |
7612 return force_to_mode (XEXP (x, 0), mode, mask, next_select); | |
7613 | |
7614 /* If this is a shift by a constant, get a mask that contains those bits | |
7615 that are not copies of the sign bit. We then have two cases: If | |
7616 MASK only includes those bits, this can be a logical shift, which may | |
7617 allow simplifications. If MASK is a single-bit field not within | |
7618 those bits, we are requesting a copy of the sign bit and hence can | |
7619 shift the sign bit to the appropriate location. */ | |
7620 | |
7621 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0 | |
7622 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) | |
7623 { | |
7624 int i; | |
7625 | |
7626 /* If the considered data is wider than HOST_WIDE_INT, we can't | |
7627 represent a mask for all its bits in a single scalar. | |
7628 But we only care about the lower bits, so calculate these. */ | |
7629 | |
7630 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) | |
7631 { | |
7632 nonzero = ~(HOST_WIDE_INT) 0; | |
7633 | |
7634 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) | |
7635 is the number of bits a full-width mask would have set. | |
7636 We need only shift if these are fewer than nonzero can | |
7637 hold. If not, we must keep all bits set in nonzero. */ | |
7638 | |
7639 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) | |
7640 < HOST_BITS_PER_WIDE_INT) | |
7641 nonzero >>= INTVAL (XEXP (x, 1)) | |
7642 + HOST_BITS_PER_WIDE_INT | |
7643 - GET_MODE_BITSIZE (GET_MODE (x)) ; | |
7644 } | |
7645 else | |
7646 { | |
7647 nonzero = GET_MODE_MASK (GET_MODE (x)); | |
7648 nonzero >>= INTVAL (XEXP (x, 1)); | |
7649 } | |
7650 | |
7651 if ((mask & ~nonzero) == 0) | |
7652 { | |
7653 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x), | |
7654 XEXP (x, 0), INTVAL (XEXP (x, 1))); | |
7655 if (GET_CODE (x) != ASHIFTRT) | |
7656 return force_to_mode (x, mode, mask, next_select); | |
7657 } | |
7658 | |
7659 else if ((i = exact_log2 (mask)) >= 0) | |
7660 { | |
7661 x = simplify_shift_const | |
7662 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0), | |
7663 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i); | |
7664 | |
7665 if (GET_CODE (x) != ASHIFTRT) | |
7666 return force_to_mode (x, mode, mask, next_select); | |
7667 } | |
7668 } | |
7669 | |
7670 /* If MASK is 1, convert this to an LSHIFTRT. This can be done | |
7671 even if the shift count isn't a constant. */ | |
7672 if (mask == 1) | |
7673 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), | |
7674 XEXP (x, 0), XEXP (x, 1)); | |
7675 | |
7676 shiftrt: | |
7677 | |
7678 /* If this is a zero- or sign-extension operation that just affects bits | |
7679 we don't care about, remove it. Be sure the call above returned | |
7680 something that is still a shift. */ | |
7681 | |
7682 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) | |
7683 && GET_CODE (XEXP (x, 1)) == CONST_INT | |
7684 && INTVAL (XEXP (x, 1)) >= 0 | |
7685 && (INTVAL (XEXP (x, 1)) | |
7686 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1)) | |
7687 && GET_CODE (XEXP (x, 0)) == ASHIFT | |
7688 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1)) | |
7689 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, | |
7690 next_select); | |
7691 | |
7692 break; | |
7693 | |
7694 case ROTATE: | |
7695 case ROTATERT: | |
7696 /* If the shift count is constant and we can do computations | |
7697 in the mode of X, compute where the bits we care about are. | |
7698 Otherwise, we can't do anything. Don't change the mode of | |
7699 the shift or propagate MODE into the shift, though. */ | |
7700 if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7701 && INTVAL (XEXP (x, 1)) >= 0) | |
7702 { | |
7703 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, | |
7704 GET_MODE (x), GEN_INT (mask), | |
7705 XEXP (x, 1)); | |
7706 if (temp && GET_CODE (temp) == CONST_INT) | |
7707 SUBST (XEXP (x, 0), | |
7708 force_to_mode (XEXP (x, 0), GET_MODE (x), | |
7709 INTVAL (temp), next_select)); | |
7710 } | |
7711 break; | |
7712 | |
7713 case NEG: | |
7714 /* If we just want the low-order bit, the NEG isn't needed since it | |
7715 won't change the low-order bit. */ | |
7716 if (mask == 1) | |
7717 return force_to_mode (XEXP (x, 0), mode, mask, just_select); | |
7718 | |
7719 /* We need any bits less significant than the most significant bit in | |
7720 MASK since carries from those bits will affect the bits we are | |
7721 interested in. */ | |
7722 mask = fuller_mask; | |
7723 goto unop; | |
7724 | |
7725 case NOT: | |
7726 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the | |
7727 same as the XOR case above. Ensure that the constant we form is not | |
7728 wider than the mode of X. */ | |
7729 | |
7730 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
7731 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
7732 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
7733 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) | |
7734 < GET_MODE_BITSIZE (GET_MODE (x))) | |
7735 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) | |
7736 { | |
7737 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), | |
7738 GET_MODE (x)); | |
7739 temp = simplify_gen_binary (XOR, GET_MODE (x), | |
7740 XEXP (XEXP (x, 0), 0), temp); | |
7741 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), | |
7742 temp, XEXP (XEXP (x, 0), 1)); | |
7743 | |
7744 return force_to_mode (x, mode, mask, next_select); | |
7745 } | |
7746 | |
7747 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must | |
7748 use the full mask inside the NOT. */ | |
7749 mask = fuller_mask; | |
7750 | |
7751 unop: | |
7752 op0 = gen_lowpart_or_truncate (op_mode, | |
7753 force_to_mode (XEXP (x, 0), mode, mask, | |
7754 next_select)); | |
7755 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) | |
7756 x = simplify_gen_unary (code, op_mode, op0, op_mode); | |
7757 break; | |
7758 | |
7759 case NE: | |
7760 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included | |
7761 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, | |
7762 which is equal to STORE_FLAG_VALUE. */ | |
7763 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx | |
7764 && GET_MODE (XEXP (x, 0)) == mode | |
7765 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0 | |
7766 && (nonzero_bits (XEXP (x, 0), mode) | |
7767 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE)) | |
7768 return force_to_mode (XEXP (x, 0), mode, mask, next_select); | |
7769 | |
7770 break; | |
7771 | |
7772 case IF_THEN_ELSE: | |
7773 /* We have no way of knowing if the IF_THEN_ELSE can itself be | |
7774 written in a narrower mode. We play it safe and do not do so. */ | |
7775 | |
7776 SUBST (XEXP (x, 1), | |
7777 gen_lowpart_or_truncate (GET_MODE (x), | |
7778 force_to_mode (XEXP (x, 1), mode, | |
7779 mask, next_select))); | |
7780 SUBST (XEXP (x, 2), | |
7781 gen_lowpart_or_truncate (GET_MODE (x), | |
7782 force_to_mode (XEXP (x, 2), mode, | |
7783 mask, next_select))); | |
7784 break; | |
7785 | |
7786 default: | |
7787 break; | |
7788 } | |
7789 | |
7790 /* Ensure we return a value of the proper mode. */ | |
7791 return gen_lowpart_or_truncate (mode, x); | |
7792 } | |
7793 | |
7794 /* Return nonzero if X is an expression that has one of two values depending on | |
7795 whether some other value is zero or nonzero. In that case, we return the | |
7796 value that is being tested, *PTRUE is set to the value if the rtx being | |
7797 returned has a nonzero value, and *PFALSE is set to the other alternative. | |
7798 | |
7799 If we return zero, we set *PTRUE and *PFALSE to X. */ | |
7800 | |
7801 static rtx | |
7802 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse) | |
7803 { | |
7804 enum machine_mode mode = GET_MODE (x); | |
7805 enum rtx_code code = GET_CODE (x); | |
7806 rtx cond0, cond1, true0, true1, false0, false1; | |
7807 unsigned HOST_WIDE_INT nz; | |
7808 | |
7809 /* If we are comparing a value against zero, we are done. */ | |
7810 if ((code == NE || code == EQ) | |
7811 && XEXP (x, 1) == const0_rtx) | |
7812 { | |
7813 *ptrue = (code == NE) ? const_true_rtx : const0_rtx; | |
7814 *pfalse = (code == NE) ? const0_rtx : const_true_rtx; | |
7815 return XEXP (x, 0); | |
7816 } | |
7817 | |
7818 /* If this is a unary operation whose operand has one of two values, apply | |
7819 our opcode to compute those values. */ | |
7820 else if (UNARY_P (x) | |
7821 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) | |
7822 { | |
7823 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0))); | |
7824 *pfalse = simplify_gen_unary (code, mode, false0, | |
7825 GET_MODE (XEXP (x, 0))); | |
7826 return cond0; | |
7827 } | |
7828 | |
7829 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would | |
7830 make can't possibly match and would suppress other optimizations. */ | |
7831 else if (code == COMPARE) | |
7832 ; | |
7833 | |
7834 /* If this is a binary operation, see if either side has only one of two | |
7835 values. If either one does or if both do and they are conditional on | |
7836 the same value, compute the new true and false values. */ | |
7837 else if (BINARY_P (x)) | |
7838 { | |
7839 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); | |
7840 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); | |
7841 | |
7842 if ((cond0 != 0 || cond1 != 0) | |
7843 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) | |
7844 { | |
7845 /* If if_then_else_cond returned zero, then true/false are the | |
7846 same rtl. We must copy one of them to prevent invalid rtl | |
7847 sharing. */ | |
7848 if (cond0 == 0) | |
7849 true0 = copy_rtx (true0); | |
7850 else if (cond1 == 0) | |
7851 true1 = copy_rtx (true1); | |
7852 | |
7853 if (COMPARISON_P (x)) | |
7854 { | |
7855 *ptrue = simplify_gen_relational (code, mode, VOIDmode, | |
7856 true0, true1); | |
7857 *pfalse = simplify_gen_relational (code, mode, VOIDmode, | |
7858 false0, false1); | |
7859 } | |
7860 else | |
7861 { | |
7862 *ptrue = simplify_gen_binary (code, mode, true0, true1); | |
7863 *pfalse = simplify_gen_binary (code, mode, false0, false1); | |
7864 } | |
7865 | |
7866 return cond0 ? cond0 : cond1; | |
7867 } | |
7868 | |
7869 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the | |
7870 operands is zero when the other is nonzero, and vice-versa, | |
7871 and STORE_FLAG_VALUE is 1 or -1. */ | |
7872 | |
7873 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
7874 && (code == PLUS || code == IOR || code == XOR || code == MINUS | |
7875 || code == UMAX) | |
7876 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) | |
7877 { | |
7878 rtx op0 = XEXP (XEXP (x, 0), 1); | |
7879 rtx op1 = XEXP (XEXP (x, 1), 1); | |
7880 | |
7881 cond0 = XEXP (XEXP (x, 0), 0); | |
7882 cond1 = XEXP (XEXP (x, 1), 0); | |
7883 | |
7884 if (COMPARISON_P (cond0) | |
7885 && COMPARISON_P (cond1) | |
7886 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) | |
7887 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) | |
7888 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) | |
7889 || ((swap_condition (GET_CODE (cond0)) | |
7890 == reversed_comparison_code (cond1, NULL)) | |
7891 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) | |
7892 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) | |
7893 && ! side_effects_p (x)) | |
7894 { | |
7895 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx); | |
7896 *pfalse = simplify_gen_binary (MULT, mode, | |
7897 (code == MINUS | |
7898 ? simplify_gen_unary (NEG, mode, | |
7899 op1, mode) | |
7900 : op1), | |
7901 const_true_rtx); | |
7902 return cond0; | |
7903 } | |
7904 } | |
7905 | |
7906 /* Similarly for MULT, AND and UMIN, except that for these the result | |
7907 is always zero. */ | |
7908 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
7909 && (code == MULT || code == AND || code == UMIN) | |
7910 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) | |
7911 { | |
7912 cond0 = XEXP (XEXP (x, 0), 0); | |
7913 cond1 = XEXP (XEXP (x, 1), 0); | |
7914 | |
7915 if (COMPARISON_P (cond0) | |
7916 && COMPARISON_P (cond1) | |
7917 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) | |
7918 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) | |
7919 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) | |
7920 || ((swap_condition (GET_CODE (cond0)) | |
7921 == reversed_comparison_code (cond1, NULL)) | |
7922 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) | |
7923 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) | |
7924 && ! side_effects_p (x)) | |
7925 { | |
7926 *ptrue = *pfalse = const0_rtx; | |
7927 return cond0; | |
7928 } | |
7929 } | |
7930 } | |
7931 | |
7932 else if (code == IF_THEN_ELSE) | |
7933 { | |
7934 /* If we have IF_THEN_ELSE already, extract the condition and | |
7935 canonicalize it if it is NE or EQ. */ | |
7936 cond0 = XEXP (x, 0); | |
7937 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); | |
7938 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) | |
7939 return XEXP (cond0, 0); | |
7940 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) | |
7941 { | |
7942 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); | |
7943 return XEXP (cond0, 0); | |
7944 } | |
7945 else | |
7946 return cond0; | |
7947 } | |
7948 | |
7949 /* If X is a SUBREG, we can narrow both the true and false values | |
7950 if the inner expression, if there is a condition. */ | |
7951 else if (code == SUBREG | |
7952 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), | |
7953 &true0, &false0))) | |
7954 { | |
7955 true0 = simplify_gen_subreg (mode, true0, | |
7956 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); | |
7957 false0 = simplify_gen_subreg (mode, false0, | |
7958 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); | |
7959 if (true0 && false0) | |
7960 { | |
7961 *ptrue = true0; | |
7962 *pfalse = false0; | |
7963 return cond0; | |
7964 } | |
7965 } | |
7966 | |
7967 /* If X is a constant, this isn't special and will cause confusions | |
7968 if we treat it as such. Likewise if it is equivalent to a constant. */ | |
7969 else if (CONSTANT_P (x) | |
7970 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) | |
7971 ; | |
7972 | |
7973 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that | |
7974 will be least confusing to the rest of the compiler. */ | |
7975 else if (mode == BImode) | |
7976 { | |
7977 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx; | |
7978 return x; | |
7979 } | |
7980 | |
7981 /* If X is known to be either 0 or -1, those are the true and | |
7982 false values when testing X. */ | |
7983 else if (x == constm1_rtx || x == const0_rtx | |
7984 || (mode != VOIDmode | |
7985 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode))) | |
7986 { | |
7987 *ptrue = constm1_rtx, *pfalse = const0_rtx; | |
7988 return x; | |
7989 } | |
7990 | |
7991 /* Likewise for 0 or a single bit. */ | |
7992 else if (SCALAR_INT_MODE_P (mode) | |
7993 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
7994 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0) | |
7995 { | |
7996 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx; | |
7997 return x; | |
7998 } | |
7999 | |
8000 /* Otherwise fail; show no condition with true and false values the same. */ | |
8001 *ptrue = *pfalse = x; | |
8002 return 0; | |
8003 } | |
8004 | |
8005 /* Return the value of expression X given the fact that condition COND | |
8006 is known to be true when applied to REG as its first operand and VAL | |
8007 as its second. X is known to not be shared and so can be modified in | |
8008 place. | |
8009 | |
8010 We only handle the simplest cases, and specifically those cases that | |
8011 arise with IF_THEN_ELSE expressions. */ | |
8012 | |
8013 static rtx | |
8014 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val) | |
8015 { | |
8016 enum rtx_code code = GET_CODE (x); | |
8017 rtx temp; | |
8018 const char *fmt; | |
8019 int i, j; | |
8020 | |
8021 if (side_effects_p (x)) | |
8022 return x; | |
8023 | |
8024 /* If either operand of the condition is a floating point value, | |
8025 then we have to avoid collapsing an EQ comparison. */ | |
8026 if (cond == EQ | |
8027 && rtx_equal_p (x, reg) | |
8028 && ! FLOAT_MODE_P (GET_MODE (x)) | |
8029 && ! FLOAT_MODE_P (GET_MODE (val))) | |
8030 return val; | |
8031 | |
8032 if (cond == UNEQ && rtx_equal_p (x, reg)) | |
8033 return val; | |
8034 | |
8035 /* If X is (abs REG) and we know something about REG's relationship | |
8036 with zero, we may be able to simplify this. */ | |
8037 | |
8038 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) | |
8039 switch (cond) | |
8040 { | |
8041 case GE: case GT: case EQ: | |
8042 return XEXP (x, 0); | |
8043 case LT: case LE: | |
8044 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)), | |
8045 XEXP (x, 0), | |
8046 GET_MODE (XEXP (x, 0))); | |
8047 default: | |
8048 break; | |
8049 } | |
8050 | |
8051 /* The only other cases we handle are MIN, MAX, and comparisons if the | |
8052 operands are the same as REG and VAL. */ | |
8053 | |
8054 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x)) | |
8055 { | |
8056 if (rtx_equal_p (XEXP (x, 0), val)) | |
8057 cond = swap_condition (cond), temp = val, val = reg, reg = temp; | |
8058 | |
8059 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) | |
8060 { | |
8061 if (COMPARISON_P (x)) | |
8062 { | |
8063 if (comparison_dominates_p (cond, code)) | |
8064 return const_true_rtx; | |
8065 | |
8066 code = reversed_comparison_code (x, NULL); | |
8067 if (code != UNKNOWN | |
8068 && comparison_dominates_p (cond, code)) | |
8069 return const0_rtx; | |
8070 else | |
8071 return x; | |
8072 } | |
8073 else if (code == SMAX || code == SMIN | |
8074 || code == UMIN || code == UMAX) | |
8075 { | |
8076 int unsignedp = (code == UMIN || code == UMAX); | |
8077 | |
8078 /* Do not reverse the condition when it is NE or EQ. | |
8079 This is because we cannot conclude anything about | |
8080 the value of 'SMAX (x, y)' when x is not equal to y, | |
8081 but we can when x equals y. */ | |
8082 if ((code == SMAX || code == UMAX) | |
8083 && ! (cond == EQ || cond == NE)) | |
8084 cond = reverse_condition (cond); | |
8085 | |
8086 switch (cond) | |
8087 { | |
8088 case GE: case GT: | |
8089 return unsignedp ? x : XEXP (x, 1); | |
8090 case LE: case LT: | |
8091 return unsignedp ? x : XEXP (x, 0); | |
8092 case GEU: case GTU: | |
8093 return unsignedp ? XEXP (x, 1) : x; | |
8094 case LEU: case LTU: | |
8095 return unsignedp ? XEXP (x, 0) : x; | |
8096 default: | |
8097 break; | |
8098 } | |
8099 } | |
8100 } | |
8101 } | |
8102 else if (code == SUBREG) | |
8103 { | |
8104 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x)); | |
8105 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val); | |
8106 | |
8107 if (SUBREG_REG (x) != r) | |
8108 { | |
8109 /* We must simplify subreg here, before we lose track of the | |
8110 original inner_mode. */ | |
8111 new_rtx = simplify_subreg (GET_MODE (x), r, | |
8112 inner_mode, SUBREG_BYTE (x)); | |
8113 if (new_rtx) | |
8114 return new_rtx; | |
8115 else | |
8116 SUBST (SUBREG_REG (x), r); | |
8117 } | |
8118 | |
8119 return x; | |
8120 } | |
8121 /* We don't have to handle SIGN_EXTEND here, because even in the | |
8122 case of replacing something with a modeless CONST_INT, a | |
8123 CONST_INT is already (supposed to be) a valid sign extension for | |
8124 its narrower mode, which implies it's already properly | |
8125 sign-extended for the wider mode. Now, for ZERO_EXTEND, the | |
8126 story is different. */ | |
8127 else if (code == ZERO_EXTEND) | |
8128 { | |
8129 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0)); | |
8130 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val); | |
8131 | |
8132 if (XEXP (x, 0) != r) | |
8133 { | |
8134 /* We must simplify the zero_extend here, before we lose | |
8135 track of the original inner_mode. */ | |
8136 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), | |
8137 r, inner_mode); | |
8138 if (new_rtx) | |
8139 return new_rtx; | |
8140 else | |
8141 SUBST (XEXP (x, 0), r); | |
8142 } | |
8143 | |
8144 return x; | |
8145 } | |
8146 | |
8147 fmt = GET_RTX_FORMAT (code); | |
8148 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
8149 { | |
8150 if (fmt[i] == 'e') | |
8151 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); | |
8152 else if (fmt[i] == 'E') | |
8153 for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
8154 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), | |
8155 cond, reg, val)); | |
8156 } | |
8157 | |
8158 return x; | |
8159 } | |
8160 | |
8161 /* See if X and Y are equal for the purposes of seeing if we can rewrite an | |
8162 assignment as a field assignment. */ | |
8163 | |
8164 static int | |
8165 rtx_equal_for_field_assignment_p (rtx x, rtx y) | |
8166 { | |
8167 if (x == y || rtx_equal_p (x, y)) | |
8168 return 1; | |
8169 | |
8170 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) | |
8171 return 0; | |
8172 | |
8173 /* Check for a paradoxical SUBREG of a MEM compared with the MEM. | |
8174 Note that all SUBREGs of MEM are paradoxical; otherwise they | |
8175 would have been rewritten. */ | |
8176 if (MEM_P (x) && GET_CODE (y) == SUBREG | |
8177 && MEM_P (SUBREG_REG (y)) | |
8178 && rtx_equal_p (SUBREG_REG (y), | |
8179 gen_lowpart (GET_MODE (SUBREG_REG (y)), x))) | |
8180 return 1; | |
8181 | |
8182 if (MEM_P (y) && GET_CODE (x) == SUBREG | |
8183 && MEM_P (SUBREG_REG (x)) | |
8184 && rtx_equal_p (SUBREG_REG (x), | |
8185 gen_lowpart (GET_MODE (SUBREG_REG (x)), y))) | |
8186 return 1; | |
8187 | |
8188 /* We used to see if get_last_value of X and Y were the same but that's | |
8189 not correct. In one direction, we'll cause the assignment to have | |
8190 the wrong destination and in the case, we'll import a register into this | |
8191 insn that might have already have been dead. So fail if none of the | |
8192 above cases are true. */ | |
8193 return 0; | |
8194 } | |
8195 | |
8196 /* See if X, a SET operation, can be rewritten as a bit-field assignment. | |
8197 Return that assignment if so. | |
8198 | |
8199 We only handle the most common cases. */ | |
8200 | |
8201 static rtx | |
8202 make_field_assignment (rtx x) | |
8203 { | |
8204 rtx dest = SET_DEST (x); | |
8205 rtx src = SET_SRC (x); | |
8206 rtx assign; | |
8207 rtx rhs, lhs; | |
8208 HOST_WIDE_INT c1; | |
8209 HOST_WIDE_INT pos; | |
8210 unsigned HOST_WIDE_INT len; | |
8211 rtx other; | |
8212 enum machine_mode mode; | |
8213 | |
8214 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is | |
8215 a clear of a one-bit field. We will have changed it to | |
8216 (and (rotate (const_int -2) POS) DEST), so check for that. Also check | |
8217 for a SUBREG. */ | |
8218 | |
8219 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE | |
8220 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT | |
8221 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 | |
8222 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) | |
8223 { | |
8224 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), | |
8225 1, 1, 1, 0); | |
8226 if (assign != 0) | |
8227 return gen_rtx_SET (VOIDmode, assign, const0_rtx); | |
8228 return x; | |
8229 } | |
8230 | |
8231 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG | |
8232 && subreg_lowpart_p (XEXP (src, 0)) | |
8233 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) | |
8234 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) | |
8235 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE | |
8236 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT | |
8237 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 | |
8238 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) | |
8239 { | |
8240 assign = make_extraction (VOIDmode, dest, 0, | |
8241 XEXP (SUBREG_REG (XEXP (src, 0)), 1), | |
8242 1, 1, 1, 0); | |
8243 if (assign != 0) | |
8244 return gen_rtx_SET (VOIDmode, assign, const0_rtx); | |
8245 return x; | |
8246 } | |
8247 | |
8248 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a | |
8249 one-bit field. */ | |
8250 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT | |
8251 && XEXP (XEXP (src, 0), 0) == const1_rtx | |
8252 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) | |
8253 { | |
8254 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), | |
8255 1, 1, 1, 0); | |
8256 if (assign != 0) | |
8257 return gen_rtx_SET (VOIDmode, assign, const1_rtx); | |
8258 return x; | |
8259 } | |
8260 | |
8261 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the | |
8262 SRC is an AND with all bits of that field set, then we can discard | |
8263 the AND. */ | |
8264 if (GET_CODE (dest) == ZERO_EXTRACT | |
8265 && GET_CODE (XEXP (dest, 1)) == CONST_INT | |
8266 && GET_CODE (src) == AND | |
8267 && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
8268 { | |
8269 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1)); | |
8270 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1)); | |
8271 unsigned HOST_WIDE_INT ze_mask; | |
8272 | |
8273 if (width >= HOST_BITS_PER_WIDE_INT) | |
8274 ze_mask = -1; | |
8275 else | |
8276 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1; | |
8277 | |
8278 /* Complete overlap. We can remove the source AND. */ | |
8279 if ((and_mask & ze_mask) == ze_mask) | |
8280 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0)); | |
8281 | |
8282 /* Partial overlap. We can reduce the source AND. */ | |
8283 if ((and_mask & ze_mask) != and_mask) | |
8284 { | |
8285 mode = GET_MODE (src); | |
8286 src = gen_rtx_AND (mode, XEXP (src, 0), | |
8287 gen_int_mode (and_mask & ze_mask, mode)); | |
8288 return gen_rtx_SET (VOIDmode, dest, src); | |
8289 } | |
8290 } | |
8291 | |
8292 /* The other case we handle is assignments into a constant-position | |
8293 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents | |
8294 a mask that has all one bits except for a group of zero bits and | |
8295 OTHER is known to have zeros where C1 has ones, this is such an | |
8296 assignment. Compute the position and length from C1. Shift OTHER | |
8297 to the appropriate position, force it to the required mode, and | |
8298 make the extraction. Check for the AND in both operands. */ | |
8299 | |
8300 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) | |
8301 return x; | |
8302 | |
8303 rhs = expand_compound_operation (XEXP (src, 0)); | |
8304 lhs = expand_compound_operation (XEXP (src, 1)); | |
8305 | |
8306 if (GET_CODE (rhs) == AND | |
8307 && GET_CODE (XEXP (rhs, 1)) == CONST_INT | |
8308 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) | |
8309 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; | |
8310 else if (GET_CODE (lhs) == AND | |
8311 && GET_CODE (XEXP (lhs, 1)) == CONST_INT | |
8312 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) | |
8313 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; | |
8314 else | |
8315 return x; | |
8316 | |
8317 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len); | |
8318 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) | |
8319 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT | |
8320 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) | |
8321 return x; | |
8322 | |
8323 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); | |
8324 if (assign == 0) | |
8325 return x; | |
8326 | |
8327 /* The mode to use for the source is the mode of the assignment, or of | |
8328 what is inside a possible STRICT_LOW_PART. */ | |
8329 mode = (GET_CODE (assign) == STRICT_LOW_PART | |
8330 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); | |
8331 | |
8332 /* Shift OTHER right POS places and make it the source, restricting it | |
8333 to the proper length and mode. */ | |
8334 | |
8335 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT, | |
8336 GET_MODE (src), | |
8337 other, pos), | |
8338 dest); | |
8339 src = force_to_mode (src, mode, | |
8340 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT | |
8341 ? ~(unsigned HOST_WIDE_INT) 0 | |
8342 : ((unsigned HOST_WIDE_INT) 1 << len) - 1, | |
8343 0); | |
8344 | |
8345 /* If SRC is masked by an AND that does not make a difference in | |
8346 the value being stored, strip it. */ | |
8347 if (GET_CODE (assign) == ZERO_EXTRACT | |
8348 && GET_CODE (XEXP (assign, 1)) == CONST_INT | |
8349 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT | |
8350 && GET_CODE (src) == AND | |
8351 && GET_CODE (XEXP (src, 1)) == CONST_INT | |
8352 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1)) | |
8353 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)) | |
8354 src = XEXP (src, 0); | |
8355 | |
8356 return gen_rtx_SET (VOIDmode, assign, src); | |
8357 } | |
8358 | |
8359 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) | |
8360 if so. */ | |
8361 | |
8362 static rtx | |
8363 apply_distributive_law (rtx x) | |
8364 { | |
8365 enum rtx_code code = GET_CODE (x); | |
8366 enum rtx_code inner_code; | |
8367 rtx lhs, rhs, other; | |
8368 rtx tem; | |
8369 | |
8370 /* Distributivity is not true for floating point as it can change the | |
8371 value. So we don't do it unless -funsafe-math-optimizations. */ | |
8372 if (FLOAT_MODE_P (GET_MODE (x)) | |
8373 && ! flag_unsafe_math_optimizations) | |
8374 return x; | |
8375 | |
8376 /* The outer operation can only be one of the following: */ | |
8377 if (code != IOR && code != AND && code != XOR | |
8378 && code != PLUS && code != MINUS) | |
8379 return x; | |
8380 | |
8381 lhs = XEXP (x, 0); | |
8382 rhs = XEXP (x, 1); | |
8383 | |
8384 /* If either operand is a primitive we can't do anything, so get out | |
8385 fast. */ | |
8386 if (OBJECT_P (lhs) || OBJECT_P (rhs)) | |
8387 return x; | |
8388 | |
8389 lhs = expand_compound_operation (lhs); | |
8390 rhs = expand_compound_operation (rhs); | |
8391 inner_code = GET_CODE (lhs); | |
8392 if (inner_code != GET_CODE (rhs)) | |
8393 return x; | |
8394 | |
8395 /* See if the inner and outer operations distribute. */ | |
8396 switch (inner_code) | |
8397 { | |
8398 case LSHIFTRT: | |
8399 case ASHIFTRT: | |
8400 case AND: | |
8401 case IOR: | |
8402 /* These all distribute except over PLUS. */ | |
8403 if (code == PLUS || code == MINUS) | |
8404 return x; | |
8405 break; | |
8406 | |
8407 case MULT: | |
8408 if (code != PLUS && code != MINUS) | |
8409 return x; | |
8410 break; | |
8411 | |
8412 case ASHIFT: | |
8413 /* This is also a multiply, so it distributes over everything. */ | |
8414 break; | |
8415 | |
8416 case SUBREG: | |
8417 /* Non-paradoxical SUBREGs distributes over all operations, | |
8418 provided the inner modes and byte offsets are the same, this | |
8419 is an extraction of a low-order part, we don't convert an fp | |
8420 operation to int or vice versa, this is not a vector mode, | |
8421 and we would not be converting a single-word operation into a | |
8422 multi-word operation. The latter test is not required, but | |
8423 it prevents generating unneeded multi-word operations. Some | |
8424 of the previous tests are redundant given the latter test, | |
8425 but are retained because they are required for correctness. | |
8426 | |
8427 We produce the result slightly differently in this case. */ | |
8428 | |
8429 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) | |
8430 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs) | |
8431 || ! subreg_lowpart_p (lhs) | |
8432 || (GET_MODE_CLASS (GET_MODE (lhs)) | |
8433 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) | |
8434 || (GET_MODE_SIZE (GET_MODE (lhs)) | |
8435 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) | |
8436 || VECTOR_MODE_P (GET_MODE (lhs)) | |
8437 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD | |
8438 /* Result might need to be truncated. Don't change mode if | |
8439 explicit truncation is needed. */ | |
8440 || !TRULY_NOOP_TRUNCATION | |
8441 (GET_MODE_BITSIZE (GET_MODE (x)), | |
8442 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs))))) | |
8443 return x; | |
8444 | |
8445 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)), | |
8446 SUBREG_REG (lhs), SUBREG_REG (rhs)); | |
8447 return gen_lowpart (GET_MODE (x), tem); | |
8448 | |
8449 default: | |
8450 return x; | |
8451 } | |
8452 | |
8453 /* Set LHS and RHS to the inner operands (A and B in the example | |
8454 above) and set OTHER to the common operand (C in the example). | |
8455 There is only one way to do this unless the inner operation is | |
8456 commutative. */ | |
8457 if (COMMUTATIVE_ARITH_P (lhs) | |
8458 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) | |
8459 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); | |
8460 else if (COMMUTATIVE_ARITH_P (lhs) | |
8461 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) | |
8462 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); | |
8463 else if (COMMUTATIVE_ARITH_P (lhs) | |
8464 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) | |
8465 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); | |
8466 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) | |
8467 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); | |
8468 else | |
8469 return x; | |
8470 | |
8471 /* Form the new inner operation, seeing if it simplifies first. */ | |
8472 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs); | |
8473 | |
8474 /* There is one exception to the general way of distributing: | |
8475 (a | c) ^ (b | c) -> (a ^ b) & ~c */ | |
8476 if (code == XOR && inner_code == IOR) | |
8477 { | |
8478 inner_code = AND; | |
8479 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x)); | |
8480 } | |
8481 | |
8482 /* We may be able to continuing distributing the result, so call | |
8483 ourselves recursively on the inner operation before forming the | |
8484 outer operation, which we return. */ | |
8485 return simplify_gen_binary (inner_code, GET_MODE (x), | |
8486 apply_distributive_law (tem), other); | |
8487 } | |
8488 | |
8489 /* See if X is of the form (* (+ A B) C), and if so convert to | |
8490 (+ (* A C) (* B C)) and try to simplify. | |
8491 | |
8492 Most of the time, this results in no change. However, if some of | |
8493 the operands are the same or inverses of each other, simplifications | |
8494 will result. | |
8495 | |
8496 For example, (and (ior A B) (not B)) can occur as the result of | |
8497 expanding a bit field assignment. When we apply the distributive | |
8498 law to this, we get (ior (and (A (not B))) (and (B (not B)))), | |
8499 which then simplifies to (and (A (not B))). | |
8500 | |
8501 Note that no checks happen on the validity of applying the inverse | |
8502 distributive law. This is pointless since we can do it in the | |
8503 few places where this routine is called. | |
8504 | |
8505 N is the index of the term that is decomposed (the arithmetic operation, | |
8506 i.e. (+ A B) in the first example above). !N is the index of the term that | |
8507 is distributed, i.e. of C in the first example above. */ | |
8508 static rtx | |
8509 distribute_and_simplify_rtx (rtx x, int n) | |
8510 { | |
8511 enum machine_mode mode; | |
8512 enum rtx_code outer_code, inner_code; | |
8513 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp; | |
8514 | |
8515 decomposed = XEXP (x, n); | |
8516 if (!ARITHMETIC_P (decomposed)) | |
8517 return NULL_RTX; | |
8518 | |
8519 mode = GET_MODE (x); | |
8520 outer_code = GET_CODE (x); | |
8521 distributed = XEXP (x, !n); | |
8522 | |
8523 inner_code = GET_CODE (decomposed); | |
8524 inner_op0 = XEXP (decomposed, 0); | |
8525 inner_op1 = XEXP (decomposed, 1); | |
8526 | |
8527 /* Special case (and (xor B C) (not A)), which is equivalent to | |
8528 (xor (ior A B) (ior A C)) */ | |
8529 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT) | |
8530 { | |
8531 distributed = XEXP (distributed, 0); | |
8532 outer_code = IOR; | |
8533 } | |
8534 | |
8535 if (n == 0) | |
8536 { | |
8537 /* Distribute the second term. */ | |
8538 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed); | |
8539 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed); | |
8540 } | |
8541 else | |
8542 { | |
8543 /* Distribute the first term. */ | |
8544 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0); | |
8545 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1); | |
8546 } | |
8547 | |
8548 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode, | |
8549 new_op0, new_op1)); | |
8550 if (GET_CODE (tmp) != outer_code | |
8551 && rtx_cost (tmp, SET, optimize_this_for_speed_p) | |
8552 < rtx_cost (x, SET, optimize_this_for_speed_p)) | |
8553 return tmp; | |
8554 | |
8555 return NULL_RTX; | |
8556 } | |
8557 | |
8558 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done | |
8559 in MODE. Return an equivalent form, if different from (and VAROP | |
8560 (const_int CONSTOP)). Otherwise, return NULL_RTX. */ | |
8561 | |
8562 static rtx | |
8563 simplify_and_const_int_1 (enum machine_mode mode, rtx varop, | |
8564 unsigned HOST_WIDE_INT constop) | |
8565 { | |
8566 unsigned HOST_WIDE_INT nonzero; | |
8567 unsigned HOST_WIDE_INT orig_constop; | |
8568 rtx orig_varop; | |
8569 int i; | |
8570 | |
8571 orig_varop = varop; | |
8572 orig_constop = constop; | |
8573 if (GET_CODE (varop) == CLOBBER) | |
8574 return NULL_RTX; | |
8575 | |
8576 /* Simplify VAROP knowing that we will be only looking at some of the | |
8577 bits in it. | |
8578 | |
8579 Note by passing in CONSTOP, we guarantee that the bits not set in | |
8580 CONSTOP are not significant and will never be examined. We must | |
8581 ensure that is the case by explicitly masking out those bits | |
8582 before returning. */ | |
8583 varop = force_to_mode (varop, mode, constop, 0); | |
8584 | |
8585 /* If VAROP is a CLOBBER, we will fail so return it. */ | |
8586 if (GET_CODE (varop) == CLOBBER) | |
8587 return varop; | |
8588 | |
8589 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP | |
8590 to VAROP and return the new constant. */ | |
8591 if (GET_CODE (varop) == CONST_INT) | |
8592 return gen_int_mode (INTVAL (varop) & constop, mode); | |
8593 | |
8594 /* See what bits may be nonzero in VAROP. Unlike the general case of | |
8595 a call to nonzero_bits, here we don't care about bits outside | |
8596 MODE. */ | |
8597 | |
8598 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); | |
8599 | |
8600 /* Turn off all bits in the constant that are known to already be zero. | |
8601 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS | |
8602 which is tested below. */ | |
8603 | |
8604 constop &= nonzero; | |
8605 | |
8606 /* If we don't have any bits left, return zero. */ | |
8607 if (constop == 0) | |
8608 return const0_rtx; | |
8609 | |
8610 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is | |
8611 a power of two, we can replace this with an ASHIFT. */ | |
8612 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 | |
8613 && (i = exact_log2 (constop)) >= 0) | |
8614 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); | |
8615 | |
8616 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR | |
8617 or XOR, then try to apply the distributive law. This may eliminate | |
8618 operations if either branch can be simplified because of the AND. | |
8619 It may also make some cases more complex, but those cases probably | |
8620 won't match a pattern either with or without this. */ | |
8621 | |
8622 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) | |
8623 return | |
8624 gen_lowpart | |
8625 (mode, | |
8626 apply_distributive_law | |
8627 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop), | |
8628 simplify_and_const_int (NULL_RTX, | |
8629 GET_MODE (varop), | |
8630 XEXP (varop, 0), | |
8631 constop), | |
8632 simplify_and_const_int (NULL_RTX, | |
8633 GET_MODE (varop), | |
8634 XEXP (varop, 1), | |
8635 constop)))); | |
8636 | |
8637 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute | |
8638 the AND and see if one of the operands simplifies to zero. If so, we | |
8639 may eliminate it. */ | |
8640 | |
8641 if (GET_CODE (varop) == PLUS | |
8642 && exact_log2 (constop + 1) >= 0) | |
8643 { | |
8644 rtx o0, o1; | |
8645 | |
8646 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop); | |
8647 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop); | |
8648 if (o0 == const0_rtx) | |
8649 return o1; | |
8650 if (o1 == const0_rtx) | |
8651 return o0; | |
8652 } | |
8653 | |
8654 /* Make a SUBREG if necessary. If we can't make it, fail. */ | |
8655 varop = gen_lowpart (mode, varop); | |
8656 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) | |
8657 return NULL_RTX; | |
8658 | |
8659 /* If we are only masking insignificant bits, return VAROP. */ | |
8660 if (constop == nonzero) | |
8661 return varop; | |
8662 | |
8663 if (varop == orig_varop && constop == orig_constop) | |
8664 return NULL_RTX; | |
8665 | |
8666 /* Otherwise, return an AND. */ | |
8667 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode)); | |
8668 } | |
8669 | |
8670 | |
8671 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done | |
8672 in MODE. | |
8673 | |
8674 Return an equivalent form, if different from X. Otherwise, return X. If | |
8675 X is zero, we are to always construct the equivalent form. */ | |
8676 | |
8677 static rtx | |
8678 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop, | |
8679 unsigned HOST_WIDE_INT constop) | |
8680 { | |
8681 rtx tem = simplify_and_const_int_1 (mode, varop, constop); | |
8682 if (tem) | |
8683 return tem; | |
8684 | |
8685 if (!x) | |
8686 x = simplify_gen_binary (AND, GET_MODE (varop), varop, | |
8687 gen_int_mode (constop, mode)); | |
8688 if (GET_MODE (x) != mode) | |
8689 x = gen_lowpart (mode, x); | |
8690 return x; | |
8691 } | |
8692 | |
8693 /* Given a REG, X, compute which bits in X can be nonzero. | |
8694 We don't care about bits outside of those defined in MODE. | |
8695 | |
8696 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is | |
8697 a shift, AND, or zero_extract, we can do better. */ | |
8698 | |
8699 static rtx | |
8700 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode, | |
8701 const_rtx known_x ATTRIBUTE_UNUSED, | |
8702 enum machine_mode known_mode ATTRIBUTE_UNUSED, | |
8703 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED, | |
8704 unsigned HOST_WIDE_INT *nonzero) | |
8705 { | |
8706 rtx tem; | |
8707 reg_stat_type *rsp; | |
8708 | |
8709 /* If X is a register whose nonzero bits value is current, use it. | |
8710 Otherwise, if X is a register whose value we can find, use that | |
8711 value. Otherwise, use the previously-computed global nonzero bits | |
8712 for this register. */ | |
8713 | |
8714 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x)); | |
8715 if (rsp->last_set_value != 0 | |
8716 && (rsp->last_set_mode == mode | |
8717 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT | |
8718 && GET_MODE_CLASS (mode) == MODE_INT)) | |
8719 && ((rsp->last_set_label >= label_tick_ebb_start | |
8720 && rsp->last_set_label < label_tick) | |
8721 || (rsp->last_set_label == label_tick | |
8722 && DF_INSN_LUID (rsp->last_set) < subst_low_luid) | |
8723 || (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
8724 && REG_N_SETS (REGNO (x)) == 1 | |
8725 && !REGNO_REG_SET_P | |
8726 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))))) | |
8727 { | |
8728 *nonzero &= rsp->last_set_nonzero_bits; | |
8729 return NULL; | |
8730 } | |
8731 | |
8732 tem = get_last_value (x); | |
8733 | |
8734 if (tem) | |
8735 { | |
8736 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND | |
8737 /* If X is narrower than MODE and TEM is a non-negative | |
8738 constant that would appear negative in the mode of X, | |
8739 sign-extend it for use in reg_nonzero_bits because some | |
8740 machines (maybe most) will actually do the sign-extension | |
8741 and this is the conservative approach. | |
8742 | |
8743 ??? For 2.5, try to tighten up the MD files in this regard | |
8744 instead of this kludge. */ | |
8745 | |
8746 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode) | |
8747 && GET_CODE (tem) == CONST_INT | |
8748 && INTVAL (tem) > 0 | |
8749 && 0 != (INTVAL (tem) | |
8750 & ((HOST_WIDE_INT) 1 | |
8751 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) | |
8752 tem = GEN_INT (INTVAL (tem) | |
8753 | ((HOST_WIDE_INT) (-1) | |
8754 << GET_MODE_BITSIZE (GET_MODE (x)))); | |
8755 #endif | |
8756 return tem; | |
8757 } | |
8758 else if (nonzero_sign_valid && rsp->nonzero_bits) | |
8759 { | |
8760 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits; | |
8761 | |
8762 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)) | |
8763 /* We don't know anything about the upper bits. */ | |
8764 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x)); | |
8765 *nonzero &= mask; | |
8766 } | |
8767 | |
8768 return NULL; | |
8769 } | |
8770 | |
8771 /* Return the number of bits at the high-order end of X that are known to | |
8772 be equal to the sign bit. X will be used in mode MODE; if MODE is | |
8773 VOIDmode, X will be used in its own mode. The returned value will always | |
8774 be between 1 and the number of bits in MODE. */ | |
8775 | |
8776 static rtx | |
8777 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode, | |
8778 const_rtx known_x ATTRIBUTE_UNUSED, | |
8779 enum machine_mode known_mode | |
8780 ATTRIBUTE_UNUSED, | |
8781 unsigned int known_ret ATTRIBUTE_UNUSED, | |
8782 unsigned int *result) | |
8783 { | |
8784 rtx tem; | |
8785 reg_stat_type *rsp; | |
8786 | |
8787 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x)); | |
8788 if (rsp->last_set_value != 0 | |
8789 && rsp->last_set_mode == mode | |
8790 && ((rsp->last_set_label >= label_tick_ebb_start | |
8791 && rsp->last_set_label < label_tick) | |
8792 || (rsp->last_set_label == label_tick | |
8793 && DF_INSN_LUID (rsp->last_set) < subst_low_luid) | |
8794 || (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
8795 && REG_N_SETS (REGNO (x)) == 1 | |
8796 && !REGNO_REG_SET_P | |
8797 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))))) | |
8798 { | |
8799 *result = rsp->last_set_sign_bit_copies; | |
8800 return NULL; | |
8801 } | |
8802 | |
8803 tem = get_last_value (x); | |
8804 if (tem != 0) | |
8805 return tem; | |
8806 | |
8807 if (nonzero_sign_valid && rsp->sign_bit_copies != 0 | |
8808 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode)) | |
8809 *result = rsp->sign_bit_copies; | |
8810 | |
8811 return NULL; | |
8812 } | |
8813 | |
8814 /* Return the number of "extended" bits there are in X, when interpreted | |
8815 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For | |
8816 unsigned quantities, this is the number of high-order zero bits. | |
8817 For signed quantities, this is the number of copies of the sign bit | |
8818 minus 1. In both case, this function returns the number of "spare" | |
8819 bits. For example, if two quantities for which this function returns | |
8820 at least 1 are added, the addition is known not to overflow. | |
8821 | |
8822 This function will always return 0 unless called during combine, which | |
8823 implies that it must be called from a define_split. */ | |
8824 | |
8825 unsigned int | |
8826 extended_count (const_rtx x, enum machine_mode mode, int unsignedp) | |
8827 { | |
8828 if (nonzero_sign_valid == 0) | |
8829 return 0; | |
8830 | |
8831 return (unsignedp | |
8832 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
8833 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1 | |
8834 - floor_log2 (nonzero_bits (x, mode))) | |
8835 : 0) | |
8836 : num_sign_bit_copies (x, mode) - 1); | |
8837 } | |
8838 | |
8839 /* This function is called from `simplify_shift_const' to merge two | |
8840 outer operations. Specifically, we have already found that we need | |
8841 to perform operation *POP0 with constant *PCONST0 at the outermost | |
8842 position. We would now like to also perform OP1 with constant CONST1 | |
8843 (with *POP0 being done last). | |
8844 | |
8845 Return 1 if we can do the operation and update *POP0 and *PCONST0 with | |
8846 the resulting operation. *PCOMP_P is set to 1 if we would need to | |
8847 complement the innermost operand, otherwise it is unchanged. | |
8848 | |
8849 MODE is the mode in which the operation will be done. No bits outside | |
8850 the width of this mode matter. It is assumed that the width of this mode | |
8851 is smaller than or equal to HOST_BITS_PER_WIDE_INT. | |
8852 | |
8853 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS, | |
8854 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper | |
8855 result is simply *PCONST0. | |
8856 | |
8857 If the resulting operation cannot be expressed as one operation, we | |
8858 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ | |
8859 | |
8860 static int | |
8861 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p) | |
8862 { | |
8863 enum rtx_code op0 = *pop0; | |
8864 HOST_WIDE_INT const0 = *pconst0; | |
8865 | |
8866 const0 &= GET_MODE_MASK (mode); | |
8867 const1 &= GET_MODE_MASK (mode); | |
8868 | |
8869 /* If OP0 is an AND, clear unimportant bits in CONST1. */ | |
8870 if (op0 == AND) | |
8871 const1 &= const0; | |
8872 | |
8873 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or | |
8874 if OP0 is SET. */ | |
8875 | |
8876 if (op1 == UNKNOWN || op0 == SET) | |
8877 return 1; | |
8878 | |
8879 else if (op0 == UNKNOWN) | |
8880 op0 = op1, const0 = const1; | |
8881 | |
8882 else if (op0 == op1) | |
8883 { | |
8884 switch (op0) | |
8885 { | |
8886 case AND: | |
8887 const0 &= const1; | |
8888 break; | |
8889 case IOR: | |
8890 const0 |= const1; | |
8891 break; | |
8892 case XOR: | |
8893 const0 ^= const1; | |
8894 break; | |
8895 case PLUS: | |
8896 const0 += const1; | |
8897 break; | |
8898 case NEG: | |
8899 op0 = UNKNOWN; | |
8900 break; | |
8901 default: | |
8902 break; | |
8903 } | |
8904 } | |
8905 | |
8906 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ | |
8907 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) | |
8908 return 0; | |
8909 | |
8910 /* If the two constants aren't the same, we can't do anything. The | |
8911 remaining six cases can all be done. */ | |
8912 else if (const0 != const1) | |
8913 return 0; | |
8914 | |
8915 else | |
8916 switch (op0) | |
8917 { | |
8918 case IOR: | |
8919 if (op1 == AND) | |
8920 /* (a & b) | b == b */ | |
8921 op0 = SET; | |
8922 else /* op1 == XOR */ | |
8923 /* (a ^ b) | b == a | b */ | |
8924 {;} | |
8925 break; | |
8926 | |
8927 case XOR: | |
8928 if (op1 == AND) | |
8929 /* (a & b) ^ b == (~a) & b */ | |
8930 op0 = AND, *pcomp_p = 1; | |
8931 else /* op1 == IOR */ | |
8932 /* (a | b) ^ b == a & ~b */ | |
8933 op0 = AND, const0 = ~const0; | |
8934 break; | |
8935 | |
8936 case AND: | |
8937 if (op1 == IOR) | |
8938 /* (a | b) & b == b */ | |
8939 op0 = SET; | |
8940 else /* op1 == XOR */ | |
8941 /* (a ^ b) & b) == (~a) & b */ | |
8942 *pcomp_p = 1; | |
8943 break; | |
8944 default: | |
8945 break; | |
8946 } | |
8947 | |
8948 /* Check for NO-OP cases. */ | |
8949 const0 &= GET_MODE_MASK (mode); | |
8950 if (const0 == 0 | |
8951 && (op0 == IOR || op0 == XOR || op0 == PLUS)) | |
8952 op0 = UNKNOWN; | |
8953 else if (const0 == 0 && op0 == AND) | |
8954 op0 = SET; | |
8955 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) | |
8956 && op0 == AND) | |
8957 op0 = UNKNOWN; | |
8958 | |
8959 *pop0 = op0; | |
8960 | |
8961 /* ??? Slightly redundant with the above mask, but not entirely. | |
8962 Moving this above means we'd have to sign-extend the mode mask | |
8963 for the final test. */ | |
8964 if (op0 != UNKNOWN && op0 != NEG) | |
8965 *pconst0 = trunc_int_for_mode (const0, mode); | |
8966 | |
8967 return 1; | |
8968 } | |
8969 | |
8970 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. | |
8971 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot | |
8972 simplify it. Otherwise, return a simplified value. | |
8973 | |
8974 The shift is normally computed in the widest mode we find in VAROP, as | |
8975 long as it isn't a different number of words than RESULT_MODE. Exceptions | |
8976 are ASHIFTRT and ROTATE, which are always done in their original mode. */ | |
8977 | |
8978 static rtx | |
8979 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode, | |
8980 rtx varop, int orig_count) | |
8981 { | |
8982 enum rtx_code orig_code = code; | |
8983 rtx orig_varop = varop; | |
8984 int count; | |
8985 enum machine_mode mode = result_mode; | |
8986 enum machine_mode shift_mode, tmode; | |
8987 unsigned int mode_words | |
8988 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; | |
8989 /* We form (outer_op (code varop count) (outer_const)). */ | |
8990 enum rtx_code outer_op = UNKNOWN; | |
8991 HOST_WIDE_INT outer_const = 0; | |
8992 int complement_p = 0; | |
8993 rtx new_rtx, x; | |
8994 | |
8995 /* Make sure and truncate the "natural" shift on the way in. We don't | |
8996 want to do this inside the loop as it makes it more difficult to | |
8997 combine shifts. */ | |
8998 if (SHIFT_COUNT_TRUNCATED) | |
8999 orig_count &= GET_MODE_BITSIZE (mode) - 1; | |
9000 | |
9001 /* If we were given an invalid count, don't do anything except exactly | |
9002 what was requested. */ | |
9003 | |
9004 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode)) | |
9005 return NULL_RTX; | |
9006 | |
9007 count = orig_count; | |
9008 | |
9009 /* Unless one of the branches of the `if' in this loop does a `continue', | |
9010 we will `break' the loop after the `if'. */ | |
9011 | |
9012 while (count != 0) | |
9013 { | |
9014 /* If we have an operand of (clobber (const_int 0)), fail. */ | |
9015 if (GET_CODE (varop) == CLOBBER) | |
9016 return NULL_RTX; | |
9017 | |
9018 /* Convert ROTATERT to ROTATE. */ | |
9019 if (code == ROTATERT) | |
9020 { | |
9021 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);; | |
9022 code = ROTATE; | |
9023 if (VECTOR_MODE_P (result_mode)) | |
9024 count = bitsize / GET_MODE_NUNITS (result_mode) - count; | |
9025 else | |
9026 count = bitsize - count; | |
9027 } | |
9028 | |
9029 /* We need to determine what mode we will do the shift in. If the | |
9030 shift is a right shift or a ROTATE, we must always do it in the mode | |
9031 it was originally done in. Otherwise, we can do it in MODE, the | |
9032 widest mode encountered. */ | |
9033 shift_mode | |
9034 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE | |
9035 ? result_mode : mode); | |
9036 | |
9037 /* Handle cases where the count is greater than the size of the mode | |
9038 minus 1. For ASHIFT, use the size minus one as the count (this can | |
9039 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, | |
9040 take the count modulo the size. For other shifts, the result is | |
9041 zero. | |
9042 | |
9043 Since these shifts are being produced by the compiler by combining | |
9044 multiple operations, each of which are defined, we know what the | |
9045 result is supposed to be. */ | |
9046 | |
9047 if (count > (GET_MODE_BITSIZE (shift_mode) - 1)) | |
9048 { | |
9049 if (code == ASHIFTRT) | |
9050 count = GET_MODE_BITSIZE (shift_mode) - 1; | |
9051 else if (code == ROTATE || code == ROTATERT) | |
9052 count %= GET_MODE_BITSIZE (shift_mode); | |
9053 else | |
9054 { | |
9055 /* We can't simply return zero because there may be an | |
9056 outer op. */ | |
9057 varop = const0_rtx; | |
9058 count = 0; | |
9059 break; | |
9060 } | |
9061 } | |
9062 | |
9063 /* If we discovered we had to complement VAROP, leave. Making a NOT | |
9064 here would cause an infinite loop. */ | |
9065 if (complement_p) | |
9066 break; | |
9067 | |
9068 /* An arithmetic right shift of a quantity known to be -1 or 0 | |
9069 is a no-op. */ | |
9070 if (code == ASHIFTRT | |
9071 && (num_sign_bit_copies (varop, shift_mode) | |
9072 == GET_MODE_BITSIZE (shift_mode))) | |
9073 { | |
9074 count = 0; | |
9075 break; | |
9076 } | |
9077 | |
9078 /* If we are doing an arithmetic right shift and discarding all but | |
9079 the sign bit copies, this is equivalent to doing a shift by the | |
9080 bitsize minus one. Convert it into that shift because it will often | |
9081 allow other simplifications. */ | |
9082 | |
9083 if (code == ASHIFTRT | |
9084 && (count + num_sign_bit_copies (varop, shift_mode) | |
9085 >= GET_MODE_BITSIZE (shift_mode))) | |
9086 count = GET_MODE_BITSIZE (shift_mode) - 1; | |
9087 | |
9088 /* We simplify the tests below and elsewhere by converting | |
9089 ASHIFTRT to LSHIFTRT if we know the sign bit is clear. | |
9090 `make_compound_operation' will convert it to an ASHIFTRT for | |
9091 those machines (such as VAX) that don't have an LSHIFTRT. */ | |
9092 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT | |
9093 && code == ASHIFTRT | |
9094 && ((nonzero_bits (varop, shift_mode) | |
9095 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1))) | |
9096 == 0)) | |
9097 code = LSHIFTRT; | |
9098 | |
9099 if (((code == LSHIFTRT | |
9100 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT | |
9101 && !(nonzero_bits (varop, shift_mode) >> count)) | |
9102 || (code == ASHIFT | |
9103 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT | |
9104 && !((nonzero_bits (varop, shift_mode) << count) | |
9105 & GET_MODE_MASK (shift_mode)))) | |
9106 && !side_effects_p (varop)) | |
9107 varop = const0_rtx; | |
9108 | |
9109 switch (GET_CODE (varop)) | |
9110 { | |
9111 case SIGN_EXTEND: | |
9112 case ZERO_EXTEND: | |
9113 case SIGN_EXTRACT: | |
9114 case ZERO_EXTRACT: | |
9115 new_rtx = expand_compound_operation (varop); | |
9116 if (new_rtx != varop) | |
9117 { | |
9118 varop = new_rtx; | |
9119 continue; | |
9120 } | |
9121 break; | |
9122 | |
9123 case MEM: | |
9124 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH | |
9125 minus the width of a smaller mode, we can do this with a | |
9126 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ | |
9127 if ((code == ASHIFTRT || code == LSHIFTRT) | |
9128 && ! mode_dependent_address_p (XEXP (varop, 0)) | |
9129 && ! MEM_VOLATILE_P (varop) | |
9130 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, | |
9131 MODE_INT, 1)) != BLKmode) | |
9132 { | |
9133 new_rtx = adjust_address_nv (varop, tmode, | |
9134 BYTES_BIG_ENDIAN ? 0 | |
9135 : count / BITS_PER_UNIT); | |
9136 | |
9137 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND | |
9138 : ZERO_EXTEND, mode, new_rtx); | |
9139 count = 0; | |
9140 continue; | |
9141 } | |
9142 break; | |
9143 | |
9144 case SUBREG: | |
9145 /* If VAROP is a SUBREG, strip it as long as the inner operand has | |
9146 the same number of words as what we've seen so far. Then store | |
9147 the widest mode in MODE. */ | |
9148 if (subreg_lowpart_p (varop) | |
9149 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) | |
9150 > GET_MODE_SIZE (GET_MODE (varop))) | |
9151 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) | |
9152 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
9153 == mode_words) | |
9154 { | |
9155 varop = SUBREG_REG (varop); | |
9156 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) | |
9157 mode = GET_MODE (varop); | |
9158 continue; | |
9159 } | |
9160 break; | |
9161 | |
9162 case MULT: | |
9163 /* Some machines use MULT instead of ASHIFT because MULT | |
9164 is cheaper. But it is still better on those machines to | |
9165 merge two shifts into one. */ | |
9166 if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9167 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) | |
9168 { | |
9169 varop | |
9170 = simplify_gen_binary (ASHIFT, GET_MODE (varop), | |
9171 XEXP (varop, 0), | |
9172 GEN_INT (exact_log2 ( | |
9173 INTVAL (XEXP (varop, 1))))); | |
9174 continue; | |
9175 } | |
9176 break; | |
9177 | |
9178 case UDIV: | |
9179 /* Similar, for when divides are cheaper. */ | |
9180 if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9181 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) | |
9182 { | |
9183 varop | |
9184 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop), | |
9185 XEXP (varop, 0), | |
9186 GEN_INT (exact_log2 ( | |
9187 INTVAL (XEXP (varop, 1))))); | |
9188 continue; | |
9189 } | |
9190 break; | |
9191 | |
9192 case ASHIFTRT: | |
9193 /* If we are extracting just the sign bit of an arithmetic | |
9194 right shift, that shift is not needed. However, the sign | |
9195 bit of a wider mode may be different from what would be | |
9196 interpreted as the sign bit in a narrower mode, so, if | |
9197 the result is narrower, don't discard the shift. */ | |
9198 if (code == LSHIFTRT | |
9199 && count == (GET_MODE_BITSIZE (result_mode) - 1) | |
9200 && (GET_MODE_BITSIZE (result_mode) | |
9201 >= GET_MODE_BITSIZE (GET_MODE (varop)))) | |
9202 { | |
9203 varop = XEXP (varop, 0); | |
9204 continue; | |
9205 } | |
9206 | |
9207 /* ... fall through ... */ | |
9208 | |
9209 case LSHIFTRT: | |
9210 case ASHIFT: | |
9211 case ROTATE: | |
9212 /* Here we have two nested shifts. The result is usually the | |
9213 AND of a new shift with a mask. We compute the result below. */ | |
9214 if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9215 && INTVAL (XEXP (varop, 1)) >= 0 | |
9216 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) | |
9217 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT | |
9218 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
9219 && !VECTOR_MODE_P (result_mode)) | |
9220 { | |
9221 enum rtx_code first_code = GET_CODE (varop); | |
9222 unsigned int first_count = INTVAL (XEXP (varop, 1)); | |
9223 unsigned HOST_WIDE_INT mask; | |
9224 rtx mask_rtx; | |
9225 | |
9226 /* We have one common special case. We can't do any merging if | |
9227 the inner code is an ASHIFTRT of a smaller mode. However, if | |
9228 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) | |
9229 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), | |
9230 we can convert it to | |
9231 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). | |
9232 This simplifies certain SIGN_EXTEND operations. */ | |
9233 if (code == ASHIFT && first_code == ASHIFTRT | |
9234 && count == (GET_MODE_BITSIZE (result_mode) | |
9235 - GET_MODE_BITSIZE (GET_MODE (varop)))) | |
9236 { | |
9237 /* C3 has the low-order C1 bits zero. */ | |
9238 | |
9239 mask = (GET_MODE_MASK (mode) | |
9240 & ~(((HOST_WIDE_INT) 1 << first_count) - 1)); | |
9241 | |
9242 varop = simplify_and_const_int (NULL_RTX, result_mode, | |
9243 XEXP (varop, 0), mask); | |
9244 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, | |
9245 varop, count); | |
9246 count = first_count; | |
9247 code = ASHIFTRT; | |
9248 continue; | |
9249 } | |
9250 | |
9251 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more | |
9252 than C1 high-order bits equal to the sign bit, we can convert | |
9253 this to either an ASHIFT or an ASHIFTRT depending on the | |
9254 two counts. | |
9255 | |
9256 We cannot do this if VAROP's mode is not SHIFT_MODE. */ | |
9257 | |
9258 if (code == ASHIFTRT && first_code == ASHIFT | |
9259 && GET_MODE (varop) == shift_mode | |
9260 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) | |
9261 > first_count)) | |
9262 { | |
9263 varop = XEXP (varop, 0); | |
9264 count -= first_count; | |
9265 if (count < 0) | |
9266 { | |
9267 count = -count; | |
9268 code = ASHIFT; | |
9269 } | |
9270 | |
9271 continue; | |
9272 } | |
9273 | |
9274 /* There are some cases we can't do. If CODE is ASHIFTRT, | |
9275 we can only do this if FIRST_CODE is also ASHIFTRT. | |
9276 | |
9277 We can't do the case when CODE is ROTATE and FIRST_CODE is | |
9278 ASHIFTRT. | |
9279 | |
9280 If the mode of this shift is not the mode of the outer shift, | |
9281 we can't do this if either shift is a right shift or ROTATE. | |
9282 | |
9283 Finally, we can't do any of these if the mode is too wide | |
9284 unless the codes are the same. | |
9285 | |
9286 Handle the case where the shift codes are the same | |
9287 first. */ | |
9288 | |
9289 if (code == first_code) | |
9290 { | |
9291 if (GET_MODE (varop) != result_mode | |
9292 && (code == ASHIFTRT || code == LSHIFTRT | |
9293 || code == ROTATE)) | |
9294 break; | |
9295 | |
9296 count += first_count; | |
9297 varop = XEXP (varop, 0); | |
9298 continue; | |
9299 } | |
9300 | |
9301 if (code == ASHIFTRT | |
9302 || (code == ROTATE && first_code == ASHIFTRT) | |
9303 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT | |
9304 || (GET_MODE (varop) != result_mode | |
9305 && (first_code == ASHIFTRT || first_code == LSHIFTRT | |
9306 || first_code == ROTATE | |
9307 || code == ROTATE))) | |
9308 break; | |
9309 | |
9310 /* To compute the mask to apply after the shift, shift the | |
9311 nonzero bits of the inner shift the same way the | |
9312 outer shift will. */ | |
9313 | |
9314 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop))); | |
9315 | |
9316 mask_rtx | |
9317 = simplify_const_binary_operation (code, result_mode, mask_rtx, | |
9318 GEN_INT (count)); | |
9319 | |
9320 /* Give up if we can't compute an outer operation to use. */ | |
9321 if (mask_rtx == 0 | |
9322 || GET_CODE (mask_rtx) != CONST_INT | |
9323 || ! merge_outer_ops (&outer_op, &outer_const, AND, | |
9324 INTVAL (mask_rtx), | |
9325 result_mode, &complement_p)) | |
9326 break; | |
9327 | |
9328 /* If the shifts are in the same direction, we add the | |
9329 counts. Otherwise, we subtract them. */ | |
9330 if ((code == ASHIFTRT || code == LSHIFTRT) | |
9331 == (first_code == ASHIFTRT || first_code == LSHIFTRT)) | |
9332 count += first_count; | |
9333 else | |
9334 count -= first_count; | |
9335 | |
9336 /* If COUNT is positive, the new shift is usually CODE, | |
9337 except for the two exceptions below, in which case it is | |
9338 FIRST_CODE. If the count is negative, FIRST_CODE should | |
9339 always be used */ | |
9340 if (count > 0 | |
9341 && ((first_code == ROTATE && code == ASHIFT) | |
9342 || (first_code == ASHIFTRT && code == LSHIFTRT))) | |
9343 code = first_code; | |
9344 else if (count < 0) | |
9345 code = first_code, count = -count; | |
9346 | |
9347 varop = XEXP (varop, 0); | |
9348 continue; | |
9349 } | |
9350 | |
9351 /* If we have (A << B << C) for any shift, we can convert this to | |
9352 (A << C << B). This wins if A is a constant. Only try this if | |
9353 B is not a constant. */ | |
9354 | |
9355 else if (GET_CODE (varop) == code | |
9356 && GET_CODE (XEXP (varop, 0)) == CONST_INT | |
9357 && GET_CODE (XEXP (varop, 1)) != CONST_INT) | |
9358 { | |
9359 rtx new_rtx = simplify_const_binary_operation (code, mode, | |
9360 XEXP (varop, 0), | |
9361 GEN_INT (count)); | |
9362 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1)); | |
9363 count = 0; | |
9364 continue; | |
9365 } | |
9366 break; | |
9367 | |
9368 case NOT: | |
9369 if (VECTOR_MODE_P (mode)) | |
9370 break; | |
9371 | |
9372 /* Make this fit the case below. */ | |
9373 varop = gen_rtx_XOR (mode, XEXP (varop, 0), | |
9374 GEN_INT (GET_MODE_MASK (mode))); | |
9375 continue; | |
9376 | |
9377 case IOR: | |
9378 case AND: | |
9379 case XOR: | |
9380 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) | |
9381 with C the size of VAROP - 1 and the shift is logical if | |
9382 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
9383 we have an (le X 0) operation. If we have an arithmetic shift | |
9384 and STORE_FLAG_VALUE is 1 or we have a logical shift with | |
9385 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ | |
9386 | |
9387 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS | |
9388 && XEXP (XEXP (varop, 0), 1) == constm1_rtx | |
9389 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
9390 && (code == LSHIFTRT || code == ASHIFTRT) | |
9391 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1) | |
9392 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) | |
9393 { | |
9394 count = 0; | |
9395 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1), | |
9396 const0_rtx); | |
9397 | |
9398 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
9399 varop = gen_rtx_NEG (GET_MODE (varop), varop); | |
9400 | |
9401 continue; | |
9402 } | |
9403 | |
9404 /* If we have (shift (logical)), move the logical to the outside | |
9405 to allow it to possibly combine with another logical and the | |
9406 shift to combine with another shift. This also canonicalizes to | |
9407 what a ZERO_EXTRACT looks like. Also, some machines have | |
9408 (and (shift)) insns. */ | |
9409 | |
9410 if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9411 /* We can't do this if we have (ashiftrt (xor)) and the | |
9412 constant has its sign bit set in shift_mode. */ | |
9413 && !(code == ASHIFTRT && GET_CODE (varop) == XOR | |
9414 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), | |
9415 shift_mode)) | |
9416 && (new_rtx = simplify_const_binary_operation (code, result_mode, | |
9417 XEXP (varop, 1), | |
9418 GEN_INT (count))) != 0 | |
9419 && GET_CODE (new_rtx) == CONST_INT | |
9420 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), | |
9421 INTVAL (new_rtx), result_mode, &complement_p)) | |
9422 { | |
9423 varop = XEXP (varop, 0); | |
9424 continue; | |
9425 } | |
9426 | |
9427 /* If we can't do that, try to simplify the shift in each arm of the | |
9428 logical expression, make a new logical expression, and apply | |
9429 the inverse distributive law. This also can't be done | |
9430 for some (ashiftrt (xor)). */ | |
9431 if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9432 && !(code == ASHIFTRT && GET_CODE (varop) == XOR | |
9433 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), | |
9434 shift_mode))) | |
9435 { | |
9436 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, | |
9437 XEXP (varop, 0), count); | |
9438 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, | |
9439 XEXP (varop, 1), count); | |
9440 | |
9441 varop = simplify_gen_binary (GET_CODE (varop), shift_mode, | |
9442 lhs, rhs); | |
9443 varop = apply_distributive_law (varop); | |
9444 | |
9445 count = 0; | |
9446 continue; | |
9447 } | |
9448 break; | |
9449 | |
9450 case EQ: | |
9451 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE | |
9452 says that the sign bit can be tested, FOO has mode MODE, C is | |
9453 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit | |
9454 that may be nonzero. */ | |
9455 if (code == LSHIFTRT | |
9456 && XEXP (varop, 1) == const0_rtx | |
9457 && GET_MODE (XEXP (varop, 0)) == result_mode | |
9458 && count == (GET_MODE_BITSIZE (result_mode) - 1) | |
9459 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT | |
9460 && STORE_FLAG_VALUE == -1 | |
9461 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 | |
9462 && merge_outer_ops (&outer_op, &outer_const, XOR, | |
9463 (HOST_WIDE_INT) 1, result_mode, | |
9464 &complement_p)) | |
9465 { | |
9466 varop = XEXP (varop, 0); | |
9467 count = 0; | |
9468 continue; | |
9469 } | |
9470 break; | |
9471 | |
9472 case NEG: | |
9473 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less | |
9474 than the number of bits in the mode is equivalent to A. */ | |
9475 if (code == LSHIFTRT | |
9476 && count == (GET_MODE_BITSIZE (result_mode) - 1) | |
9477 && nonzero_bits (XEXP (varop, 0), result_mode) == 1) | |
9478 { | |
9479 varop = XEXP (varop, 0); | |
9480 count = 0; | |
9481 continue; | |
9482 } | |
9483 | |
9484 /* NEG commutes with ASHIFT since it is multiplication. Move the | |
9485 NEG outside to allow shifts to combine. */ | |
9486 if (code == ASHIFT | |
9487 && merge_outer_ops (&outer_op, &outer_const, NEG, | |
9488 (HOST_WIDE_INT) 0, result_mode, | |
9489 &complement_p)) | |
9490 { | |
9491 varop = XEXP (varop, 0); | |
9492 continue; | |
9493 } | |
9494 break; | |
9495 | |
9496 case PLUS: | |
9497 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C | |
9498 is one less than the number of bits in the mode is | |
9499 equivalent to (xor A 1). */ | |
9500 if (code == LSHIFTRT | |
9501 && count == (GET_MODE_BITSIZE (result_mode) - 1) | |
9502 && XEXP (varop, 1) == constm1_rtx | |
9503 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 | |
9504 && merge_outer_ops (&outer_op, &outer_const, XOR, | |
9505 (HOST_WIDE_INT) 1, result_mode, | |
9506 &complement_p)) | |
9507 { | |
9508 count = 0; | |
9509 varop = XEXP (varop, 0); | |
9510 continue; | |
9511 } | |
9512 | |
9513 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits | |
9514 that might be nonzero in BAR are those being shifted out and those | |
9515 bits are known zero in FOO, we can replace the PLUS with FOO. | |
9516 Similarly in the other operand order. This code occurs when | |
9517 we are computing the size of a variable-size array. */ | |
9518 | |
9519 if ((code == ASHIFTRT || code == LSHIFTRT) | |
9520 && count < HOST_BITS_PER_WIDE_INT | |
9521 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 | |
9522 && (nonzero_bits (XEXP (varop, 1), result_mode) | |
9523 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) | |
9524 { | |
9525 varop = XEXP (varop, 0); | |
9526 continue; | |
9527 } | |
9528 else if ((code == ASHIFTRT || code == LSHIFTRT) | |
9529 && count < HOST_BITS_PER_WIDE_INT | |
9530 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT | |
9531 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) | |
9532 >> count) | |
9533 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) | |
9534 & nonzero_bits (XEXP (varop, 1), | |
9535 result_mode))) | |
9536 { | |
9537 varop = XEXP (varop, 1); | |
9538 continue; | |
9539 } | |
9540 | |
9541 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ | |
9542 if (code == ASHIFT | |
9543 && GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9544 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode, | |
9545 XEXP (varop, 1), | |
9546 GEN_INT (count))) != 0 | |
9547 && GET_CODE (new_rtx) == CONST_INT | |
9548 && merge_outer_ops (&outer_op, &outer_const, PLUS, | |
9549 INTVAL (new_rtx), result_mode, &complement_p)) | |
9550 { | |
9551 varop = XEXP (varop, 0); | |
9552 continue; | |
9553 } | |
9554 | |
9555 /* Check for 'PLUS signbit', which is the canonical form of 'XOR | |
9556 signbit', and attempt to change the PLUS to an XOR and move it to | |
9557 the outer operation as is done above in the AND/IOR/XOR case | |
9558 leg for shift(logical). See details in logical handling above | |
9559 for reasoning in doing so. */ | |
9560 if (code == LSHIFTRT | |
9561 && GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9562 && mode_signbit_p (result_mode, XEXP (varop, 1)) | |
9563 && (new_rtx = simplify_const_binary_operation (code, result_mode, | |
9564 XEXP (varop, 1), | |
9565 GEN_INT (count))) != 0 | |
9566 && GET_CODE (new_rtx) == CONST_INT | |
9567 && merge_outer_ops (&outer_op, &outer_const, XOR, | |
9568 INTVAL (new_rtx), result_mode, &complement_p)) | |
9569 { | |
9570 varop = XEXP (varop, 0); | |
9571 continue; | |
9572 } | |
9573 | |
9574 break; | |
9575 | |
9576 case MINUS: | |
9577 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) | |
9578 with C the size of VAROP - 1 and the shift is logical if | |
9579 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
9580 we have a (gt X 0) operation. If the shift is arithmetic with | |
9581 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, | |
9582 we have a (neg (gt X 0)) operation. */ | |
9583 | |
9584 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
9585 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT | |
9586 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1) | |
9587 && (code == LSHIFTRT || code == ASHIFTRT) | |
9588 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
9589 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count | |
9590 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) | |
9591 { | |
9592 count = 0; | |
9593 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1), | |
9594 const0_rtx); | |
9595 | |
9596 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
9597 varop = gen_rtx_NEG (GET_MODE (varop), varop); | |
9598 | |
9599 continue; | |
9600 } | |
9601 break; | |
9602 | |
9603 case TRUNCATE: | |
9604 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) | |
9605 if the truncate does not affect the value. */ | |
9606 if (code == LSHIFTRT | |
9607 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT | |
9608 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
9609 && (INTVAL (XEXP (XEXP (varop, 0), 1)) | |
9610 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0))) | |
9611 - GET_MODE_BITSIZE (GET_MODE (varop))))) | |
9612 { | |
9613 rtx varop_inner = XEXP (varop, 0); | |
9614 | |
9615 varop_inner | |
9616 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner), | |
9617 XEXP (varop_inner, 0), | |
9618 GEN_INT | |
9619 (count + INTVAL (XEXP (varop_inner, 1)))); | |
9620 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner); | |
9621 count = 0; | |
9622 continue; | |
9623 } | |
9624 break; | |
9625 | |
9626 default: | |
9627 break; | |
9628 } | |
9629 | |
9630 break; | |
9631 } | |
9632 | |
9633 /* We need to determine what mode to do the shift in. If the shift is | |
9634 a right shift or ROTATE, we must always do it in the mode it was | |
9635 originally done in. Otherwise, we can do it in MODE, the widest mode | |
9636 encountered. The code we care about is that of the shift that will | |
9637 actually be done, not the shift that was originally requested. */ | |
9638 shift_mode | |
9639 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE | |
9640 ? result_mode : mode); | |
9641 | |
9642 /* We have now finished analyzing the shift. The result should be | |
9643 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If | |
9644 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied | |
9645 to the result of the shift. OUTER_CONST is the relevant constant, | |
9646 but we must turn off all bits turned off in the shift. */ | |
9647 | |
9648 if (outer_op == UNKNOWN | |
9649 && orig_code == code && orig_count == count | |
9650 && varop == orig_varop | |
9651 && shift_mode == GET_MODE (varop)) | |
9652 return NULL_RTX; | |
9653 | |
9654 /* Make a SUBREG if necessary. If we can't make it, fail. */ | |
9655 varop = gen_lowpart (shift_mode, varop); | |
9656 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) | |
9657 return NULL_RTX; | |
9658 | |
9659 /* If we have an outer operation and we just made a shift, it is | |
9660 possible that we could have simplified the shift were it not | |
9661 for the outer operation. So try to do the simplification | |
9662 recursively. */ | |
9663 | |
9664 if (outer_op != UNKNOWN) | |
9665 x = simplify_shift_const_1 (code, shift_mode, varop, count); | |
9666 else | |
9667 x = NULL_RTX; | |
9668 | |
9669 if (x == NULL_RTX) | |
9670 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count)); | |
9671 | |
9672 /* If we were doing an LSHIFTRT in a wider mode than it was originally, | |
9673 turn off all the bits that the shift would have turned off. */ | |
9674 if (orig_code == LSHIFTRT && result_mode != shift_mode) | |
9675 x = simplify_and_const_int (NULL_RTX, shift_mode, x, | |
9676 GET_MODE_MASK (result_mode) >> orig_count); | |
9677 | |
9678 /* Do the remainder of the processing in RESULT_MODE. */ | |
9679 x = gen_lowpart_or_truncate (result_mode, x); | |
9680 | |
9681 /* If COMPLEMENT_P is set, we have to complement X before doing the outer | |
9682 operation. */ | |
9683 if (complement_p) | |
9684 x = simplify_gen_unary (NOT, result_mode, x, result_mode); | |
9685 | |
9686 if (outer_op != UNKNOWN) | |
9687 { | |
9688 if (GET_RTX_CLASS (outer_op) != RTX_UNARY | |
9689 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) | |
9690 outer_const = trunc_int_for_mode (outer_const, result_mode); | |
9691 | |
9692 if (outer_op == AND) | |
9693 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); | |
9694 else if (outer_op == SET) | |
9695 { | |
9696 /* This means that we have determined that the result is | |
9697 equivalent to a constant. This should be rare. */ | |
9698 if (!side_effects_p (x)) | |
9699 x = GEN_INT (outer_const); | |
9700 } | |
9701 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY) | |
9702 x = simplify_gen_unary (outer_op, result_mode, x, result_mode); | |
9703 else | |
9704 x = simplify_gen_binary (outer_op, result_mode, x, | |
9705 GEN_INT (outer_const)); | |
9706 } | |
9707 | |
9708 return x; | |
9709 } | |
9710 | |
9711 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. | |
9712 The result of the shift is RESULT_MODE. If we cannot simplify it, | |
9713 return X or, if it is NULL, synthesize the expression with | |
9714 simplify_gen_binary. Otherwise, return a simplified value. | |
9715 | |
9716 The shift is normally computed in the widest mode we find in VAROP, as | |
9717 long as it isn't a different number of words than RESULT_MODE. Exceptions | |
9718 are ASHIFTRT and ROTATE, which are always done in their original mode. */ | |
9719 | |
9720 static rtx | |
9721 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode, | |
9722 rtx varop, int count) | |
9723 { | |
9724 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count); | |
9725 if (tem) | |
9726 return tem; | |
9727 | |
9728 if (!x) | |
9729 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count)); | |
9730 if (GET_MODE (x) != result_mode) | |
9731 x = gen_lowpart (result_mode, x); | |
9732 return x; | |
9733 } | |
9734 | |
9735 | |
9736 /* Like recog, but we receive the address of a pointer to a new pattern. | |
9737 We try to match the rtx that the pointer points to. | |
9738 If that fails, we may try to modify or replace the pattern, | |
9739 storing the replacement into the same pointer object. | |
9740 | |
9741 Modifications include deletion or addition of CLOBBERs. | |
9742 | |
9743 PNOTES is a pointer to a location where any REG_UNUSED notes added for | |
9744 the CLOBBERs are placed. | |
9745 | |
9746 The value is the final insn code from the pattern ultimately matched, | |
9747 or -1. */ | |
9748 | |
9749 static int | |
9750 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes) | |
9751 { | |
9752 rtx pat = *pnewpat; | |
9753 int insn_code_number; | |
9754 int num_clobbers_to_add = 0; | |
9755 int i; | |
9756 rtx notes = 0; | |
9757 rtx old_notes, old_pat; | |
9758 | |
9759 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER | |
9760 we use to indicate that something didn't match. If we find such a | |
9761 thing, force rejection. */ | |
9762 if (GET_CODE (pat) == PARALLEL) | |
9763 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) | |
9764 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER | |
9765 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) | |
9766 return -1; | |
9767 | |
9768 old_pat = PATTERN (insn); | |
9769 old_notes = REG_NOTES (insn); | |
9770 PATTERN (insn) = pat; | |
9771 REG_NOTES (insn) = 0; | |
9772 | |
9773 insn_code_number = recog (pat, insn, &num_clobbers_to_add); | |
9774 if (dump_file && (dump_flags & TDF_DETAILS)) | |
9775 { | |
9776 if (insn_code_number < 0) | |
9777 fputs ("Failed to match this instruction:\n", dump_file); | |
9778 else | |
9779 fputs ("Successfully matched this instruction:\n", dump_file); | |
9780 print_rtl_single (dump_file, pat); | |
9781 } | |
9782 | |
9783 /* If it isn't, there is the possibility that we previously had an insn | |
9784 that clobbered some register as a side effect, but the combined | |
9785 insn doesn't need to do that. So try once more without the clobbers | |
9786 unless this represents an ASM insn. */ | |
9787 | |
9788 if (insn_code_number < 0 && ! check_asm_operands (pat) | |
9789 && GET_CODE (pat) == PARALLEL) | |
9790 { | |
9791 int pos; | |
9792 | |
9793 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) | |
9794 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) | |
9795 { | |
9796 if (i != pos) | |
9797 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); | |
9798 pos++; | |
9799 } | |
9800 | |
9801 SUBST_INT (XVECLEN (pat, 0), pos); | |
9802 | |
9803 if (pos == 1) | |
9804 pat = XVECEXP (pat, 0, 0); | |
9805 | |
9806 PATTERN (insn) = pat; | |
9807 insn_code_number = recog (pat, insn, &num_clobbers_to_add); | |
9808 if (dump_file && (dump_flags & TDF_DETAILS)) | |
9809 { | |
9810 if (insn_code_number < 0) | |
9811 fputs ("Failed to match this instruction:\n", dump_file); | |
9812 else | |
9813 fputs ("Successfully matched this instruction:\n", dump_file); | |
9814 print_rtl_single (dump_file, pat); | |
9815 } | |
9816 } | |
9817 PATTERN (insn) = old_pat; | |
9818 REG_NOTES (insn) = old_notes; | |
9819 | |
9820 /* Recognize all noop sets, these will be killed by followup pass. */ | |
9821 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat)) | |
9822 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0; | |
9823 | |
9824 /* If we had any clobbers to add, make a new pattern than contains | |
9825 them. Then check to make sure that all of them are dead. */ | |
9826 if (num_clobbers_to_add) | |
9827 { | |
9828 rtx newpat = gen_rtx_PARALLEL (VOIDmode, | |
9829 rtvec_alloc (GET_CODE (pat) == PARALLEL | |
9830 ? (XVECLEN (pat, 0) | |
9831 + num_clobbers_to_add) | |
9832 : num_clobbers_to_add + 1)); | |
9833 | |
9834 if (GET_CODE (pat) == PARALLEL) | |
9835 for (i = 0; i < XVECLEN (pat, 0); i++) | |
9836 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); | |
9837 else | |
9838 XVECEXP (newpat, 0, 0) = pat; | |
9839 | |
9840 add_clobbers (newpat, insn_code_number); | |
9841 | |
9842 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; | |
9843 i < XVECLEN (newpat, 0); i++) | |
9844 { | |
9845 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)) | |
9846 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) | |
9847 return -1; | |
9848 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH) | |
9849 { | |
9850 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))); | |
9851 notes = gen_rtx_EXPR_LIST (REG_UNUSED, | |
9852 XEXP (XVECEXP (newpat, 0, i), 0), notes); | |
9853 } | |
9854 } | |
9855 pat = newpat; | |
9856 } | |
9857 | |
9858 *pnewpat = pat; | |
9859 *pnotes = notes; | |
9860 | |
9861 return insn_code_number; | |
9862 } | |
9863 | |
9864 /* Like gen_lowpart_general but for use by combine. In combine it | |
9865 is not possible to create any new pseudoregs. However, it is | |
9866 safe to create invalid memory addresses, because combine will | |
9867 try to recognize them and all they will do is make the combine | |
9868 attempt fail. | |
9869 | |
9870 If for some reason this cannot do its job, an rtx | |
9871 (clobber (const_int 0)) is returned. | |
9872 An insn containing that will not be recognized. */ | |
9873 | |
9874 static rtx | |
9875 gen_lowpart_for_combine (enum machine_mode omode, rtx x) | |
9876 { | |
9877 enum machine_mode imode = GET_MODE (x); | |
9878 unsigned int osize = GET_MODE_SIZE (omode); | |
9879 unsigned int isize = GET_MODE_SIZE (imode); | |
9880 rtx result; | |
9881 | |
9882 if (omode == imode) | |
9883 return x; | |
9884 | |
9885 /* Return identity if this is a CONST or symbolic reference. */ | |
9886 if (omode == Pmode | |
9887 && (GET_CODE (x) == CONST | |
9888 || GET_CODE (x) == SYMBOL_REF | |
9889 || GET_CODE (x) == LABEL_REF)) | |
9890 return x; | |
9891 | |
9892 /* We can only support MODE being wider than a word if X is a | |
9893 constant integer or has a mode the same size. */ | |
9894 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD | |
9895 && ! ((imode == VOIDmode | |
9896 && (GET_CODE (x) == CONST_INT | |
9897 || GET_CODE (x) == CONST_DOUBLE)) | |
9898 || isize == osize)) | |
9899 goto fail; | |
9900 | |
9901 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart | |
9902 won't know what to do. So we will strip off the SUBREG here and | |
9903 process normally. */ | |
9904 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x))) | |
9905 { | |
9906 x = SUBREG_REG (x); | |
9907 | |
9908 /* For use in case we fall down into the address adjustments | |
9909 further below, we need to adjust the known mode and size of | |
9910 x; imode and isize, since we just adjusted x. */ | |
9911 imode = GET_MODE (x); | |
9912 | |
9913 if (imode == omode) | |
9914 return x; | |
9915 | |
9916 isize = GET_MODE_SIZE (imode); | |
9917 } | |
9918 | |
9919 result = gen_lowpart_common (omode, x); | |
9920 | |
9921 if (result) | |
9922 return result; | |
9923 | |
9924 if (MEM_P (x)) | |
9925 { | |
9926 int offset = 0; | |
9927 | |
9928 /* Refuse to work on a volatile memory ref or one with a mode-dependent | |
9929 address. */ | |
9930 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) | |
9931 goto fail; | |
9932 | |
9933 /* If we want to refer to something bigger than the original memref, | |
9934 generate a paradoxical subreg instead. That will force a reload | |
9935 of the original memref X. */ | |
9936 if (isize < osize) | |
9937 return gen_rtx_SUBREG (omode, x, 0); | |
9938 | |
9939 if (WORDS_BIG_ENDIAN) | |
9940 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD); | |
9941 | |
9942 /* Adjust the address so that the address-after-the-data is | |
9943 unchanged. */ | |
9944 if (BYTES_BIG_ENDIAN) | |
9945 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize); | |
9946 | |
9947 return adjust_address_nv (x, omode, offset); | |
9948 } | |
9949 | |
9950 /* If X is a comparison operator, rewrite it in a new mode. This | |
9951 probably won't match, but may allow further simplifications. */ | |
9952 else if (COMPARISON_P (x)) | |
9953 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1)); | |
9954 | |
9955 /* If we couldn't simplify X any other way, just enclose it in a | |
9956 SUBREG. Normally, this SUBREG won't match, but some patterns may | |
9957 include an explicit SUBREG or we may simplify it further in combine. */ | |
9958 else | |
9959 { | |
9960 int offset = 0; | |
9961 rtx res; | |
9962 | |
9963 offset = subreg_lowpart_offset (omode, imode); | |
9964 if (imode == VOIDmode) | |
9965 { | |
9966 imode = int_mode_for_mode (omode); | |
9967 x = gen_lowpart_common (imode, x); | |
9968 if (x == NULL) | |
9969 goto fail; | |
9970 } | |
9971 res = simplify_gen_subreg (omode, x, imode, offset); | |
9972 if (res) | |
9973 return res; | |
9974 } | |
9975 | |
9976 fail: | |
9977 return gen_rtx_CLOBBER (omode, const0_rtx); | |
9978 } | |
9979 | |
9980 /* Simplify a comparison between *POP0 and *POP1 where CODE is the | |
9981 comparison code that will be tested. | |
9982 | |
9983 The result is a possibly different comparison code to use. *POP0 and | |
9984 *POP1 may be updated. | |
9985 | |
9986 It is possible that we might detect that a comparison is either always | |
9987 true or always false. However, we do not perform general constant | |
9988 folding in combine, so this knowledge isn't useful. Such tautologies | |
9989 should have been detected earlier. Hence we ignore all such cases. */ | |
9990 | |
9991 static enum rtx_code | |
9992 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) | |
9993 { | |
9994 rtx op0 = *pop0; | |
9995 rtx op1 = *pop1; | |
9996 rtx tem, tem1; | |
9997 int i; | |
9998 enum machine_mode mode, tmode; | |
9999 | |
10000 /* Try a few ways of applying the same transformation to both operands. */ | |
10001 while (1) | |
10002 { | |
10003 #ifndef WORD_REGISTER_OPERATIONS | |
10004 /* The test below this one won't handle SIGN_EXTENDs on these machines, | |
10005 so check specially. */ | |
10006 if (code != GTU && code != GEU && code != LTU && code != LEU | |
10007 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT | |
10008 && GET_CODE (XEXP (op0, 0)) == ASHIFT | |
10009 && GET_CODE (XEXP (op1, 0)) == ASHIFT | |
10010 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG | |
10011 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG | |
10012 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) | |
10013 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) | |
10014 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10015 && XEXP (op0, 1) == XEXP (op1, 1) | |
10016 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) | |
10017 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1) | |
10018 && (INTVAL (XEXP (op0, 1)) | |
10019 == (GET_MODE_BITSIZE (GET_MODE (op0)) | |
10020 - (GET_MODE_BITSIZE | |
10021 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) | |
10022 { | |
10023 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); | |
10024 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); | |
10025 } | |
10026 #endif | |
10027 | |
10028 /* If both operands are the same constant shift, see if we can ignore the | |
10029 shift. We can if the shift is a rotate or if the bits shifted out of | |
10030 this shift are known to be zero for both inputs and if the type of | |
10031 comparison is compatible with the shift. */ | |
10032 if (GET_CODE (op0) == GET_CODE (op1) | |
10033 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT | |
10034 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) | |
10035 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) | |
10036 && (code != GT && code != LT && code != GE && code != LE)) | |
10037 || (GET_CODE (op0) == ASHIFTRT | |
10038 && (code != GTU && code != LTU | |
10039 && code != GEU && code != LEU))) | |
10040 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10041 && INTVAL (XEXP (op0, 1)) >= 0 | |
10042 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT | |
10043 && XEXP (op0, 1) == XEXP (op1, 1)) | |
10044 { | |
10045 enum machine_mode mode = GET_MODE (op0); | |
10046 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); | |
10047 int shift_count = INTVAL (XEXP (op0, 1)); | |
10048 | |
10049 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) | |
10050 mask &= (mask >> shift_count) << shift_count; | |
10051 else if (GET_CODE (op0) == ASHIFT) | |
10052 mask = (mask & (mask << shift_count)) >> shift_count; | |
10053 | |
10054 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0 | |
10055 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0) | |
10056 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); | |
10057 else | |
10058 break; | |
10059 } | |
10060 | |
10061 /* If both operands are AND's of a paradoxical SUBREG by constant, the | |
10062 SUBREGs are of the same mode, and, in both cases, the AND would | |
10063 be redundant if the comparison was done in the narrower mode, | |
10064 do the comparison in the narrower mode (e.g., we are AND'ing with 1 | |
10065 and the operand's possibly nonzero bits are 0xffffff01; in that case | |
10066 if we only care about QImode, we don't need the AND). This case | |
10067 occurs if the output mode of an scc insn is not SImode and | |
10068 STORE_FLAG_VALUE == 1 (e.g., the 386). | |
10069 | |
10070 Similarly, check for a case where the AND's are ZERO_EXTEND | |
10071 operations from some narrower mode even though a SUBREG is not | |
10072 present. */ | |
10073 | |
10074 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND | |
10075 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10076 && GET_CODE (XEXP (op1, 1)) == CONST_INT) | |
10077 { | |
10078 rtx inner_op0 = XEXP (op0, 0); | |
10079 rtx inner_op1 = XEXP (op1, 0); | |
10080 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); | |
10081 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); | |
10082 int changed = 0; | |
10083 | |
10084 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG | |
10085 && (GET_MODE_SIZE (GET_MODE (inner_op0)) | |
10086 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0)))) | |
10087 && (GET_MODE (SUBREG_REG (inner_op0)) | |
10088 == GET_MODE (SUBREG_REG (inner_op1))) | |
10089 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0))) | |
10090 <= HOST_BITS_PER_WIDE_INT) | |
10091 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), | |
10092 GET_MODE (SUBREG_REG (inner_op0))))) | |
10093 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), | |
10094 GET_MODE (SUBREG_REG (inner_op1)))))) | |
10095 { | |
10096 op0 = SUBREG_REG (inner_op0); | |
10097 op1 = SUBREG_REG (inner_op1); | |
10098 | |
10099 /* The resulting comparison is always unsigned since we masked | |
10100 off the original sign bit. */ | |
10101 code = unsigned_condition (code); | |
10102 | |
10103 changed = 1; | |
10104 } | |
10105 | |
10106 else if (c0 == c1) | |
10107 for (tmode = GET_CLASS_NARROWEST_MODE | |
10108 (GET_MODE_CLASS (GET_MODE (op0))); | |
10109 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) | |
10110 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) | |
10111 { | |
10112 op0 = gen_lowpart (tmode, inner_op0); | |
10113 op1 = gen_lowpart (tmode, inner_op1); | |
10114 code = unsigned_condition (code); | |
10115 changed = 1; | |
10116 break; | |
10117 } | |
10118 | |
10119 if (! changed) | |
10120 break; | |
10121 } | |
10122 | |
10123 /* If both operands are NOT, we can strip off the outer operation | |
10124 and adjust the comparison code for swapped operands; similarly for | |
10125 NEG, except that this must be an equality comparison. */ | |
10126 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) | |
10127 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG | |
10128 && (code == EQ || code == NE))) | |
10129 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); | |
10130 | |
10131 else | |
10132 break; | |
10133 } | |
10134 | |
10135 /* If the first operand is a constant, swap the operands and adjust the | |
10136 comparison code appropriately, but don't do this if the second operand | |
10137 is already a constant integer. */ | |
10138 if (swap_commutative_operands_p (op0, op1)) | |
10139 { | |
10140 tem = op0, op0 = op1, op1 = tem; | |
10141 code = swap_condition (code); | |
10142 } | |
10143 | |
10144 /* We now enter a loop during which we will try to simplify the comparison. | |
10145 For the most part, we only are concerned with comparisons with zero, | |
10146 but some things may really be comparisons with zero but not start | |
10147 out looking that way. */ | |
10148 | |
10149 while (GET_CODE (op1) == CONST_INT) | |
10150 { | |
10151 enum machine_mode mode = GET_MODE (op0); | |
10152 unsigned int mode_width = GET_MODE_BITSIZE (mode); | |
10153 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); | |
10154 int equality_comparison_p; | |
10155 int sign_bit_comparison_p; | |
10156 int unsigned_comparison_p; | |
10157 HOST_WIDE_INT const_op; | |
10158 | |
10159 /* We only want to handle integral modes. This catches VOIDmode, | |
10160 CCmode, and the floating-point modes. An exception is that we | |
10161 can handle VOIDmode if OP0 is a COMPARE or a comparison | |
10162 operation. */ | |
10163 | |
10164 if (GET_MODE_CLASS (mode) != MODE_INT | |
10165 && ! (mode == VOIDmode | |
10166 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0)))) | |
10167 break; | |
10168 | |
10169 /* Get the constant we are comparing against and turn off all bits | |
10170 not on in our mode. */ | |
10171 const_op = INTVAL (op1); | |
10172 if (mode != VOIDmode) | |
10173 const_op = trunc_int_for_mode (const_op, mode); | |
10174 op1 = GEN_INT (const_op); | |
10175 | |
10176 /* If we are comparing against a constant power of two and the value | |
10177 being compared can only have that single bit nonzero (e.g., it was | |
10178 `and'ed with that bit), we can replace this with a comparison | |
10179 with zero. */ | |
10180 if (const_op | |
10181 && (code == EQ || code == NE || code == GE || code == GEU | |
10182 || code == LT || code == LTU) | |
10183 && mode_width <= HOST_BITS_PER_WIDE_INT | |
10184 && exact_log2 (const_op) >= 0 | |
10185 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op) | |
10186 { | |
10187 code = (code == EQ || code == GE || code == GEU ? NE : EQ); | |
10188 op1 = const0_rtx, const_op = 0; | |
10189 } | |
10190 | |
10191 /* Similarly, if we are comparing a value known to be either -1 or | |
10192 0 with -1, change it to the opposite comparison against zero. */ | |
10193 | |
10194 if (const_op == -1 | |
10195 && (code == EQ || code == NE || code == GT || code == LE | |
10196 || code == GEU || code == LTU) | |
10197 && num_sign_bit_copies (op0, mode) == mode_width) | |
10198 { | |
10199 code = (code == EQ || code == LE || code == GEU ? NE : EQ); | |
10200 op1 = const0_rtx, const_op = 0; | |
10201 } | |
10202 | |
10203 /* Do some canonicalizations based on the comparison code. We prefer | |
10204 comparisons against zero and then prefer equality comparisons. | |
10205 If we can reduce the size of a constant, we will do that too. */ | |
10206 | |
10207 switch (code) | |
10208 { | |
10209 case LT: | |
10210 /* < C is equivalent to <= (C - 1) */ | |
10211 if (const_op > 0) | |
10212 { | |
10213 const_op -= 1; | |
10214 op1 = GEN_INT (const_op); | |
10215 code = LE; | |
10216 /* ... fall through to LE case below. */ | |
10217 } | |
10218 else | |
10219 break; | |
10220 | |
10221 case LE: | |
10222 /* <= C is equivalent to < (C + 1); we do this for C < 0 */ | |
10223 if (const_op < 0) | |
10224 { | |
10225 const_op += 1; | |
10226 op1 = GEN_INT (const_op); | |
10227 code = LT; | |
10228 } | |
10229 | |
10230 /* If we are doing a <= 0 comparison on a value known to have | |
10231 a zero sign bit, we can replace this with == 0. */ | |
10232 else if (const_op == 0 | |
10233 && mode_width <= HOST_BITS_PER_WIDE_INT | |
10234 && (nonzero_bits (op0, mode) | |
10235 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) | |
10236 code = EQ; | |
10237 break; | |
10238 | |
10239 case GE: | |
10240 /* >= C is equivalent to > (C - 1). */ | |
10241 if (const_op > 0) | |
10242 { | |
10243 const_op -= 1; | |
10244 op1 = GEN_INT (const_op); | |
10245 code = GT; | |
10246 /* ... fall through to GT below. */ | |
10247 } | |
10248 else | |
10249 break; | |
10250 | |
10251 case GT: | |
10252 /* > C is equivalent to >= (C + 1); we do this for C < 0. */ | |
10253 if (const_op < 0) | |
10254 { | |
10255 const_op += 1; | |
10256 op1 = GEN_INT (const_op); | |
10257 code = GE; | |
10258 } | |
10259 | |
10260 /* If we are doing a > 0 comparison on a value known to have | |
10261 a zero sign bit, we can replace this with != 0. */ | |
10262 else if (const_op == 0 | |
10263 && mode_width <= HOST_BITS_PER_WIDE_INT | |
10264 && (nonzero_bits (op0, mode) | |
10265 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) | |
10266 code = NE; | |
10267 break; | |
10268 | |
10269 case LTU: | |
10270 /* < C is equivalent to <= (C - 1). */ | |
10271 if (const_op > 0) | |
10272 { | |
10273 const_op -= 1; | |
10274 op1 = GEN_INT (const_op); | |
10275 code = LEU; | |
10276 /* ... fall through ... */ | |
10277 } | |
10278 | |
10279 /* (unsigned) < 0x80000000 is equivalent to >= 0. */ | |
10280 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) | |
10281 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) | |
10282 { | |
10283 const_op = 0, op1 = const0_rtx; | |
10284 code = GE; | |
10285 break; | |
10286 } | |
10287 else | |
10288 break; | |
10289 | |
10290 case LEU: | |
10291 /* unsigned <= 0 is equivalent to == 0 */ | |
10292 if (const_op == 0) | |
10293 code = EQ; | |
10294 | |
10295 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ | |
10296 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) | |
10297 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) | |
10298 { | |
10299 const_op = 0, op1 = const0_rtx; | |
10300 code = GE; | |
10301 } | |
10302 break; | |
10303 | |
10304 case GEU: | |
10305 /* >= C is equivalent to > (C - 1). */ | |
10306 if (const_op > 1) | |
10307 { | |
10308 const_op -= 1; | |
10309 op1 = GEN_INT (const_op); | |
10310 code = GTU; | |
10311 /* ... fall through ... */ | |
10312 } | |
10313 | |
10314 /* (unsigned) >= 0x80000000 is equivalent to < 0. */ | |
10315 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) | |
10316 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) | |
10317 { | |
10318 const_op = 0, op1 = const0_rtx; | |
10319 code = LT; | |
10320 break; | |
10321 } | |
10322 else | |
10323 break; | |
10324 | |
10325 case GTU: | |
10326 /* unsigned > 0 is equivalent to != 0 */ | |
10327 if (const_op == 0) | |
10328 code = NE; | |
10329 | |
10330 /* (unsigned) > 0x7fffffff is equivalent to < 0. */ | |
10331 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) | |
10332 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) | |
10333 { | |
10334 const_op = 0, op1 = const0_rtx; | |
10335 code = LT; | |
10336 } | |
10337 break; | |
10338 | |
10339 default: | |
10340 break; | |
10341 } | |
10342 | |
10343 /* Compute some predicates to simplify code below. */ | |
10344 | |
10345 equality_comparison_p = (code == EQ || code == NE); | |
10346 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); | |
10347 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU | |
10348 || code == GEU); | |
10349 | |
10350 /* If this is a sign bit comparison and we can do arithmetic in | |
10351 MODE, say that we will only be needing the sign bit of OP0. */ | |
10352 if (sign_bit_comparison_p | |
10353 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
10354 op0 = force_to_mode (op0, mode, | |
10355 ((HOST_WIDE_INT) 1 | |
10356 << (GET_MODE_BITSIZE (mode) - 1)), | |
10357 0); | |
10358 | |
10359 /* Now try cases based on the opcode of OP0. If none of the cases | |
10360 does a "continue", we exit this loop immediately after the | |
10361 switch. */ | |
10362 | |
10363 switch (GET_CODE (op0)) | |
10364 { | |
10365 case ZERO_EXTRACT: | |
10366 /* If we are extracting a single bit from a variable position in | |
10367 a constant that has only a single bit set and are comparing it | |
10368 with zero, we can convert this into an equality comparison | |
10369 between the position and the location of the single bit. */ | |
10370 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might | |
10371 have already reduced the shift count modulo the word size. */ | |
10372 if (!SHIFT_COUNT_TRUNCATED | |
10373 && GET_CODE (XEXP (op0, 0)) == CONST_INT | |
10374 && XEXP (op0, 1) == const1_rtx | |
10375 && equality_comparison_p && const_op == 0 | |
10376 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) | |
10377 { | |
10378 if (BITS_BIG_ENDIAN) | |
10379 { | |
10380 enum machine_mode new_mode | |
10381 = mode_for_extraction (EP_extzv, 1); | |
10382 if (new_mode == MAX_MACHINE_MODE) | |
10383 i = BITS_PER_WORD - 1 - i; | |
10384 else | |
10385 { | |
10386 mode = new_mode; | |
10387 i = (GET_MODE_BITSIZE (mode) - 1 - i); | |
10388 } | |
10389 } | |
10390 | |
10391 op0 = XEXP (op0, 2); | |
10392 op1 = GEN_INT (i); | |
10393 const_op = i; | |
10394 | |
10395 /* Result is nonzero iff shift count is equal to I. */ | |
10396 code = reverse_condition (code); | |
10397 continue; | |
10398 } | |
10399 | |
10400 /* ... fall through ... */ | |
10401 | |
10402 case SIGN_EXTRACT: | |
10403 tem = expand_compound_operation (op0); | |
10404 if (tem != op0) | |
10405 { | |
10406 op0 = tem; | |
10407 continue; | |
10408 } | |
10409 break; | |
10410 | |
10411 case NOT: | |
10412 /* If testing for equality, we can take the NOT of the constant. */ | |
10413 if (equality_comparison_p | |
10414 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) | |
10415 { | |
10416 op0 = XEXP (op0, 0); | |
10417 op1 = tem; | |
10418 continue; | |
10419 } | |
10420 | |
10421 /* If just looking at the sign bit, reverse the sense of the | |
10422 comparison. */ | |
10423 if (sign_bit_comparison_p) | |
10424 { | |
10425 op0 = XEXP (op0, 0); | |
10426 code = (code == GE ? LT : GE); | |
10427 continue; | |
10428 } | |
10429 break; | |
10430 | |
10431 case NEG: | |
10432 /* If testing for equality, we can take the NEG of the constant. */ | |
10433 if (equality_comparison_p | |
10434 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) | |
10435 { | |
10436 op0 = XEXP (op0, 0); | |
10437 op1 = tem; | |
10438 continue; | |
10439 } | |
10440 | |
10441 /* The remaining cases only apply to comparisons with zero. */ | |
10442 if (const_op != 0) | |
10443 break; | |
10444 | |
10445 /* When X is ABS or is known positive, | |
10446 (neg X) is < 0 if and only if X != 0. */ | |
10447 | |
10448 if (sign_bit_comparison_p | |
10449 && (GET_CODE (XEXP (op0, 0)) == ABS | |
10450 || (mode_width <= HOST_BITS_PER_WIDE_INT | |
10451 && (nonzero_bits (XEXP (op0, 0), mode) | |
10452 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0))) | |
10453 { | |
10454 op0 = XEXP (op0, 0); | |
10455 code = (code == LT ? NE : EQ); | |
10456 continue; | |
10457 } | |
10458 | |
10459 /* If we have NEG of something whose two high-order bits are the | |
10460 same, we know that "(-a) < 0" is equivalent to "a > 0". */ | |
10461 if (num_sign_bit_copies (op0, mode) >= 2) | |
10462 { | |
10463 op0 = XEXP (op0, 0); | |
10464 code = swap_condition (code); | |
10465 continue; | |
10466 } | |
10467 break; | |
10468 | |
10469 case ROTATE: | |
10470 /* If we are testing equality and our count is a constant, we | |
10471 can perform the inverse operation on our RHS. */ | |
10472 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10473 && (tem = simplify_binary_operation (ROTATERT, mode, | |
10474 op1, XEXP (op0, 1))) != 0) | |
10475 { | |
10476 op0 = XEXP (op0, 0); | |
10477 op1 = tem; | |
10478 continue; | |
10479 } | |
10480 | |
10481 /* If we are doing a < 0 or >= 0 comparison, it means we are testing | |
10482 a particular bit. Convert it to an AND of a constant of that | |
10483 bit. This will be converted into a ZERO_EXTRACT. */ | |
10484 if (const_op == 0 && sign_bit_comparison_p | |
10485 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10486 && mode_width <= HOST_BITS_PER_WIDE_INT) | |
10487 { | |
10488 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), | |
10489 ((HOST_WIDE_INT) 1 | |
10490 << (mode_width - 1 | |
10491 - INTVAL (XEXP (op0, 1))))); | |
10492 code = (code == LT ? NE : EQ); | |
10493 continue; | |
10494 } | |
10495 | |
10496 /* Fall through. */ | |
10497 | |
10498 case ABS: | |
10499 /* ABS is ignorable inside an equality comparison with zero. */ | |
10500 if (const_op == 0 && equality_comparison_p) | |
10501 { | |
10502 op0 = XEXP (op0, 0); | |
10503 continue; | |
10504 } | |
10505 break; | |
10506 | |
10507 case SIGN_EXTEND: | |
10508 /* Can simplify (compare (zero/sign_extend FOO) CONST) to | |
10509 (compare FOO CONST) if CONST fits in FOO's mode and we | |
10510 are either testing inequality or have an unsigned | |
10511 comparison with ZERO_EXTEND or a signed comparison with | |
10512 SIGN_EXTEND. But don't do it if we don't have a compare | |
10513 insn of the given mode, since we'd have to revert it | |
10514 later on, and then we wouldn't know whether to sign- or | |
10515 zero-extend. */ | |
10516 mode = GET_MODE (XEXP (op0, 0)); | |
10517 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
10518 && ! unsigned_comparison_p | |
10519 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
10520 && ((unsigned HOST_WIDE_INT) const_op | |
10521 < (((unsigned HOST_WIDE_INT) 1 | |
10522 << (GET_MODE_BITSIZE (mode) - 1)))) | |
10523 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing) | |
10524 { | |
10525 op0 = XEXP (op0, 0); | |
10526 continue; | |
10527 } | |
10528 break; | |
10529 | |
10530 case SUBREG: | |
10531 /* Check for the case where we are comparing A - C1 with C2, that is | |
10532 | |
10533 (subreg:MODE (plus (A) (-C1))) op (C2) | |
10534 | |
10535 with C1 a constant, and try to lift the SUBREG, i.e. to do the | |
10536 comparison in the wider mode. One of the following two conditions | |
10537 must be true in order for this to be valid: | |
10538 | |
10539 1. The mode extension results in the same bit pattern being added | |
10540 on both sides and the comparison is equality or unsigned. As | |
10541 C2 has been truncated to fit in MODE, the pattern can only be | |
10542 all 0s or all 1s. | |
10543 | |
10544 2. The mode extension results in the sign bit being copied on | |
10545 each side. | |
10546 | |
10547 The difficulty here is that we have predicates for A but not for | |
10548 (A - C1) so we need to check that C1 is within proper bounds so | |
10549 as to perturbate A as little as possible. */ | |
10550 | |
10551 if (mode_width <= HOST_BITS_PER_WIDE_INT | |
10552 && subreg_lowpart_p (op0) | |
10553 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width | |
10554 && GET_CODE (SUBREG_REG (op0)) == PLUS | |
10555 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT) | |
10556 { | |
10557 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); | |
10558 rtx a = XEXP (SUBREG_REG (op0), 0); | |
10559 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1)); | |
10560 | |
10561 if ((c1 > 0 | |
10562 && (unsigned HOST_WIDE_INT) c1 | |
10563 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1) | |
10564 && (equality_comparison_p || unsigned_comparison_p) | |
10565 /* (A - C1) zero-extends if it is positive and sign-extends | |
10566 if it is negative, C2 both zero- and sign-extends. */ | |
10567 && ((0 == (nonzero_bits (a, inner_mode) | |
10568 & ~GET_MODE_MASK (mode)) | |
10569 && const_op >= 0) | |
10570 /* (A - C1) sign-extends if it is positive and 1-extends | |
10571 if it is negative, C2 both sign- and 1-extends. */ | |
10572 || (num_sign_bit_copies (a, inner_mode) | |
10573 > (unsigned int) (GET_MODE_BITSIZE (inner_mode) | |
10574 - mode_width) | |
10575 && const_op < 0))) | |
10576 || ((unsigned HOST_WIDE_INT) c1 | |
10577 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2) | |
10578 /* (A - C1) always sign-extends, like C2. */ | |
10579 && num_sign_bit_copies (a, inner_mode) | |
10580 > (unsigned int) (GET_MODE_BITSIZE (inner_mode) | |
10581 - (mode_width - 1)))) | |
10582 { | |
10583 op0 = SUBREG_REG (op0); | |
10584 continue; | |
10585 } | |
10586 } | |
10587 | |
10588 /* If the inner mode is narrower and we are extracting the low part, | |
10589 we can treat the SUBREG as if it were a ZERO_EXTEND. */ | |
10590 if (subreg_lowpart_p (op0) | |
10591 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width) | |
10592 /* Fall through */ ; | |
10593 else | |
10594 break; | |
10595 | |
10596 /* ... fall through ... */ | |
10597 | |
10598 case ZERO_EXTEND: | |
10599 mode = GET_MODE (XEXP (op0, 0)); | |
10600 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
10601 && (unsigned_comparison_p || equality_comparison_p) | |
10602 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
10603 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode)) | |
10604 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing) | |
10605 { | |
10606 op0 = XEXP (op0, 0); | |
10607 continue; | |
10608 } | |
10609 break; | |
10610 | |
10611 case PLUS: | |
10612 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do | |
10613 this for equality comparisons due to pathological cases involving | |
10614 overflows. */ | |
10615 if (equality_comparison_p | |
10616 && 0 != (tem = simplify_binary_operation (MINUS, mode, | |
10617 op1, XEXP (op0, 1)))) | |
10618 { | |
10619 op0 = XEXP (op0, 0); | |
10620 op1 = tem; | |
10621 continue; | |
10622 } | |
10623 | |
10624 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ | |
10625 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx | |
10626 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) | |
10627 { | |
10628 op0 = XEXP (XEXP (op0, 0), 0); | |
10629 code = (code == LT ? EQ : NE); | |
10630 continue; | |
10631 } | |
10632 break; | |
10633 | |
10634 case MINUS: | |
10635 /* We used to optimize signed comparisons against zero, but that | |
10636 was incorrect. Unsigned comparisons against zero (GTU, LEU) | |
10637 arrive here as equality comparisons, or (GEU, LTU) are | |
10638 optimized away. No need to special-case them. */ | |
10639 | |
10640 /* (eq (minus A B) C) -> (eq A (plus B C)) or | |
10641 (eq B (minus A C)), whichever simplifies. We can only do | |
10642 this for equality comparisons due to pathological cases involving | |
10643 overflows. */ | |
10644 if (equality_comparison_p | |
10645 && 0 != (tem = simplify_binary_operation (PLUS, mode, | |
10646 XEXP (op0, 1), op1))) | |
10647 { | |
10648 op0 = XEXP (op0, 0); | |
10649 op1 = tem; | |
10650 continue; | |
10651 } | |
10652 | |
10653 if (equality_comparison_p | |
10654 && 0 != (tem = simplify_binary_operation (MINUS, mode, | |
10655 XEXP (op0, 0), op1))) | |
10656 { | |
10657 op0 = XEXP (op0, 1); | |
10658 op1 = tem; | |
10659 continue; | |
10660 } | |
10661 | |
10662 /* The sign bit of (minus (ashiftrt X C) X), where C is the number | |
10663 of bits in X minus 1, is one iff X > 0. */ | |
10664 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT | |
10665 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
10666 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1)) | |
10667 == mode_width - 1 | |
10668 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) | |
10669 { | |
10670 op0 = XEXP (op0, 1); | |
10671 code = (code == GE ? LE : GT); | |
10672 continue; | |
10673 } | |
10674 break; | |
10675 | |
10676 case XOR: | |
10677 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification | |
10678 if C is zero or B is a constant. */ | |
10679 if (equality_comparison_p | |
10680 && 0 != (tem = simplify_binary_operation (XOR, mode, | |
10681 XEXP (op0, 1), op1))) | |
10682 { | |
10683 op0 = XEXP (op0, 0); | |
10684 op1 = tem; | |
10685 continue; | |
10686 } | |
10687 break; | |
10688 | |
10689 case EQ: case NE: | |
10690 case UNEQ: case LTGT: | |
10691 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE: | |
10692 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE: | |
10693 case UNORDERED: case ORDERED: | |
10694 /* We can't do anything if OP0 is a condition code value, rather | |
10695 than an actual data value. */ | |
10696 if (const_op != 0 | |
10697 || CC0_P (XEXP (op0, 0)) | |
10698 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) | |
10699 break; | |
10700 | |
10701 /* Get the two operands being compared. */ | |
10702 if (GET_CODE (XEXP (op0, 0)) == COMPARE) | |
10703 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); | |
10704 else | |
10705 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); | |
10706 | |
10707 /* Check for the cases where we simply want the result of the | |
10708 earlier test or the opposite of that result. */ | |
10709 if (code == NE || code == EQ | |
10710 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT | |
10711 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
10712 && (STORE_FLAG_VALUE | |
10713 & (((HOST_WIDE_INT) 1 | |
10714 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) | |
10715 && (code == LT || code == GE))) | |
10716 { | |
10717 enum rtx_code new_code; | |
10718 if (code == LT || code == NE) | |
10719 new_code = GET_CODE (op0); | |
10720 else | |
10721 new_code = reversed_comparison_code (op0, NULL); | |
10722 | |
10723 if (new_code != UNKNOWN) | |
10724 { | |
10725 code = new_code; | |
10726 op0 = tem; | |
10727 op1 = tem1; | |
10728 continue; | |
10729 } | |
10730 } | |
10731 break; | |
10732 | |
10733 case IOR: | |
10734 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero | |
10735 iff X <= 0. */ | |
10736 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS | |
10737 && XEXP (XEXP (op0, 0), 1) == constm1_rtx | |
10738 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) | |
10739 { | |
10740 op0 = XEXP (op0, 1); | |
10741 code = (code == GE ? GT : LE); | |
10742 continue; | |
10743 } | |
10744 break; | |
10745 | |
10746 case AND: | |
10747 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This | |
10748 will be converted to a ZERO_EXTRACT later. */ | |
10749 if (const_op == 0 && equality_comparison_p | |
10750 && GET_CODE (XEXP (op0, 0)) == ASHIFT | |
10751 && XEXP (XEXP (op0, 0), 0) == const1_rtx) | |
10752 { | |
10753 op0 = simplify_and_const_int | |
10754 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode, | |
10755 XEXP (op0, 1), | |
10756 XEXP (XEXP (op0, 0), 1)), | |
10757 (HOST_WIDE_INT) 1); | |
10758 continue; | |
10759 } | |
10760 | |
10761 /* If we are comparing (and (lshiftrt X C1) C2) for equality with | |
10762 zero and X is a comparison and C1 and C2 describe only bits set | |
10763 in STORE_FLAG_VALUE, we can compare with X. */ | |
10764 if (const_op == 0 && equality_comparison_p | |
10765 && mode_width <= HOST_BITS_PER_WIDE_INT | |
10766 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10767 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT | |
10768 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
10769 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 | |
10770 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) | |
10771 { | |
10772 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) | |
10773 << INTVAL (XEXP (XEXP (op0, 0), 1))); | |
10774 if ((~STORE_FLAG_VALUE & mask) == 0 | |
10775 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0)) | |
10776 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 | |
10777 && COMPARISON_P (tem)))) | |
10778 { | |
10779 op0 = XEXP (XEXP (op0, 0), 0); | |
10780 continue; | |
10781 } | |
10782 } | |
10783 | |
10784 /* If we are doing an equality comparison of an AND of a bit equal | |
10785 to the sign bit, replace this with a LT or GE comparison of | |
10786 the underlying value. */ | |
10787 if (equality_comparison_p | |
10788 && const_op == 0 | |
10789 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10790 && mode_width <= HOST_BITS_PER_WIDE_INT | |
10791 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) | |
10792 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) | |
10793 { | |
10794 op0 = XEXP (op0, 0); | |
10795 code = (code == EQ ? GE : LT); | |
10796 continue; | |
10797 } | |
10798 | |
10799 /* If this AND operation is really a ZERO_EXTEND from a narrower | |
10800 mode, the constant fits within that mode, and this is either an | |
10801 equality or unsigned comparison, try to do this comparison in | |
10802 the narrower mode. | |
10803 | |
10804 Note that in: | |
10805 | |
10806 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0)) | |
10807 -> (ne:DI (reg:SI 4) (const_int 0)) | |
10808 | |
10809 unless TRULY_NOOP_TRUNCATION allows it or the register is | |
10810 known to hold a value of the required mode the | |
10811 transformation is invalid. */ | |
10812 if ((equality_comparison_p || unsigned_comparison_p) | |
10813 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10814 && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) | |
10815 & GET_MODE_MASK (mode)) | |
10816 + 1)) >= 0 | |
10817 && const_op >> i == 0 | |
10818 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode | |
10819 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode), | |
10820 GET_MODE_BITSIZE (GET_MODE (op0))) | |
10821 || (REG_P (XEXP (op0, 0)) | |
10822 && reg_truncated_to_mode (tmode, XEXP (op0, 0))))) | |
10823 { | |
10824 op0 = gen_lowpart (tmode, XEXP (op0, 0)); | |
10825 continue; | |
10826 } | |
10827 | |
10828 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 | |
10829 fits in both M1 and M2 and the SUBREG is either paradoxical | |
10830 or represents the low part, permute the SUBREG and the AND | |
10831 and try again. */ | |
10832 if (GET_CODE (XEXP (op0, 0)) == SUBREG) | |
10833 { | |
10834 unsigned HOST_WIDE_INT c1; | |
10835 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0))); | |
10836 /* Require an integral mode, to avoid creating something like | |
10837 (AND:SF ...). */ | |
10838 if (SCALAR_INT_MODE_P (tmode) | |
10839 /* It is unsafe to commute the AND into the SUBREG if the | |
10840 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is | |
10841 not defined. As originally written the upper bits | |
10842 have a defined value due to the AND operation. | |
10843 However, if we commute the AND inside the SUBREG then | |
10844 they no longer have defined values and the meaning of | |
10845 the code has been changed. */ | |
10846 && (0 | |
10847 #ifdef WORD_REGISTER_OPERATIONS | |
10848 || (mode_width > GET_MODE_BITSIZE (tmode) | |
10849 && mode_width <= BITS_PER_WORD) | |
10850 #endif | |
10851 || (mode_width <= GET_MODE_BITSIZE (tmode) | |
10852 && subreg_lowpart_p (XEXP (op0, 0)))) | |
10853 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10854 && mode_width <= HOST_BITS_PER_WIDE_INT | |
10855 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT | |
10856 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0 | |
10857 && (c1 & ~GET_MODE_MASK (tmode)) == 0 | |
10858 && c1 != mask | |
10859 && c1 != GET_MODE_MASK (tmode)) | |
10860 { | |
10861 op0 = simplify_gen_binary (AND, tmode, | |
10862 SUBREG_REG (XEXP (op0, 0)), | |
10863 gen_int_mode (c1, tmode)); | |
10864 op0 = gen_lowpart (mode, op0); | |
10865 continue; | |
10866 } | |
10867 } | |
10868 | |
10869 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */ | |
10870 if (const_op == 0 && equality_comparison_p | |
10871 && XEXP (op0, 1) == const1_rtx | |
10872 && GET_CODE (XEXP (op0, 0)) == NOT) | |
10873 { | |
10874 op0 = simplify_and_const_int | |
10875 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1); | |
10876 code = (code == NE ? EQ : NE); | |
10877 continue; | |
10878 } | |
10879 | |
10880 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to | |
10881 (eq (and (lshiftrt X) 1) 0). | |
10882 Also handle the case where (not X) is expressed using xor. */ | |
10883 if (const_op == 0 && equality_comparison_p | |
10884 && XEXP (op0, 1) == const1_rtx | |
10885 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT) | |
10886 { | |
10887 rtx shift_op = XEXP (XEXP (op0, 0), 0); | |
10888 rtx shift_count = XEXP (XEXP (op0, 0), 1); | |
10889 | |
10890 if (GET_CODE (shift_op) == NOT | |
10891 || (GET_CODE (shift_op) == XOR | |
10892 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT | |
10893 && GET_CODE (shift_count) == CONST_INT | |
10894 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
10895 && (INTVAL (XEXP (shift_op, 1)) | |
10896 == (HOST_WIDE_INT) 1 << INTVAL (shift_count)))) | |
10897 { | |
10898 op0 = simplify_and_const_int | |
10899 (NULL_RTX, mode, | |
10900 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count), | |
10901 (HOST_WIDE_INT) 1); | |
10902 code = (code == NE ? EQ : NE); | |
10903 continue; | |
10904 } | |
10905 } | |
10906 break; | |
10907 | |
10908 case ASHIFT: | |
10909 /* If we have (compare (ashift FOO N) (const_int C)) and | |
10910 the high order N bits of FOO (N+1 if an inequality comparison) | |
10911 are known to be zero, we can do this by comparing FOO with C | |
10912 shifted right N bits so long as the low-order N bits of C are | |
10913 zero. */ | |
10914 if (GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10915 && INTVAL (XEXP (op0, 1)) >= 0 | |
10916 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) | |
10917 < HOST_BITS_PER_WIDE_INT) | |
10918 && ((const_op | |
10919 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0) | |
10920 && mode_width <= HOST_BITS_PER_WIDE_INT | |
10921 && (nonzero_bits (XEXP (op0, 0), mode) | |
10922 & ~(mask >> (INTVAL (XEXP (op0, 1)) | |
10923 + ! equality_comparison_p))) == 0) | |
10924 { | |
10925 /* We must perform a logical shift, not an arithmetic one, | |
10926 as we want the top N bits of C to be zero. */ | |
10927 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode); | |
10928 | |
10929 temp >>= INTVAL (XEXP (op0, 1)); | |
10930 op1 = gen_int_mode (temp, mode); | |
10931 op0 = XEXP (op0, 0); | |
10932 continue; | |
10933 } | |
10934 | |
10935 /* If we are doing a sign bit comparison, it means we are testing | |
10936 a particular bit. Convert it to the appropriate AND. */ | |
10937 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10938 && mode_width <= HOST_BITS_PER_WIDE_INT) | |
10939 { | |
10940 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), | |
10941 ((HOST_WIDE_INT) 1 | |
10942 << (mode_width - 1 | |
10943 - INTVAL (XEXP (op0, 1))))); | |
10944 code = (code == LT ? NE : EQ); | |
10945 continue; | |
10946 } | |
10947 | |
10948 /* If this an equality comparison with zero and we are shifting | |
10949 the low bit to the sign bit, we can convert this to an AND of the | |
10950 low-order bit. */ | |
10951 if (const_op == 0 && equality_comparison_p | |
10952 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10953 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) | |
10954 == mode_width - 1) | |
10955 { | |
10956 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), | |
10957 (HOST_WIDE_INT) 1); | |
10958 continue; | |
10959 } | |
10960 break; | |
10961 | |
10962 case ASHIFTRT: | |
10963 /* If this is an equality comparison with zero, we can do this | |
10964 as a logical shift, which might be much simpler. */ | |
10965 if (equality_comparison_p && const_op == 0 | |
10966 && GET_CODE (XEXP (op0, 1)) == CONST_INT) | |
10967 { | |
10968 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, | |
10969 XEXP (op0, 0), | |
10970 INTVAL (XEXP (op0, 1))); | |
10971 continue; | |
10972 } | |
10973 | |
10974 /* If OP0 is a sign extension and CODE is not an unsigned comparison, | |
10975 do the comparison in a narrower mode. */ | |
10976 if (! unsigned_comparison_p | |
10977 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10978 && GET_CODE (XEXP (op0, 0)) == ASHIFT | |
10979 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) | |
10980 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), | |
10981 MODE_INT, 1)) != BLKmode | |
10982 && (((unsigned HOST_WIDE_INT) const_op | |
10983 + (GET_MODE_MASK (tmode) >> 1) + 1) | |
10984 <= GET_MODE_MASK (tmode))) | |
10985 { | |
10986 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0)); | |
10987 continue; | |
10988 } | |
10989 | |
10990 /* Likewise if OP0 is a PLUS of a sign extension with a | |
10991 constant, which is usually represented with the PLUS | |
10992 between the shifts. */ | |
10993 if (! unsigned_comparison_p | |
10994 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10995 && GET_CODE (XEXP (op0, 0)) == PLUS | |
10996 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
10997 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT | |
10998 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1) | |
10999 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), | |
11000 MODE_INT, 1)) != BLKmode | |
11001 && (((unsigned HOST_WIDE_INT) const_op | |
11002 + (GET_MODE_MASK (tmode) >> 1) + 1) | |
11003 <= GET_MODE_MASK (tmode))) | |
11004 { | |
11005 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0); | |
11006 rtx add_const = XEXP (XEXP (op0, 0), 1); | |
11007 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0), | |
11008 add_const, XEXP (op0, 1)); | |
11009 | |
11010 op0 = simplify_gen_binary (PLUS, tmode, | |
11011 gen_lowpart (tmode, inner), | |
11012 new_const); | |
11013 continue; | |
11014 } | |
11015 | |
11016 /* ... fall through ... */ | |
11017 case LSHIFTRT: | |
11018 /* If we have (compare (xshiftrt FOO N) (const_int C)) and | |
11019 the low order N bits of FOO are known to be zero, we can do this | |
11020 by comparing FOO with C shifted left N bits so long as no | |
11021 overflow occurs. */ | |
11022 if (GET_CODE (XEXP (op0, 1)) == CONST_INT | |
11023 && INTVAL (XEXP (op0, 1)) >= 0 | |
11024 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT | |
11025 && mode_width <= HOST_BITS_PER_WIDE_INT | |
11026 && (nonzero_bits (XEXP (op0, 0), mode) | |
11027 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 | |
11028 && (((unsigned HOST_WIDE_INT) const_op | |
11029 + (GET_CODE (op0) != LSHIFTRT | |
11030 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1) | |
11031 + 1) | |
11032 : 0)) | |
11033 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)))) | |
11034 { | |
11035 /* If the shift was logical, then we must make the condition | |
11036 unsigned. */ | |
11037 if (GET_CODE (op0) == LSHIFTRT) | |
11038 code = unsigned_condition (code); | |
11039 | |
11040 const_op <<= INTVAL (XEXP (op0, 1)); | |
11041 op1 = GEN_INT (const_op); | |
11042 op0 = XEXP (op0, 0); | |
11043 continue; | |
11044 } | |
11045 | |
11046 /* If we are using this shift to extract just the sign bit, we | |
11047 can replace this with an LT or GE comparison. */ | |
11048 if (const_op == 0 | |
11049 && (equality_comparison_p || sign_bit_comparison_p) | |
11050 && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
11051 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) | |
11052 == mode_width - 1) | |
11053 { | |
11054 op0 = XEXP (op0, 0); | |
11055 code = (code == NE || code == GT ? LT : GE); | |
11056 continue; | |
11057 } | |
11058 break; | |
11059 | |
11060 default: | |
11061 break; | |
11062 } | |
11063 | |
11064 break; | |
11065 } | |
11066 | |
11067 /* Now make any compound operations involved in this comparison. Then, | |
11068 check for an outmost SUBREG on OP0 that is not doing anything or is | |
11069 paradoxical. The latter transformation must only be performed when | |
11070 it is known that the "extra" bits will be the same in op0 and op1 or | |
11071 that they don't matter. There are three cases to consider: | |
11072 | |
11073 1. SUBREG_REG (op0) is a register. In this case the bits are don't | |
11074 care bits and we can assume they have any convenient value. So | |
11075 making the transformation is safe. | |
11076 | |
11077 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined. | |
11078 In this case the upper bits of op0 are undefined. We should not make | |
11079 the simplification in that case as we do not know the contents of | |
11080 those bits. | |
11081 | |
11082 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not | |
11083 UNKNOWN. In that case we know those bits are zeros or ones. We must | |
11084 also be sure that they are the same as the upper bits of op1. | |
11085 | |
11086 We can never remove a SUBREG for a non-equality comparison because | |
11087 the sign bit is in a different place in the underlying object. */ | |
11088 | |
11089 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); | |
11090 op1 = make_compound_operation (op1, SET); | |
11091 | |
11092 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) | |
11093 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
11094 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT | |
11095 && (code == NE || code == EQ)) | |
11096 { | |
11097 if (GET_MODE_SIZE (GET_MODE (op0)) | |
11098 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))) | |
11099 { | |
11100 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't | |
11101 implemented. */ | |
11102 if (REG_P (SUBREG_REG (op0))) | |
11103 { | |
11104 op0 = SUBREG_REG (op0); | |
11105 op1 = gen_lowpart (GET_MODE (op0), op1); | |
11106 } | |
11107 } | |
11108 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) | |
11109 <= HOST_BITS_PER_WIDE_INT) | |
11110 && (nonzero_bits (SUBREG_REG (op0), | |
11111 GET_MODE (SUBREG_REG (op0))) | |
11112 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) | |
11113 { | |
11114 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1); | |
11115 | |
11116 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) | |
11117 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) | |
11118 op0 = SUBREG_REG (op0), op1 = tem; | |
11119 } | |
11120 } | |
11121 | |
11122 /* We now do the opposite procedure: Some machines don't have compare | |
11123 insns in all modes. If OP0's mode is an integer mode smaller than a | |
11124 word and we can't do a compare in that mode, see if there is a larger | |
11125 mode for which we can do the compare. There are a number of cases in | |
11126 which we can use the wider mode. */ | |
11127 | |
11128 mode = GET_MODE (op0); | |
11129 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
11130 && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
11131 && ! have_insn_for (COMPARE, mode)) | |
11132 for (tmode = GET_MODE_WIDER_MODE (mode); | |
11133 (tmode != VOIDmode | |
11134 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT); | |
11135 tmode = GET_MODE_WIDER_MODE (tmode)) | |
11136 if (have_insn_for (COMPARE, tmode)) | |
11137 { | |
11138 int zero_extended; | |
11139 | |
11140 /* If the only nonzero bits in OP0 and OP1 are those in the | |
11141 narrower mode and this is an equality or unsigned comparison, | |
11142 we can use the wider mode. Similarly for sign-extended | |
11143 values, in which case it is true for all comparisons. */ | |
11144 zero_extended = ((code == EQ || code == NE | |
11145 || code == GEU || code == GTU | |
11146 || code == LEU || code == LTU) | |
11147 && (nonzero_bits (op0, tmode) | |
11148 & ~GET_MODE_MASK (mode)) == 0 | |
11149 && ((GET_CODE (op1) == CONST_INT | |
11150 || (nonzero_bits (op1, tmode) | |
11151 & ~GET_MODE_MASK (mode)) == 0))); | |
11152 | |
11153 if (zero_extended | |
11154 || ((num_sign_bit_copies (op0, tmode) | |
11155 > (unsigned int) (GET_MODE_BITSIZE (tmode) | |
11156 - GET_MODE_BITSIZE (mode))) | |
11157 && (num_sign_bit_copies (op1, tmode) | |
11158 > (unsigned int) (GET_MODE_BITSIZE (tmode) | |
11159 - GET_MODE_BITSIZE (mode))))) | |
11160 { | |
11161 /* If OP0 is an AND and we don't have an AND in MODE either, | |
11162 make a new AND in the proper mode. */ | |
11163 if (GET_CODE (op0) == AND | |
11164 && !have_insn_for (AND, mode)) | |
11165 op0 = simplify_gen_binary (AND, tmode, | |
11166 gen_lowpart (tmode, | |
11167 XEXP (op0, 0)), | |
11168 gen_lowpart (tmode, | |
11169 XEXP (op0, 1))); | |
11170 | |
11171 op0 = gen_lowpart (tmode, op0); | |
11172 if (zero_extended && GET_CODE (op1) == CONST_INT) | |
11173 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode)); | |
11174 op1 = gen_lowpart (tmode, op1); | |
11175 break; | |
11176 } | |
11177 | |
11178 /* If this is a test for negative, we can make an explicit | |
11179 test of the sign bit. */ | |
11180 | |
11181 if (op1 == const0_rtx && (code == LT || code == GE) | |
11182 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
11183 { | |
11184 op0 = simplify_gen_binary (AND, tmode, | |
11185 gen_lowpart (tmode, op0), | |
11186 GEN_INT ((HOST_WIDE_INT) 1 | |
11187 << (GET_MODE_BITSIZE (mode) | |
11188 - 1))); | |
11189 code = (code == LT) ? NE : EQ; | |
11190 break; | |
11191 } | |
11192 } | |
11193 | |
11194 #ifdef CANONICALIZE_COMPARISON | |
11195 /* If this machine only supports a subset of valid comparisons, see if we | |
11196 can convert an unsupported one into a supported one. */ | |
11197 CANONICALIZE_COMPARISON (code, op0, op1); | |
11198 #endif | |
11199 | |
11200 *pop0 = op0; | |
11201 *pop1 = op1; | |
11202 | |
11203 return code; | |
11204 } | |
11205 | |
11206 /* Utility function for record_value_for_reg. Count number of | |
11207 rtxs in X. */ | |
11208 static int | |
11209 count_rtxs (rtx x) | |
11210 { | |
11211 enum rtx_code code = GET_CODE (x); | |
11212 const char *fmt; | |
11213 int i, j, ret = 1; | |
11214 | |
11215 if (GET_RTX_CLASS (code) == '2' | |
11216 || GET_RTX_CLASS (code) == 'c') | |
11217 { | |
11218 rtx x0 = XEXP (x, 0); | |
11219 rtx x1 = XEXP (x, 1); | |
11220 | |
11221 if (x0 == x1) | |
11222 return 1 + 2 * count_rtxs (x0); | |
11223 | |
11224 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2' | |
11225 || GET_RTX_CLASS (GET_CODE (x1)) == 'c') | |
11226 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) | |
11227 return 2 + 2 * count_rtxs (x0) | |
11228 + count_rtxs (x == XEXP (x1, 0) | |
11229 ? XEXP (x1, 1) : XEXP (x1, 0)); | |
11230 | |
11231 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2' | |
11232 || GET_RTX_CLASS (GET_CODE (x0)) == 'c') | |
11233 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) | |
11234 return 2 + 2 * count_rtxs (x1) | |
11235 + count_rtxs (x == XEXP (x0, 0) | |
11236 ? XEXP (x0, 1) : XEXP (x0, 0)); | |
11237 } | |
11238 | |
11239 fmt = GET_RTX_FORMAT (code); | |
11240 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
11241 if (fmt[i] == 'e') | |
11242 ret += count_rtxs (XEXP (x, i)); | |
11243 else if (fmt[i] == 'E') | |
11244 for (j = 0; j < XVECLEN (x, i); j++) | |
11245 ret += count_rtxs (XVECEXP (x, i, j)); | |
11246 | |
11247 return ret; | |
11248 } | |
11249 | |
11250 /* Utility function for following routine. Called when X is part of a value | |
11251 being stored into last_set_value. Sets last_set_table_tick | |
11252 for each register mentioned. Similar to mention_regs in cse.c */ | |
11253 | |
11254 static void | |
11255 update_table_tick (rtx x) | |
11256 { | |
11257 enum rtx_code code = GET_CODE (x); | |
11258 const char *fmt = GET_RTX_FORMAT (code); | |
11259 int i, j; | |
11260 | |
11261 if (code == REG) | |
11262 { | |
11263 unsigned int regno = REGNO (x); | |
11264 unsigned int endregno = END_REGNO (x); | |
11265 unsigned int r; | |
11266 | |
11267 for (r = regno; r < endregno; r++) | |
11268 { | |
11269 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r); | |
11270 rsp->last_set_table_tick = label_tick; | |
11271 } | |
11272 | |
11273 return; | |
11274 } | |
11275 | |
11276 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
11277 if (fmt[i] == 'e') | |
11278 { | |
11279 /* Check for identical subexpressions. If x contains | |
11280 identical subexpression we only have to traverse one of | |
11281 them. */ | |
11282 if (i == 0 && ARITHMETIC_P (x)) | |
11283 { | |
11284 /* Note that at this point x1 has already been | |
11285 processed. */ | |
11286 rtx x0 = XEXP (x, 0); | |
11287 rtx x1 = XEXP (x, 1); | |
11288 | |
11289 /* If x0 and x1 are identical then there is no need to | |
11290 process x0. */ | |
11291 if (x0 == x1) | |
11292 break; | |
11293 | |
11294 /* If x0 is identical to a subexpression of x1 then while | |
11295 processing x1, x0 has already been processed. Thus we | |
11296 are done with x. */ | |
11297 if (ARITHMETIC_P (x1) | |
11298 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) | |
11299 break; | |
11300 | |
11301 /* If x1 is identical to a subexpression of x0 then we | |
11302 still have to process the rest of x0. */ | |
11303 if (ARITHMETIC_P (x0) | |
11304 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) | |
11305 { | |
11306 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0)); | |
11307 break; | |
11308 } | |
11309 } | |
11310 | |
11311 update_table_tick (XEXP (x, i)); | |
11312 } | |
11313 else if (fmt[i] == 'E') | |
11314 for (j = 0; j < XVECLEN (x, i); j++) | |
11315 update_table_tick (XVECEXP (x, i, j)); | |
11316 } | |
11317 | |
11318 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we | |
11319 are saying that the register is clobbered and we no longer know its | |
11320 value. If INSN is zero, don't update reg_stat[].last_set; this is | |
11321 only permitted with VALUE also zero and is used to invalidate the | |
11322 register. */ | |
11323 | |
11324 static void | |
11325 record_value_for_reg (rtx reg, rtx insn, rtx value) | |
11326 { | |
11327 unsigned int regno = REGNO (reg); | |
11328 unsigned int endregno = END_REGNO (reg); | |
11329 unsigned int i; | |
11330 reg_stat_type *rsp; | |
11331 | |
11332 /* If VALUE contains REG and we have a previous value for REG, substitute | |
11333 the previous value. */ | |
11334 if (value && insn && reg_overlap_mentioned_p (reg, value)) | |
11335 { | |
11336 rtx tem; | |
11337 | |
11338 /* Set things up so get_last_value is allowed to see anything set up to | |
11339 our insn. */ | |
11340 subst_low_luid = DF_INSN_LUID (insn); | |
11341 tem = get_last_value (reg); | |
11342 | |
11343 /* If TEM is simply a binary operation with two CLOBBERs as operands, | |
11344 it isn't going to be useful and will take a lot of time to process, | |
11345 so just use the CLOBBER. */ | |
11346 | |
11347 if (tem) | |
11348 { | |
11349 if (ARITHMETIC_P (tem) | |
11350 && GET_CODE (XEXP (tem, 0)) == CLOBBER | |
11351 && GET_CODE (XEXP (tem, 1)) == CLOBBER) | |
11352 tem = XEXP (tem, 0); | |
11353 else if (count_occurrences (value, reg, 1) >= 2) | |
11354 { | |
11355 /* If there are two or more occurrences of REG in VALUE, | |
11356 prevent the value from growing too much. */ | |
11357 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL) | |
11358 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx); | |
11359 } | |
11360 | |
11361 value = replace_rtx (copy_rtx (value), reg, tem); | |
11362 } | |
11363 } | |
11364 | |
11365 /* For each register modified, show we don't know its value, that | |
11366 we don't know about its bitwise content, that its value has been | |
11367 updated, and that we don't know the location of the death of the | |
11368 register. */ | |
11369 for (i = regno; i < endregno; i++) | |
11370 { | |
11371 rsp = VEC_index (reg_stat_type, reg_stat, i); | |
11372 | |
11373 if (insn) | |
11374 rsp->last_set = insn; | |
11375 | |
11376 rsp->last_set_value = 0; | |
11377 rsp->last_set_mode = 0; | |
11378 rsp->last_set_nonzero_bits = 0; | |
11379 rsp->last_set_sign_bit_copies = 0; | |
11380 rsp->last_death = 0; | |
11381 rsp->truncated_to_mode = 0; | |
11382 } | |
11383 | |
11384 /* Mark registers that are being referenced in this value. */ | |
11385 if (value) | |
11386 update_table_tick (value); | |
11387 | |
11388 /* Now update the status of each register being set. | |
11389 If someone is using this register in this block, set this register | |
11390 to invalid since we will get confused between the two lives in this | |
11391 basic block. This makes using this register always invalid. In cse, we | |
11392 scan the table to invalidate all entries using this register, but this | |
11393 is too much work for us. */ | |
11394 | |
11395 for (i = regno; i < endregno; i++) | |
11396 { | |
11397 rsp = VEC_index (reg_stat_type, reg_stat, i); | |
11398 rsp->last_set_label = label_tick; | |
11399 if (!insn | |
11400 || (value && rsp->last_set_table_tick >= label_tick_ebb_start)) | |
11401 rsp->last_set_invalid = 1; | |
11402 else | |
11403 rsp->last_set_invalid = 0; | |
11404 } | |
11405 | |
11406 /* The value being assigned might refer to X (like in "x++;"). In that | |
11407 case, we must replace it with (clobber (const_int 0)) to prevent | |
11408 infinite loops. */ | |
11409 rsp = VEC_index (reg_stat_type, reg_stat, regno); | |
11410 if (value && ! get_last_value_validate (&value, insn, | |
11411 rsp->last_set_label, 0)) | |
11412 { | |
11413 value = copy_rtx (value); | |
11414 if (! get_last_value_validate (&value, insn, | |
11415 rsp->last_set_label, 1)) | |
11416 value = 0; | |
11417 } | |
11418 | |
11419 /* For the main register being modified, update the value, the mode, the | |
11420 nonzero bits, and the number of sign bit copies. */ | |
11421 | |
11422 rsp->last_set_value = value; | |
11423 | |
11424 if (value) | |
11425 { | |
11426 enum machine_mode mode = GET_MODE (reg); | |
11427 subst_low_luid = DF_INSN_LUID (insn); | |
11428 rsp->last_set_mode = mode; | |
11429 if (GET_MODE_CLASS (mode) == MODE_INT | |
11430 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
11431 mode = nonzero_bits_mode; | |
11432 rsp->last_set_nonzero_bits = nonzero_bits (value, mode); | |
11433 rsp->last_set_sign_bit_copies | |
11434 = num_sign_bit_copies (value, GET_MODE (reg)); | |
11435 } | |
11436 } | |
11437 | |
11438 /* Called via note_stores from record_dead_and_set_regs to handle one | |
11439 SET or CLOBBER in an insn. DATA is the instruction in which the | |
11440 set is occurring. */ | |
11441 | |
11442 static void | |
11443 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data) | |
11444 { | |
11445 rtx record_dead_insn = (rtx) data; | |
11446 | |
11447 if (GET_CODE (dest) == SUBREG) | |
11448 dest = SUBREG_REG (dest); | |
11449 | |
11450 if (!record_dead_insn) | |
11451 { | |
11452 if (REG_P (dest)) | |
11453 record_value_for_reg (dest, NULL_RTX, NULL_RTX); | |
11454 return; | |
11455 } | |
11456 | |
11457 if (REG_P (dest)) | |
11458 { | |
11459 /* If we are setting the whole register, we know its value. Otherwise | |
11460 show that we don't know the value. We can handle SUBREG in | |
11461 some cases. */ | |
11462 if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) | |
11463 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); | |
11464 else if (GET_CODE (setter) == SET | |
11465 && GET_CODE (SET_DEST (setter)) == SUBREG | |
11466 && SUBREG_REG (SET_DEST (setter)) == dest | |
11467 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD | |
11468 && subreg_lowpart_p (SET_DEST (setter))) | |
11469 record_value_for_reg (dest, record_dead_insn, | |
11470 gen_lowpart (GET_MODE (dest), | |
11471 SET_SRC (setter))); | |
11472 else | |
11473 record_value_for_reg (dest, record_dead_insn, NULL_RTX); | |
11474 } | |
11475 else if (MEM_P (dest) | |
11476 /* Ignore pushes, they clobber nothing. */ | |
11477 && ! push_operand (dest, GET_MODE (dest))) | |
11478 mem_last_set = DF_INSN_LUID (record_dead_insn); | |
11479 } | |
11480 | |
11481 /* Update the records of when each REG was most recently set or killed | |
11482 for the things done by INSN. This is the last thing done in processing | |
11483 INSN in the combiner loop. | |
11484 | |
11485 We update reg_stat[], in particular fields last_set, last_set_value, | |
11486 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies, | |
11487 last_death, and also the similar information mem_last_set (which insn | |
11488 most recently modified memory) and last_call_luid (which insn was the | |
11489 most recent subroutine call). */ | |
11490 | |
11491 static void | |
11492 record_dead_and_set_regs (rtx insn) | |
11493 { | |
11494 rtx link; | |
11495 unsigned int i; | |
11496 | |
11497 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
11498 { | |
11499 if (REG_NOTE_KIND (link) == REG_DEAD | |
11500 && REG_P (XEXP (link, 0))) | |
11501 { | |
11502 unsigned int regno = REGNO (XEXP (link, 0)); | |
11503 unsigned int endregno = END_REGNO (XEXP (link, 0)); | |
11504 | |
11505 for (i = regno; i < endregno; i++) | |
11506 { | |
11507 reg_stat_type *rsp; | |
11508 | |
11509 rsp = VEC_index (reg_stat_type, reg_stat, i); | |
11510 rsp->last_death = insn; | |
11511 } | |
11512 } | |
11513 else if (REG_NOTE_KIND (link) == REG_INC) | |
11514 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); | |
11515 } | |
11516 | |
11517 if (CALL_P (insn)) | |
11518 { | |
11519 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
11520 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i)) | |
11521 { | |
11522 reg_stat_type *rsp; | |
11523 | |
11524 rsp = VEC_index (reg_stat_type, reg_stat, i); | |
11525 rsp->last_set_invalid = 1; | |
11526 rsp->last_set = insn; | |
11527 rsp->last_set_value = 0; | |
11528 rsp->last_set_mode = 0; | |
11529 rsp->last_set_nonzero_bits = 0; | |
11530 rsp->last_set_sign_bit_copies = 0; | |
11531 rsp->last_death = 0; | |
11532 rsp->truncated_to_mode = 0; | |
11533 } | |
11534 | |
11535 last_call_luid = mem_last_set = DF_INSN_LUID (insn); | |
11536 | |
11537 /* We can't combine into a call pattern. Remember, though, that | |
11538 the return value register is set at this LUID. We could | |
11539 still replace a register with the return value from the | |
11540 wrong subroutine call! */ | |
11541 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX); | |
11542 } | |
11543 else | |
11544 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn); | |
11545 } | |
11546 | |
11547 /* If a SUBREG has the promoted bit set, it is in fact a property of the | |
11548 register present in the SUBREG, so for each such SUBREG go back and | |
11549 adjust nonzero and sign bit information of the registers that are | |
11550 known to have some zero/sign bits set. | |
11551 | |
11552 This is needed because when combine blows the SUBREGs away, the | |
11553 information on zero/sign bits is lost and further combines can be | |
11554 missed because of that. */ | |
11555 | |
11556 static void | |
11557 record_promoted_value (rtx insn, rtx subreg) | |
11558 { | |
11559 rtx links, set; | |
11560 unsigned int regno = REGNO (SUBREG_REG (subreg)); | |
11561 enum machine_mode mode = GET_MODE (subreg); | |
11562 | |
11563 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
11564 return; | |
11565 | |
11566 for (links = LOG_LINKS (insn); links;) | |
11567 { | |
11568 reg_stat_type *rsp; | |
11569 | |
11570 insn = XEXP (links, 0); | |
11571 set = single_set (insn); | |
11572 | |
11573 if (! set || !REG_P (SET_DEST (set)) | |
11574 || REGNO (SET_DEST (set)) != regno | |
11575 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg))) | |
11576 { | |
11577 links = XEXP (links, 1); | |
11578 continue; | |
11579 } | |
11580 | |
11581 rsp = VEC_index (reg_stat_type, reg_stat, regno); | |
11582 if (rsp->last_set == insn) | |
11583 { | |
11584 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0) | |
11585 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode); | |
11586 } | |
11587 | |
11588 if (REG_P (SET_SRC (set))) | |
11589 { | |
11590 regno = REGNO (SET_SRC (set)); | |
11591 links = LOG_LINKS (insn); | |
11592 } | |
11593 else | |
11594 break; | |
11595 } | |
11596 } | |
11597 | |
11598 /* Check if X, a register, is known to contain a value already | |
11599 truncated to MODE. In this case we can use a subreg to refer to | |
11600 the truncated value even though in the generic case we would need | |
11601 an explicit truncation. */ | |
11602 | |
11603 static bool | |
11604 reg_truncated_to_mode (enum machine_mode mode, const_rtx x) | |
11605 { | |
11606 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x)); | |
11607 enum machine_mode truncated = rsp->truncated_to_mode; | |
11608 | |
11609 if (truncated == 0 | |
11610 || rsp->truncation_label < label_tick_ebb_start) | |
11611 return false; | |
11612 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode)) | |
11613 return true; | |
11614 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
11615 GET_MODE_BITSIZE (truncated))) | |
11616 return true; | |
11617 return false; | |
11618 } | |
11619 | |
11620 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode | |
11621 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we | |
11622 might be able to turn a truncate into a subreg using this information. | |
11623 Return -1 if traversing *P is complete or 0 otherwise. */ | |
11624 | |
11625 static int | |
11626 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED) | |
11627 { | |
11628 rtx x = *p; | |
11629 enum machine_mode truncated_mode; | |
11630 reg_stat_type *rsp; | |
11631 | |
11632 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))) | |
11633 { | |
11634 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x)); | |
11635 truncated_mode = GET_MODE (x); | |
11636 | |
11637 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode)) | |
11638 return -1; | |
11639 | |
11640 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode), | |
11641 GET_MODE_BITSIZE (original_mode))) | |
11642 return -1; | |
11643 | |
11644 x = SUBREG_REG (x); | |
11645 } | |
11646 /* ??? For hard-regs we now record everything. We might be able to | |
11647 optimize this using last_set_mode. */ | |
11648 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
11649 truncated_mode = GET_MODE (x); | |
11650 else | |
11651 return 0; | |
11652 | |
11653 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x)); | |
11654 if (rsp->truncated_to_mode == 0 | |
11655 || rsp->truncation_label < label_tick_ebb_start | |
11656 || (GET_MODE_SIZE (truncated_mode) | |
11657 < GET_MODE_SIZE (rsp->truncated_to_mode))) | |
11658 { | |
11659 rsp->truncated_to_mode = truncated_mode; | |
11660 rsp->truncation_label = label_tick; | |
11661 } | |
11662 | |
11663 return -1; | |
11664 } | |
11665 | |
11666 /* Callback for note_uses. Find hardregs and subregs of pseudos and | |
11667 the modes they are used in. This can help truning TRUNCATEs into | |
11668 SUBREGs. */ | |
11669 | |
11670 static void | |
11671 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED) | |
11672 { | |
11673 for_each_rtx (x, record_truncated_value, NULL); | |
11674 } | |
11675 | |
11676 /* Scan X for promoted SUBREGs. For each one found, | |
11677 note what it implies to the registers used in it. */ | |
11678 | |
11679 static void | |
11680 check_promoted_subreg (rtx insn, rtx x) | |
11681 { | |
11682 if (GET_CODE (x) == SUBREG | |
11683 && SUBREG_PROMOTED_VAR_P (x) | |
11684 && REG_P (SUBREG_REG (x))) | |
11685 record_promoted_value (insn, x); | |
11686 else | |
11687 { | |
11688 const char *format = GET_RTX_FORMAT (GET_CODE (x)); | |
11689 int i, j; | |
11690 | |
11691 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) | |
11692 switch (format[i]) | |
11693 { | |
11694 case 'e': | |
11695 check_promoted_subreg (insn, XEXP (x, i)); | |
11696 break; | |
11697 case 'V': | |
11698 case 'E': | |
11699 if (XVEC (x, i) != 0) | |
11700 for (j = 0; j < XVECLEN (x, i); j++) | |
11701 check_promoted_subreg (insn, XVECEXP (x, i, j)); | |
11702 break; | |
11703 } | |
11704 } | |
11705 } | |
11706 | |
11707 /* Utility routine for the following function. Verify that all the registers | |
11708 mentioned in *LOC are valid when *LOC was part of a value set when | |
11709 label_tick == TICK. Return 0 if some are not. | |
11710 | |
11711 If REPLACE is nonzero, replace the invalid reference with | |
11712 (clobber (const_int 0)) and return 1. This replacement is useful because | |
11713 we often can get useful information about the form of a value (e.g., if | |
11714 it was produced by a shift that always produces -1 or 0) even though | |
11715 we don't know exactly what registers it was produced from. */ | |
11716 | |
11717 static int | |
11718 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace) | |
11719 { | |
11720 rtx x = *loc; | |
11721 const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
11722 int len = GET_RTX_LENGTH (GET_CODE (x)); | |
11723 int i, j; | |
11724 | |
11725 if (REG_P (x)) | |
11726 { | |
11727 unsigned int regno = REGNO (x); | |
11728 unsigned int endregno = END_REGNO (x); | |
11729 unsigned int j; | |
11730 | |
11731 for (j = regno; j < endregno; j++) | |
11732 { | |
11733 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j); | |
11734 if (rsp->last_set_invalid | |
11735 /* If this is a pseudo-register that was only set once and not | |
11736 live at the beginning of the function, it is always valid. */ | |
11737 || (! (regno >= FIRST_PSEUDO_REGISTER | |
11738 && REG_N_SETS (regno) == 1 | |
11739 && (!REGNO_REG_SET_P | |
11740 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))) | |
11741 && rsp->last_set_label > tick)) | |
11742 { | |
11743 if (replace) | |
11744 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); | |
11745 return replace; | |
11746 } | |
11747 } | |
11748 | |
11749 return 1; | |
11750 } | |
11751 /* If this is a memory reference, make sure that there were | |
11752 no stores after it that might have clobbered the value. We don't | |
11753 have alias info, so we assume any store invalidates it. */ | |
11754 else if (MEM_P (x) && !MEM_READONLY_P (x) | |
11755 && DF_INSN_LUID (insn) <= mem_last_set) | |
11756 { | |
11757 if (replace) | |
11758 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); | |
11759 return replace; | |
11760 } | |
11761 | |
11762 for (i = 0; i < len; i++) | |
11763 { | |
11764 if (fmt[i] == 'e') | |
11765 { | |
11766 /* Check for identical subexpressions. If x contains | |
11767 identical subexpression we only have to traverse one of | |
11768 them. */ | |
11769 if (i == 1 && ARITHMETIC_P (x)) | |
11770 { | |
11771 /* Note that at this point x0 has already been checked | |
11772 and found valid. */ | |
11773 rtx x0 = XEXP (x, 0); | |
11774 rtx x1 = XEXP (x, 1); | |
11775 | |
11776 /* If x0 and x1 are identical then x is also valid. */ | |
11777 if (x0 == x1) | |
11778 return 1; | |
11779 | |
11780 /* If x1 is identical to a subexpression of x0 then | |
11781 while checking x0, x1 has already been checked. Thus | |
11782 it is valid and so as x. */ | |
11783 if (ARITHMETIC_P (x0) | |
11784 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) | |
11785 return 1; | |
11786 | |
11787 /* If x0 is identical to a subexpression of x1 then x is | |
11788 valid iff the rest of x1 is valid. */ | |
11789 if (ARITHMETIC_P (x1) | |
11790 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) | |
11791 return | |
11792 get_last_value_validate (&XEXP (x1, | |
11793 x0 == XEXP (x1, 0) ? 1 : 0), | |
11794 insn, tick, replace); | |
11795 } | |
11796 | |
11797 if (get_last_value_validate (&XEXP (x, i), insn, tick, | |
11798 replace) == 0) | |
11799 return 0; | |
11800 } | |
11801 else if (fmt[i] == 'E') | |
11802 for (j = 0; j < XVECLEN (x, i); j++) | |
11803 if (get_last_value_validate (&XVECEXP (x, i, j), | |
11804 insn, tick, replace) == 0) | |
11805 return 0; | |
11806 } | |
11807 | |
11808 /* If we haven't found a reason for it to be invalid, it is valid. */ | |
11809 return 1; | |
11810 } | |
11811 | |
11812 /* Get the last value assigned to X, if known. Some registers | |
11813 in the value may be replaced with (clobber (const_int 0)) if their value | |
11814 is known longer known reliably. */ | |
11815 | |
11816 static rtx | |
11817 get_last_value (const_rtx x) | |
11818 { | |
11819 unsigned int regno; | |
11820 rtx value; | |
11821 reg_stat_type *rsp; | |
11822 | |
11823 /* If this is a non-paradoxical SUBREG, get the value of its operand and | |
11824 then convert it to the desired mode. If this is a paradoxical SUBREG, | |
11825 we cannot predict what values the "extra" bits might have. */ | |
11826 if (GET_CODE (x) == SUBREG | |
11827 && subreg_lowpart_p (x) | |
11828 && (GET_MODE_SIZE (GET_MODE (x)) | |
11829 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
11830 && (value = get_last_value (SUBREG_REG (x))) != 0) | |
11831 return gen_lowpart (GET_MODE (x), value); | |
11832 | |
11833 if (!REG_P (x)) | |
11834 return 0; | |
11835 | |
11836 regno = REGNO (x); | |
11837 rsp = VEC_index (reg_stat_type, reg_stat, regno); | |
11838 value = rsp->last_set_value; | |
11839 | |
11840 /* If we don't have a value, or if it isn't for this basic block and | |
11841 it's either a hard register, set more than once, or it's a live | |
11842 at the beginning of the function, return 0. | |
11843 | |
11844 Because if it's not live at the beginning of the function then the reg | |
11845 is always set before being used (is never used without being set). | |
11846 And, if it's set only once, and it's always set before use, then all | |
11847 uses must have the same last value, even if it's not from this basic | |
11848 block. */ | |
11849 | |
11850 if (value == 0 | |
11851 || (rsp->last_set_label < label_tick_ebb_start | |
11852 && (regno < FIRST_PSEUDO_REGISTER | |
11853 || REG_N_SETS (regno) != 1 | |
11854 || REGNO_REG_SET_P | |
11855 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))) | |
11856 return 0; | |
11857 | |
11858 /* If the value was set in a later insn than the ones we are processing, | |
11859 we can't use it even if the register was only set once. */ | |
11860 if (rsp->last_set_label == label_tick | |
11861 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid) | |
11862 return 0; | |
11863 | |
11864 /* If the value has all its registers valid, return it. */ | |
11865 if (get_last_value_validate (&value, rsp->last_set, | |
11866 rsp->last_set_label, 0)) | |
11867 return value; | |
11868 | |
11869 /* Otherwise, make a copy and replace any invalid register with | |
11870 (clobber (const_int 0)). If that fails for some reason, return 0. */ | |
11871 | |
11872 value = copy_rtx (value); | |
11873 if (get_last_value_validate (&value, rsp->last_set, | |
11874 rsp->last_set_label, 1)) | |
11875 return value; | |
11876 | |
11877 return 0; | |
11878 } | |
11879 | |
11880 /* Return nonzero if expression X refers to a REG or to memory | |
11881 that is set in an instruction more recent than FROM_LUID. */ | |
11882 | |
11883 static int | |
11884 use_crosses_set_p (const_rtx x, int from_luid) | |
11885 { | |
11886 const char *fmt; | |
11887 int i; | |
11888 enum rtx_code code = GET_CODE (x); | |
11889 | |
11890 if (code == REG) | |
11891 { | |
11892 unsigned int regno = REGNO (x); | |
11893 unsigned endreg = END_REGNO (x); | |
11894 | |
11895 #ifdef PUSH_ROUNDING | |
11896 /* Don't allow uses of the stack pointer to be moved, | |
11897 because we don't know whether the move crosses a push insn. */ | |
11898 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS) | |
11899 return 1; | |
11900 #endif | |
11901 for (; regno < endreg; regno++) | |
11902 { | |
11903 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno); | |
11904 if (rsp->last_set | |
11905 && rsp->last_set_label == label_tick | |
11906 && DF_INSN_LUID (rsp->last_set) > from_luid) | |
11907 return 1; | |
11908 } | |
11909 return 0; | |
11910 } | |
11911 | |
11912 if (code == MEM && mem_last_set > from_luid) | |
11913 return 1; | |
11914 | |
11915 fmt = GET_RTX_FORMAT (code); | |
11916 | |
11917 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
11918 { | |
11919 if (fmt[i] == 'E') | |
11920 { | |
11921 int j; | |
11922 for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
11923 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid)) | |
11924 return 1; | |
11925 } | |
11926 else if (fmt[i] == 'e' | |
11927 && use_crosses_set_p (XEXP (x, i), from_luid)) | |
11928 return 1; | |
11929 } | |
11930 return 0; | |
11931 } | |
11932 | |
11933 /* Define three variables used for communication between the following | |
11934 routines. */ | |
11935 | |
11936 static unsigned int reg_dead_regno, reg_dead_endregno; | |
11937 static int reg_dead_flag; | |
11938 | |
11939 /* Function called via note_stores from reg_dead_at_p. | |
11940 | |
11941 If DEST is within [reg_dead_regno, reg_dead_endregno), set | |
11942 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ | |
11943 | |
11944 static void | |
11945 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) | |
11946 { | |
11947 unsigned int regno, endregno; | |
11948 | |
11949 if (!REG_P (dest)) | |
11950 return; | |
11951 | |
11952 regno = REGNO (dest); | |
11953 endregno = END_REGNO (dest); | |
11954 if (reg_dead_endregno > regno && reg_dead_regno < endregno) | |
11955 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; | |
11956 } | |
11957 | |
11958 /* Return nonzero if REG is known to be dead at INSN. | |
11959 | |
11960 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER | |
11961 referencing REG, it is dead. If we hit a SET referencing REG, it is | |
11962 live. Otherwise, see if it is live or dead at the start of the basic | |
11963 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS | |
11964 must be assumed to be always live. */ | |
11965 | |
11966 static int | |
11967 reg_dead_at_p (rtx reg, rtx insn) | |
11968 { | |
11969 basic_block block; | |
11970 unsigned int i; | |
11971 | |
11972 /* Set variables for reg_dead_at_p_1. */ | |
11973 reg_dead_regno = REGNO (reg); | |
11974 reg_dead_endregno = END_REGNO (reg); | |
11975 | |
11976 reg_dead_flag = 0; | |
11977 | |
11978 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers | |
11979 we allow the machine description to decide whether use-and-clobber | |
11980 patterns are OK. */ | |
11981 if (reg_dead_regno < FIRST_PSEUDO_REGISTER) | |
11982 { | |
11983 for (i = reg_dead_regno; i < reg_dead_endregno; i++) | |
11984 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i)) | |
11985 return 0; | |
11986 } | |
11987 | |
11988 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or | |
11989 beginning of function. */ | |
11990 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn); | |
11991 insn = prev_nonnote_insn (insn)) | |
11992 { | |
11993 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL); | |
11994 if (reg_dead_flag) | |
11995 return reg_dead_flag == 1 ? 1 : 0; | |
11996 | |
11997 if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) | |
11998 return 1; | |
11999 } | |
12000 | |
12001 /* Get the basic block that we were in. */ | |
12002 if (insn == 0) | |
12003 block = ENTRY_BLOCK_PTR->next_bb; | |
12004 else | |
12005 { | |
12006 FOR_EACH_BB (block) | |
12007 if (insn == BB_HEAD (block)) | |
12008 break; | |
12009 | |
12010 if (block == EXIT_BLOCK_PTR) | |
12011 return 0; | |
12012 } | |
12013 | |
12014 for (i = reg_dead_regno; i < reg_dead_endregno; i++) | |
12015 if (REGNO_REG_SET_P (df_get_live_in (block), i)) | |
12016 return 0; | |
12017 | |
12018 return 1; | |
12019 } | |
12020 | |
12021 /* Note hard registers in X that are used. */ | |
12022 | |
12023 static void | |
12024 mark_used_regs_combine (rtx x) | |
12025 { | |
12026 RTX_CODE code = GET_CODE (x); | |
12027 unsigned int regno; | |
12028 int i; | |
12029 | |
12030 switch (code) | |
12031 { | |
12032 case LABEL_REF: | |
12033 case SYMBOL_REF: | |
12034 case CONST_INT: | |
12035 case CONST: | |
12036 case CONST_DOUBLE: | |
12037 case CONST_VECTOR: | |
12038 case PC: | |
12039 case ADDR_VEC: | |
12040 case ADDR_DIFF_VEC: | |
12041 case ASM_INPUT: | |
12042 #ifdef HAVE_cc0 | |
12043 /* CC0 must die in the insn after it is set, so we don't need to take | |
12044 special note of it here. */ | |
12045 case CC0: | |
12046 #endif | |
12047 return; | |
12048 | |
12049 case CLOBBER: | |
12050 /* If we are clobbering a MEM, mark any hard registers inside the | |
12051 address as used. */ | |
12052 if (MEM_P (XEXP (x, 0))) | |
12053 mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); | |
12054 return; | |
12055 | |
12056 case REG: | |
12057 regno = REGNO (x); | |
12058 /* A hard reg in a wide mode may really be multiple registers. | |
12059 If so, mark all of them just like the first. */ | |
12060 if (regno < FIRST_PSEUDO_REGISTER) | |
12061 { | |
12062 /* None of this applies to the stack, frame or arg pointers. */ | |
12063 if (regno == STACK_POINTER_REGNUM | |
12064 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
12065 || regno == HARD_FRAME_POINTER_REGNUM | |
12066 #endif | |
12067 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
12068 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) | |
12069 #endif | |
12070 || regno == FRAME_POINTER_REGNUM) | |
12071 return; | |
12072 | |
12073 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno); | |
12074 } | |
12075 return; | |
12076 | |
12077 case SET: | |
12078 { | |
12079 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in | |
12080 the address. */ | |
12081 rtx testreg = SET_DEST (x); | |
12082 | |
12083 while (GET_CODE (testreg) == SUBREG | |
12084 || GET_CODE (testreg) == ZERO_EXTRACT | |
12085 || GET_CODE (testreg) == STRICT_LOW_PART) | |
12086 testreg = XEXP (testreg, 0); | |
12087 | |
12088 if (MEM_P (testreg)) | |
12089 mark_used_regs_combine (XEXP (testreg, 0)); | |
12090 | |
12091 mark_used_regs_combine (SET_SRC (x)); | |
12092 } | |
12093 return; | |
12094 | |
12095 default: | |
12096 break; | |
12097 } | |
12098 | |
12099 /* Recursively scan the operands of this expression. */ | |
12100 | |
12101 { | |
12102 const char *fmt = GET_RTX_FORMAT (code); | |
12103 | |
12104 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
12105 { | |
12106 if (fmt[i] == 'e') | |
12107 mark_used_regs_combine (XEXP (x, i)); | |
12108 else if (fmt[i] == 'E') | |
12109 { | |
12110 int j; | |
12111 | |
12112 for (j = 0; j < XVECLEN (x, i); j++) | |
12113 mark_used_regs_combine (XVECEXP (x, i, j)); | |
12114 } | |
12115 } | |
12116 } | |
12117 } | |
12118 | |
12119 /* Remove register number REGNO from the dead registers list of INSN. | |
12120 | |
12121 Return the note used to record the death, if there was one. */ | |
12122 | |
12123 rtx | |
12124 remove_death (unsigned int regno, rtx insn) | |
12125 { | |
12126 rtx note = find_regno_note (insn, REG_DEAD, regno); | |
12127 | |
12128 if (note) | |
12129 remove_note (insn, note); | |
12130 | |
12131 return note; | |
12132 } | |
12133 | |
12134 /* For each register (hardware or pseudo) used within expression X, if its | |
12135 death is in an instruction with luid between FROM_LUID (inclusive) and | |
12136 TO_INSN (exclusive), put a REG_DEAD note for that register in the | |
12137 list headed by PNOTES. | |
12138 | |
12139 That said, don't move registers killed by maybe_kill_insn. | |
12140 | |
12141 This is done when X is being merged by combination into TO_INSN. These | |
12142 notes will then be distributed as needed. */ | |
12143 | |
12144 static void | |
12145 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn, | |
12146 rtx *pnotes) | |
12147 { | |
12148 const char *fmt; | |
12149 int len, i; | |
12150 enum rtx_code code = GET_CODE (x); | |
12151 | |
12152 if (code == REG) | |
12153 { | |
12154 unsigned int regno = REGNO (x); | |
12155 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death; | |
12156 | |
12157 /* Don't move the register if it gets killed in between from and to. */ | |
12158 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) | |
12159 && ! reg_referenced_p (x, maybe_kill_insn)) | |
12160 return; | |
12161 | |
12162 if (where_dead | |
12163 && DF_INSN_LUID (where_dead) >= from_luid | |
12164 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn)) | |
12165 { | |
12166 rtx note = remove_death (regno, where_dead); | |
12167 | |
12168 /* It is possible for the call above to return 0. This can occur | |
12169 when last_death points to I2 or I1 that we combined with. | |
12170 In that case make a new note. | |
12171 | |
12172 We must also check for the case where X is a hard register | |
12173 and NOTE is a death note for a range of hard registers | |
12174 including X. In that case, we must put REG_DEAD notes for | |
12175 the remaining registers in place of NOTE. */ | |
12176 | |
12177 if (note != 0 && regno < FIRST_PSEUDO_REGISTER | |
12178 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
12179 > GET_MODE_SIZE (GET_MODE (x)))) | |
12180 { | |
12181 unsigned int deadregno = REGNO (XEXP (note, 0)); | |
12182 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0)); | |
12183 unsigned int ourend = END_HARD_REGNO (x); | |
12184 unsigned int i; | |
12185 | |
12186 for (i = deadregno; i < deadend; i++) | |
12187 if (i < regno || i >= ourend) | |
12188 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]); | |
12189 } | |
12190 | |
12191 /* If we didn't find any note, or if we found a REG_DEAD note that | |
12192 covers only part of the given reg, and we have a multi-reg hard | |
12193 register, then to be safe we must check for REG_DEAD notes | |
12194 for each register other than the first. They could have | |
12195 their own REG_DEAD notes lying around. */ | |
12196 else if ((note == 0 | |
12197 || (note != 0 | |
12198 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
12199 < GET_MODE_SIZE (GET_MODE (x))))) | |
12200 && regno < FIRST_PSEUDO_REGISTER | |
12201 && hard_regno_nregs[regno][GET_MODE (x)] > 1) | |
12202 { | |
12203 unsigned int ourend = END_HARD_REGNO (x); | |
12204 unsigned int i, offset; | |
12205 rtx oldnotes = 0; | |
12206 | |
12207 if (note) | |
12208 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))]; | |
12209 else | |
12210 offset = 1; | |
12211 | |
12212 for (i = regno + offset; i < ourend; i++) | |
12213 move_deaths (regno_reg_rtx[i], | |
12214 maybe_kill_insn, from_luid, to_insn, &oldnotes); | |
12215 } | |
12216 | |
12217 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) | |
12218 { | |
12219 XEXP (note, 1) = *pnotes; | |
12220 *pnotes = note; | |
12221 } | |
12222 else | |
12223 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes); | |
12224 } | |
12225 | |
12226 return; | |
12227 } | |
12228 | |
12229 else if (GET_CODE (x) == SET) | |
12230 { | |
12231 rtx dest = SET_DEST (x); | |
12232 | |
12233 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes); | |
12234 | |
12235 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG | |
12236 that accesses one word of a multi-word item, some | |
12237 piece of everything register in the expression is used by | |
12238 this insn, so remove any old death. */ | |
12239 /* ??? So why do we test for equality of the sizes? */ | |
12240 | |
12241 if (GET_CODE (dest) == ZERO_EXTRACT | |
12242 || GET_CODE (dest) == STRICT_LOW_PART | |
12243 || (GET_CODE (dest) == SUBREG | |
12244 && (((GET_MODE_SIZE (GET_MODE (dest)) | |
12245 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
12246 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) | |
12247 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) | |
12248 { | |
12249 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes); | |
12250 return; | |
12251 } | |
12252 | |
12253 /* If this is some other SUBREG, we know it replaces the entire | |
12254 value, so use that as the destination. */ | |
12255 if (GET_CODE (dest) == SUBREG) | |
12256 dest = SUBREG_REG (dest); | |
12257 | |
12258 /* If this is a MEM, adjust deaths of anything used in the address. | |
12259 For a REG (the only other possibility), the entire value is | |
12260 being replaced so the old value is not used in this insn. */ | |
12261 | |
12262 if (MEM_P (dest)) | |
12263 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid, | |
12264 to_insn, pnotes); | |
12265 return; | |
12266 } | |
12267 | |
12268 else if (GET_CODE (x) == CLOBBER) | |
12269 return; | |
12270 | |
12271 len = GET_RTX_LENGTH (code); | |
12272 fmt = GET_RTX_FORMAT (code); | |
12273 | |
12274 for (i = 0; i < len; i++) | |
12275 { | |
12276 if (fmt[i] == 'E') | |
12277 { | |
12278 int j; | |
12279 for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
12280 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid, | |
12281 to_insn, pnotes); | |
12282 } | |
12283 else if (fmt[i] == 'e') | |
12284 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes); | |
12285 } | |
12286 } | |
12287 | |
12288 /* Return 1 if X is the target of a bit-field assignment in BODY, the | |
12289 pattern of an insn. X must be a REG. */ | |
12290 | |
12291 static int | |
12292 reg_bitfield_target_p (rtx x, rtx body) | |
12293 { | |
12294 int i; | |
12295 | |
12296 if (GET_CODE (body) == SET) | |
12297 { | |
12298 rtx dest = SET_DEST (body); | |
12299 rtx target; | |
12300 unsigned int regno, tregno, endregno, endtregno; | |
12301 | |
12302 if (GET_CODE (dest) == ZERO_EXTRACT) | |
12303 target = XEXP (dest, 0); | |
12304 else if (GET_CODE (dest) == STRICT_LOW_PART) | |
12305 target = SUBREG_REG (XEXP (dest, 0)); | |
12306 else | |
12307 return 0; | |
12308 | |
12309 if (GET_CODE (target) == SUBREG) | |
12310 target = SUBREG_REG (target); | |
12311 | |
12312 if (!REG_P (target)) | |
12313 return 0; | |
12314 | |
12315 tregno = REGNO (target), regno = REGNO (x); | |
12316 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) | |
12317 return target == x; | |
12318 | |
12319 endtregno = end_hard_regno (GET_MODE (target), tregno); | |
12320 endregno = end_hard_regno (GET_MODE (x), regno); | |
12321 | |
12322 return endregno > tregno && regno < endtregno; | |
12323 } | |
12324 | |
12325 else if (GET_CODE (body) == PARALLEL) | |
12326 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) | |
12327 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) | |
12328 return 1; | |
12329 | |
12330 return 0; | |
12331 } | |
12332 | |
12333 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them | |
12334 as appropriate. I3 and I2 are the insns resulting from the combination | |
12335 insns including FROM (I2 may be zero). | |
12336 | |
12337 ELIM_I2 and ELIM_I1 are either zero or registers that we know will | |
12338 not need REG_DEAD notes because they are being substituted for. This | |
12339 saves searching in the most common cases. | |
12340 | |
12341 Each note in the list is either ignored or placed on some insns, depending | |
12342 on the type of note. */ | |
12343 | |
12344 static void | |
12345 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2, | |
12346 rtx elim_i1) | |
12347 { | |
12348 rtx note, next_note; | |
12349 rtx tem; | |
12350 | |
12351 for (note = notes; note; note = next_note) | |
12352 { | |
12353 rtx place = 0, place2 = 0; | |
12354 | |
12355 next_note = XEXP (note, 1); | |
12356 switch (REG_NOTE_KIND (note)) | |
12357 { | |
12358 case REG_BR_PROB: | |
12359 case REG_BR_PRED: | |
12360 /* Doesn't matter much where we put this, as long as it's somewhere. | |
12361 It is preferable to keep these notes on branches, which is most | |
12362 likely to be i3. */ | |
12363 place = i3; | |
12364 break; | |
12365 | |
12366 case REG_VALUE_PROFILE: | |
12367 /* Just get rid of this note, as it is unused later anyway. */ | |
12368 break; | |
12369 | |
12370 case REG_NON_LOCAL_GOTO: | |
12371 if (JUMP_P (i3)) | |
12372 place = i3; | |
12373 else | |
12374 { | |
12375 gcc_assert (i2 && JUMP_P (i2)); | |
12376 place = i2; | |
12377 } | |
12378 break; | |
12379 | |
12380 case REG_EH_REGION: | |
12381 /* These notes must remain with the call or trapping instruction. */ | |
12382 if (CALL_P (i3)) | |
12383 place = i3; | |
12384 else if (i2 && CALL_P (i2)) | |
12385 place = i2; | |
12386 else | |
12387 { | |
12388 gcc_assert (flag_non_call_exceptions); | |
12389 if (may_trap_p (i3)) | |
12390 place = i3; | |
12391 else if (i2 && may_trap_p (i2)) | |
12392 place = i2; | |
12393 /* ??? Otherwise assume we've combined things such that we | |
12394 can now prove that the instructions can't trap. Drop the | |
12395 note in this case. */ | |
12396 } | |
12397 break; | |
12398 | |
12399 case REG_NORETURN: | |
12400 case REG_SETJMP: | |
12401 /* These notes must remain with the call. It should not be | |
12402 possible for both I2 and I3 to be a call. */ | |
12403 if (CALL_P (i3)) | |
12404 place = i3; | |
12405 else | |
12406 { | |
12407 gcc_assert (i2 && CALL_P (i2)); | |
12408 place = i2; | |
12409 } | |
12410 break; | |
12411 | |
12412 case REG_UNUSED: | |
12413 /* Any clobbers for i3 may still exist, and so we must process | |
12414 REG_UNUSED notes from that insn. | |
12415 | |
12416 Any clobbers from i2 or i1 can only exist if they were added by | |
12417 recog_for_combine. In that case, recog_for_combine created the | |
12418 necessary REG_UNUSED notes. Trying to keep any original | |
12419 REG_UNUSED notes from these insns can cause incorrect output | |
12420 if it is for the same register as the original i3 dest. | |
12421 In that case, we will notice that the register is set in i3, | |
12422 and then add a REG_UNUSED note for the destination of i3, which | |
12423 is wrong. However, it is possible to have REG_UNUSED notes from | |
12424 i2 or i1 for register which were both used and clobbered, so | |
12425 we keep notes from i2 or i1 if they will turn into REG_DEAD | |
12426 notes. */ | |
12427 | |
12428 /* If this register is set or clobbered in I3, put the note there | |
12429 unless there is one already. */ | |
12430 if (reg_set_p (XEXP (note, 0), PATTERN (i3))) | |
12431 { | |
12432 if (from_insn != i3) | |
12433 break; | |
12434 | |
12435 if (! (REG_P (XEXP (note, 0)) | |
12436 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) | |
12437 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) | |
12438 place = i3; | |
12439 } | |
12440 /* Otherwise, if this register is used by I3, then this register | |
12441 now dies here, so we must put a REG_DEAD note here unless there | |
12442 is one already. */ | |
12443 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) | |
12444 && ! (REG_P (XEXP (note, 0)) | |
12445 ? find_regno_note (i3, REG_DEAD, | |
12446 REGNO (XEXP (note, 0))) | |
12447 : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) | |
12448 { | |
12449 PUT_REG_NOTE_KIND (note, REG_DEAD); | |
12450 place = i3; | |
12451 } | |
12452 break; | |
12453 | |
12454 case REG_EQUAL: | |
12455 case REG_EQUIV: | |
12456 case REG_NOALIAS: | |
12457 /* These notes say something about results of an insn. We can | |
12458 only support them if they used to be on I3 in which case they | |
12459 remain on I3. Otherwise they are ignored. | |
12460 | |
12461 If the note refers to an expression that is not a constant, we | |
12462 must also ignore the note since we cannot tell whether the | |
12463 equivalence is still true. It might be possible to do | |
12464 slightly better than this (we only have a problem if I2DEST | |
12465 or I1DEST is present in the expression), but it doesn't | |
12466 seem worth the trouble. */ | |
12467 | |
12468 if (from_insn == i3 | |
12469 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) | |
12470 place = i3; | |
12471 break; | |
12472 | |
12473 case REG_INC: | |
12474 /* These notes say something about how a register is used. They must | |
12475 be present on any use of the register in I2 or I3. */ | |
12476 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) | |
12477 place = i3; | |
12478 | |
12479 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) | |
12480 { | |
12481 if (place) | |
12482 place2 = i2; | |
12483 else | |
12484 place = i2; | |
12485 } | |
12486 break; | |
12487 | |
12488 case REG_LABEL_TARGET: | |
12489 case REG_LABEL_OPERAND: | |
12490 /* This can show up in several ways -- either directly in the | |
12491 pattern, or hidden off in the constant pool with (or without?) | |
12492 a REG_EQUAL note. */ | |
12493 /* ??? Ignore the without-reg_equal-note problem for now. */ | |
12494 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) | |
12495 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX)) | |
12496 && GET_CODE (XEXP (tem, 0)) == LABEL_REF | |
12497 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))) | |
12498 place = i3; | |
12499 | |
12500 if (i2 | |
12501 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) | |
12502 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX)) | |
12503 && GET_CODE (XEXP (tem, 0)) == LABEL_REF | |
12504 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))) | |
12505 { | |
12506 if (place) | |
12507 place2 = i2; | |
12508 else | |
12509 place = i2; | |
12510 } | |
12511 | |
12512 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note | |
12513 as a JUMP_LABEL or decrement LABEL_NUSES if it's already | |
12514 there. */ | |
12515 if (place && JUMP_P (place) | |
12516 && REG_NOTE_KIND (note) == REG_LABEL_TARGET | |
12517 && (JUMP_LABEL (place) == NULL | |
12518 || JUMP_LABEL (place) == XEXP (note, 0))) | |
12519 { | |
12520 rtx label = JUMP_LABEL (place); | |
12521 | |
12522 if (!label) | |
12523 JUMP_LABEL (place) = XEXP (note, 0); | |
12524 else if (LABEL_P (label)) | |
12525 LABEL_NUSES (label)--; | |
12526 } | |
12527 | |
12528 if (place2 && JUMP_P (place2) | |
12529 && REG_NOTE_KIND (note) == REG_LABEL_TARGET | |
12530 && (JUMP_LABEL (place2) == NULL | |
12531 || JUMP_LABEL (place2) == XEXP (note, 0))) | |
12532 { | |
12533 rtx label = JUMP_LABEL (place2); | |
12534 | |
12535 if (!label) | |
12536 JUMP_LABEL (place2) = XEXP (note, 0); | |
12537 else if (LABEL_P (label)) | |
12538 LABEL_NUSES (label)--; | |
12539 place2 = 0; | |
12540 } | |
12541 break; | |
12542 | |
12543 case REG_NONNEG: | |
12544 /* This note says something about the value of a register prior | |
12545 to the execution of an insn. It is too much trouble to see | |
12546 if the note is still correct in all situations. It is better | |
12547 to simply delete it. */ | |
12548 break; | |
12549 | |
12550 case REG_DEAD: | |
12551 /* If we replaced the right hand side of FROM_INSN with a | |
12552 REG_EQUAL note, the original use of the dying register | |
12553 will not have been combined into I3 and I2. In such cases, | |
12554 FROM_INSN is guaranteed to be the first of the combined | |
12555 instructions, so we simply need to search back before | |
12556 FROM_INSN for the previous use or set of this register, | |
12557 then alter the notes there appropriately. | |
12558 | |
12559 If the register is used as an input in I3, it dies there. | |
12560 Similarly for I2, if it is nonzero and adjacent to I3. | |
12561 | |
12562 If the register is not used as an input in either I3 or I2 | |
12563 and it is not one of the registers we were supposed to eliminate, | |
12564 there are two possibilities. We might have a non-adjacent I2 | |
12565 or we might have somehow eliminated an additional register | |
12566 from a computation. For example, we might have had A & B where | |
12567 we discover that B will always be zero. In this case we will | |
12568 eliminate the reference to A. | |
12569 | |
12570 In both cases, we must search to see if we can find a previous | |
12571 use of A and put the death note there. */ | |
12572 | |
12573 if (from_insn | |
12574 && from_insn == i2mod | |
12575 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs)) | |
12576 tem = from_insn; | |
12577 else | |
12578 { | |
12579 if (from_insn | |
12580 && CALL_P (from_insn) | |
12581 && find_reg_fusage (from_insn, USE, XEXP (note, 0))) | |
12582 place = from_insn; | |
12583 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) | |
12584 place = i3; | |
12585 else if (i2 != 0 && next_nonnote_insn (i2) == i3 | |
12586 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) | |
12587 place = i2; | |
12588 else if ((rtx_equal_p (XEXP (note, 0), elim_i2) | |
12589 && !(i2mod | |
12590 && reg_overlap_mentioned_p (XEXP (note, 0), | |
12591 i2mod_old_rhs))) | |
12592 || rtx_equal_p (XEXP (note, 0), elim_i1)) | |
12593 break; | |
12594 tem = i3; | |
12595 } | |
12596 | |
12597 if (place == 0) | |
12598 { | |
12599 basic_block bb = this_basic_block; | |
12600 | |
12601 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem)) | |
12602 { | |
12603 if (! INSN_P (tem)) | |
12604 { | |
12605 if (tem == BB_HEAD (bb)) | |
12606 break; | |
12607 continue; | |
12608 } | |
12609 | |
12610 /* If the register is being set at TEM, see if that is all | |
12611 TEM is doing. If so, delete TEM. Otherwise, make this | |
12612 into a REG_UNUSED note instead. Don't delete sets to | |
12613 global register vars. */ | |
12614 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER | |
12615 || !global_regs[REGNO (XEXP (note, 0))]) | |
12616 && reg_set_p (XEXP (note, 0), PATTERN (tem))) | |
12617 { | |
12618 rtx set = single_set (tem); | |
12619 rtx inner_dest = 0; | |
12620 #ifdef HAVE_cc0 | |
12621 rtx cc0_setter = NULL_RTX; | |
12622 #endif | |
12623 | |
12624 if (set != 0) | |
12625 for (inner_dest = SET_DEST (set); | |
12626 (GET_CODE (inner_dest) == STRICT_LOW_PART | |
12627 || GET_CODE (inner_dest) == SUBREG | |
12628 || GET_CODE (inner_dest) == ZERO_EXTRACT); | |
12629 inner_dest = XEXP (inner_dest, 0)) | |
12630 ; | |
12631 | |
12632 /* Verify that it was the set, and not a clobber that | |
12633 modified the register. | |
12634 | |
12635 CC0 targets must be careful to maintain setter/user | |
12636 pairs. If we cannot delete the setter due to side | |
12637 effects, mark the user with an UNUSED note instead | |
12638 of deleting it. */ | |
12639 | |
12640 if (set != 0 && ! side_effects_p (SET_SRC (set)) | |
12641 && rtx_equal_p (XEXP (note, 0), inner_dest) | |
12642 #ifdef HAVE_cc0 | |
12643 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) | |
12644 || ((cc0_setter = prev_cc0_setter (tem)) != NULL | |
12645 && sets_cc0_p (PATTERN (cc0_setter)) > 0)) | |
12646 #endif | |
12647 ) | |
12648 { | |
12649 /* Move the notes and links of TEM elsewhere. | |
12650 This might delete other dead insns recursively. | |
12651 First set the pattern to something that won't use | |
12652 any register. */ | |
12653 rtx old_notes = REG_NOTES (tem); | |
12654 | |
12655 PATTERN (tem) = pc_rtx; | |
12656 REG_NOTES (tem) = NULL; | |
12657 | |
12658 distribute_notes (old_notes, tem, tem, NULL_RTX, | |
12659 NULL_RTX, NULL_RTX); | |
12660 distribute_links (LOG_LINKS (tem)); | |
12661 | |
12662 SET_INSN_DELETED (tem); | |
12663 if (tem == i2) | |
12664 i2 = NULL_RTX; | |
12665 | |
12666 #ifdef HAVE_cc0 | |
12667 /* Delete the setter too. */ | |
12668 if (cc0_setter) | |
12669 { | |
12670 PATTERN (cc0_setter) = pc_rtx; | |
12671 old_notes = REG_NOTES (cc0_setter); | |
12672 REG_NOTES (cc0_setter) = NULL; | |
12673 | |
12674 distribute_notes (old_notes, cc0_setter, | |
12675 cc0_setter, NULL_RTX, | |
12676 NULL_RTX, NULL_RTX); | |
12677 distribute_links (LOG_LINKS (cc0_setter)); | |
12678 | |
12679 SET_INSN_DELETED (cc0_setter); | |
12680 if (cc0_setter == i2) | |
12681 i2 = NULL_RTX; | |
12682 } | |
12683 #endif | |
12684 } | |
12685 else | |
12686 { | |
12687 PUT_REG_NOTE_KIND (note, REG_UNUSED); | |
12688 | |
12689 /* If there isn't already a REG_UNUSED note, put one | |
12690 here. Do not place a REG_DEAD note, even if | |
12691 the register is also used here; that would not | |
12692 match the algorithm used in lifetime analysis | |
12693 and can cause the consistency check in the | |
12694 scheduler to fail. */ | |
12695 if (! find_regno_note (tem, REG_UNUSED, | |
12696 REGNO (XEXP (note, 0)))) | |
12697 place = tem; | |
12698 break; | |
12699 } | |
12700 } | |
12701 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)) | |
12702 || (CALL_P (tem) | |
12703 && find_reg_fusage (tem, USE, XEXP (note, 0)))) | |
12704 { | |
12705 place = tem; | |
12706 | |
12707 /* If we are doing a 3->2 combination, and we have a | |
12708 register which formerly died in i3 and was not used | |
12709 by i2, which now no longer dies in i3 and is used in | |
12710 i2 but does not die in i2, and place is between i2 | |
12711 and i3, then we may need to move a link from place to | |
12712 i2. */ | |
12713 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2) | |
12714 && from_insn | |
12715 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2) | |
12716 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) | |
12717 { | |
12718 rtx links = LOG_LINKS (place); | |
12719 LOG_LINKS (place) = 0; | |
12720 distribute_links (links); | |
12721 } | |
12722 break; | |
12723 } | |
12724 | |
12725 if (tem == BB_HEAD (bb)) | |
12726 break; | |
12727 } | |
12728 | |
12729 } | |
12730 | |
12731 /* If the register is set or already dead at PLACE, we needn't do | |
12732 anything with this note if it is still a REG_DEAD note. | |
12733 We check here if it is set at all, not if is it totally replaced, | |
12734 which is what `dead_or_set_p' checks, so also check for it being | |
12735 set partially. */ | |
12736 | |
12737 if (place && REG_NOTE_KIND (note) == REG_DEAD) | |
12738 { | |
12739 unsigned int regno = REGNO (XEXP (note, 0)); | |
12740 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno); | |
12741 | |
12742 if (dead_or_set_p (place, XEXP (note, 0)) | |
12743 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) | |
12744 { | |
12745 /* Unless the register previously died in PLACE, clear | |
12746 last_death. [I no longer understand why this is | |
12747 being done.] */ | |
12748 if (rsp->last_death != place) | |
12749 rsp->last_death = 0; | |
12750 place = 0; | |
12751 } | |
12752 else | |
12753 rsp->last_death = place; | |
12754 | |
12755 /* If this is a death note for a hard reg that is occupying | |
12756 multiple registers, ensure that we are still using all | |
12757 parts of the object. If we find a piece of the object | |
12758 that is unused, we must arrange for an appropriate REG_DEAD | |
12759 note to be added for it. However, we can't just emit a USE | |
12760 and tag the note to it, since the register might actually | |
12761 be dead; so we recourse, and the recursive call then finds | |
12762 the previous insn that used this register. */ | |
12763 | |
12764 if (place && regno < FIRST_PSEUDO_REGISTER | |
12765 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1) | |
12766 { | |
12767 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0)); | |
12768 int all_used = 1; | |
12769 unsigned int i; | |
12770 | |
12771 for (i = regno; i < endregno; i++) | |
12772 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0) | |
12773 && ! find_regno_fusage (place, USE, i)) | |
12774 || dead_or_set_regno_p (place, i)) | |
12775 all_used = 0; | |
12776 | |
12777 if (! all_used) | |
12778 { | |
12779 /* Put only REG_DEAD notes for pieces that are | |
12780 not already dead or set. */ | |
12781 | |
12782 for (i = regno; i < endregno; | |
12783 i += hard_regno_nregs[i][reg_raw_mode[i]]) | |
12784 { | |
12785 rtx piece = regno_reg_rtx[i]; | |
12786 basic_block bb = this_basic_block; | |
12787 | |
12788 if (! dead_or_set_p (place, piece) | |
12789 && ! reg_bitfield_target_p (piece, | |
12790 PATTERN (place))) | |
12791 { | |
12792 rtx new_note | |
12793 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX); | |
12794 | |
12795 distribute_notes (new_note, place, place, | |
12796 NULL_RTX, NULL_RTX, NULL_RTX); | |
12797 } | |
12798 else if (! refers_to_regno_p (i, i + 1, | |
12799 PATTERN (place), 0) | |
12800 && ! find_regno_fusage (place, USE, i)) | |
12801 for (tem = PREV_INSN (place); ; | |
12802 tem = PREV_INSN (tem)) | |
12803 { | |
12804 if (! INSN_P (tem)) | |
12805 { | |
12806 if (tem == BB_HEAD (bb)) | |
12807 break; | |
12808 continue; | |
12809 } | |
12810 if (dead_or_set_p (tem, piece) | |
12811 || reg_bitfield_target_p (piece, | |
12812 PATTERN (tem))) | |
12813 { | |
12814 add_reg_note (tem, REG_UNUSED, piece); | |
12815 break; | |
12816 } | |
12817 } | |
12818 | |
12819 } | |
12820 | |
12821 place = 0; | |
12822 } | |
12823 } | |
12824 } | |
12825 break; | |
12826 | |
12827 default: | |
12828 /* Any other notes should not be present at this point in the | |
12829 compilation. */ | |
12830 gcc_unreachable (); | |
12831 } | |
12832 | |
12833 if (place) | |
12834 { | |
12835 XEXP (note, 1) = REG_NOTES (place); | |
12836 REG_NOTES (place) = note; | |
12837 } | |
12838 | |
12839 if (place2) | |
12840 REG_NOTES (place2) | |
12841 = gen_rtx_fmt_ee (GET_CODE (note), REG_NOTE_KIND (note), | |
12842 XEXP (note, 0), REG_NOTES (place2)); | |
12843 } | |
12844 } | |
12845 | |
12846 /* Similarly to above, distribute the LOG_LINKS that used to be present on | |
12847 I3, I2, and I1 to new locations. This is also called to add a link | |
12848 pointing at I3 when I3's destination is changed. */ | |
12849 | |
12850 static void | |
12851 distribute_links (rtx links) | |
12852 { | |
12853 rtx link, next_link; | |
12854 | |
12855 for (link = links; link; link = next_link) | |
12856 { | |
12857 rtx place = 0; | |
12858 rtx insn; | |
12859 rtx set, reg; | |
12860 | |
12861 next_link = XEXP (link, 1); | |
12862 | |
12863 /* If the insn that this link points to is a NOTE or isn't a single | |
12864 set, ignore it. In the latter case, it isn't clear what we | |
12865 can do other than ignore the link, since we can't tell which | |
12866 register it was for. Such links wouldn't be used by combine | |
12867 anyway. | |
12868 | |
12869 It is not possible for the destination of the target of the link to | |
12870 have been changed by combine. The only potential of this is if we | |
12871 replace I3, I2, and I1 by I3 and I2. But in that case the | |
12872 destination of I2 also remains unchanged. */ | |
12873 | |
12874 if (NOTE_P (XEXP (link, 0)) | |
12875 || (set = single_set (XEXP (link, 0))) == 0) | |
12876 continue; | |
12877 | |
12878 reg = SET_DEST (set); | |
12879 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
12880 || GET_CODE (reg) == STRICT_LOW_PART) | |
12881 reg = XEXP (reg, 0); | |
12882 | |
12883 /* A LOG_LINK is defined as being placed on the first insn that uses | |
12884 a register and points to the insn that sets the register. Start | |
12885 searching at the next insn after the target of the link and stop | |
12886 when we reach a set of the register or the end of the basic block. | |
12887 | |
12888 Note that this correctly handles the link that used to point from | |
12889 I3 to I2. Also note that not much searching is typically done here | |
12890 since most links don't point very far away. */ | |
12891 | |
12892 for (insn = NEXT_INSN (XEXP (link, 0)); | |
12893 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR | |
12894 || BB_HEAD (this_basic_block->next_bb) != insn)); | |
12895 insn = NEXT_INSN (insn)) | |
12896 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
12897 { | |
12898 if (reg_referenced_p (reg, PATTERN (insn))) | |
12899 place = insn; | |
12900 break; | |
12901 } | |
12902 else if (CALL_P (insn) | |
12903 && find_reg_fusage (insn, USE, reg)) | |
12904 { | |
12905 place = insn; | |
12906 break; | |
12907 } | |
12908 else if (INSN_P (insn) && reg_set_p (reg, insn)) | |
12909 break; | |
12910 | |
12911 /* If we found a place to put the link, place it there unless there | |
12912 is already a link to the same insn as LINK at that point. */ | |
12913 | |
12914 if (place) | |
12915 { | |
12916 rtx link2; | |
12917 | |
12918 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) | |
12919 if (XEXP (link2, 0) == XEXP (link, 0)) | |
12920 break; | |
12921 | |
12922 if (link2 == 0) | |
12923 { | |
12924 XEXP (link, 1) = LOG_LINKS (place); | |
12925 LOG_LINKS (place) = link; | |
12926 | |
12927 /* Set added_links_insn to the earliest insn we added a | |
12928 link to. */ | |
12929 if (added_links_insn == 0 | |
12930 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place)) | |
12931 added_links_insn = place; | |
12932 } | |
12933 } | |
12934 } | |
12935 } | |
12936 | |
12937 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx. | |
12938 Check whether the expression pointer to by LOC is a register or | |
12939 memory, and if so return 1 if it isn't mentioned in the rtx EXPR. | |
12940 Otherwise return zero. */ | |
12941 | |
12942 static int | |
12943 unmentioned_reg_p_1 (rtx *loc, void *expr) | |
12944 { | |
12945 rtx x = *loc; | |
12946 | |
12947 if (x != NULL_RTX | |
12948 && (REG_P (x) || MEM_P (x)) | |
12949 && ! reg_mentioned_p (x, (rtx) expr)) | |
12950 return 1; | |
12951 return 0; | |
12952 } | |
12953 | |
12954 /* Check for any register or memory mentioned in EQUIV that is not | |
12955 mentioned in EXPR. This is used to restrict EQUIV to "specializations" | |
12956 of EXPR where some registers may have been replaced by constants. */ | |
12957 | |
12958 static bool | |
12959 unmentioned_reg_p (rtx equiv, rtx expr) | |
12960 { | |
12961 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr); | |
12962 } | |
12963 | |
12964 void | |
12965 dump_combine_stats (FILE *file) | |
12966 { | |
12967 fprintf | |
12968 (file, | |
12969 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", | |
12970 combine_attempts, combine_merges, combine_extras, combine_successes); | |
12971 } | |
12972 | |
12973 void | |
12974 dump_combine_total_stats (FILE *file) | |
12975 { | |
12976 fprintf | |
12977 (file, | |
12978 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", | |
12979 total_attempts, total_merges, total_extras, total_successes); | |
12980 } | |
12981 | |
12982 static bool | |
12983 gate_handle_combine (void) | |
12984 { | |
12985 return (optimize > 0); | |
12986 } | |
12987 | |
12988 /* Try combining insns through substitution. */ | |
12989 static unsigned int | |
12990 rest_of_handle_combine (void) | |
12991 { | |
12992 int rebuild_jump_labels_after_combine; | |
12993 | |
12994 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN); | |
12995 df_note_add_problem (); | |
12996 df_analyze (); | |
12997 | |
12998 regstat_init_n_sets_and_refs (); | |
12999 | |
13000 rebuild_jump_labels_after_combine | |
13001 = combine_instructions (get_insns (), max_reg_num ()); | |
13002 | |
13003 /* Combining insns may have turned an indirect jump into a | |
13004 direct jump. Rebuild the JUMP_LABEL fields of jumping | |
13005 instructions. */ | |
13006 if (rebuild_jump_labels_after_combine) | |
13007 { | |
13008 timevar_push (TV_JUMP); | |
13009 rebuild_jump_labels (get_insns ()); | |
13010 cleanup_cfg (0); | |
13011 timevar_pop (TV_JUMP); | |
13012 } | |
13013 | |
13014 regstat_free_n_sets_and_refs (); | |
13015 return 0; | |
13016 } | |
13017 | |
13018 struct rtl_opt_pass pass_combine = | |
13019 { | |
13020 { | |
13021 RTL_PASS, | |
13022 "combine", /* name */ | |
13023 gate_handle_combine, /* gate */ | |
13024 rest_of_handle_combine, /* execute */ | |
13025 NULL, /* sub */ | |
13026 NULL, /* next */ | |
13027 0, /* static_pass_number */ | |
13028 TV_COMBINE, /* tv_id */ | |
13029 0, /* properties_required */ | |
13030 0, /* properties_provided */ | |
13031 0, /* properties_destroyed */ | |
13032 0, /* todo_flags_start */ | |
13033 TODO_dump_func | | |
13034 TODO_df_finish | TODO_verify_rtl_sharing | | |
13035 TODO_ggc_collect, /* todo_flags_finish */ | |
13036 } | |
13037 }; | |
13038 |