Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/alpha/ev5.md @ 0:a06113de4d67

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
first commit
author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
parents
children 04ced10e8804
comparison
equal deleted inserted replaced
-1:000000000000 0:a06113de4d67
1 ;; Scheduling description for Alpha EV5.
2 ;; Copyright (C) 2002, 2004, 2005, 2007 Free Software Foundation, Inc.
3 ;;
4 ;; This file is part of GCC.
5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
9 ;; any later version.
10 ;;
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
15 ;;
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
19
20 ;; EV5 has two asymmetric integer units, E0 and E1, plus separate
21 ;; FP add and multiply units.
22
23 (define_automaton "ev5_0,ev5_1")
24 (define_cpu_unit "ev5_e0,ev5_e1,ev5_fa,ev5_fm" "ev5_0")
25 (define_reservation "ev5_e01" "ev5_e0|ev5_e1")
26 (define_reservation "ev5_fam" "ev5_fa|ev5_fm")
27 (define_cpu_unit "ev5_imul" "ev5_0")
28 (define_cpu_unit "ev5_fdiv" "ev5_1")
29
30 ; Assume type "multi" single issues.
31 (define_insn_reservation "ev5_multi" 1
32 (and (eq_attr "tune" "ev5")
33 (eq_attr "type" "multi"))
34 "ev5_e0+ev5_e1+ev5_fa+ev5_fm")
35
36 ; Stores can only issue to E0, and may not issue with loads.
37 ; Model this with some fake units.
38
39 (define_cpu_unit "ev5_l0,ev5_l1,ev5_st" "ev5_0")
40 (define_reservation "ev5_ld" "ev5_l0|ev5_l1")
41 (exclusion_set "ev5_l0,ev5_l1" "ev5_st")
42
43 (define_insn_reservation "ev5_st" 1
44 (and (eq_attr "tune" "ev5")
45 (eq_attr "type" "ist,fst,st_c,mb"))
46 "ev5_e0+ev5_st")
47
48 ; Loads from L0 complete in two cycles. adjust_cost still factors
49 ; in user-specified memory latency, so return 1 here.
50 (define_insn_reservation "ev5_ld" 1
51 (and (eq_attr "tune" "ev5")
52 (eq_attr "type" "ild,fld,ldsym"))
53 "ev5_e01+ev5_ld")
54
55 (define_insn_reservation "ev5_ld_l" 1
56 (and (eq_attr "tune" "ev5")
57 (eq_attr "type" "ld_l"))
58 "ev5_e0+ev5_ld")
59
60 ; Integer branches slot only to E1.
61 (define_insn_reservation "ev5_ibr" 1
62 (and (eq_attr "tune" "ev5")
63 (eq_attr "type" "ibr"))
64 "ev5_e1")
65
66 (define_insn_reservation "ev5_callpal" 1
67 (and (eq_attr "tune" "ev5")
68 (eq_attr "type" "callpal"))
69 "ev5_e1")
70
71 (define_insn_reservation "ev5_jsr" 1
72 (and (eq_attr "tune" "ev5")
73 (eq_attr "type" "jsr"))
74 "ev5_e1")
75
76 (define_insn_reservation "ev5_shift" 1
77 (and (eq_attr "tune" "ev5")
78 (eq_attr "type" "shift"))
79 "ev5_e0")
80
81 (define_insn_reservation "ev5_mvi" 2
82 (and (eq_attr "tune" "ev5")
83 (eq_attr "type" "mvi"))
84 "ev5_e0")
85
86 (define_insn_reservation "ev5_cmov" 2
87 (and (eq_attr "tune" "ev5")
88 (eq_attr "type" "icmov"))
89 "ev5_e01")
90
91 (define_insn_reservation "ev5_iadd" 1
92 (and (eq_attr "tune" "ev5")
93 (eq_attr "type" "iadd"))
94 "ev5_e01")
95
96 (define_insn_reservation "ev5_ilogcmp" 1
97 (and (eq_attr "tune" "ev5")
98 (eq_attr "type" "ilog,icmp"))
99 "ev5_e01")
100
101 ; Conditional move and branch can issue the same cycle as the test.
102 (define_bypass 0 "ev5_ilogcmp" "ev5_ibr,ev5_cmov" "if_test_bypass_p")
103
104 ; Multiplies use a non-pipelined imul unit. Also, "no insn can be issued
105 ; to E0 exactly two cycles before an integer multiply completes".
106
107 (define_insn_reservation "ev5_imull" 8
108 (and (eq_attr "tune" "ev5")
109 (and (eq_attr "type" "imul")
110 (eq_attr "opsize" "si")))
111 "ev5_e0+ev5_imul,ev5_imul*3,nothing,ev5_e0")
112
113 (define_insn_reservation "ev5_imulq" 12
114 (and (eq_attr "tune" "ev5")
115 (and (eq_attr "type" "imul")
116 (eq_attr "opsize" "di")))
117 "ev5_e0+ev5_imul,ev5_imul*7,nothing,ev5_e0")
118
119 (define_insn_reservation "ev5_imulh" 14
120 (and (eq_attr "tune" "ev5")
121 (and (eq_attr "type" "imul")
122 (eq_attr "opsize" "udi")))
123 "ev5_e0+ev5_imul,ev5_imul*7,nothing*3,ev5_e0")
124
125 ; The multiplier is unable to receive data from Ebox bypass paths. The
126 ; instruction issues at the expected time, but its latency is increased
127 ; by the time it takes for the input data to become available to the
128 ; multiplier. For example, an IMULL instruction issued one cycle later
129 ; than an ADDL instruction, which produced one of its operands, has a
130 ; latency of 10 (8 + 2). If the IMULL instruction is issued two cycles
131 ; later than the ADDL instruction, the latency is 9 (8 + 1).
132 ;
133 ; Model this instead with increased latency on the input instruction.
134
135 (define_bypass 3
136 "ev5_ld,ev5_ld_l,ev5_shift,ev5_mvi,ev5_cmov,ev5_iadd,ev5_ilogcmp"
137 "ev5_imull,ev5_imulq,ev5_imulh")
138
139 (define_bypass 9 "ev5_imull" "ev5_imull,ev5_imulq,ev5_imulh")
140 (define_bypass 13 "ev5_imulq" "ev5_imull,ev5_imulq,ev5_imulh")
141 (define_bypass 15 "ev5_imulh" "ev5_imull,ev5_imulq,ev5_imulh")
142
143 ; Similarly for the FPU we have two asymmetric units.
144
145 (define_insn_reservation "ev5_fadd" 4
146 (and (eq_attr "tune" "ev5")
147 (eq_attr "type" "fadd,fcmov"))
148 "ev5_fa")
149
150 (define_insn_reservation "ev5_fbr" 1
151 (and (eq_attr "tune" "ev5")
152 (eq_attr "type" "fbr"))
153 "ev5_fa")
154
155 (define_insn_reservation "ev5_fcpys" 4
156 (and (eq_attr "tune" "ev5")
157 (eq_attr "type" "fcpys"))
158 "ev5_fam")
159
160 (define_insn_reservation "ev5_fmul" 4
161 (and (eq_attr "tune" "ev5")
162 (eq_attr "type" "fmul"))
163 "ev5_fm")
164
165 ; The floating point divider is not pipelined. Also, "no insn can be issued
166 ; to FA exactly five before an fdiv insn completes".
167 ;
168 ; ??? Do not model this late reservation due to the enormously increased
169 ; size of the resulting DFA.
170 ;
171 ; ??? Putting ev5_fa and ev5_fdiv alone into the same automata produces
172 ; a DFA of acceptable size, but putting ev5_fm and ev5_fa into separate
173 ; automata produces incorrect results for insns that can choose one or
174 ; the other, i.e. ev5_fcpys.
175
176 (define_insn_reservation "ev5_fdivsf" 15
177 (and (eq_attr "tune" "ev5")
178 (and (eq_attr "type" "fdiv")
179 (eq_attr "opsize" "si")))
180 ; "ev5_fa+ev5_fdiv,ev5_fdiv*9,ev5_fa+ev5_fdiv,ev5_fdiv*4"
181 "ev5_fa+ev5_fdiv,ev5_fdiv*14")
182
183 (define_insn_reservation "ev5_fdivdf" 22
184 (and (eq_attr "tune" "ev5")
185 (and (eq_attr "type" "fdiv")
186 (eq_attr "opsize" "di")))
187 ; "ev5_fa+ev5_fdiv,ev5_fdiv*17,ev5_fa+ev5_fdiv,ev5_fdiv*4"
188 "ev5_fa+ev5_fdiv,ev5_fdiv*21")
189
190 ; Traps don't consume or produce data; rpcc is latency 2 if we ever add it.
191 (define_insn_reservation "ev5_misc" 2
192 (and (eq_attr "tune" "ev5")
193 (eq_attr "type" "misc"))
194 "ev5_e0")