Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/arm/arm-generic.md @ 0:a06113de4d67
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author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
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date | Fri, 17 Jul 2009 14:47:48 +0900 |
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children | b7f97abdc517 |
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1 ;; Generic ARM Pipeline Description | |
2 ;; Copyright (C) 2003, 2007 Free Software Foundation, Inc. | |
3 ;; | |
4 ;; This file is part of GCC. | |
5 ;; | |
6 ;; GCC is free software; you can redistribute it and/or modify it | |
7 ;; under the terms of the GNU General Public License as published by | |
8 ;; the Free Software Foundation; either version 3, or (at your option) | |
9 ;; any later version. | |
10 ;; | |
11 ;; GCC is distributed in the hope that it will be useful, but | |
12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 ;; General Public License for more details. | |
15 ;; | |
16 ;; You should have received a copy of the GNU General Public License | |
17 ;; along with GCC; see the file COPYING3. If not see | |
18 ;; <http://www.gnu.org/licenses/>. */ | |
19 | |
20 (define_automaton "arm") | |
21 | |
22 ;; Write buffer | |
23 ; | |
24 ; Strictly, we should model a 4-deep write buffer for ARM7xx based chips | |
25 ; | |
26 ; The write buffer on some of the arm6 processors is hard to model exactly. | |
27 ; There is room in the buffer for up to two addresses and up to eight words | |
28 ; of memory, but the two needn't be split evenly. When writing the two | |
29 ; addresses are fully pipelined. However, a read from memory that is not | |
30 ; currently in the cache will block until the writes have completed. | |
31 ; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so | |
32 ; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous | |
33 ; (they aren't allowed to be at present) then there is a startup cost of 1MCLK | |
34 ; cycle to add as well. | |
35 (define_cpu_unit "write_buf" "arm") | |
36 | |
37 ;; Write blockage unit | |
38 ; | |
39 ; The write_blockage unit models (partially), the fact that reads will stall | |
40 ; until the write buffer empties. | |
41 ; The f_mem_r and r_mem_f could also block, but they are to the stack, | |
42 ; so we don't model them here | |
43 (define_cpu_unit "write_blockage" "arm") | |
44 | |
45 ;; Core | |
46 ; | |
47 (define_cpu_unit "core" "arm") | |
48 | |
49 (define_insn_reservation "r_mem_f_wbuf" 5 | |
50 (and (eq_attr "generic_sched" "yes") | |
51 (and (eq_attr "model_wbuf" "yes") | |
52 (eq_attr "type" "r_mem_f"))) | |
53 "core+write_buf*3") | |
54 | |
55 (define_insn_reservation "store_wbuf" 5 | |
56 (and (eq_attr "generic_sched" "yes") | |
57 (and (eq_attr "model_wbuf" "yes") | |
58 (eq_attr "type" "store1"))) | |
59 "core+write_buf*3+write_blockage*5") | |
60 | |
61 (define_insn_reservation "store2_wbuf" 7 | |
62 (and (eq_attr "generic_sched" "yes") | |
63 (and (eq_attr "model_wbuf" "yes") | |
64 (eq_attr "type" "store2"))) | |
65 "core+write_buf*4+write_blockage*7") | |
66 | |
67 (define_insn_reservation "store3_wbuf" 9 | |
68 (and (eq_attr "generic_sched" "yes") | |
69 (and (eq_attr "model_wbuf" "yes") | |
70 (eq_attr "type" "store3"))) | |
71 "core+write_buf*5+write_blockage*9") | |
72 | |
73 (define_insn_reservation "store4_wbuf" 11 | |
74 (and (eq_attr "generic_sched" "yes") | |
75 (and (eq_attr "model_wbuf" "yes") | |
76 (eq_attr "type" "store4"))) | |
77 "core+write_buf*6+write_blockage*11") | |
78 | |
79 (define_insn_reservation "store2" 3 | |
80 (and (eq_attr "generic_sched" "yes") | |
81 (and (eq_attr "model_wbuf" "no") | |
82 (eq_attr "type" "store2"))) | |
83 "core*3") | |
84 | |
85 (define_insn_reservation "store3" 4 | |
86 (and (eq_attr "generic_sched" "yes") | |
87 (and (eq_attr "model_wbuf" "no") | |
88 (eq_attr "type" "store3"))) | |
89 "core*4") | |
90 | |
91 (define_insn_reservation "store4" 5 | |
92 (and (eq_attr "generic_sched" "yes") | |
93 (and (eq_attr "model_wbuf" "no") | |
94 (eq_attr "type" "store4"))) | |
95 "core*5") | |
96 | |
97 (define_insn_reservation "store_ldsched" 1 | |
98 (and (eq_attr "generic_sched" "yes") | |
99 (and (eq_attr "ldsched" "yes") | |
100 (eq_attr "type" "store1"))) | |
101 "core") | |
102 | |
103 (define_insn_reservation "load_ldsched_xscale" 3 | |
104 (and (eq_attr "generic_sched" "yes") | |
105 (and (eq_attr "ldsched" "yes") | |
106 (and (eq_attr "type" "load_byte,load1") | |
107 (eq_attr "is_xscale" "yes")))) | |
108 "core") | |
109 | |
110 (define_insn_reservation "load_ldsched" 2 | |
111 (and (eq_attr "generic_sched" "yes") | |
112 (and (eq_attr "ldsched" "yes") | |
113 (and (eq_attr "type" "load_byte,load1") | |
114 (eq_attr "is_xscale" "no")))) | |
115 "core") | |
116 | |
117 (define_insn_reservation "load_or_store" 2 | |
118 (and (eq_attr "generic_sched" "yes") | |
119 (and (eq_attr "ldsched" "!yes") | |
120 (eq_attr "type" "load_byte,load1,load2,load3,load4,store1"))) | |
121 "core*2") | |
122 | |
123 (define_insn_reservation "mult" 16 | |
124 (and (eq_attr "generic_sched" "yes") | |
125 (and (eq_attr "ldsched" "no") (eq_attr "type" "mult"))) | |
126 "core*16") | |
127 | |
128 (define_insn_reservation "mult_ldsched_strongarm" 3 | |
129 (and (eq_attr "generic_sched" "yes") | |
130 (and (eq_attr "ldsched" "yes") | |
131 (and (eq_attr "is_strongarm" "yes") | |
132 (eq_attr "type" "mult")))) | |
133 "core*2") | |
134 | |
135 (define_insn_reservation "mult_ldsched" 4 | |
136 (and (eq_attr "generic_sched" "yes") | |
137 (and (eq_attr "ldsched" "yes") | |
138 (and (eq_attr "is_strongarm" "no") | |
139 (eq_attr "type" "mult")))) | |
140 "core*4") | |
141 | |
142 (define_insn_reservation "multi_cycle" 32 | |
143 (and (eq_attr "generic_sched" "yes") | |
144 (and (eq_attr "core_cycles" "multi") | |
145 (eq_attr "type" "!mult,load_byte,load1,load2,load3,load4,store1,store2,store3,store4"))) | |
146 "core*32") | |
147 | |
148 (define_insn_reservation "single_cycle" 1 | |
149 (and (eq_attr "generic_sched" "yes") | |
150 (eq_attr "core_cycles" "single")) | |
151 "core") |