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comparison gcc/config/arm/cirrus.md @ 0:a06113de4d67

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author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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-1:000000000000 0:a06113de4d67
1 ;; Cirrus EP9312 "Maverick" ARM floating point co-processor description.
2 ;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat.
4 ;; Written by Aldy Hernandez (aldyh@redhat.com)
5
6 ;; This file is part of GCC.
7
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; any later version.
12
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
21
22
23 ; Cirrus types for invalid insn combinations
24 ; not Not a cirrus insn
25 ; normal Any Cirrus insn not covered by the special cases below
26 ; double cfldrd, cfldr64, cfstrd, cfstr64
27 ; compare cfcmps, cfcmpd, cfcmp32, cfcmp64
28 ; move cfmvdlr, cfmvdhr, cfmvsr, cfmv64lr, cfmv64hr
29 (define_attr "cirrus" "not,normal,double,compare,move" (const_string "not"))
30
31
32 (define_insn "cirrus_adddi3"
33 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
34 (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
35 (match_operand:DI 2 "cirrus_fp_register" "v")))]
36 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
37 "cfadd64%?\\t%V0, %V1, %V2"
38 [(set_attr "type" "mav_farith")
39 (set_attr "cirrus" "normal")]
40 )
41
42 (define_insn "*cirrus_addsi3"
43 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
44 (plus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
45 (match_operand:SI 2 "cirrus_fp_register" "v")))]
46 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
47 "cfadd32%?\\t%V0, %V1, %V2"
48 [(set_attr "type" "mav_farith")
49 (set_attr "cirrus" "normal")]
50 )
51
52 (define_insn "*cirrus_addsf3"
53 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
54 (plus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
55 (match_operand:SF 2 "cirrus_fp_register" "v")))]
56 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
57 "cfadds%?\\t%V0, %V1, %V2"
58 [(set_attr "type" "mav_farith")
59 (set_attr "cirrus" "normal")]
60 )
61
62 (define_insn "*cirrus_adddf3"
63 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
64 (plus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
65 (match_operand:DF 2 "cirrus_fp_register" "v")))]
66 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
67 "cfaddd%?\\t%V0, %V1, %V2"
68 [(set_attr "type" "mav_farith")
69 (set_attr "cirrus" "normal")]
70 )
71
72 (define_insn "cirrus_subdi3"
73 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
74 (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
75 (match_operand:DI 2 "cirrus_fp_register" "v")))]
76 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
77 "cfsub64%?\\t%V0, %V1, %V2"
78 [(set_attr "type" "mav_farith")
79 (set_attr "cirrus" "normal")]
80 )
81
82 (define_insn "*cirrus_subsi3_insn"
83 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
84 (minus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
85 (match_operand:SI 2 "cirrus_fp_register" "v")))]
86 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
87 "cfsub32%?\\t%V0, %V1, %V2"
88 [(set_attr "type" "mav_farith")
89 (set_attr "cirrus" "normal")]
90 )
91
92 (define_insn "*cirrus_subsf3"
93 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
94 (minus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
95 (match_operand:SF 2 "cirrus_fp_register" "v")))]
96 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
97 "cfsubs%?\\t%V0, %V1, %V2"
98 [(set_attr "type" "mav_farith")
99 (set_attr "cirrus" "normal")]
100 )
101
102 (define_insn "*cirrus_subdf3"
103 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
104 (minus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
105 (match_operand:DF 2 "cirrus_fp_register" "v")))]
106 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
107 "cfsubd%?\\t%V0, %V1, %V2"
108 [(set_attr "type" "mav_farith")
109 (set_attr "cirrus" "normal")]
110 )
111
112 (define_insn "*cirrus_mulsi3"
113 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
114 (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
115 (match_operand:SI 1 "cirrus_fp_register" "v")))]
116 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
117 "cfmul32%?\\t%V0, %V1, %V2"
118 [(set_attr "type" "mav_farith")
119 (set_attr "cirrus" "normal")]
120 )
121
122 (define_insn "muldi3"
123 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
124 (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v")
125 (match_operand:DI 1 "cirrus_fp_register" "v")))]
126 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
127 "cfmul64%?\\t%V0, %V1, %V2"
128 [(set_attr "type" "mav_dmult")
129 (set_attr "cirrus" "normal")]
130 )
131
132 (define_insn "*cirrus_mulsi3addsi"
133 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
134 (plus:SI
135 (mult:SI (match_operand:SI 1 "cirrus_fp_register" "v")
136 (match_operand:SI 2 "cirrus_fp_register" "v"))
137 (match_operand:SI 3 "cirrus_fp_register" "0")))]
138 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
139 "cfmac32%?\\t%V0, %V1, %V2"
140 [(set_attr "type" "mav_farith")
141 (set_attr "cirrus" "normal")]
142 )
143
144 ;; Cirrus SI multiply-subtract
145 (define_insn "*cirrus_mulsi3subsi"
146 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
147 (minus:SI
148 (match_operand:SI 1 "cirrus_fp_register" "0")
149 (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
150 (match_operand:SI 3 "cirrus_fp_register" "v"))))]
151 "0 && TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
152 "cfmsc32%?\\t%V0, %V2, %V3"
153 [(set_attr "type" "mav_farith")
154 (set_attr "cirrus" "normal")]
155 )
156
157 (define_insn "*cirrus_mulsf3"
158 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
159 (mult:SF (match_operand:SF 1 "cirrus_fp_register" "v")
160 (match_operand:SF 2 "cirrus_fp_register" "v")))]
161 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
162 "cfmuls%?\\t%V0, %V1, %V2"
163 [(set_attr "type" "mav_farith")
164 (set_attr "cirrus" "normal")]
165 )
166
167 (define_insn "*cirrus_muldf3"
168 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
169 (mult:DF (match_operand:DF 1 "cirrus_fp_register" "v")
170 (match_operand:DF 2 "cirrus_fp_register" "v")))]
171 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
172 "cfmuld%?\\t%V0, %V1, %V2"
173 [(set_attr "type" "mav_dmult")
174 (set_attr "cirrus" "normal")]
175 )
176
177 (define_insn "cirrus_ashl_const"
178 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
179 (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v")
180 (match_operand:SI 2 "cirrus_shift_const" "")))]
181 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
182 "cfsh32%?\\t%V0, %V1, #%s2"
183 [(set_attr "cirrus" "normal")]
184 )
185
186 (define_insn "cirrus_ashiftrt_const"
187 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
188 (ashiftrt:SI (match_operand:SI 1 "cirrus_fp_register" "v")
189 (match_operand:SI 2 "cirrus_shift_const" "")))]
190 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
191 "cfsh32%?\\t%V0, %V1, #-%s2"
192 [(set_attr "cirrus" "normal")]
193 )
194
195 (define_insn "cirrus_ashlsi3"
196 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
197 (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v")
198 (match_operand:SI 2 "register_operand" "r")))]
199 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
200 "cfrshl32%?\\t%V1, %V0, %s2"
201 [(set_attr "cirrus" "normal")]
202 )
203
204 (define_insn "ashldi3_cirrus"
205 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
206 (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
207 (match_operand:SI 2 "register_operand" "r")))]
208 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
209 "cfrshl64%?\\t%V1, %V0, %s2"
210 [(set_attr "cirrus" "normal")]
211 )
212
213 (define_insn "cirrus_ashldi_const"
214 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
215 (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
216 (match_operand:SI 2 "cirrus_shift_const" "")))]
217 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
218 "cfsh64%?\\t%V0, %V1, #%s2"
219 [(set_attr "cirrus" "normal")]
220 )
221
222 (define_insn "cirrus_ashiftrtdi_const"
223 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
224 (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v")
225 (match_operand:SI 2 "cirrus_shift_const" "")))]
226 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
227 "cfsh64%?\\t%V0, %V1, #-%s2"
228 [(set_attr "cirrus" "normal")]
229 )
230
231 (define_insn "*cirrus_absdi2"
232 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
233 (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))]
234 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
235 "cfabs64%?\\t%V0, %V1"
236 [(set_attr "cirrus" "normal")]
237 )
238
239 ;; This doesn't really clobber ``cc''. Fixme: aldyh.
240 (define_insn "*cirrus_negdi2"
241 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
242 (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v")))
243 (clobber (reg:CC CC_REGNUM))]
244 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
245 "cfneg64%?\\t%V0, %V1"
246 [(set_attr "cirrus" "normal")]
247 )
248
249 (define_insn "*cirrus_negsi2"
250 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
251 (neg:SI (match_operand:SI 1 "cirrus_fp_register" "v")))]
252 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
253 "cfneg32%?\\t%V0, %V1"
254 [(set_attr "cirrus" "normal")]
255 )
256
257 (define_insn "*cirrus_negsf2"
258 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
259 (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
260 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
261 "cfnegs%?\\t%V0, %V1"
262 [(set_attr "cirrus" "normal")]
263 )
264
265 (define_insn "*cirrus_negdf2"
266 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
267 (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
268 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
269 "cfnegd%?\\t%V0, %V1"
270 [(set_attr "cirrus" "normal")]
271 )
272
273 ;; This doesn't really clobber the condition codes either.
274 (define_insn "*cirrus_abssi2"
275 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
276 (abs:SI (match_operand:SI 1 "cirrus_fp_register" "v")))
277 (clobber (reg:CC CC_REGNUM))]
278 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
279 "cfabs32%?\\t%V0, %V1"
280 [(set_attr "cirrus" "normal")]
281 )
282
283 (define_insn "*cirrus_abssf2"
284 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
285 (abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
286 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
287 "cfabss%?\\t%V0, %V1"
288 [(set_attr "cirrus" "normal")]
289 )
290
291 (define_insn "*cirrus_absdf2"
292 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
293 (abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
294 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
295 "cfabsd%?\\t%V0, %V1"
296 [(set_attr "cirrus" "normal")]
297 )
298
299 ;; Convert Cirrus-SI to Cirrus-SF
300 (define_insn "cirrus_floatsisf2"
301 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
302 (float:SF (match_operand:SI 1 "s_register_operand" "r")))
303 (clobber (match_scratch:DF 2 "=v"))]
304 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
305 "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
306 [(set_attr "length" "8")
307 (set_attr "cirrus" "move")]
308 )
309
310 (define_insn "cirrus_floatsidf2"
311 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
312 (float:DF (match_operand:SI 1 "s_register_operand" "r")))
313 (clobber (match_scratch:DF 2 "=v"))]
314 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
315 "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
316 [(set_attr "length" "8")
317 (set_attr "cirrus" "move")]
318 )
319
320 (define_insn "floatdisf2"
321 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
322 (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
323 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
324 "cfcvt64s%?\\t%V0, %V1"
325 [(set_attr "cirrus" "normal")])
326
327 (define_insn "floatdidf2"
328 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
329 (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
330 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
331 "cfcvt64d%?\\t%V0, %V1"
332 [(set_attr "cirrus" "normal")])
333
334 (define_insn "cirrus_truncsfsi2"
335 [(set (match_operand:SI 0 "s_register_operand" "=r")
336 (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v"))))
337 (clobber (match_scratch:DF 2 "=v"))]
338 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
339 "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
340 [(set_attr "length" "8")
341 (set_attr "cirrus" "normal")]
342 )
343
344 (define_insn "cirrus_truncdfsi2"
345 [(set (match_operand:SI 0 "s_register_operand" "=r")
346 (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v"))))
347 (clobber (match_scratch:DF 2 "=v"))]
348 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
349 "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
350 [(set_attr "length" "8")]
351 )
352
353 (define_insn "*cirrus_truncdfsf2"
354 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
355 (float_truncate:SF
356 (match_operand:DF 1 "cirrus_fp_register" "v")))]
357 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
358 "cfcvtds%?\\t%V0, %V1"
359 [(set_attr "cirrus" "normal")]
360 )
361
362 (define_insn "*cirrus_extendsfdf2"
363 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
364 (float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))]
365 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
366 "cfcvtsd%?\\t%V0, %V1"
367 [(set_attr "cirrus" "normal")]
368 )
369
370 (define_insn "*cirrus_arm_movdi"
371 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
372 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))]
373 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
374 "*
375 {
376 switch (which_alternative)
377 {
378 case 0:
379 return \"#\";
380 case 1:
381 case 2:
382 return output_move_double (operands);
383
384 case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\";
385 case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\";
386
387 case 5: return \"cfldr64%?\\t%V0, %1\";
388 case 6: return \"cfstr64%?\\t%V1, %0\";
389
390 /* Shifting by 0 will just copy %1 into %0. */
391 case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
392
393 default: gcc_unreachable ();
394 }
395 }"
396 [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4")
397 (set_attr "type" " *,load2,store2, *, *, load2,store2, *")
398 (set_attr "pool_range" " *,1020, *, *, *, 1020, *, *")
399 (set_attr "neg_pool_range" " *,1012, *, *, *, 1008, *, *")
400 (set_attr "cirrus" "not, not, not,move,normal,double,double,normal")]
401 )
402
403 ;; Cirrus SI values have been outlawed. Look in arm.h for the comment
404 ;; on HARD_REGNO_MODE_OK.
405
406 (define_insn "*cirrus_movsf_hard_insn"
407 [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
408 (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))]
409 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK
410 && (GET_CODE (operands[0]) != MEM
411 || register_operand (operands[1], SFmode))"
412 "@
413 cfcpys%?\\t%V0, %V1
414 cfldrs%?\\t%V0, %1
415 cfmvsr%?\\t%V0, %1
416 cfmvrs%?\\t%0, %V1
417 cfstrs%?\\t%V1, %0
418 mov%?\\t%0, %1
419 ldr%?\\t%0, %1\\t%@ float
420 str%?\\t%1, %0\\t%@ float"
421 [(set_attr "length" " *, *, *, *, *, 4, 4, 4")
422 (set_attr "type" " *, load1, *, *,store1, *,load1,store1")
423 (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *")
424 (set_attr "neg_pool_range" " *, 1008, *, *, *, *,4084, *")
425 (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")]
426 )
427
428 (define_insn "*cirrus_movdf_hard_insn"
429 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
430 (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))]
431 "TARGET_ARM
432 && TARGET_HARD_FLOAT && TARGET_MAVERICK
433 && (GET_CODE (operands[0]) != MEM
434 || register_operand (operands[1], DFmode))"
435 "*
436 {
437 switch (which_alternative)
438 {
439 case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
440 case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
441 case 2: return \"#\";
442 case 3: case 4: return output_move_double (operands);
443 case 5: return \"cfcpyd%?\\t%V0, %V1\";
444 case 6: return \"cfldrd%?\\t%V0, %1\";
445 case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
446 case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
447 case 9: return \"cfstrd%?\\t%V1, %0\";
448 default: gcc_unreachable ();
449 }
450 }"
451 [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2")
452 (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4")
453 (set_attr "pool_range" " *, *, *, *, 252, *, 1020, *, *, *")
454 (set_attr "neg_pool_range" " *, *, *, *, 244, *, 1008, *, *, *")
455 (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")]
456 )
457
458 (define_insn "*cirrus_thumb2_movdi"
459 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
460 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))]
461 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK"
462 "*
463 {
464 switch (which_alternative)
465 {
466 case 0:
467 case 1:
468 case 2:
469 return (output_move_double (operands));
470
471 case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\";
472 case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\";
473
474 case 5: return \"cfldr64%?\\t%V0, %1\";
475 case 6: return \"cfstr64%?\\t%V1, %0\";
476
477 /* Shifting by 0 will just copy %1 into %0. */
478 case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
479
480 default: abort ();
481 }
482 }"
483 [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4")
484 (set_attr "type" " *,load2,store2, *, *, load2,store2, *")
485 (set_attr "pool_range" " *,4096, *, *, *, 1020, *, *")
486 (set_attr "neg_pool_range" " *, 0, *, *, *, 1008, *, *")
487 (set_attr "cirrus" "not, not, not,move,normal,double,double,normal")]
488 )
489
490 (define_insn "*thumb2_cirrus_movsf_hard_insn"
491 [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
492 (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))]
493 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK
494 && (GET_CODE (operands[0]) != MEM
495 || register_operand (operands[1], SFmode))"
496 "@
497 cfcpys%?\\t%V0, %V1
498 cfldrs%?\\t%V0, %1
499 cfmvsr%?\\t%V0, %1
500 cfmvrs%?\\t%0, %V1
501 cfstrs%?\\t%V1, %0
502 mov%?\\t%0, %1
503 ldr%?\\t%0, %1\\t%@ float
504 str%?\\t%1, %0\\t%@ float"
505 [(set_attr "length" " *, *, *, *, *, 4, 4, 4")
506 (set_attr "type" " *, load1, *, *,store1, *,load1,store1")
507 (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *")
508 (set_attr "neg_pool_range" " *, 1008, *, *, *, *, 0, *")
509 (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")]
510 )
511
512 (define_insn "*thumb2_cirrus_movdf_hard_insn"
513 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
514 (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))]
515 "TARGET_THUMB2
516 && TARGET_HARD_FLOAT && TARGET_MAVERICK
517 && (GET_CODE (operands[0]) != MEM
518 || register_operand (operands[1], DFmode))"
519 "*
520 {
521 switch (which_alternative)
522 {
523 case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
524 case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
525 case 2: case 3: case 4: return output_move_double (operands);
526 case 5: return \"cfcpyd%?\\t%V0, %V1\";
527 case 6: return \"cfldrd%?\\t%V0, %1\";
528 case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
529 case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
530 case 9: return \"cfstrd%?\\t%V1, %0\";
531 default: abort ();
532 }
533 }"
534 [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2")
535 (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4")
536 (set_attr "pool_range" " *, *, *, *,4092, *, 1020, *, *, *")
537 (set_attr "neg_pool_range" " *, *, *, *, 0, *, 1008, *, *, *")
538 (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")]
539 )
540