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comparison gcc/config/arm/cortex-a8.md @ 0:a06113de4d67
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author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
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date | Fri, 17 Jul 2009 14:47:48 +0900 |
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children | f6334be47118 |
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1 ;; ARM Cortex-A8 scheduling description. | |
2 ;; Copyright (C) 2007 Free Software Foundation, Inc. | |
3 ;; Contributed by CodeSourcery. | |
4 | |
5 ;; This file is part of GCC. | |
6 | |
7 ;; GCC is free software; you can redistribute it and/or modify it | |
8 ;; under the terms of the GNU General Public License as published | |
9 ;; by the Free Software Foundation; either version 3, or (at your | |
10 ;; option) any later version. | |
11 | |
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 ;; License for more details. | |
16 | |
17 ;; You should have received a copy of the GNU General Public License | |
18 ;; along with GCC; see the file COPYING3. If not see | |
19 ;; <http://www.gnu.org/licenses/>. | |
20 | |
21 (define_automaton "cortex_a8") | |
22 | |
23 ;; Only one load/store instruction can be issued per cycle | |
24 ;; (although reservation of this unit is only required for single | |
25 ;; loads and stores -- see below). | |
26 (define_cpu_unit "cortex_a8_issue_ls" "cortex_a8") | |
27 | |
28 ;; Only one branch instruction can be issued per cycle. | |
29 (define_cpu_unit "cortex_a8_issue_branch" "cortex_a8") | |
30 | |
31 ;; The two ALU pipelines. | |
32 (define_cpu_unit "cortex_a8_alu0" "cortex_a8") | |
33 (define_cpu_unit "cortex_a8_alu1" "cortex_a8") | |
34 | |
35 ;; The usual flow of an instruction through the pipelines. | |
36 (define_reservation "cortex_a8_default" | |
37 "cortex_a8_alu0|cortex_a8_alu1") | |
38 | |
39 ;; The flow of a branch instruction through the pipelines. | |
40 (define_reservation "cortex_a8_branch" | |
41 "(cortex_a8_alu0+cortex_a8_issue_branch)|\ | |
42 (cortex_a8_alu1+cortex_a8_issue_branch)") | |
43 | |
44 ;; The flow of a load or store instruction through the pipeline in | |
45 ;; the case where that instruction consists of only one micro-op... | |
46 (define_reservation "cortex_a8_load_store_1" | |
47 "(cortex_a8_alu0+cortex_a8_issue_ls)|\ | |
48 (cortex_a8_alu1+cortex_a8_issue_ls)") | |
49 | |
50 ;; ...and in the case of two micro-ops. We don't need to reserve | |
51 ;; cortex_a8_issue_ls here because dual issue is altogether forbidden | |
52 ;; during the issue cycle of the first micro-op. (Instead of modelling | |
53 ;; a separate issue unit, we instead reserve alu0 and alu1 to | |
54 ;; prevent any other instructions from being issued upon that first cycle.) | |
55 ;; Even though the load/store pipeline is usually available in either | |
56 ;; ALU pipe, multi-cycle instructions always issue in pipeline 0. This | |
57 ;; reservation is therefore the same as cortex_a8_multiply_2 below. | |
58 (define_reservation "cortex_a8_load_store_2" | |
59 "cortex_a8_alu0+cortex_a8_alu1,\ | |
60 cortex_a8_alu0") | |
61 | |
62 ;; The flow of a single-cycle multiplication. | |
63 (define_reservation "cortex_a8_multiply" | |
64 "cortex_a8_alu0") | |
65 | |
66 ;; The flow of a multiplication instruction that gets decomposed into | |
67 ;; two micro-ops. The two micro-ops will be issued to pipeline 0 on | |
68 ;; successive cycles. Dual issue cannot happen at the same time as the | |
69 ;; first of the micro-ops. | |
70 (define_reservation "cortex_a8_multiply_2" | |
71 "cortex_a8_alu0+cortex_a8_alu1,\ | |
72 cortex_a8_alu0") | |
73 | |
74 ;; Similarly, the flow of a multiplication instruction that gets | |
75 ;; decomposed into three micro-ops. Dual issue cannot occur except on | |
76 ;; the cycle upon which the third micro-op is issued. | |
77 (define_reservation "cortex_a8_multiply_3" | |
78 "cortex_a8_alu0+cortex_a8_alu1,\ | |
79 cortex_a8_alu0+cortex_a8_alu1,\ | |
80 cortex_a8_alu0") | |
81 | |
82 ;; The model given here assumes that all instructions are unconditional. | |
83 | |
84 ;; Data processing instructions, but not move instructions. | |
85 | |
86 ;; We include CLZ with these since it has the same execution pattern | |
87 ;; (source read in E2 and destination available at the end of that cycle). | |
88 (define_insn_reservation "cortex_a8_alu" 2 | |
89 (and (eq_attr "tune" "cortexa8") | |
90 (ior (and (eq_attr "type" "alu") | |
91 (not (eq_attr "insn" "mov,mvn"))) | |
92 (eq_attr "insn" "clz"))) | |
93 "cortex_a8_default") | |
94 | |
95 (define_insn_reservation "cortex_a8_alu_shift" 2 | |
96 (and (eq_attr "tune" "cortexa8") | |
97 (and (eq_attr "type" "alu_shift") | |
98 (not (eq_attr "insn" "mov,mvn")))) | |
99 "cortex_a8_default") | |
100 | |
101 (define_insn_reservation "cortex_a8_alu_shift_reg" 2 | |
102 (and (eq_attr "tune" "cortexa8") | |
103 (and (eq_attr "type" "alu_shift_reg") | |
104 (not (eq_attr "insn" "mov,mvn")))) | |
105 "cortex_a8_default") | |
106 | |
107 ;; Move instructions. | |
108 | |
109 (define_insn_reservation "cortex_a8_mov" 1 | |
110 (and (eq_attr "tune" "cortexa8") | |
111 (and (eq_attr "type" "alu,alu_shift,alu_shift_reg") | |
112 (eq_attr "insn" "mov,mvn"))) | |
113 "cortex_a8_default") | |
114 | |
115 ;; Exceptions to the default latencies for data processing instructions. | |
116 | |
117 ;; A move followed by an ALU instruction with no early dep. | |
118 ;; (Such a pair can be issued in parallel, hence latency zero.) | |
119 (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu") | |
120 (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu_shift" | |
121 "arm_no_early_alu_shift_dep") | |
122 (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu_shift_reg" | |
123 "arm_no_early_alu_shift_value_dep") | |
124 | |
125 ;; An ALU instruction followed by an ALU instruction with no early dep. | |
126 (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg" | |
127 "cortex_a8_alu") | |
128 (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg" | |
129 "cortex_a8_alu_shift" | |
130 "arm_no_early_alu_shift_dep") | |
131 (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg" | |
132 "cortex_a8_alu_shift_reg" | |
133 "arm_no_early_alu_shift_value_dep") | |
134 | |
135 ;; Multiplication instructions. These are categorized according to their | |
136 ;; reservation behavior and the need below to distinguish certain | |
137 ;; varieties for bypasses. Results are available at the E5 stage | |
138 ;; (but some of these are multi-cycle instructions which explains the | |
139 ;; latencies below). | |
140 | |
141 (define_insn_reservation "cortex_a8_mul" 6 | |
142 (and (eq_attr "tune" "cortexa8") | |
143 (eq_attr "insn" "mul,smulxy,smmul")) | |
144 "cortex_a8_multiply_2") | |
145 | |
146 (define_insn_reservation "cortex_a8_mla" 6 | |
147 (and (eq_attr "tune" "cortexa8") | |
148 (eq_attr "insn" "mla,smlaxy,smlawy,smmla,smlad,smlsd")) | |
149 "cortex_a8_multiply_2") | |
150 | |
151 (define_insn_reservation "cortex_a8_mull" 7 | |
152 (and (eq_attr "tune" "cortexa8") | |
153 (eq_attr "insn" "smull,umull,smlal,umlal,umaal,smlalxy")) | |
154 "cortex_a8_multiply_3") | |
155 | |
156 (define_insn_reservation "cortex_a8_smulwy" 5 | |
157 (and (eq_attr "tune" "cortexa8") | |
158 (eq_attr "insn" "smulwy,smuad,smusd")) | |
159 "cortex_a8_multiply") | |
160 | |
161 ;; smlald and smlsld are multiply-accumulate instructions but do not | |
162 ;; received bypassed data from other multiplication results; thus, they | |
163 ;; cannot go in cortex_a8_mla above. (See below for bypass details.) | |
164 (define_insn_reservation "cortex_a8_smlald" 6 | |
165 (and (eq_attr "tune" "cortexa8") | |
166 (eq_attr "insn" "smlald,smlsld")) | |
167 "cortex_a8_multiply_2") | |
168 | |
169 ;; A multiply with a single-register result or an MLA, followed by an | |
170 ;; MLA with an accumulator dependency, has its result forwarded so two | |
171 ;; such instructions can issue back-to-back. | |
172 (define_bypass 1 "cortex_a8_mul,cortex_a8_mla,cortex_a8_smulwy" | |
173 "cortex_a8_mla" | |
174 "arm_mac_accumulator_is_mul_result") | |
175 | |
176 ;; A multiply followed by an ALU instruction needing the multiply | |
177 ;; result only at E2 has lower latency than one needing it at E1. | |
178 (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\ | |
179 cortex_a8_smulwy,cortex_a8_smlald" | |
180 "cortex_a8_alu") | |
181 (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\ | |
182 cortex_a8_smulwy,cortex_a8_smlald" | |
183 "cortex_a8_alu_shift" | |
184 "arm_no_early_alu_shift_dep") | |
185 (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\ | |
186 cortex_a8_smulwy,cortex_a8_smlald" | |
187 "cortex_a8_alu_shift_reg" | |
188 "arm_no_early_alu_shift_value_dep") | |
189 | |
190 ;; Load instructions. | |
191 ;; The presence of any register writeback is ignored here. | |
192 | |
193 ;; A load result has latency 3 unless the dependent instruction has | |
194 ;; no early dep, in which case it is only latency two. | |
195 ;; We assume 64-bit alignment for doubleword loads. | |
196 (define_insn_reservation "cortex_a8_load1_2" 3 | |
197 (and (eq_attr "tune" "cortexa8") | |
198 (eq_attr "type" "load1,load2,load_byte")) | |
199 "cortex_a8_load_store_1") | |
200 | |
201 (define_bypass 2 "cortex_a8_load1_2" | |
202 "cortex_a8_alu") | |
203 (define_bypass 2 "cortex_a8_load1_2" | |
204 "cortex_a8_alu_shift" | |
205 "arm_no_early_alu_shift_dep") | |
206 (define_bypass 2 "cortex_a8_load1_2" | |
207 "cortex_a8_alu_shift_reg" | |
208 "arm_no_early_alu_shift_value_dep") | |
209 | |
210 ;; We do not currently model the fact that loads with scaled register | |
211 ;; offsets that are not LSL #2 have an extra cycle latency (they issue | |
212 ;; as two micro-ops). | |
213 | |
214 ;; A load multiple of three registers is usually issued as two micro-ops. | |
215 ;; The first register will be available at E3 of the first iteration, | |
216 ;; the second at E3 of the second iteration, and the third at E4 of | |
217 ;; the second iteration. A load multiple of four registers is usually | |
218 ;; issued as two micro-ops. | |
219 (define_insn_reservation "cortex_a8_load3_4" 5 | |
220 (and (eq_attr "tune" "cortexa8") | |
221 (eq_attr "type" "load3,load4")) | |
222 "cortex_a8_load_store_2") | |
223 | |
224 (define_bypass 4 "cortex_a8_load3_4" | |
225 "cortex_a8_alu") | |
226 (define_bypass 4 "cortex_a8_load3_4" | |
227 "cortex_a8_alu_shift" | |
228 "arm_no_early_alu_shift_dep") | |
229 (define_bypass 4 "cortex_a8_load3_4" | |
230 "cortex_a8_alu_shift_reg" | |
231 "arm_no_early_alu_shift_value_dep") | |
232 | |
233 ;; Store instructions. | |
234 ;; Writeback is again ignored. | |
235 | |
236 (define_insn_reservation "cortex_a8_store1_2" 0 | |
237 (and (eq_attr "tune" "cortexa8") | |
238 (eq_attr "type" "store1,store2")) | |
239 "cortex_a8_load_store_1") | |
240 | |
241 (define_insn_reservation "cortex_a8_store3_4" 0 | |
242 (and (eq_attr "tune" "cortexa8") | |
243 (eq_attr "type" "store3,store4")) | |
244 "cortex_a8_load_store_2") | |
245 | |
246 ;; An ALU instruction acting as a producer for a store instruction | |
247 ;; that only uses the result as the value to be stored (as opposed to | |
248 ;; using it to calculate the address) has latency zero; the store | |
249 ;; reads the value to be stored at the start of E3 and the ALU insn | |
250 ;; writes it at the end of E2. Move instructions actually produce the | |
251 ;; result at the end of E1, but since we don't have delay slots, the | |
252 ;; scheduling behavior will be the same. | |
253 (define_bypass 0 "cortex_a8_alu,cortex_a8_alu_shift,\ | |
254 cortex_a8_alu_shift_reg,cortex_a8_mov" | |
255 "cortex_a8_store1_2,cortex_a8_store3_4" | |
256 "arm_no_early_store_addr_dep") | |
257 | |
258 ;; Branch instructions | |
259 | |
260 (define_insn_reservation "cortex_a8_branch" 0 | |
261 (and (eq_attr "tune" "cortexa8") | |
262 (eq_attr "type" "branch")) | |
263 "cortex_a8_branch") | |
264 | |
265 ;; Call latencies are not predictable. A semi-arbitrary very large | |
266 ;; number is used as "positive infinity" so that everything should be | |
267 ;; finished by the time of return. | |
268 (define_insn_reservation "cortex_a8_call" 32 | |
269 (and (eq_attr "tune" "cortexa8") | |
270 (eq_attr "type" "call")) | |
271 "cortex_a8_issue_branch") | |
272 | |
273 ;; NEON (including VFP) instructions. | |
274 | |
275 (include "cortex-a8-neon.md") | |
276 |