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comparison gcc/config/arm/cortex-r4f.md @ 0:a06113de4d67

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author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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1 ;; ARM Cortex-R4F VFP pipeline description
2 ;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20
21 ;; With the exception of simple VMOV <freg>, <freg> instructions and
22 ;; the accululate operand of a multiply-accumulate instruction, all
23 ;; registers are early registers. Thus base latencies are 1 more than
24 ;; those listed in the TRM.
25
26 ;; We use the A, B abd C units from the integer core, plus two additional
27 ;; units to enforce VFP dual issue constraints.
28
29 ;; A B C V1 VMLA
30 ;; fcpy 1 2
31 ;; farith 1 2 1
32 ;; fmrc 1 2
33 ;; fconst 1 2 * *
34 ;; ffarith 1 2 * *
35 ;; fmac 1 2 1 2
36 ;; fdiv 1 2 *
37 ;; f_loads * * *
38 ;; f_stores * * *
39
40 (define_cpu_unit "cortex_r4_v1" "cortex_r4")
41
42 (define_cpu_unit "cortex_r4_vmla" "cortex_r4")
43
44 (define_reservation "cortex_r4_issue_ab"
45 "(cortex_r4_issue_a|cortex_r4_issue_b)")
46 (define_reservation "cortex_r4_single_issue"
47 "cortex_r4_issue_a+cortex_r4_issue_b")
48
49 (define_insn_reservation "cortex_r4_fcpys" 2
50 (and (eq_attr "tune_cortexr4" "yes")
51 (eq_attr "type" "fcpys"))
52 "cortex_r4_issue_ab")
53
54 (define_insn_reservation "cortex_r4_ffariths" 2
55 (and (eq_attr "tune_cortexr4" "yes")
56 (eq_attr "type" "ffariths,fconsts,fcmps"))
57 "cortex_r4_issue_ab+cortex_r4_issue_c+cortex_r4_v1")
58
59 (define_insn_reservation "cortex_r4_fariths" 3
60 (and (eq_attr "tune_cortexr4" "yes")
61 (eq_attr "type" "fadds,fmuls"))
62 "(cortex_r4_issue_a+cortex_r4_v1)|cortex_r4_issue_b")
63
64 (define_insn_reservation "cortex_r4_fmacs" 6
65 (and (eq_attr "tune_cortexr4" "yes")
66 (eq_attr "type" "fmacs"))
67 "(cortex_r4_issue_a+cortex_r4_v1)|(cortex_r4_issue_b+cortex_r4_vmla)")
68
69 (define_insn_reservation "cortex_r4_fdivs" 17
70 (and (eq_attr "tune_cortexr4" "yes")
71 (eq_attr "type" "fdivs"))
72 "cortex_r4_issue_ab+cortex_r4_v1,cortex_r4_issue_a+cortex_r4_v1")
73
74 (define_insn_reservation "cortex_r4_floads" 2
75 (and (eq_attr "tune_cortexr4" "yes")
76 (eq_attr "type" "f_loads"))
77 "cortex_r4_issue_a+cortex_r4_issue_c+cortex_r4_v1")
78
79 (define_insn_reservation "cortex_r4_fstores" 1
80 (and (eq_attr "tune_cortexr4" "yes")
81 (eq_attr "type" "f_stores"))
82 "cortex_r4_issue_a+cortex_r4_issue_c+cortex_r4_vmla")
83
84 (define_insn_reservation "cortex_r4_mcr" 2
85 (and (eq_attr "tune_cortexr4" "yes")
86 (eq_attr "type" "r_2_f"))
87 "cortex_r4_issue_ab")
88
89 (define_insn_reservation "cortex_r4_mrc" 3
90 (and (eq_attr "tune_cortexr4" "yes")
91 (eq_attr "type" "f_2_r"))
92 "cortex_r4_issue_ab")
93
94 ;; Bypasses for normal (not early) regs.
95 (define_bypass 1 "cortex_r4_ffariths,cortex_r4_fcpys,cortex_r4_mcr"
96 "cortex_r4_fcpys")
97 (define_bypass 2 "cortex_r4_fariths"
98 "cortex_r4_fcpys")
99 (define_bypass 5 "cortex_r4_fmacs"
100 "cortex_r4_fcpys")
101 (define_bypass 16 "cortex_r4_fdivs"
102 "cortex_r4_fcpys")
103
104 (define_bypass 1 "cortex_r4_ffariths,cortex_r4_fcpys,cortex_r4_mcr"
105 "cortex_r4_fmacs"
106 "arm_no_early_mul_dep")
107 (define_bypass 2 "cortex_r4_fariths"
108 "cortex_r4_fmacs"
109 "arm_no_early_mul_dep")
110 ;; mac->mac has an extra forwarding path.
111 (define_bypass 3 "cortex_r4_fmacs"
112 "cortex_r4_fmacs"
113 "arm_no_early_mul_dep")
114 (define_bypass 16 "cortex_r4_fdivs"
115 "cortex_r4_fmacs"
116 "arm_no_early_mul_dep")
117
118 ;; Double precision operations. These can not dual issue.
119
120 (define_insn_reservation "cortex_r4_fmacd" 20
121 (and (eq_attr "tune_cortexr4" "yes")
122 (eq_attr "type" "fmacd"))
123 "cortex_r4_single_issue*13")
124
125 (define_insn_reservation "cortex_r4_farith" 10
126 (and (eq_attr "tune_cortexr4" "yes")
127 (eq_attr "type" "faddd,fmuld"))
128 "cortex_r4_single_issue*3")
129
130 ;; FIXME: The short cycle count suggests these instructions complete
131 ;; out of order. Chances are this is not a pipelined operation.
132 (define_insn_reservation "cortex_r4_fdivd" 97
133 (and (eq_attr "tune_cortexr4" "yes")
134 (eq_attr "type" "fdivd"))
135 "cortex_r4_single_issue*3")
136
137 (define_insn_reservation "cortex_r4_ffarithd" 2
138 (and (eq_attr "tune_cortexr4" "yes")
139 (eq_attr "type" "ffarithd,fconstd"))
140 "cortex_r4_single_issue")
141
142 (define_insn_reservation "cortex_r4_fcmpd" 2
143 (and (eq_attr "tune_cortexr4" "yes")
144 (eq_attr "type" "fcmpd"))
145 "cortex_r4_single_issue*2")
146
147 (define_insn_reservation "cortex_r4_f_cvt" 8
148 (and (eq_attr "tune_cortexr4" "yes")
149 (eq_attr "type" "f_cvt"))
150 "cortex_r4_single_issue*3")
151
152 (define_insn_reservation "cortex_r4_f_memd" 8
153 (and (eq_attr "tune_cortexr4" "yes")
154 (eq_attr "type" "f_loadd,f_stored"))
155 "cortex_r4_single_issue")
156
157 (define_insn_reservation "cortex_r4_f_flag" 1
158 (and (eq_attr "tune_cortexr4" "yes")
159 (eq_attr "type" "f_stores"))
160 "cortex_r4_single_issue")
161