Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/i386/constraints.md @ 0:a06113de4d67
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author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
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date | Fri, 17 Jul 2009 14:47:48 +0900 |
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children | 58ad6c70ea60 |
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1 ;; Constraint definitions for IA-32 and x86-64. | |
2 ;; Copyright (C) 2006, 2007 Free Software Foundation, Inc. | |
3 ;; | |
4 ;; This file is part of GCC. | |
5 ;; | |
6 ;; GCC is free software; you can redistribute it and/or modify | |
7 ;; it under the terms of the GNU General Public License as published by | |
8 ;; the Free Software Foundation; either version 3, or (at your option) | |
9 ;; any later version. | |
10 ;; | |
11 ;; GCC is distributed in the hope that it will be useful, | |
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 ;; GNU General Public License for more details. | |
15 ;; | |
16 ;; You should have received a copy of the GNU General Public License | |
17 ;; along with GCC; see the file COPYING3. If not see | |
18 ;; <http://www.gnu.org/licenses/>. | |
19 | |
20 ;;; Unused letters: | |
21 ;;; B H TU W | |
22 ;;; h jk vw z | |
23 | |
24 ;; Integer register constraints. | |
25 ;; It is not necessary to define 'r' here. | |
26 (define_register_constraint "R" "LEGACY_REGS" | |
27 "Legacy register---the eight integer registers available on all | |
28 i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, | |
29 @code{si}, @code{di}, @code{bp}, @code{sp}).") | |
30 | |
31 (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS" | |
32 "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, | |
33 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.") | |
34 | |
35 (define_register_constraint "Q" "Q_REGS" | |
36 "Any register accessible as @code{@var{r}h}: @code{a}, @code{b}, | |
37 @code{c}, and @code{d}.") | |
38 | |
39 (define_register_constraint "l" "INDEX_REGS" | |
40 "@internal Any register that can be used as the index in a base+index | |
41 memory access: that is, any general register except the stack pointer.") | |
42 | |
43 (define_register_constraint "a" "AREG" | |
44 "The @code{a} register.") | |
45 | |
46 (define_register_constraint "b" "BREG" | |
47 "The @code{b} register.") | |
48 | |
49 (define_register_constraint "c" "CREG" | |
50 "The @code{c} register.") | |
51 | |
52 (define_register_constraint "d" "DREG" | |
53 "The @code{d} register.") | |
54 | |
55 (define_register_constraint "S" "SIREG" | |
56 "The @code{si} register.") | |
57 | |
58 (define_register_constraint "D" "DIREG" | |
59 "The @code{di} register.") | |
60 | |
61 (define_register_constraint "A" "AD_REGS" | |
62 "The @code{a} and @code{d} registers, as a pair (for instructions | |
63 that return half the result in one and half in the other).") | |
64 | |
65 ;; Floating-point register constraints. | |
66 (define_register_constraint "f" | |
67 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS" | |
68 "Any 80387 floating-point (stack) register.") | |
69 | |
70 (define_register_constraint "t" | |
71 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS" | |
72 "Top of 80387 floating-point stack (@code{%st(0)}).") | |
73 | |
74 (define_register_constraint "u" | |
75 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS" | |
76 "Second from top of 80387 floating-point stack (@code{%st(1)}).") | |
77 | |
78 ;; Vector registers (also used for plain floating point nowadays). | |
79 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS" | |
80 "Any MMX register.") | |
81 | |
82 (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS" | |
83 "Any SSE register.") | |
84 | |
85 ;; We use the Y prefix to denote any number of conditional register sets: | |
86 ;; z First SSE register. | |
87 ;; 2 SSE2 enabled | |
88 ;; i SSE2 inter-unit moves enabled | |
89 ;; m MMX inter-unit moves enabled | |
90 | |
91 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" | |
92 "First SSE register (@code{%xmm0}).") | |
93 | |
94 (define_register_constraint "Y2" "TARGET_SSE2 ? SSE_REGS : NO_REGS" | |
95 "@internal Any SSE register, when SSE2 is enabled.") | |
96 | |
97 (define_register_constraint "Yi" | |
98 "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES ? SSE_REGS : NO_REGS" | |
99 "@internal Any SSE register, when SSE2 and inter-unit moves are enabled.") | |
100 | |
101 (define_register_constraint "Ym" | |
102 "TARGET_MMX && TARGET_INTER_UNIT_MOVES ? MMX_REGS : NO_REGS" | |
103 "@internal Any MMX register, when inter-unit moves are enabled.") | |
104 | |
105 ;; Integer constant constraints. | |
106 (define_constraint "I" | |
107 "Integer constant in the range 0 @dots{} 31, for 32-bit shifts." | |
108 (and (match_code "const_int") | |
109 (match_test "IN_RANGE (ival, 0, 31)"))) | |
110 | |
111 (define_constraint "J" | |
112 "Integer constant in the range 0 @dots{} 63, for 64-bit shifts." | |
113 (and (match_code "const_int") | |
114 (match_test "IN_RANGE (ival, 0, 63)"))) | |
115 | |
116 (define_constraint "K" | |
117 "Signed 8-bit integer constant." | |
118 (and (match_code "const_int") | |
119 (match_test "IN_RANGE (ival, -128, 127)"))) | |
120 | |
121 (define_constraint "L" | |
122 "@code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move." | |
123 (and (match_code "const_int") | |
124 (match_test "ival == 0xFF || ival == 0xFFFF"))) | |
125 | |
126 (define_constraint "M" | |
127 "0, 1, 2, or 3 (shifts for the @code{lea} instruction)." | |
128 (and (match_code "const_int") | |
129 (match_test "IN_RANGE (ival, 0, 3)"))) | |
130 | |
131 (define_constraint "N" | |
132 "Unsigned 8-bit integer constant (for @code{in} and @code{out} | |
133 instructions)." | |
134 (and (match_code "const_int") | |
135 (match_test "IN_RANGE (ival, 0, 255)"))) | |
136 | |
137 (define_constraint "O" | |
138 "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts." | |
139 (and (match_code "const_int") | |
140 (match_test "IN_RANGE (ival, 0, 127)"))) | |
141 | |
142 ;; Floating-point constant constraints. | |
143 ;; We allow constants even if TARGET_80387 isn't set, because the | |
144 ;; stack register converter may need to load 0.0 into the function | |
145 ;; value register (top of stack). | |
146 (define_constraint "G" | |
147 "Standard 80387 floating point constant." | |
148 (and (match_code "const_double") | |
149 (match_test "standard_80387_constant_p (op)"))) | |
150 | |
151 ;; This can theoretically be any mode's CONST0_RTX. | |
152 (define_constraint "C" | |
153 "Standard SSE floating point constant." | |
154 (match_test "standard_sse_constant_p (op)")) | |
155 | |
156 ;; Constant-or-symbol-reference constraints. | |
157 | |
158 (define_constraint "e" | |
159 "32-bit signed integer constant, or a symbolic reference known | |
160 to fit that range (for immediate operands in sign-extending x86-64 | |
161 instructions)." | |
162 (match_operand 0 "x86_64_immediate_operand")) | |
163 | |
164 (define_constraint "Z" | |
165 "32-bit unsigned integer constant, or a symbolic reference known | |
166 to fit that range (for immediate operands in zero-extending x86-64 | |
167 instructions)." | |
168 (match_operand 0 "x86_64_zext_immediate_operand")) |