Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/m32r/m32r.c @ 0:a06113de4d67
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author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
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date | Fri, 17 Jul 2009 14:47:48 +0900 |
parents | |
children | 77e2b8dfacca |
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1 /* Subroutines used for code generation on the Renesas M32R cpu. | |
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, | |
3 2005, 2007, 2008 Free Software Foundation, Inc. | |
4 | |
5 This file is part of GCC. | |
6 | |
7 GCC is free software; you can redistribute it and/or modify it | |
8 under the terms of the GNU General Public License as published | |
9 by the Free Software Foundation; either version 3, or (at your | |
10 option) any later version. | |
11 | |
12 GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 License for more details. | |
16 | |
17 You should have received a copy of the GNU General Public License | |
18 along with GCC; see the file COPYING3. If not see | |
19 <http://www.gnu.org/licenses/>. */ | |
20 | |
21 #include "config.h" | |
22 #include "system.h" | |
23 #include "coretypes.h" | |
24 #include "tm.h" | |
25 #include "tree.h" | |
26 #include "rtl.h" | |
27 #include "regs.h" | |
28 #include "hard-reg-set.h" | |
29 #include "real.h" | |
30 #include "insn-config.h" | |
31 #include "conditions.h" | |
32 #include "output.h" | |
33 #include "insn-attr.h" | |
34 #include "flags.h" | |
35 #include "expr.h" | |
36 #include "function.h" | |
37 #include "recog.h" | |
38 #include "toplev.h" | |
39 #include "ggc.h" | |
40 #include "integrate.h" | |
41 #include "tm_p.h" | |
42 #include "target.h" | |
43 #include "target-def.h" | |
44 #include "tm-constrs.h" | |
45 | |
46 /* Save the operands last given to a compare for use when we | |
47 generate a scc or bcc insn. */ | |
48 rtx m32r_compare_op0, m32r_compare_op1; | |
49 | |
50 /* Array of valid operand punctuation characters. */ | |
51 char m32r_punct_chars[256]; | |
52 | |
53 /* Selected code model. */ | |
54 enum m32r_model m32r_model = M32R_MODEL_DEFAULT; | |
55 | |
56 /* Selected SDA support. */ | |
57 enum m32r_sdata m32r_sdata = M32R_SDATA_DEFAULT; | |
58 | |
59 /* Machine-specific symbol_ref flags. */ | |
60 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT | |
61 #define SYMBOL_REF_MODEL(X) \ | |
62 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3)) | |
63 | |
64 /* For string literals, etc. */ | |
65 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.') | |
66 | |
67 /* Forward declaration. */ | |
68 static bool m32r_handle_option (size_t, const char *, int); | |
69 static void init_reg_tables (void); | |
70 static void block_move_call (rtx, rtx, rtx); | |
71 static int m32r_is_insn (rtx); | |
72 const struct attribute_spec m32r_attribute_table[]; | |
73 static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *); | |
74 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT); | |
75 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
76 | |
77 static void m32r_file_start (void); | |
78 | |
79 static int m32r_adjust_priority (rtx, int); | |
80 static int m32r_issue_rate (void); | |
81 | |
82 static void m32r_encode_section_info (tree, rtx, int); | |
83 static bool m32r_in_small_data_p (const_tree); | |
84 static bool m32r_return_in_memory (const_tree, const_tree); | |
85 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, | |
86 tree, int *, int); | |
87 static void init_idents (void); | |
88 static bool m32r_rtx_costs (rtx, int, int, int *, bool speed); | |
89 static bool m32r_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, | |
90 const_tree, bool); | |
91 static int m32r_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, | |
92 tree, bool); | |
93 | |
94 /* Initialize the GCC target structure. */ | |
95 #undef TARGET_ATTRIBUTE_TABLE | |
96 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table | |
97 | |
98 #undef TARGET_ASM_ALIGNED_HI_OP | |
99 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
100 #undef TARGET_ASM_ALIGNED_SI_OP | |
101 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
102 | |
103 #undef TARGET_ASM_FUNCTION_PROLOGUE | |
104 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue | |
105 #undef TARGET_ASM_FUNCTION_EPILOGUE | |
106 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue | |
107 | |
108 #undef TARGET_ASM_FILE_START | |
109 #define TARGET_ASM_FILE_START m32r_file_start | |
110 | |
111 #undef TARGET_SCHED_ADJUST_PRIORITY | |
112 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority | |
113 #undef TARGET_SCHED_ISSUE_RATE | |
114 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate | |
115 | |
116 #undef TARGET_DEFAULT_TARGET_FLAGS | |
117 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_CPU_DEFAULT | |
118 #undef TARGET_HANDLE_OPTION | |
119 #define TARGET_HANDLE_OPTION m32r_handle_option | |
120 | |
121 #undef TARGET_ENCODE_SECTION_INFO | |
122 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info | |
123 #undef TARGET_IN_SMALL_DATA_P | |
124 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p | |
125 | |
126 #undef TARGET_RTX_COSTS | |
127 #define TARGET_RTX_COSTS m32r_rtx_costs | |
128 #undef TARGET_ADDRESS_COST | |
129 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0 | |
130 | |
131 #undef TARGET_PROMOTE_PROTOTYPES | |
132 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
133 #undef TARGET_RETURN_IN_MEMORY | |
134 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory | |
135 #undef TARGET_SETUP_INCOMING_VARARGS | |
136 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs | |
137 #undef TARGET_MUST_PASS_IN_STACK | |
138 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
139 #undef TARGET_PASS_BY_REFERENCE | |
140 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference | |
141 #undef TARGET_ARG_PARTIAL_BYTES | |
142 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes | |
143 | |
144 struct gcc_target targetm = TARGET_INITIALIZER; | |
145 | |
146 /* Implement TARGET_HANDLE_OPTION. */ | |
147 | |
148 static bool | |
149 m32r_handle_option (size_t code, const char *arg, int value) | |
150 { | |
151 switch (code) | |
152 { | |
153 case OPT_m32r: | |
154 target_flags &= ~(MASK_M32R2 | MASK_M32RX); | |
155 return true; | |
156 | |
157 case OPT_mmodel_: | |
158 if (strcmp (arg, "small") == 0) | |
159 m32r_model = M32R_MODEL_SMALL; | |
160 else if (strcmp (arg, "medium") == 0) | |
161 m32r_model = M32R_MODEL_MEDIUM; | |
162 else if (strcmp (arg, "large") == 0) | |
163 m32r_model = M32R_MODEL_LARGE; | |
164 else | |
165 return false; | |
166 return true; | |
167 | |
168 case OPT_msdata_: | |
169 if (strcmp (arg, "none") == 0) | |
170 m32r_sdata = M32R_SDATA_NONE; | |
171 else if (strcmp (arg, "sdata") == 0) | |
172 m32r_sdata = M32R_SDATA_SDATA; | |
173 else if (strcmp (arg, "use") == 0) | |
174 m32r_sdata = M32R_SDATA_USE; | |
175 else | |
176 return false; | |
177 return true; | |
178 | |
179 case OPT_mno_flush_func: | |
180 m32r_cache_flush_func = NULL; | |
181 return true; | |
182 | |
183 case OPT_mflush_trap_: | |
184 return value <= 15; | |
185 | |
186 case OPT_mno_flush_trap: | |
187 m32r_cache_flush_trap = -1; | |
188 return true; | |
189 | |
190 default: | |
191 return true; | |
192 } | |
193 } | |
194 | |
195 /* Called by OVERRIDE_OPTIONS to initialize various things. */ | |
196 | |
197 void | |
198 m32r_init (void) | |
199 { | |
200 init_reg_tables (); | |
201 | |
202 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */ | |
203 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars)); | |
204 m32r_punct_chars['#'] = 1; | |
205 m32r_punct_chars['@'] = 1; /* ??? no longer used */ | |
206 | |
207 /* Provide default value if not specified. */ | |
208 if (!g_switch_set) | |
209 g_switch_value = SDATA_DEFAULT_SIZE; | |
210 } | |
211 | |
212 /* Vectors to keep interesting information about registers where it can easily | |
213 be got. We use to use the actual mode value as the bit number, but there | |
214 is (or may be) more than 32 modes now. Instead we use two tables: one | |
215 indexed by hard register number, and one indexed by mode. */ | |
216 | |
217 /* The purpose of m32r_mode_class is to shrink the range of modes so that | |
218 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is | |
219 mapped into one m32r_mode_class mode. */ | |
220 | |
221 enum m32r_mode_class | |
222 { | |
223 C_MODE, | |
224 S_MODE, D_MODE, T_MODE, O_MODE, | |
225 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE | |
226 }; | |
227 | |
228 /* Modes for condition codes. */ | |
229 #define C_MODES (1 << (int) C_MODE) | |
230 | |
231 /* Modes for single-word and smaller quantities. */ | |
232 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
233 | |
234 /* Modes for double-word and smaller quantities. */ | |
235 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
236 | |
237 /* Modes for quad-word and smaller quantities. */ | |
238 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
239 | |
240 /* Modes for accumulators. */ | |
241 #define A_MODES (1 << (int) A_MODE) | |
242 | |
243 /* Value is 1 if register/mode pair is acceptable on arc. */ | |
244 | |
245 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = | |
246 { | |
247 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, | |
248 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES, | |
249 S_MODES, C_MODES, A_MODES, A_MODES | |
250 }; | |
251 | |
252 unsigned int m32r_mode_class [NUM_MACHINE_MODES]; | |
253 | |
254 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
255 | |
256 static void | |
257 init_reg_tables (void) | |
258 { | |
259 int i; | |
260 | |
261 for (i = 0; i < NUM_MACHINE_MODES; i++) | |
262 { | |
263 switch (GET_MODE_CLASS (i)) | |
264 { | |
265 case MODE_INT: | |
266 case MODE_PARTIAL_INT: | |
267 case MODE_COMPLEX_INT: | |
268 if (GET_MODE_SIZE (i) <= 4) | |
269 m32r_mode_class[i] = 1 << (int) S_MODE; | |
270 else if (GET_MODE_SIZE (i) == 8) | |
271 m32r_mode_class[i] = 1 << (int) D_MODE; | |
272 else if (GET_MODE_SIZE (i) == 16) | |
273 m32r_mode_class[i] = 1 << (int) T_MODE; | |
274 else if (GET_MODE_SIZE (i) == 32) | |
275 m32r_mode_class[i] = 1 << (int) O_MODE; | |
276 else | |
277 m32r_mode_class[i] = 0; | |
278 break; | |
279 case MODE_FLOAT: | |
280 case MODE_COMPLEX_FLOAT: | |
281 if (GET_MODE_SIZE (i) <= 4) | |
282 m32r_mode_class[i] = 1 << (int) SF_MODE; | |
283 else if (GET_MODE_SIZE (i) == 8) | |
284 m32r_mode_class[i] = 1 << (int) DF_MODE; | |
285 else if (GET_MODE_SIZE (i) == 16) | |
286 m32r_mode_class[i] = 1 << (int) TF_MODE; | |
287 else if (GET_MODE_SIZE (i) == 32) | |
288 m32r_mode_class[i] = 1 << (int) OF_MODE; | |
289 else | |
290 m32r_mode_class[i] = 0; | |
291 break; | |
292 case MODE_CC: | |
293 m32r_mode_class[i] = 1 << (int) C_MODE; | |
294 break; | |
295 default: | |
296 m32r_mode_class[i] = 0; | |
297 break; | |
298 } | |
299 } | |
300 | |
301 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
302 { | |
303 if (GPR_P (i)) | |
304 m32r_regno_reg_class[i] = GENERAL_REGS; | |
305 else if (i == ARG_POINTER_REGNUM) | |
306 m32r_regno_reg_class[i] = GENERAL_REGS; | |
307 else | |
308 m32r_regno_reg_class[i] = NO_REGS; | |
309 } | |
310 } | |
311 | |
312 /* M32R specific attribute support. | |
313 | |
314 interrupt - for interrupt functions | |
315 | |
316 model - select code model used to access object | |
317 | |
318 small: addresses use 24 bits, use bl to make calls | |
319 medium: addresses use 32 bits, use bl to make calls | |
320 large: addresses use 32 bits, use seth/add3/jl to make calls | |
321 | |
322 Grep for MODEL in m32r.h for more info. */ | |
323 | |
324 static tree small_ident1; | |
325 static tree small_ident2; | |
326 static tree medium_ident1; | |
327 static tree medium_ident2; | |
328 static tree large_ident1; | |
329 static tree large_ident2; | |
330 | |
331 static void | |
332 init_idents (void) | |
333 { | |
334 if (small_ident1 == 0) | |
335 { | |
336 small_ident1 = get_identifier ("small"); | |
337 small_ident2 = get_identifier ("__small__"); | |
338 medium_ident1 = get_identifier ("medium"); | |
339 medium_ident2 = get_identifier ("__medium__"); | |
340 large_ident1 = get_identifier ("large"); | |
341 large_ident2 = get_identifier ("__large__"); | |
342 } | |
343 } | |
344 | |
345 const struct attribute_spec m32r_attribute_table[] = | |
346 { | |
347 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
348 { "interrupt", 0, 0, true, false, false, NULL }, | |
349 { "model", 1, 1, true, false, false, m32r_handle_model_attribute }, | |
350 { NULL, 0, 0, false, false, false, NULL } | |
351 }; | |
352 | |
353 | |
354 /* Handle an "model" attribute; arguments as in | |
355 struct attribute_spec.handler. */ | |
356 static tree | |
357 m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name, | |
358 tree args, int flags ATTRIBUTE_UNUSED, | |
359 bool *no_add_attrs) | |
360 { | |
361 tree arg; | |
362 | |
363 init_idents (); | |
364 arg = TREE_VALUE (args); | |
365 | |
366 if (arg != small_ident1 | |
367 && arg != small_ident2 | |
368 && arg != medium_ident1 | |
369 && arg != medium_ident2 | |
370 && arg != large_ident1 | |
371 && arg != large_ident2) | |
372 { | |
373 warning (OPT_Wattributes, "invalid argument of %qs attribute", | |
374 IDENTIFIER_POINTER (name)); | |
375 *no_add_attrs = true; | |
376 } | |
377 | |
378 return NULL_TREE; | |
379 } | |
380 | |
381 /* Encode section information of DECL, which is either a VAR_DECL, | |
382 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???. | |
383 | |
384 For the M32R we want to record: | |
385 | |
386 - whether the object lives in .sdata/.sbss. | |
387 - what code model should be used to access the object | |
388 */ | |
389 | |
390 static void | |
391 m32r_encode_section_info (tree decl, rtx rtl, int first) | |
392 { | |
393 int extra_flags = 0; | |
394 tree model_attr; | |
395 enum m32r_model model; | |
396 | |
397 default_encode_section_info (decl, rtl, first); | |
398 | |
399 if (!DECL_P (decl)) | |
400 return; | |
401 | |
402 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl)); | |
403 if (model_attr) | |
404 { | |
405 tree id; | |
406 | |
407 init_idents (); | |
408 | |
409 id = TREE_VALUE (TREE_VALUE (model_attr)); | |
410 | |
411 if (id == small_ident1 || id == small_ident2) | |
412 model = M32R_MODEL_SMALL; | |
413 else if (id == medium_ident1 || id == medium_ident2) | |
414 model = M32R_MODEL_MEDIUM; | |
415 else if (id == large_ident1 || id == large_ident2) | |
416 model = M32R_MODEL_LARGE; | |
417 else | |
418 gcc_unreachable (); /* shouldn't happen */ | |
419 } | |
420 else | |
421 { | |
422 if (TARGET_MODEL_SMALL) | |
423 model = M32R_MODEL_SMALL; | |
424 else if (TARGET_MODEL_MEDIUM) | |
425 model = M32R_MODEL_MEDIUM; | |
426 else if (TARGET_MODEL_LARGE) | |
427 model = M32R_MODEL_LARGE; | |
428 else | |
429 gcc_unreachable (); /* shouldn't happen */ | |
430 } | |
431 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT; | |
432 | |
433 if (extra_flags) | |
434 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags; | |
435 } | |
436 | |
437 /* Only mark the object as being small data area addressable if | |
438 it hasn't been explicitly marked with a code model. | |
439 | |
440 The user can explicitly put an object in the small data area with the | |
441 section attribute. If the object is in sdata/sbss and marked with a | |
442 code model do both [put the object in .sdata and mark it as being | |
443 addressed with a specific code model - don't mark it as being addressed | |
444 with an SDA reloc though]. This is ok and might be useful at times. If | |
445 the object doesn't fit the linker will give an error. */ | |
446 | |
447 static bool | |
448 m32r_in_small_data_p (const_tree decl) | |
449 { | |
450 const_tree section; | |
451 | |
452 if (TREE_CODE (decl) != VAR_DECL) | |
453 return false; | |
454 | |
455 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl))) | |
456 return false; | |
457 | |
458 section = DECL_SECTION_NAME (decl); | |
459 if (section) | |
460 { | |
461 const char *const name = TREE_STRING_POINTER (section); | |
462 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0) | |
463 return true; | |
464 } | |
465 else | |
466 { | |
467 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE) | |
468 { | |
469 int size = int_size_in_bytes (TREE_TYPE (decl)); | |
470 | |
471 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) | |
472 return true; | |
473 } | |
474 } | |
475 | |
476 return false; | |
477 } | |
478 | |
479 /* Do anything needed before RTL is emitted for each function. */ | |
480 | |
481 void | |
482 m32r_init_expanders (void) | |
483 { | |
484 /* ??? At one point there was code here. The function is left in | |
485 to make it easy to experiment. */ | |
486 } | |
487 | |
488 int | |
489 call_operand (rtx op, enum machine_mode mode) | |
490 { | |
491 if (GET_CODE (op) != MEM) | |
492 return 0; | |
493 op = XEXP (op, 0); | |
494 return call_address_operand (op, mode); | |
495 } | |
496 | |
497 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */ | |
498 | |
499 int | |
500 small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
501 { | |
502 if (! TARGET_SDATA_USE) | |
503 return 0; | |
504 | |
505 if (GET_CODE (op) == SYMBOL_REF) | |
506 return SYMBOL_REF_SMALL_P (op); | |
507 | |
508 if (GET_CODE (op) == CONST | |
509 && GET_CODE (XEXP (op, 0)) == PLUS | |
510 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF | |
511 && satisfies_constraint_J (XEXP (XEXP (op, 0), 1))) | |
512 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0)); | |
513 | |
514 return 0; | |
515 } | |
516 | |
517 /* Return 1 if OP is a symbol that can use 24-bit addressing. */ | |
518 | |
519 int | |
520 addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
521 { | |
522 rtx sym; | |
523 | |
524 if (flag_pic) | |
525 return 0; | |
526 | |
527 if (GET_CODE (op) == LABEL_REF) | |
528 return TARGET_ADDR24; | |
529 | |
530 if (GET_CODE (op) == SYMBOL_REF) | |
531 sym = op; | |
532 else if (GET_CODE (op) == CONST | |
533 && GET_CODE (XEXP (op, 0)) == PLUS | |
534 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF | |
535 && satisfies_constraint_M (XEXP (XEXP (op, 0), 1))) | |
536 sym = XEXP (XEXP (op, 0), 0); | |
537 else | |
538 return 0; | |
539 | |
540 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL) | |
541 return 1; | |
542 | |
543 if (TARGET_ADDR24 | |
544 && (CONSTANT_POOL_ADDRESS_P (sym) | |
545 || LIT_NAME_P (XSTR (sym, 0)))) | |
546 return 1; | |
547 | |
548 return 0; | |
549 } | |
550 | |
551 /* Return 1 if OP is a symbol that needs 32-bit addressing. */ | |
552 | |
553 int | |
554 addr32_operand (rtx op, enum machine_mode mode) | |
555 { | |
556 rtx sym; | |
557 | |
558 if (GET_CODE (op) == LABEL_REF) | |
559 return TARGET_ADDR32; | |
560 | |
561 if (GET_CODE (op) == SYMBOL_REF) | |
562 sym = op; | |
563 else if (GET_CODE (op) == CONST | |
564 && GET_CODE (XEXP (op, 0)) == PLUS | |
565 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF | |
566 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT | |
567 && ! flag_pic) | |
568 sym = XEXP (XEXP (op, 0), 0); | |
569 else | |
570 return 0; | |
571 | |
572 return (! addr24_operand (sym, mode) | |
573 && ! small_data_operand (sym, mode)); | |
574 } | |
575 | |
576 /* Return 1 if OP is a function that can be called with the `bl' insn. */ | |
577 | |
578 int | |
579 call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
580 { | |
581 if (flag_pic) | |
582 return 1; | |
583 | |
584 if (GET_CODE (op) == SYMBOL_REF) | |
585 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE; | |
586 | |
587 return TARGET_CALL26; | |
588 } | |
589 | |
590 /* Return 1 if OP is a DImode const we want to handle inline. | |
591 This must match the code in the movdi pattern. | |
592 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */ | |
593 | |
594 int | |
595 easy_di_const (rtx op) | |
596 { | |
597 rtx high_rtx, low_rtx; | |
598 HOST_WIDE_INT high, low; | |
599 | |
600 split_double (op, &high_rtx, &low_rtx); | |
601 high = INTVAL (high_rtx); | |
602 low = INTVAL (low_rtx); | |
603 /* Pick constants loadable with 2 16-bit `ldi' insns. */ | |
604 if (high >= -128 && high <= 127 | |
605 && low >= -128 && low <= 127) | |
606 return 1; | |
607 return 0; | |
608 } | |
609 | |
610 /* Return 1 if OP is a DFmode const we want to handle inline. | |
611 This must match the code in the movdf pattern. | |
612 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */ | |
613 | |
614 int | |
615 easy_df_const (rtx op) | |
616 { | |
617 REAL_VALUE_TYPE r; | |
618 long l[2]; | |
619 | |
620 REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
621 REAL_VALUE_TO_TARGET_DOUBLE (r, l); | |
622 if (l[0] == 0 && l[1] == 0) | |
623 return 1; | |
624 if ((l[0] & 0xffff) == 0 && l[1] == 0) | |
625 return 1; | |
626 return 0; | |
627 } | |
628 | |
629 /* Return 1 if OP is (mem (reg ...)). | |
630 This is used in insn length calcs. */ | |
631 | |
632 int | |
633 memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
634 { | |
635 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG; | |
636 } | |
637 | |
638 /* Return nonzero if TYPE must be passed by indirect reference. */ | |
639 | |
640 static bool | |
641 m32r_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, | |
642 enum machine_mode mode, const_tree type, | |
643 bool named ATTRIBUTE_UNUSED) | |
644 { | |
645 int size; | |
646 | |
647 if (type) | |
648 size = int_size_in_bytes (type); | |
649 else | |
650 size = GET_MODE_SIZE (mode); | |
651 | |
652 return (size < 0 || size > 8); | |
653 } | |
654 | |
655 /* Comparisons. */ | |
656 | |
657 /* X and Y are two things to compare using CODE. Emit the compare insn and | |
658 return the rtx for compare [arg0 of the if_then_else]. | |
659 If need_compare is true then the comparison insn must be generated, rather | |
660 than being subsumed into the following branch instruction. */ | |
661 | |
662 rtx | |
663 gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) | |
664 { | |
665 enum rtx_code compare_code; | |
666 enum rtx_code branch_code; | |
667 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM); | |
668 int must_swap = 0; | |
669 | |
670 switch (code) | |
671 { | |
672 case EQ: compare_code = EQ; branch_code = NE; break; | |
673 case NE: compare_code = EQ; branch_code = EQ; break; | |
674 case LT: compare_code = LT; branch_code = NE; break; | |
675 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break; | |
676 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break; | |
677 case GE: compare_code = LT; branch_code = EQ; break; | |
678 case LTU: compare_code = LTU; branch_code = NE; break; | |
679 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break; | |
680 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break; | |
681 case GEU: compare_code = LTU; branch_code = EQ; break; | |
682 | |
683 default: | |
684 gcc_unreachable (); | |
685 } | |
686 | |
687 if (need_compare) | |
688 { | |
689 switch (compare_code) | |
690 { | |
691 case EQ: | |
692 if (satisfies_constraint_P (y) /* Reg equal to small const. */ | |
693 && y != const0_rtx) | |
694 { | |
695 rtx tmp = gen_reg_rtx (SImode); | |
696 | |
697 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y)))); | |
698 x = tmp; | |
699 y = const0_rtx; | |
700 } | |
701 else if (CONSTANT_P (y)) /* Reg equal to const. */ | |
702 { | |
703 rtx tmp = force_reg (GET_MODE (x), y); | |
704 y = tmp; | |
705 } | |
706 | |
707 if (register_operand (y, SImode) /* Reg equal to reg. */ | |
708 || y == const0_rtx) /* Reg equal to zero. */ | |
709 { | |
710 emit_insn (gen_cmp_eqsi_insn (x, y)); | |
711 | |
712 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx); | |
713 } | |
714 break; | |
715 | |
716 case LT: | |
717 if (register_operand (y, SImode) | |
718 || satisfies_constraint_P (y)) | |
719 { | |
720 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */ | |
721 | |
722 switch (code) | |
723 { | |
724 case LT: | |
725 emit_insn (gen_cmp_ltsi_insn (x, y)); | |
726 code = EQ; | |
727 break; | |
728 case LE: | |
729 if (y == const0_rtx) | |
730 tmp = const1_rtx; | |
731 else | |
732 emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); | |
733 emit_insn (gen_cmp_ltsi_insn (x, tmp)); | |
734 code = EQ; | |
735 break; | |
736 case GT: | |
737 if (GET_CODE (y) == CONST_INT) | |
738 tmp = gen_rtx_PLUS (SImode, y, const1_rtx); | |
739 else | |
740 emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); | |
741 emit_insn (gen_cmp_ltsi_insn (x, tmp)); | |
742 code = NE; | |
743 break; | |
744 case GE: | |
745 emit_insn (gen_cmp_ltsi_insn (x, y)); | |
746 code = NE; | |
747 break; | |
748 default: | |
749 gcc_unreachable (); | |
750 } | |
751 | |
752 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx); | |
753 } | |
754 break; | |
755 | |
756 case LTU: | |
757 if (register_operand (y, SImode) | |
758 || satisfies_constraint_P (y)) | |
759 { | |
760 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */ | |
761 | |
762 switch (code) | |
763 { | |
764 case LTU: | |
765 emit_insn (gen_cmp_ltusi_insn (x, y)); | |
766 code = EQ; | |
767 break; | |
768 case LEU: | |
769 if (y == const0_rtx) | |
770 tmp = const1_rtx; | |
771 else | |
772 emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); | |
773 emit_insn (gen_cmp_ltusi_insn (x, tmp)); | |
774 code = EQ; | |
775 break; | |
776 case GTU: | |
777 if (GET_CODE (y) == CONST_INT) | |
778 tmp = gen_rtx_PLUS (SImode, y, const1_rtx); | |
779 else | |
780 emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); | |
781 emit_insn (gen_cmp_ltusi_insn (x, tmp)); | |
782 code = NE; | |
783 break; | |
784 case GEU: | |
785 emit_insn (gen_cmp_ltusi_insn (x, y)); | |
786 code = NE; | |
787 break; | |
788 default: | |
789 gcc_unreachable (); | |
790 } | |
791 | |
792 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx); | |
793 } | |
794 break; | |
795 | |
796 default: | |
797 gcc_unreachable (); | |
798 } | |
799 } | |
800 else | |
801 { | |
802 /* Reg/reg equal comparison. */ | |
803 if (compare_code == EQ | |
804 && register_operand (y, SImode)) | |
805 return gen_rtx_fmt_ee (code, CCmode, x, y); | |
806 | |
807 /* Reg/zero signed comparison. */ | |
808 if ((compare_code == EQ || compare_code == LT) | |
809 && y == const0_rtx) | |
810 return gen_rtx_fmt_ee (code, CCmode, x, y); | |
811 | |
812 /* Reg/smallconst equal comparison. */ | |
813 if (compare_code == EQ | |
814 && satisfies_constraint_P (y)) | |
815 { | |
816 rtx tmp = gen_reg_rtx (SImode); | |
817 | |
818 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y)))); | |
819 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx); | |
820 } | |
821 | |
822 /* Reg/const equal comparison. */ | |
823 if (compare_code == EQ | |
824 && CONSTANT_P (y)) | |
825 { | |
826 rtx tmp = force_reg (GET_MODE (x), y); | |
827 | |
828 return gen_rtx_fmt_ee (code, CCmode, x, tmp); | |
829 } | |
830 } | |
831 | |
832 if (CONSTANT_P (y)) | |
833 { | |
834 if (must_swap) | |
835 y = force_reg (GET_MODE (x), y); | |
836 else | |
837 { | |
838 int ok_const = reg_or_int16_operand (y, GET_MODE (y)); | |
839 | |
840 if (! ok_const) | |
841 y = force_reg (GET_MODE (x), y); | |
842 } | |
843 } | |
844 | |
845 switch (compare_code) | |
846 { | |
847 case EQ : | |
848 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y)); | |
849 break; | |
850 case LT : | |
851 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y)); | |
852 break; | |
853 case LTU : | |
854 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y)); | |
855 break; | |
856 | |
857 default: | |
858 gcc_unreachable (); | |
859 } | |
860 | |
861 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode)); | |
862 } | |
863 | |
864 /* Split a 2 word move (DI or DF) into component parts. */ | |
865 | |
866 rtx | |
867 gen_split_move_double (rtx operands[]) | |
868 { | |
869 enum machine_mode mode = GET_MODE (operands[0]); | |
870 rtx dest = operands[0]; | |
871 rtx src = operands[1]; | |
872 rtx val; | |
873 | |
874 /* We might have (SUBREG (MEM)) here, so just get rid of the | |
875 subregs to make this code simpler. It is safe to call | |
876 alter_subreg any time after reload. */ | |
877 if (GET_CODE (dest) == SUBREG) | |
878 alter_subreg (&dest); | |
879 if (GET_CODE (src) == SUBREG) | |
880 alter_subreg (&src); | |
881 | |
882 start_sequence (); | |
883 if (GET_CODE (dest) == REG) | |
884 { | |
885 int dregno = REGNO (dest); | |
886 | |
887 /* Reg = reg. */ | |
888 if (GET_CODE (src) == REG) | |
889 { | |
890 int sregno = REGNO (src); | |
891 | |
892 int reverse = (dregno == sregno + 1); | |
893 | |
894 /* We normally copy the low-numbered register first. However, if | |
895 the first register operand 0 is the same as the second register of | |
896 operand 1, we must copy in the opposite order. */ | |
897 emit_insn (gen_rtx_SET (VOIDmode, | |
898 operand_subword (dest, reverse, TRUE, mode), | |
899 operand_subword (src, reverse, TRUE, mode))); | |
900 | |
901 emit_insn (gen_rtx_SET (VOIDmode, | |
902 operand_subword (dest, !reverse, TRUE, mode), | |
903 operand_subword (src, !reverse, TRUE, mode))); | |
904 } | |
905 | |
906 /* Reg = constant. */ | |
907 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE) | |
908 { | |
909 rtx words[2]; | |
910 split_double (src, &words[0], &words[1]); | |
911 emit_insn (gen_rtx_SET (VOIDmode, | |
912 operand_subword (dest, 0, TRUE, mode), | |
913 words[0])); | |
914 | |
915 emit_insn (gen_rtx_SET (VOIDmode, | |
916 operand_subword (dest, 1, TRUE, mode), | |
917 words[1])); | |
918 } | |
919 | |
920 /* Reg = mem. */ | |
921 else if (GET_CODE (src) == MEM) | |
922 { | |
923 /* If the high-address word is used in the address, we must load it | |
924 last. Otherwise, load it first. */ | |
925 int reverse | |
926 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0); | |
927 | |
928 /* We used to optimize loads from single registers as | |
929 | |
930 ld r1,r3+; ld r2,r3 | |
931 | |
932 if r3 were not used subsequently. However, the REG_NOTES aren't | |
933 propagated correctly by the reload phase, and it can cause bad | |
934 code to be generated. We could still try: | |
935 | |
936 ld r1,r3+; ld r2,r3; addi r3,-4 | |
937 | |
938 which saves 2 bytes and doesn't force longword alignment. */ | |
939 emit_insn (gen_rtx_SET (VOIDmode, | |
940 operand_subword (dest, reverse, TRUE, mode), | |
941 adjust_address (src, SImode, | |
942 reverse * UNITS_PER_WORD))); | |
943 | |
944 emit_insn (gen_rtx_SET (VOIDmode, | |
945 operand_subword (dest, !reverse, TRUE, mode), | |
946 adjust_address (src, SImode, | |
947 !reverse * UNITS_PER_WORD))); | |
948 } | |
949 else | |
950 gcc_unreachable (); | |
951 } | |
952 | |
953 /* Mem = reg. */ | |
954 /* We used to optimize loads from single registers as | |
955 | |
956 st r1,r3; st r2,+r3 | |
957 | |
958 if r3 were not used subsequently. However, the REG_NOTES aren't | |
959 propagated correctly by the reload phase, and it can cause bad | |
960 code to be generated. We could still try: | |
961 | |
962 st r1,r3; st r2,+r3; addi r3,-4 | |
963 | |
964 which saves 2 bytes and doesn't force longword alignment. */ | |
965 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG) | |
966 { | |
967 emit_insn (gen_rtx_SET (VOIDmode, | |
968 adjust_address (dest, SImode, 0), | |
969 operand_subword (src, 0, TRUE, mode))); | |
970 | |
971 emit_insn (gen_rtx_SET (VOIDmode, | |
972 adjust_address (dest, SImode, UNITS_PER_WORD), | |
973 operand_subword (src, 1, TRUE, mode))); | |
974 } | |
975 | |
976 else | |
977 gcc_unreachable (); | |
978 | |
979 val = get_insns (); | |
980 end_sequence (); | |
981 return val; | |
982 } | |
983 | |
984 | |
985 static int | |
986 m32r_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
987 tree type, bool named ATTRIBUTE_UNUSED) | |
988 { | |
989 int words; | |
990 unsigned int size = | |
991 (((mode == BLKmode && type) | |
992 ? (unsigned int) int_size_in_bytes (type) | |
993 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1) | |
994 / UNITS_PER_WORD; | |
995 | |
996 if (*cum >= M32R_MAX_PARM_REGS) | |
997 words = 0; | |
998 else if (*cum + size > M32R_MAX_PARM_REGS) | |
999 words = (*cum + size) - M32R_MAX_PARM_REGS; | |
1000 else | |
1001 words = 0; | |
1002 | |
1003 return words * UNITS_PER_WORD; | |
1004 } | |
1005 | |
1006 /* Worker function for TARGET_RETURN_IN_MEMORY. */ | |
1007 | |
1008 static bool | |
1009 m32r_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) | |
1010 { | |
1011 return m32r_pass_by_reference (NULL, TYPE_MODE (type), type, false); | |
1012 } | |
1013 | |
1014 /* Do any needed setup for a variadic function. For the M32R, we must | |
1015 create a register parameter block, and then copy any anonymous arguments | |
1016 in registers to memory. | |
1017 | |
1018 CUM has not been updated for the last named argument which has type TYPE | |
1019 and mode MODE, and we rely on this fact. */ | |
1020 | |
1021 static void | |
1022 m32r_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1023 tree type, int *pretend_size, int no_rtl) | |
1024 { | |
1025 int first_anon_arg; | |
1026 | |
1027 if (no_rtl) | |
1028 return; | |
1029 | |
1030 /* All BLKmode values are passed by reference. */ | |
1031 gcc_assert (mode != BLKmode); | |
1032 | |
1033 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type) | |
1034 + ROUND_ADVANCE_ARG (mode, type)); | |
1035 | |
1036 if (first_anon_arg < M32R_MAX_PARM_REGS) | |
1037 { | |
1038 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */ | |
1039 int first_reg_offset = first_anon_arg; | |
1040 /* Size in words to "pretend" allocate. */ | |
1041 int size = M32R_MAX_PARM_REGS - first_reg_offset; | |
1042 rtx regblock; | |
1043 | |
1044 regblock = gen_frame_mem (BLKmode, | |
1045 plus_constant (arg_pointer_rtx, | |
1046 FIRST_PARM_OFFSET (0))); | |
1047 set_mem_alias_set (regblock, get_varargs_alias_set ()); | |
1048 move_block_from_reg (first_reg_offset, regblock, size); | |
1049 | |
1050 *pretend_size = (size * UNITS_PER_WORD); | |
1051 } | |
1052 } | |
1053 | |
1054 | |
1055 /* Return true if INSN is real instruction bearing insn. */ | |
1056 | |
1057 static int | |
1058 m32r_is_insn (rtx insn) | |
1059 { | |
1060 return (INSN_P (insn) | |
1061 && GET_CODE (PATTERN (insn)) != USE | |
1062 && GET_CODE (PATTERN (insn)) != CLOBBER | |
1063 && GET_CODE (PATTERN (insn)) != ADDR_VEC); | |
1064 } | |
1065 | |
1066 /* Increase the priority of long instructions so that the | |
1067 short instructions are scheduled ahead of the long ones. */ | |
1068 | |
1069 static int | |
1070 m32r_adjust_priority (rtx insn, int priority) | |
1071 { | |
1072 if (m32r_is_insn (insn) | |
1073 && get_attr_insn_size (insn) != INSN_SIZE_SHORT) | |
1074 priority <<= 3; | |
1075 | |
1076 return priority; | |
1077 } | |
1078 | |
1079 | |
1080 /* Indicate how many instructions can be issued at the same time. | |
1081 This is sort of a lie. The m32r can issue only 1 long insn at | |
1082 once, but it can issue 2 short insns. The default therefore is | |
1083 set at 2, but this can be overridden by the command line option | |
1084 -missue-rate=1. */ | |
1085 | |
1086 static int | |
1087 m32r_issue_rate (void) | |
1088 { | |
1089 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2); | |
1090 } | |
1091 | |
1092 /* Cost functions. */ | |
1093 | |
1094 static bool | |
1095 m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total, | |
1096 bool speed ATTRIBUTE_UNUSED) | |
1097 { | |
1098 switch (code) | |
1099 { | |
1100 /* Small integers are as cheap as registers. 4 byte values can be | |
1101 fetched as immediate constants - let's give that the cost of an | |
1102 extra insn. */ | |
1103 case CONST_INT: | |
1104 if (INT16_P (INTVAL (x))) | |
1105 { | |
1106 *total = 0; | |
1107 return true; | |
1108 } | |
1109 /* FALLTHRU */ | |
1110 | |
1111 case CONST: | |
1112 case LABEL_REF: | |
1113 case SYMBOL_REF: | |
1114 *total = COSTS_N_INSNS (1); | |
1115 return true; | |
1116 | |
1117 case CONST_DOUBLE: | |
1118 { | |
1119 rtx high, low; | |
1120 | |
1121 split_double (x, &high, &low); | |
1122 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high)) | |
1123 + !INT16_P (INTVAL (low))); | |
1124 return true; | |
1125 } | |
1126 | |
1127 case MULT: | |
1128 *total = COSTS_N_INSNS (3); | |
1129 return true; | |
1130 | |
1131 case DIV: | |
1132 case UDIV: | |
1133 case MOD: | |
1134 case UMOD: | |
1135 *total = COSTS_N_INSNS (10); | |
1136 return true; | |
1137 | |
1138 default: | |
1139 return false; | |
1140 } | |
1141 } | |
1142 | |
1143 /* Type of function DECL. | |
1144 | |
1145 The result is cached. To reset the cache at the end of a function, | |
1146 call with DECL = NULL_TREE. */ | |
1147 | |
1148 enum m32r_function_type | |
1149 m32r_compute_function_type (tree decl) | |
1150 { | |
1151 /* Cached value. */ | |
1152 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN; | |
1153 /* Last function we were called for. */ | |
1154 static tree last_fn = NULL_TREE; | |
1155 | |
1156 /* Resetting the cached value? */ | |
1157 if (decl == NULL_TREE) | |
1158 { | |
1159 fn_type = M32R_FUNCTION_UNKNOWN; | |
1160 last_fn = NULL_TREE; | |
1161 return fn_type; | |
1162 } | |
1163 | |
1164 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN) | |
1165 return fn_type; | |
1166 | |
1167 /* Compute function type. */ | |
1168 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE | |
1169 ? M32R_FUNCTION_INTERRUPT | |
1170 : M32R_FUNCTION_NORMAL); | |
1171 | |
1172 last_fn = decl; | |
1173 return fn_type; | |
1174 } | |
1175 /* Function prologue/epilogue handlers. */ | |
1176 | |
1177 /* M32R stack frames look like: | |
1178 | |
1179 Before call After call | |
1180 +-----------------------+ +-----------------------+ | |
1181 | | | | | |
1182 high | local variables, | | local variables, | | |
1183 mem | reg save area, etc. | | reg save area, etc. | | |
1184 | | | | | |
1185 +-----------------------+ +-----------------------+ | |
1186 | | | | | |
1187 | arguments on stack. | | arguments on stack. | | |
1188 | | | | | |
1189 SP+0->+-----------------------+ +-----------------------+ | |
1190 | reg parm save area, | | |
1191 | only created for | | |
1192 | variable argument | | |
1193 | functions | | |
1194 +-----------------------+ | |
1195 | previous frame ptr | | |
1196 +-----------------------+ | |
1197 | | | |
1198 | register save area | | |
1199 | | | |
1200 +-----------------------+ | |
1201 | return address | | |
1202 +-----------------------+ | |
1203 | | | |
1204 | local variables | | |
1205 | | | |
1206 +-----------------------+ | |
1207 | | | |
1208 | alloca allocations | | |
1209 | | | |
1210 +-----------------------+ | |
1211 | | | |
1212 low | arguments on stack | | |
1213 memory | | | |
1214 SP+0->+-----------------------+ | |
1215 | |
1216 Notes: | |
1217 1) The "reg parm save area" does not exist for non variable argument fns. | |
1218 2) The "reg parm save area" can be eliminated completely if we saved regs | |
1219 containing anonymous args separately but that complicates things too | |
1220 much (so it's not done). | |
1221 3) The return address is saved after the register save area so as to have as | |
1222 many insns as possible between the restoration of `lr' and the `jmp lr'. */ | |
1223 | |
1224 /* Structure to be filled in by m32r_compute_frame_size with register | |
1225 save masks, and offsets for the current function. */ | |
1226 struct m32r_frame_info | |
1227 { | |
1228 unsigned int total_size; /* # bytes that the entire frame takes up. */ | |
1229 unsigned int extra_size; /* # bytes of extra stuff. */ | |
1230 unsigned int pretend_size; /* # bytes we push and pretend caller did. */ | |
1231 unsigned int args_size; /* # bytes that outgoing arguments take up. */ | |
1232 unsigned int reg_size; /* # bytes needed to store regs. */ | |
1233 unsigned int var_size; /* # bytes that variables take up. */ | |
1234 unsigned int gmask; /* Mask of saved gp registers. */ | |
1235 unsigned int save_fp; /* Nonzero if fp must be saved. */ | |
1236 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */ | |
1237 int initialized; /* Nonzero if frame size already calculated. */ | |
1238 }; | |
1239 | |
1240 /* Current frame information calculated by m32r_compute_frame_size. */ | |
1241 static struct m32r_frame_info current_frame_info; | |
1242 | |
1243 /* Zero structure to initialize current_frame_info. */ | |
1244 static struct m32r_frame_info zero_frame_info; | |
1245 | |
1246 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM)) | |
1247 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) | |
1248 | |
1249 /* Tell prologue and epilogue if register REGNO should be saved / restored. | |
1250 The return address and frame pointer are treated separately. | |
1251 Don't consider them here. */ | |
1252 #define MUST_SAVE_REGISTER(regno, interrupt_p) \ | |
1253 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \ | |
1254 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p))) | |
1255 | |
1256 #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM)) | |
1257 #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile) | |
1258 | |
1259 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */ | |
1260 #define LONG_INSN_SIZE 4 /* Size of long instructions. */ | |
1261 | |
1262 /* Return the bytes needed to compute the frame pointer from the current | |
1263 stack pointer. | |
1264 | |
1265 SIZE is the size needed for local variables. */ | |
1266 | |
1267 unsigned int | |
1268 m32r_compute_frame_size (int size) /* # of var. bytes allocated. */ | |
1269 { | |
1270 unsigned int regno; | |
1271 unsigned int total_size, var_size, args_size, pretend_size, extra_size; | |
1272 unsigned int reg_size, frame_size; | |
1273 unsigned int gmask; | |
1274 enum m32r_function_type fn_type; | |
1275 int interrupt_p; | |
1276 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table | |
1277 | crtl->profile); | |
1278 | |
1279 var_size = M32R_STACK_ALIGN (size); | |
1280 args_size = M32R_STACK_ALIGN (crtl->outgoing_args_size); | |
1281 pretend_size = crtl->args.pretend_args_size; | |
1282 extra_size = FIRST_PARM_OFFSET (0); | |
1283 total_size = extra_size + pretend_size + args_size + var_size; | |
1284 reg_size = 0; | |
1285 gmask = 0; | |
1286 | |
1287 /* See if this is an interrupt handler. Call used registers must be saved | |
1288 for them too. */ | |
1289 fn_type = m32r_compute_function_type (current_function_decl); | |
1290 interrupt_p = M32R_INTERRUPT_P (fn_type); | |
1291 | |
1292 /* Calculate space needed for registers. */ | |
1293 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++) | |
1294 { | |
1295 if (MUST_SAVE_REGISTER (regno, interrupt_p) | |
1296 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) | |
1297 { | |
1298 reg_size += UNITS_PER_WORD; | |
1299 gmask |= 1 << regno; | |
1300 } | |
1301 } | |
1302 | |
1303 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER; | |
1304 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used; | |
1305 | |
1306 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr) | |
1307 * UNITS_PER_WORD); | |
1308 total_size += reg_size; | |
1309 | |
1310 /* ??? Not sure this is necessary, and I don't think the epilogue | |
1311 handler will do the right thing if this changes total_size. */ | |
1312 total_size = M32R_STACK_ALIGN (total_size); | |
1313 | |
1314 frame_size = total_size - (pretend_size + reg_size); | |
1315 | |
1316 /* Save computed information. */ | |
1317 current_frame_info.total_size = total_size; | |
1318 current_frame_info.extra_size = extra_size; | |
1319 current_frame_info.pretend_size = pretend_size; | |
1320 current_frame_info.var_size = var_size; | |
1321 current_frame_info.args_size = args_size; | |
1322 current_frame_info.reg_size = reg_size; | |
1323 current_frame_info.gmask = gmask; | |
1324 current_frame_info.initialized = reload_completed; | |
1325 | |
1326 /* Ok, we're done. */ | |
1327 return total_size; | |
1328 } | |
1329 | |
1330 /* The table we use to reference PIC data. */ | |
1331 static rtx global_offset_table; | |
1332 | |
1333 static void | |
1334 m32r_reload_lr (rtx sp, int size) | |
1335 { | |
1336 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); | |
1337 | |
1338 if (size == 0) | |
1339 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, sp))); | |
1340 else if (size < 32768) | |
1341 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, | |
1342 gen_rtx_PLUS (Pmode, sp, | |
1343 GEN_INT (size))))); | |
1344 else | |
1345 { | |
1346 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); | |
1347 | |
1348 emit_insn (gen_movsi (tmp, GEN_INT (size))); | |
1349 emit_insn (gen_addsi3 (tmp, tmp, sp)); | |
1350 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, tmp))); | |
1351 } | |
1352 | |
1353 emit_use (lr); | |
1354 } | |
1355 | |
1356 void | |
1357 m32r_load_pic_register (void) | |
1358 { | |
1359 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
1360 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, | |
1361 GEN_INT (TARGET_MODEL_SMALL))); | |
1362 | |
1363 /* Need to emit this whether or not we obey regdecls, | |
1364 since setjmp/longjmp can cause life info to screw up. */ | |
1365 emit_use (pic_offset_table_rtx); | |
1366 } | |
1367 | |
1368 /* Expand the m32r prologue as a series of insns. */ | |
1369 | |
1370 void | |
1371 m32r_expand_prologue (void) | |
1372 { | |
1373 int regno; | |
1374 int frame_size; | |
1375 unsigned int gmask; | |
1376 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table | |
1377 | crtl->profile); | |
1378 | |
1379 if (! current_frame_info.initialized) | |
1380 m32r_compute_frame_size (get_frame_size ()); | |
1381 | |
1382 gmask = current_frame_info.gmask; | |
1383 | |
1384 /* These cases shouldn't happen. Catch them now. */ | |
1385 gcc_assert (current_frame_info.total_size || !gmask); | |
1386 | |
1387 /* Allocate space for register arguments if this is a variadic function. */ | |
1388 if (current_frame_info.pretend_size != 0) | |
1389 { | |
1390 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives | |
1391 the wrong result on a 64-bit host. */ | |
1392 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size; | |
1393 emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1394 stack_pointer_rtx, | |
1395 GEN_INT (-pretend_size))); | |
1396 } | |
1397 | |
1398 /* Save any registers we need to and set up fp. */ | |
1399 if (current_frame_info.save_fp) | |
1400 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx)); | |
1401 | |
1402 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK); | |
1403 | |
1404 /* Save any needed call-saved regs (and call-used if this is an | |
1405 interrupt handler). */ | |
1406 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno) | |
1407 { | |
1408 if ((gmask & (1 << regno)) != 0) | |
1409 emit_insn (gen_movsi_push (stack_pointer_rtx, | |
1410 gen_rtx_REG (Pmode, regno))); | |
1411 } | |
1412 | |
1413 if (current_frame_info.save_lr) | |
1414 emit_insn (gen_movsi_push (stack_pointer_rtx, | |
1415 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM))); | |
1416 | |
1417 /* Allocate the stack frame. */ | |
1418 frame_size = (current_frame_info.total_size | |
1419 - (current_frame_info.pretend_size | |
1420 + current_frame_info.reg_size)); | |
1421 | |
1422 if (frame_size == 0) | |
1423 ; /* Nothing to do. */ | |
1424 else if (frame_size <= 32768) | |
1425 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
1426 GEN_INT (-frame_size))); | |
1427 else | |
1428 { | |
1429 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); | |
1430 | |
1431 emit_insn (gen_movsi (tmp, GEN_INT (frame_size))); | |
1432 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp)); | |
1433 } | |
1434 | |
1435 if (frame_pointer_needed) | |
1436 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx)); | |
1437 | |
1438 if (crtl->profile) | |
1439 /* Push lr for mcount (form_pc, x). */ | |
1440 emit_insn (gen_movsi_push (stack_pointer_rtx, | |
1441 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM))); | |
1442 | |
1443 if (pic_reg_used) | |
1444 { | |
1445 m32r_load_pic_register (); | |
1446 m32r_reload_lr (stack_pointer_rtx, | |
1447 (crtl->profile ? 0 : frame_size)); | |
1448 } | |
1449 | |
1450 if (crtl->profile && !pic_reg_used) | |
1451 emit_insn (gen_blockage ()); | |
1452 } | |
1453 | |
1454 | |
1455 /* Set up the stack and frame pointer (if desired) for the function. | |
1456 Note, if this is changed, you need to mirror the changes in | |
1457 m32r_compute_frame_size which calculates the prolog size. */ | |
1458 | |
1459 static void | |
1460 m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size) | |
1461 { | |
1462 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl); | |
1463 | |
1464 /* If this is an interrupt handler, mark it as such. */ | |
1465 if (M32R_INTERRUPT_P (fn_type)) | |
1466 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START); | |
1467 | |
1468 if (! current_frame_info.initialized) | |
1469 m32r_compute_frame_size (size); | |
1470 | |
1471 /* This is only for the human reader. */ | |
1472 fprintf (file, | |
1473 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n", | |
1474 ASM_COMMENT_START, | |
1475 current_frame_info.var_size, | |
1476 current_frame_info.reg_size / 4, | |
1477 current_frame_info.args_size, | |
1478 current_frame_info.extra_size); | |
1479 } | |
1480 | |
1481 /* Output RTL to pop register REGNO from the stack. */ | |
1482 | |
1483 static void | |
1484 pop (int regno) | |
1485 { | |
1486 rtx x; | |
1487 | |
1488 x = emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, regno), | |
1489 stack_pointer_rtx)); | |
1490 REG_NOTES (x) | |
1491 = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0); | |
1492 } | |
1493 | |
1494 /* Expand the m32r epilogue as a series of insns. */ | |
1495 | |
1496 void | |
1497 m32r_expand_epilogue (void) | |
1498 { | |
1499 int regno; | |
1500 int noepilogue = FALSE; | |
1501 int total_size; | |
1502 | |
1503 gcc_assert (current_frame_info.initialized); | |
1504 total_size = current_frame_info.total_size; | |
1505 | |
1506 if (total_size == 0) | |
1507 { | |
1508 rtx insn = get_last_insn (); | |
1509 | |
1510 /* If the last insn was a BARRIER, we don't have to write any code | |
1511 because a jump (aka return) was put there. */ | |
1512 if (insn && GET_CODE (insn) == NOTE) | |
1513 insn = prev_nonnote_insn (insn); | |
1514 if (insn && GET_CODE (insn) == BARRIER) | |
1515 noepilogue = TRUE; | |
1516 } | |
1517 | |
1518 if (!noepilogue) | |
1519 { | |
1520 unsigned int var_size = current_frame_info.var_size; | |
1521 unsigned int args_size = current_frame_info.args_size; | |
1522 unsigned int gmask = current_frame_info.gmask; | |
1523 int can_trust_sp_p = !cfun->calls_alloca; | |
1524 | |
1525 if (flag_exceptions) | |
1526 emit_insn (gen_blockage ()); | |
1527 | |
1528 /* The first thing to do is point the sp at the bottom of the register | |
1529 save area. */ | |
1530 if (can_trust_sp_p) | |
1531 { | |
1532 unsigned int reg_offset = var_size + args_size; | |
1533 | |
1534 if (reg_offset == 0) | |
1535 ; /* Nothing to do. */ | |
1536 else if (reg_offset < 32768) | |
1537 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
1538 GEN_INT (reg_offset))); | |
1539 else | |
1540 { | |
1541 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); | |
1542 | |
1543 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset))); | |
1544 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
1545 tmp)); | |
1546 } | |
1547 } | |
1548 else if (frame_pointer_needed) | |
1549 { | |
1550 unsigned int reg_offset = var_size + args_size; | |
1551 | |
1552 if (reg_offset == 0) | |
1553 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx)); | |
1554 else if (reg_offset < 32768) | |
1555 emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx, | |
1556 GEN_INT (reg_offset))); | |
1557 else | |
1558 { | |
1559 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); | |
1560 | |
1561 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset))); | |
1562 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx)); | |
1563 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
1564 tmp)); | |
1565 } | |
1566 } | |
1567 else | |
1568 gcc_unreachable (); | |
1569 | |
1570 if (current_frame_info.save_lr) | |
1571 pop (RETURN_ADDR_REGNUM); | |
1572 | |
1573 /* Restore any saved registers, in reverse order of course. */ | |
1574 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK); | |
1575 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno) | |
1576 { | |
1577 if ((gmask & (1L << regno)) != 0) | |
1578 pop (regno); | |
1579 } | |
1580 | |
1581 if (current_frame_info.save_fp) | |
1582 pop (FRAME_POINTER_REGNUM); | |
1583 | |
1584 /* Remove varargs area if present. */ | |
1585 if (current_frame_info.pretend_size != 0) | |
1586 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
1587 GEN_INT (current_frame_info.pretend_size))); | |
1588 | |
1589 emit_insn (gen_blockage ()); | |
1590 } | |
1591 } | |
1592 | |
1593 /* Do any necessary cleanup after a function to restore stack, frame, | |
1594 and regs. */ | |
1595 | |
1596 static void | |
1597 m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED, | |
1598 HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
1599 { | |
1600 /* Reset state info for each function. */ | |
1601 current_frame_info = zero_frame_info; | |
1602 m32r_compute_function_type (NULL_TREE); | |
1603 } | |
1604 | |
1605 /* Return nonzero if this function is known to have a null or 1 instruction | |
1606 epilogue. */ | |
1607 | |
1608 int | |
1609 direct_return (void) | |
1610 { | |
1611 if (!reload_completed) | |
1612 return FALSE; | |
1613 | |
1614 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl))) | |
1615 return FALSE; | |
1616 | |
1617 if (! current_frame_info.initialized) | |
1618 m32r_compute_frame_size (get_frame_size ()); | |
1619 | |
1620 return current_frame_info.total_size == 0; | |
1621 } | |
1622 | |
1623 | |
1624 /* PIC. */ | |
1625 | |
1626 int | |
1627 m32r_legitimate_pic_operand_p (rtx x) | |
1628 { | |
1629 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1630 return 0; | |
1631 | |
1632 if (GET_CODE (x) == CONST | |
1633 && GET_CODE (XEXP (x, 0)) == PLUS | |
1634 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1635 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF) | |
1636 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) | |
1637 return 0; | |
1638 | |
1639 return 1; | |
1640 } | |
1641 | |
1642 rtx | |
1643 m32r_legitimize_pic_address (rtx orig, rtx reg) | |
1644 { | |
1645 #ifdef DEBUG_PIC | |
1646 printf("m32r_legitimize_pic_address()\n"); | |
1647 #endif | |
1648 | |
1649 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) | |
1650 { | |
1651 rtx pic_ref, address; | |
1652 rtx insn; | |
1653 int subregs = 0; | |
1654 | |
1655 if (reg == 0) | |
1656 { | |
1657 gcc_assert (!reload_in_progress && !reload_completed); | |
1658 reg = gen_reg_rtx (Pmode); | |
1659 | |
1660 subregs = 1; | |
1661 } | |
1662 | |
1663 if (subregs) | |
1664 address = gen_reg_rtx (Pmode); | |
1665 else | |
1666 address = reg; | |
1667 | |
1668 crtl->uses_pic_offset_table = 1; | |
1669 | |
1670 if (GET_CODE (orig) == LABEL_REF | |
1671 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig))) | |
1672 { | |
1673 emit_insn (gen_gotoff_load_addr (reg, orig)); | |
1674 emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx)); | |
1675 return reg; | |
1676 } | |
1677 | |
1678 emit_insn (gen_pic_load_addr (address, orig)); | |
1679 | |
1680 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx)); | |
1681 pic_ref = gen_const_mem (Pmode, address); | |
1682 insn = emit_move_insn (reg, pic_ref); | |
1683 #if 0 | |
1684 /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
1685 by loop. */ | |
1686 set_unique_reg_note (insn, REG_EQUAL, orig); | |
1687 #endif | |
1688 return reg; | |
1689 } | |
1690 else if (GET_CODE (orig) == CONST) | |
1691 { | |
1692 rtx base, offset; | |
1693 | |
1694 if (GET_CODE (XEXP (orig, 0)) == PLUS | |
1695 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx) | |
1696 return orig; | |
1697 | |
1698 if (reg == 0) | |
1699 { | |
1700 gcc_assert (!reload_in_progress && !reload_completed); | |
1701 reg = gen_reg_rtx (Pmode); | |
1702 } | |
1703 | |
1704 if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
1705 { | |
1706 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg); | |
1707 if (base == reg) | |
1708 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX); | |
1709 else | |
1710 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg); | |
1711 } | |
1712 else | |
1713 return orig; | |
1714 | |
1715 if (GET_CODE (offset) == CONST_INT) | |
1716 { | |
1717 if (INT16_P (INTVAL (offset))) | |
1718 return plus_constant (base, INTVAL (offset)); | |
1719 else | |
1720 { | |
1721 gcc_assert (! reload_in_progress && ! reload_completed); | |
1722 offset = force_reg (Pmode, offset); | |
1723 } | |
1724 } | |
1725 | |
1726 return gen_rtx_PLUS (Pmode, base, offset); | |
1727 } | |
1728 | |
1729 return orig; | |
1730 } | |
1731 | |
1732 /* Nested function support. */ | |
1733 | |
1734 /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1735 FNADDR is an RTX for the address of the function's pure code. | |
1736 CXT is an RTX for the static chain value for the function. */ | |
1737 | |
1738 void | |
1739 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED, | |
1740 rtx fnaddr ATTRIBUTE_UNUSED, | |
1741 rtx cxt ATTRIBUTE_UNUSED) | |
1742 { | |
1743 } | |
1744 | |
1745 static void | |
1746 m32r_file_start (void) | |
1747 { | |
1748 default_file_start (); | |
1749 | |
1750 if (flag_verbose_asm) | |
1751 fprintf (asm_out_file, | |
1752 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n", | |
1753 ASM_COMMENT_START, g_switch_value); | |
1754 | |
1755 if (TARGET_LITTLE_ENDIAN) | |
1756 fprintf (asm_out_file, "\t.little\n"); | |
1757 } | |
1758 | |
1759 /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1760 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1761 For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1762 | |
1763 void | |
1764 m32r_print_operand (FILE * file, rtx x, int code) | |
1765 { | |
1766 rtx addr; | |
1767 | |
1768 switch (code) | |
1769 { | |
1770 /* The 's' and 'p' codes are used by output_block_move() to | |
1771 indicate post-increment 's'tores and 'p're-increment loads. */ | |
1772 case 's': | |
1773 if (GET_CODE (x) == REG) | |
1774 fprintf (file, "@+%s", reg_names [REGNO (x)]); | |
1775 else | |
1776 output_operand_lossage ("invalid operand to %%s code"); | |
1777 return; | |
1778 | |
1779 case 'p': | |
1780 if (GET_CODE (x) == REG) | |
1781 fprintf (file, "@%s+", reg_names [REGNO (x)]); | |
1782 else | |
1783 output_operand_lossage ("invalid operand to %%p code"); | |
1784 return; | |
1785 | |
1786 case 'R' : | |
1787 /* Write second word of DImode or DFmode reference, | |
1788 register or memory. */ | |
1789 if (GET_CODE (x) == REG) | |
1790 fputs (reg_names[REGNO (x)+1], file); | |
1791 else if (GET_CODE (x) == MEM) | |
1792 { | |
1793 fprintf (file, "@("); | |
1794 /* Handle possible auto-increment. Since it is pre-increment and | |
1795 we have already done it, we can just use an offset of four. */ | |
1796 /* ??? This is taken from rs6000.c I think. I don't think it is | |
1797 currently necessary, but keep it around. */ | |
1798 if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1799 || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1800 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4)); | |
1801 else | |
1802 output_address (plus_constant (XEXP (x, 0), 4)); | |
1803 fputc (')', file); | |
1804 } | |
1805 else | |
1806 output_operand_lossage ("invalid operand to %%R code"); | |
1807 return; | |
1808 | |
1809 case 'H' : /* High word. */ | |
1810 case 'L' : /* Low word. */ | |
1811 if (GET_CODE (x) == REG) | |
1812 { | |
1813 /* L = least significant word, H = most significant word. */ | |
1814 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L')) | |
1815 fputs (reg_names[REGNO (x)], file); | |
1816 else | |
1817 fputs (reg_names[REGNO (x)+1], file); | |
1818 } | |
1819 else if (GET_CODE (x) == CONST_INT | |
1820 || GET_CODE (x) == CONST_DOUBLE) | |
1821 { | |
1822 rtx first, second; | |
1823 | |
1824 split_double (x, &first, &second); | |
1825 fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
1826 code == 'L' ? INTVAL (first) : INTVAL (second)); | |
1827 } | |
1828 else | |
1829 output_operand_lossage ("invalid operand to %%H/%%L code"); | |
1830 return; | |
1831 | |
1832 case 'A' : | |
1833 { | |
1834 char str[30]; | |
1835 | |
1836 if (GET_CODE (x) != CONST_DOUBLE | |
1837 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT) | |
1838 fatal_insn ("bad insn for 'A'", x); | |
1839 | |
1840 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1); | |
1841 fprintf (file, "%s", str); | |
1842 return; | |
1843 } | |
1844 | |
1845 case 'B' : /* Bottom half. */ | |
1846 case 'T' : /* Top half. */ | |
1847 /* Output the argument to a `seth' insn (sets the Top half-word). | |
1848 For constants output arguments to a seth/or3 pair to set Top and | |
1849 Bottom halves. For symbols output arguments to a seth/add3 pair to | |
1850 set Top and Bottom halves. The difference exists because for | |
1851 constants seth/or3 is more readable but for symbols we need to use | |
1852 the same scheme as `ld' and `st' insns (16-bit addend is signed). */ | |
1853 switch (GET_CODE (x)) | |
1854 { | |
1855 case CONST_INT : | |
1856 case CONST_DOUBLE : | |
1857 { | |
1858 rtx first, second; | |
1859 | |
1860 split_double (x, &first, &second); | |
1861 x = WORDS_BIG_ENDIAN ? second : first; | |
1862 fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
1863 (code == 'B' | |
1864 ? INTVAL (x) & 0xffff | |
1865 : (INTVAL (x) >> 16) & 0xffff)); | |
1866 } | |
1867 return; | |
1868 case CONST : | |
1869 case SYMBOL_REF : | |
1870 if (code == 'B' | |
1871 && small_data_operand (x, VOIDmode)) | |
1872 { | |
1873 fputs ("sda(", file); | |
1874 output_addr_const (file, x); | |
1875 fputc (')', file); | |
1876 return; | |
1877 } | |
1878 /* fall through */ | |
1879 case LABEL_REF : | |
1880 fputs (code == 'T' ? "shigh(" : "low(", file); | |
1881 output_addr_const (file, x); | |
1882 fputc (')', file); | |
1883 return; | |
1884 default : | |
1885 output_operand_lossage ("invalid operand to %%T/%%B code"); | |
1886 return; | |
1887 } | |
1888 break; | |
1889 | |
1890 case 'U' : | |
1891 /* ??? wip */ | |
1892 /* Output a load/store with update indicator if appropriate. */ | |
1893 if (GET_CODE (x) == MEM) | |
1894 { | |
1895 if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1896 || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1897 fputs (".a", file); | |
1898 } | |
1899 else | |
1900 output_operand_lossage ("invalid operand to %%U code"); | |
1901 return; | |
1902 | |
1903 case 'N' : | |
1904 /* Print a constant value negated. */ | |
1905 if (GET_CODE (x) == CONST_INT) | |
1906 output_addr_const (file, GEN_INT (- INTVAL (x))); | |
1907 else | |
1908 output_operand_lossage ("invalid operand to %%N code"); | |
1909 return; | |
1910 | |
1911 case 'X' : | |
1912 /* Print a const_int in hex. Used in comments. */ | |
1913 if (GET_CODE (x) == CONST_INT) | |
1914 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
1915 return; | |
1916 | |
1917 case '#' : | |
1918 fputs (IMMEDIATE_PREFIX, file); | |
1919 return; | |
1920 | |
1921 case 0 : | |
1922 /* Do nothing special. */ | |
1923 break; | |
1924 | |
1925 default : | |
1926 /* Unknown flag. */ | |
1927 output_operand_lossage ("invalid operand output code"); | |
1928 } | |
1929 | |
1930 switch (GET_CODE (x)) | |
1931 { | |
1932 case REG : | |
1933 fputs (reg_names[REGNO (x)], file); | |
1934 break; | |
1935 | |
1936 case MEM : | |
1937 addr = XEXP (x, 0); | |
1938 if (GET_CODE (addr) == PRE_INC) | |
1939 { | |
1940 if (GET_CODE (XEXP (addr, 0)) != REG) | |
1941 fatal_insn ("pre-increment address is not a register", x); | |
1942 | |
1943 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]); | |
1944 } | |
1945 else if (GET_CODE (addr) == PRE_DEC) | |
1946 { | |
1947 if (GET_CODE (XEXP (addr, 0)) != REG) | |
1948 fatal_insn ("pre-decrement address is not a register", x); | |
1949 | |
1950 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]); | |
1951 } | |
1952 else if (GET_CODE (addr) == POST_INC) | |
1953 { | |
1954 if (GET_CODE (XEXP (addr, 0)) != REG) | |
1955 fatal_insn ("post-increment address is not a register", x); | |
1956 | |
1957 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]); | |
1958 } | |
1959 else | |
1960 { | |
1961 fputs ("@(", file); | |
1962 output_address (XEXP (x, 0)); | |
1963 fputc (')', file); | |
1964 } | |
1965 break; | |
1966 | |
1967 case CONST_DOUBLE : | |
1968 /* We handle SFmode constants here as output_addr_const doesn't. */ | |
1969 if (GET_MODE (x) == SFmode) | |
1970 { | |
1971 REAL_VALUE_TYPE d; | |
1972 long l; | |
1973 | |
1974 REAL_VALUE_FROM_CONST_DOUBLE (d, x); | |
1975 REAL_VALUE_TO_TARGET_SINGLE (d, l); | |
1976 fprintf (file, "0x%08lx", l); | |
1977 break; | |
1978 } | |
1979 | |
1980 /* Fall through. Let output_addr_const deal with it. */ | |
1981 | |
1982 default : | |
1983 output_addr_const (file, x); | |
1984 break; | |
1985 } | |
1986 } | |
1987 | |
1988 /* Print a memory address as an operand to reference that memory location. */ | |
1989 | |
1990 void | |
1991 m32r_print_operand_address (FILE * file, rtx addr) | |
1992 { | |
1993 rtx base; | |
1994 rtx index = 0; | |
1995 int offset = 0; | |
1996 | |
1997 switch (GET_CODE (addr)) | |
1998 { | |
1999 case REG : | |
2000 fputs (reg_names[REGNO (addr)], file); | |
2001 break; | |
2002 | |
2003 case PLUS : | |
2004 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) | |
2005 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); | |
2006 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
2007 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); | |
2008 else | |
2009 base = XEXP (addr, 0), index = XEXP (addr, 1); | |
2010 if (GET_CODE (base) == REG) | |
2011 { | |
2012 /* Print the offset first (if present) to conform to the manual. */ | |
2013 if (index == 0) | |
2014 { | |
2015 if (offset != 0) | |
2016 fprintf (file, "%d,", offset); | |
2017 fputs (reg_names[REGNO (base)], file); | |
2018 } | |
2019 /* The chip doesn't support this, but left in for generality. */ | |
2020 else if (GET_CODE (index) == REG) | |
2021 fprintf (file, "%s,%s", | |
2022 reg_names[REGNO (base)], reg_names[REGNO (index)]); | |
2023 /* Not sure this can happen, but leave in for now. */ | |
2024 else if (GET_CODE (index) == SYMBOL_REF) | |
2025 { | |
2026 output_addr_const (file, index); | |
2027 fputc (',', file); | |
2028 fputs (reg_names[REGNO (base)], file); | |
2029 } | |
2030 else | |
2031 fatal_insn ("bad address", addr); | |
2032 } | |
2033 else if (GET_CODE (base) == LO_SUM) | |
2034 { | |
2035 gcc_assert (!index && GET_CODE (XEXP (base, 0)) == REG); | |
2036 if (small_data_operand (XEXP (base, 1), VOIDmode)) | |
2037 fputs ("sda(", file); | |
2038 else | |
2039 fputs ("low(", file); | |
2040 output_addr_const (file, plus_constant (XEXP (base, 1), offset)); | |
2041 fputs ("),", file); | |
2042 fputs (reg_names[REGNO (XEXP (base, 0))], file); | |
2043 } | |
2044 else | |
2045 fatal_insn ("bad address", addr); | |
2046 break; | |
2047 | |
2048 case LO_SUM : | |
2049 if (GET_CODE (XEXP (addr, 0)) != REG) | |
2050 fatal_insn ("lo_sum not of register", addr); | |
2051 if (small_data_operand (XEXP (addr, 1), VOIDmode)) | |
2052 fputs ("sda(", file); | |
2053 else | |
2054 fputs ("low(", file); | |
2055 output_addr_const (file, XEXP (addr, 1)); | |
2056 fputs ("),", file); | |
2057 fputs (reg_names[REGNO (XEXP (addr, 0))], file); | |
2058 break; | |
2059 | |
2060 case PRE_INC : /* Assume SImode. */ | |
2061 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]); | |
2062 break; | |
2063 | |
2064 case PRE_DEC : /* Assume SImode. */ | |
2065 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]); | |
2066 break; | |
2067 | |
2068 case POST_INC : /* Assume SImode. */ | |
2069 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]); | |
2070 break; | |
2071 | |
2072 default : | |
2073 output_addr_const (file, addr); | |
2074 break; | |
2075 } | |
2076 } | |
2077 | |
2078 /* Return true if the operands are the constants 0 and 1. */ | |
2079 | |
2080 int | |
2081 zero_and_one (rtx operand1, rtx operand2) | |
2082 { | |
2083 return | |
2084 GET_CODE (operand1) == CONST_INT | |
2085 && GET_CODE (operand2) == CONST_INT | |
2086 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1)) | |
2087 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0))); | |
2088 } | |
2089 | |
2090 /* Generate the correct assembler code to handle the conditional loading of a | |
2091 value into a register. It is known that the operands satisfy the | |
2092 conditional_move_operand() function above. The destination is operand[0]. | |
2093 The condition is operand [1]. The 'true' value is operand [2] and the | |
2094 'false' value is operand [3]. */ | |
2095 | |
2096 char * | |
2097 emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED) | |
2098 { | |
2099 static char buffer [100]; | |
2100 const char * dest = reg_names [REGNO (operands [0])]; | |
2101 | |
2102 buffer [0] = 0; | |
2103 | |
2104 /* Destination must be a register. */ | |
2105 gcc_assert (GET_CODE (operands [0]) == REG); | |
2106 gcc_assert (conditional_move_operand (operands [2], SImode)); | |
2107 gcc_assert (conditional_move_operand (operands [3], SImode)); | |
2108 | |
2109 /* Check to see if the test is reversed. */ | |
2110 if (GET_CODE (operands [1]) == NE) | |
2111 { | |
2112 rtx tmp = operands [2]; | |
2113 operands [2] = operands [3]; | |
2114 operands [3] = tmp; | |
2115 } | |
2116 | |
2117 sprintf (buffer, "mvfc %s, cbr", dest); | |
2118 | |
2119 /* If the true value was '0' then we need to invert the results of the move. */ | |
2120 if (INTVAL (operands [2]) == 0) | |
2121 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1", | |
2122 dest, dest); | |
2123 | |
2124 return buffer; | |
2125 } | |
2126 | |
2127 /* Returns true if the registers contained in the two | |
2128 rtl expressions are different. */ | |
2129 | |
2130 int | |
2131 m32r_not_same_reg (rtx a, rtx b) | |
2132 { | |
2133 int reg_a = -1; | |
2134 int reg_b = -2; | |
2135 | |
2136 while (GET_CODE (a) == SUBREG) | |
2137 a = SUBREG_REG (a); | |
2138 | |
2139 if (GET_CODE (a) == REG) | |
2140 reg_a = REGNO (a); | |
2141 | |
2142 while (GET_CODE (b) == SUBREG) | |
2143 b = SUBREG_REG (b); | |
2144 | |
2145 if (GET_CODE (b) == REG) | |
2146 reg_b = REGNO (b); | |
2147 | |
2148 return reg_a != reg_b; | |
2149 } | |
2150 | |
2151 | |
2152 rtx | |
2153 m32r_function_symbol (const char *name) | |
2154 { | |
2155 int extra_flags = 0; | |
2156 enum m32r_model model; | |
2157 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name); | |
2158 | |
2159 if (TARGET_MODEL_SMALL) | |
2160 model = M32R_MODEL_SMALL; | |
2161 else if (TARGET_MODEL_MEDIUM) | |
2162 model = M32R_MODEL_MEDIUM; | |
2163 else if (TARGET_MODEL_LARGE) | |
2164 model = M32R_MODEL_LARGE; | |
2165 else | |
2166 gcc_unreachable (); /* Shouldn't happen. */ | |
2167 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT; | |
2168 | |
2169 if (extra_flags) | |
2170 SYMBOL_REF_FLAGS (sym) |= extra_flags; | |
2171 | |
2172 return sym; | |
2173 } | |
2174 | |
2175 /* Use a library function to move some bytes. */ | |
2176 | |
2177 static void | |
2178 block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx) | |
2179 { | |
2180 /* We want to pass the size as Pmode, which will normally be SImode | |
2181 but will be DImode if we are using 64-bit longs and pointers. */ | |
2182 if (GET_MODE (bytes_rtx) != VOIDmode | |
2183 && GET_MODE (bytes_rtx) != Pmode) | |
2184 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1); | |
2185 | |
2186 emit_library_call (m32r_function_symbol ("memcpy"), 0, | |
2187 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode, | |
2188 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx, | |
2189 TYPE_UNSIGNED (sizetype)), | |
2190 TYPE_MODE (sizetype)); | |
2191 } | |
2192 | |
2193 /* Expand string/block move operations. | |
2194 | |
2195 operands[0] is the pointer to the destination. | |
2196 operands[1] is the pointer to the source. | |
2197 operands[2] is the number of bytes to move. | |
2198 operands[3] is the alignment. | |
2199 | |
2200 Returns 1 upon success, 0 otherwise. */ | |
2201 | |
2202 int | |
2203 m32r_expand_block_move (rtx operands[]) | |
2204 { | |
2205 rtx orig_dst = operands[0]; | |
2206 rtx orig_src = operands[1]; | |
2207 rtx bytes_rtx = operands[2]; | |
2208 rtx align_rtx = operands[3]; | |
2209 int constp = GET_CODE (bytes_rtx) == CONST_INT; | |
2210 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0; | |
2211 int align = INTVAL (align_rtx); | |
2212 int leftover; | |
2213 rtx src_reg; | |
2214 rtx dst_reg; | |
2215 | |
2216 if (constp && bytes <= 0) | |
2217 return 1; | |
2218 | |
2219 /* Move the address into scratch registers. */ | |
2220 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0)); | |
2221 src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
2222 | |
2223 if (align > UNITS_PER_WORD) | |
2224 align = UNITS_PER_WORD; | |
2225 | |
2226 /* If we prefer size over speed, always use a function call. | |
2227 If we do not know the size, use a function call. | |
2228 If the blocks are not word aligned, use a function call. */ | |
2229 if (optimize_size || ! constp || align != UNITS_PER_WORD) | |
2230 { | |
2231 block_move_call (dst_reg, src_reg, bytes_rtx); | |
2232 return 0; | |
2233 } | |
2234 | |
2235 leftover = bytes % MAX_MOVE_BYTES; | |
2236 bytes -= leftover; | |
2237 | |
2238 /* If necessary, generate a loop to handle the bulk of the copy. */ | |
2239 if (bytes) | |
2240 { | |
2241 rtx label = NULL_RTX; | |
2242 rtx final_src = NULL_RTX; | |
2243 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES); | |
2244 rtx rounded_total = GEN_INT (bytes); | |
2245 rtx new_dst_reg = gen_reg_rtx (SImode); | |
2246 rtx new_src_reg = gen_reg_rtx (SImode); | |
2247 | |
2248 /* If we are going to have to perform this loop more than | |
2249 once, then generate a label and compute the address the | |
2250 source register will contain upon completion of the final | |
2251 iteration. */ | |
2252 if (bytes > MAX_MOVE_BYTES) | |
2253 { | |
2254 final_src = gen_reg_rtx (Pmode); | |
2255 | |
2256 if (INT16_P(bytes)) | |
2257 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total)); | |
2258 else | |
2259 { | |
2260 emit_insn (gen_movsi (final_src, rounded_total)); | |
2261 emit_insn (gen_addsi3 (final_src, final_src, src_reg)); | |
2262 } | |
2263 | |
2264 label = gen_label_rtx (); | |
2265 emit_label (label); | |
2266 } | |
2267 | |
2268 /* It is known that output_block_move() will update src_reg to point | |
2269 to the word after the end of the source block, and dst_reg to point | |
2270 to the last word of the destination block, provided that the block | |
2271 is MAX_MOVE_BYTES long. */ | |
2272 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time, | |
2273 new_dst_reg, new_src_reg)); | |
2274 emit_move_insn (dst_reg, new_dst_reg); | |
2275 emit_move_insn (src_reg, new_src_reg); | |
2276 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4))); | |
2277 | |
2278 if (bytes > MAX_MOVE_BYTES) | |
2279 { | |
2280 emit_insn (gen_cmpsi (src_reg, final_src)); | |
2281 emit_jump_insn (gen_bne (label)); | |
2282 } | |
2283 } | |
2284 | |
2285 if (leftover) | |
2286 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover), | |
2287 gen_reg_rtx (SImode), | |
2288 gen_reg_rtx (SImode))); | |
2289 return 1; | |
2290 } | |
2291 | |
2292 | |
2293 /* Emit load/stores for a small constant word aligned block_move. | |
2294 | |
2295 operands[0] is the memory address of the destination. | |
2296 operands[1] is the memory address of the source. | |
2297 operands[2] is the number of bytes to move. | |
2298 operands[3] is a temp register. | |
2299 operands[4] is a temp register. */ | |
2300 | |
2301 void | |
2302 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[]) | |
2303 { | |
2304 HOST_WIDE_INT bytes = INTVAL (operands[2]); | |
2305 int first_time; | |
2306 int got_extra = 0; | |
2307 | |
2308 gcc_assert (bytes >= 1 && bytes <= MAX_MOVE_BYTES); | |
2309 | |
2310 /* We do not have a post-increment store available, so the first set of | |
2311 stores are done without any increment, then the remaining ones can use | |
2312 the pre-increment addressing mode. | |
2313 | |
2314 Note: expand_block_move() also relies upon this behavior when building | |
2315 loops to copy large blocks. */ | |
2316 first_time = 1; | |
2317 | |
2318 while (bytes > 0) | |
2319 { | |
2320 if (bytes >= 8) | |
2321 { | |
2322 if (first_time) | |
2323 { | |
2324 output_asm_insn ("ld\t%5, %p1", operands); | |
2325 output_asm_insn ("ld\t%6, %p1", operands); | |
2326 output_asm_insn ("st\t%5, @%0", operands); | |
2327 output_asm_insn ("st\t%6, %s0", operands); | |
2328 } | |
2329 else | |
2330 { | |
2331 output_asm_insn ("ld\t%5, %p1", operands); | |
2332 output_asm_insn ("ld\t%6, %p1", operands); | |
2333 output_asm_insn ("st\t%5, %s0", operands); | |
2334 output_asm_insn ("st\t%6, %s0", operands); | |
2335 } | |
2336 | |
2337 bytes -= 8; | |
2338 } | |
2339 else if (bytes >= 4) | |
2340 { | |
2341 if (bytes > 4) | |
2342 got_extra = 1; | |
2343 | |
2344 output_asm_insn ("ld\t%5, %p1", operands); | |
2345 | |
2346 if (got_extra) | |
2347 output_asm_insn ("ld\t%6, %p1", operands); | |
2348 | |
2349 if (first_time) | |
2350 output_asm_insn ("st\t%5, @%0", operands); | |
2351 else | |
2352 output_asm_insn ("st\t%5, %s0", operands); | |
2353 | |
2354 bytes -= 4; | |
2355 } | |
2356 else | |
2357 { | |
2358 /* Get the entire next word, even though we do not want all of it. | |
2359 The saves us from doing several smaller loads, and we assume that | |
2360 we cannot cause a page fault when at least part of the word is in | |
2361 valid memory [since we don't get called if things aren't properly | |
2362 aligned]. */ | |
2363 int dst_offset = first_time ? 0 : 4; | |
2364 /* The amount of increment we have to make to the | |
2365 destination pointer. */ | |
2366 int dst_inc_amount = dst_offset + bytes - 4; | |
2367 /* The same for the source pointer. */ | |
2368 int src_inc_amount = bytes; | |
2369 int last_shift; | |
2370 rtx my_operands[3]; | |
2371 | |
2372 /* If got_extra is true then we have already loaded | |
2373 the next word as part of loading and storing the previous word. */ | |
2374 if (! got_extra) | |
2375 output_asm_insn ("ld\t%6, @%1", operands); | |
2376 | |
2377 if (bytes >= 2) | |
2378 { | |
2379 bytes -= 2; | |
2380 | |
2381 output_asm_insn ("sra3\t%5, %6, #16", operands); | |
2382 my_operands[0] = operands[5]; | |
2383 my_operands[1] = GEN_INT (dst_offset); | |
2384 my_operands[2] = operands[0]; | |
2385 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands); | |
2386 | |
2387 /* If there is a byte left to store then increment the | |
2388 destination address and shift the contents of the source | |
2389 register down by 8 bits. We could not do the address | |
2390 increment in the store half word instruction, because it does | |
2391 not have an auto increment mode. */ | |
2392 if (bytes > 0) /* assert (bytes == 1) */ | |
2393 { | |
2394 dst_offset += 2; | |
2395 last_shift = 8; | |
2396 } | |
2397 } | |
2398 else | |
2399 last_shift = 24; | |
2400 | |
2401 if (bytes > 0) | |
2402 { | |
2403 my_operands[0] = operands[6]; | |
2404 my_operands[1] = GEN_INT (last_shift); | |
2405 output_asm_insn ("srai\t%0, #%1", my_operands); | |
2406 my_operands[0] = operands[6]; | |
2407 my_operands[1] = GEN_INT (dst_offset); | |
2408 my_operands[2] = operands[0]; | |
2409 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands); | |
2410 } | |
2411 | |
2412 /* Update the destination pointer if needed. We have to do | |
2413 this so that the patterns matches what we output in this | |
2414 function. */ | |
2415 if (dst_inc_amount | |
2416 && !find_reg_note (insn, REG_UNUSED, operands[0])) | |
2417 { | |
2418 my_operands[0] = operands[0]; | |
2419 my_operands[1] = GEN_INT (dst_inc_amount); | |
2420 output_asm_insn ("addi\t%0, #%1", my_operands); | |
2421 } | |
2422 | |
2423 /* Update the source pointer if needed. We have to do this | |
2424 so that the patterns matches what we output in this | |
2425 function. */ | |
2426 if (src_inc_amount | |
2427 && !find_reg_note (insn, REG_UNUSED, operands[1])) | |
2428 { | |
2429 my_operands[0] = operands[1]; | |
2430 my_operands[1] = GEN_INT (src_inc_amount); | |
2431 output_asm_insn ("addi\t%0, #%1", my_operands); | |
2432 } | |
2433 | |
2434 bytes = 0; | |
2435 } | |
2436 | |
2437 first_time = 0; | |
2438 } | |
2439 } | |
2440 | |
2441 /* Return true if using NEW_REG in place of OLD_REG is ok. */ | |
2442 | |
2443 int | |
2444 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, | |
2445 unsigned int new_reg) | |
2446 { | |
2447 /* Interrupt routines can't clobber any register that isn't already used. */ | |
2448 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) | |
2449 && !df_regs_ever_live_p (new_reg)) | |
2450 return 0; | |
2451 | |
2452 return 1; | |
2453 } | |
2454 | |
2455 rtx | |
2456 m32r_return_addr (int count) | |
2457 { | |
2458 if (count != 0) | |
2459 return const0_rtx; | |
2460 | |
2461 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); | |
2462 } |