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comparison gcc/config/mips/5400.md @ 0:a06113de4d67

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first commit
author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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children 77e2b8dfacca
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-1:000000000000 0:a06113de4d67
1 ;; DFA-based pipeline description for 5400
2 (define_automaton "vr54")
3 (define_cpu_unit "vr54_dp0" "vr54")
4 (define_cpu_unit "vr54_dp1" "vr54")
5 (define_cpu_unit "vr54_mem" "vr54")
6 (define_cpu_unit "vr54_mac" "vr54")
7
8 ;;
9 ;; The ordering of the instruction-execution-path/resource-usage
10 ;; descriptions (also known as reservation RTL) is roughly ordered
11 ;; based on the define attribute RTL for the "type" classification.
12 ;; When modifying, remember that the first test that matches is the
13 ;; reservation used!
14 ;;
15
16 (define_insn_reservation "ir_vr54_unknown" 1
17 (and (eq_attr "cpu" "r5400")
18 (eq_attr "type" "unknown"))
19 "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")
20
21 ;; Assume prediction fails.
22 (define_insn_reservation "ir_vr54_branch" 3
23 (and (eq_attr "cpu" "r5400")
24 (eq_attr "type" "branch,jump,call"))
25 "vr54_dp0|vr54_dp1")
26
27 (define_insn_reservation "ir_vr54_load" 2
28 (and (eq_attr "cpu" "r5400")
29 (eq_attr "type" "load,fpload,fpidxload"))
30 "vr54_mem")
31
32 (define_insn_reservation "ir_vr54_store" 1
33 (and (eq_attr "cpu" "r5400")
34 (eq_attr "type" "store"))
35 "vr54_mem")
36
37 (define_insn_reservation "ir_vr54_fstore" 1
38 (and (eq_attr "cpu" "r5400")
39 (eq_attr "type" "fpstore,fpidxstore"))
40 "vr54_mem")
41
42
43 ;; This reservation is for conditional move based on integer
44 ;; or floating point CC.
45 (define_insn_reservation "ir_vr54_condmove" 4
46 (and (eq_attr "cpu" "r5400")
47 (eq_attr "type" "condmove"))
48 "vr54_dp0|vr54_dp1")
49
50 ;; Move to/from FPU registers
51 (define_insn_reservation "ir_vr54_xfer" 2
52 (and (eq_attr "cpu" "r5400")
53 (eq_attr "type" "mfc,mtc"))
54 "vr54_dp0|vr54_dp1")
55
56 (define_insn_reservation "ir_vr54_hilo" 1
57 (and (eq_attr "cpu" "r5400")
58 (eq_attr "type" "mthilo,mfhilo"))
59 "vr54_dp0|vr54_dp1")
60
61 (define_insn_reservation "ir_vr54_arith" 1
62 (and (eq_attr "cpu" "r5400")
63 (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap"))
64 "vr54_dp0|vr54_dp1")
65
66 (define_insn_reservation "ir_vr54_imul_si" 3
67 (and (eq_attr "cpu" "r5400")
68 (and (eq_attr "type" "imul,imul3")
69 (eq_attr "mode" "SI")))
70 "vr54_dp0|vr54_dp1")
71
72 (define_insn_reservation "ir_vr54_imul_di" 4
73 (and (eq_attr "cpu" "r5400")
74 (and (eq_attr "type" "imul,imul3")
75 (eq_attr "mode" "DI")))
76 "vr54_dp0|vr54_dp1")
77
78 (define_insn_reservation "ir_vr54_imadd_si" 3
79 (and (eq_attr "cpu" "r5400")
80 (eq_attr "type" "imul,imul3"))
81 "vr54_mac")
82
83 (define_insn_reservation "ir_vr54_idiv_si" 42
84 (and (eq_attr "cpu" "r5400")
85 (and (eq_attr "type" "idiv")
86 (eq_attr "mode" "SI")))
87 "vr54_dp0|vr54_dp1")
88
89 (define_insn_reservation "ir_vr54_idiv_di" 74
90 (and (eq_attr "cpu" "r5400")
91 (and (eq_attr "type" "idiv")
92 (eq_attr "mode" "DI")))
93 "vr54_dp0|vr54_dp1")
94
95 (define_insn_reservation "ir_vr54_fadd" 4
96 (and (eq_attr "cpu" "r5400")
97 (eq_attr "type" "fadd"))
98 "vr54_dp0|vr54_dp1")
99
100 (define_insn_reservation "ir_vr54_fmul_sf" 5
101 (and (eq_attr "cpu" "r5400")
102 (and (eq_attr "type" "fmul")
103 (eq_attr "mode" "SF")))
104 "vr54_dp0|vr54_dp1")
105
106 (define_insn_reservation "ir_vr54_fmul_df" 6
107 (and (eq_attr "cpu" "r5400")
108 (and (eq_attr "type" "fmul")
109 (eq_attr "mode" "DF")))
110 "vr54_dp0|vr54_dp1")
111
112 (define_insn_reservation "ir_vr54_fmadd_sf" 9
113 (and (eq_attr "cpu" "r5400")
114 (and (eq_attr "type" "fmadd")
115 (eq_attr "mode" "SF")))
116 "vr54_dp0|vr54_dp1")
117
118 (define_insn_reservation "ir_vr54_fmadd_df" 10
119 (and (eq_attr "cpu" "r5400")
120 (and (eq_attr "type" "fmadd")
121 (eq_attr "mode" "DF")))
122 "vr54_dp0|vr54_dp1")
123
124 (define_insn_reservation "ir_vr54_fdiv_sf" 42
125 (and (eq_attr "cpu" "r5400")
126 (and (eq_attr "type" "fdiv,frdiv,fsqrt")
127 (eq_attr "mode" "SF")))
128 "vr54_dp0|vr54_dp1")
129
130 (define_insn_reservation "ir_vr54_fdiv_df" 72
131 (and (eq_attr "cpu" "r5400")
132 (and (eq_attr "type" "fdiv,frdiv,fsqrt")
133 (eq_attr "mode" "DF")))
134 "vr54_dp0|vr54_dp1")
135
136 (define_insn_reservation "ir_vr54_fabs" 2
137 (and (eq_attr "cpu" "r5400")
138 (eq_attr "type" "fabs,fneg,fmove"))
139 "vr54_dp0|vr54_dp1")
140
141 (define_insn_reservation "ir_vr54_fcmp" 2
142 (and (eq_attr "cpu" "r5400")
143 (eq_attr "type" "fcmp"))
144 "vr54_dp0|vr54_dp1")
145
146 (define_insn_reservation "ir_vr54_fcvt" 6
147 (and (eq_attr "cpu" "r5400")
148 (eq_attr "type" "fcvt"))
149 "vr54_dp0|vr54_dp1")
150
151 (define_insn_reservation "ir_vr54_frsqrt_sf" 61
152 (and (eq_attr "cpu" "r5400")
153 (and (eq_attr "type" "frsqrt")
154 (eq_attr "mode" "SF")))
155 "vr54_dp0|vr54_dp1")
156
157 (define_insn_reservation "ir_vr54_frsqrt_df" 121
158 (and (eq_attr "cpu" "r5400")
159 (and (eq_attr "type" "frsqrt")
160 (eq_attr "mode" "DF")))
161 "vr54_dp0|vr54_dp1")
162
163 (define_insn_reservation "ir_vr54_multi" 1
164 (and (eq_attr "cpu" "r5400")
165 (eq_attr "type" "multi"))
166 "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")