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comparison gcc/config/mips/5500.md @ 0:a06113de4d67

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first commit
author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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children 77e2b8dfacca
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-1:000000000000 0:a06113de4d67
1 ;; DFA-based pipeline description for 5500
2 (define_automaton "vr55")
3 (define_cpu_unit "vr55_dp0" "vr55")
4 (define_cpu_unit "vr55_dp1" "vr55")
5 (define_cpu_unit "vr55_mem" "vr55")
6 (define_cpu_unit "vr55_mac" "vr55")
7 (define_cpu_unit "vr55_fp" "vr55")
8 (define_cpu_unit "vr55_bru" "vr55")
9
10 ;;
11 ;; The ordering of the instruction-execution-path/resource-usage
12 ;; descriptions (also known as reservation RTL) is roughly ordered
13 ;; based on the define attribute RTL for the "type" classification.
14 ;; When modifying, remember that the first test that matches is the
15 ;; reservation used!
16 ;;
17
18 (define_insn_reservation "ir_vr55_unknown" 1
19 (and (eq_attr "cpu" "r5500")
20 (eq_attr "type" "unknown"))
21 "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru")
22
23 ;; Assume prediction fails.
24 (define_insn_reservation "ir_vr55_branch" 2
25 (and (eq_attr "cpu" "r5500")
26 (eq_attr "type" "branch,jump,call"))
27 "vr55_bru")
28
29 (define_insn_reservation "ir_vr55_load" 3
30 (and (eq_attr "cpu" "r5500")
31 (eq_attr "type" "load,fpload,fpidxload"))
32 "vr55_mem")
33
34 (define_bypass 4
35 "ir_vr55_load"
36 "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd,
37 ir_vr55_idiv_si,ir_vr55_idiv_di")
38
39 (define_insn_reservation "ir_vr55_store" 0
40 (and (eq_attr "cpu" "r5500")
41 (eq_attr "type" "store,fpstore,fpidxstore"))
42 "vr55_mem")
43
44 ;; This reservation is for conditional move based on integer
45 ;; or floating point CC.
46 (define_insn_reservation "ir_vr55_condmove" 2
47 (and (eq_attr "cpu" "r5500")
48 (eq_attr "type" "condmove"))
49 "vr55_dp0|vr55_dp1")
50
51 ;; Move to/from FPU registers
52 (define_insn_reservation "ir_vr55_xfer" 2
53 (and (eq_attr "cpu" "r5500")
54 (eq_attr "type" "mfc,mtc"))
55 "vr55_dp0|vr55_dp1")
56
57 (define_insn_reservation "ir_vr55_arith" 1
58 (and (eq_attr "cpu" "r5500")
59 (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap"))
60 "vr55_dp0|vr55_dp1")
61
62 (define_bypass 2
63 "ir_vr55_arith"
64 "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd,
65 ir_vr55_idiv_si,ir_vr55_idiv_di")
66
67 (define_insn_reservation "ir_vr55_mthilo" 1
68 (and (eq_attr "cpu" "r5500")
69 (eq_attr "type" "mthilo"))
70 "vr55_mac")
71
72 (define_insn_reservation "ir_vr55_mfhilo" 5
73 (and (eq_attr "cpu" "r5500")
74 (eq_attr "type" "mfhilo"))
75 "vr55_mac")
76
77 ;; The default latency is for the GPR result of a mul. Bypasses handle the
78 ;; latency of {mul,mult}->{mfhi,mflo}.
79 (define_insn_reservation "ir_vr55_imul_si" 5
80 (and (eq_attr "cpu" "r5500")
81 (and (eq_attr "type" "imul,imul3")
82 (eq_attr "mode" "SI")))
83 "vr55_mac")
84
85 ;; The default latency is for pre-reload scheduling and handles the case
86 ;; where a pseudo destination will be stored in a GPR (as it usually is).
87 ;; The delay includes the latency of the dmult itself and the anticipated
88 ;; mflo or mfhi.
89 ;;
90 ;; Once the mflo or mfhi has been created, bypasses handle the latency
91 ;; between it and the dmult.
92 (define_insn_reservation "ir_vr55_imul_di" 9
93 (and (eq_attr "cpu" "r5500")
94 (and (eq_attr "type" "imul,imul3")
95 (eq_attr "mode" "DI")))
96 "vr55_mac*4")
97
98 ;; The default latency is as for ir_vr55_imul_si.
99 (define_insn_reservation "ir_vr55_imadd" 5
100 (and (eq_attr "cpu" "r5500")
101 (eq_attr "type" "imadd"))
102 "vr55_mac")
103
104 (define_bypass 1
105 "ir_vr55_imul_si,ir_vr55_imadd"
106 "ir_vr55_imadd"
107 "mips_linked_madd_p")
108
109 (define_bypass 2
110 "ir_vr55_imul_si,ir_vr55_imadd"
111 "ir_vr55_mfhilo")
112
113 (define_bypass 4
114 "ir_vr55_imul_di"
115 "ir_vr55_mfhilo")
116
117 ;; Divide algorithm is early out with best latency of 7 pcycles.
118 ;; Use worst case for scheduling purposes.
119 (define_insn_reservation "ir_vr55_idiv_si" 42
120 (and (eq_attr "cpu" "r5500")
121 (and (eq_attr "type" "idiv")
122 (eq_attr "mode" "SI")))
123 "vr55_mac")
124
125 (define_insn_reservation "ir_vr55_idiv_di" 74
126 (and (eq_attr "cpu" "r5500")
127 (and (eq_attr "type" "idiv")
128 (eq_attr "mode" "DI")))
129 "vr55_mac")
130
131 (define_insn_reservation "ir_vr55_fadd" 4
132 (and (eq_attr "cpu" "r5500")
133 (eq_attr "type" "fadd"))
134 "vr55_fp")
135
136 (define_insn_reservation "ir_vr55_fmul_sf" 5
137 (and (eq_attr "cpu" "r5500")
138 (and (eq_attr "type" "fmul")
139 (eq_attr "mode" "SF")))
140 "vr55_mac")
141
142 (define_insn_reservation "ir_vr55_fmul_df" 6
143 (and (eq_attr "cpu" "r5500")
144 (and (eq_attr "type" "fmul")
145 (eq_attr "mode" "DF")))
146 "vr55_mac")
147
148 (define_insn_reservation "ir_vr55_fmadd_sf" 9
149 (and (eq_attr "cpu" "r5500")
150 (and (eq_attr "type" "fmadd")
151 (eq_attr "mode" "SF")))
152 "vr55_mac")
153
154 (define_insn_reservation "ir_vr55_fmadd_df" 10
155 (and (eq_attr "cpu" "r5500")
156 (and (eq_attr "type" "fmadd")
157 (eq_attr "mode" "DF")))
158 "vr55_mac")
159
160 (define_insn_reservation "ir_vr55_fdiv_sf" 30
161 (and (eq_attr "cpu" "r5500")
162 (and (eq_attr "type" "fdiv,frdiv,fsqrt")
163 (eq_attr "mode" "SF")))
164 "vr55_mac")
165
166 (define_insn_reservation "ir_vr55_fdiv_df" 59
167 (and (eq_attr "cpu" "r5500")
168 (and (eq_attr "type" "fdiv,frdiv,fsqrt")
169 (eq_attr "mode" "DF")))
170 "vr55_mac")
171
172 (define_insn_reservation "ir_vr55_fabs" 2
173 (and (eq_attr "cpu" "r5500")
174 (eq_attr "type" "fabs,fneg,fmove"))
175 "vr55_fp")
176
177 (define_insn_reservation "ir_vr55_fcmp" 2
178 (and (eq_attr "cpu" "r5500")
179 (eq_attr "type" "fcmp"))
180 "vr55_fp")
181
182 (define_insn_reservation "ir_vr55_fcvt_sf" 4
183 (and (eq_attr "cpu" "r5500")
184 (and (eq_attr "type" "fcvt")
185 (eq_attr "mode" "SF")))
186 "vr55_fp")
187
188 (define_insn_reservation "ir_vr55_fcvt_df" 6
189 (and (eq_attr "cpu" "r5500")
190 (and (eq_attr "type" "fcvt")
191 (eq_attr "mode" "DF")))
192 "vr55_fp")
193
194 (define_insn_reservation "ir_vr55_frsqrt_sf" 60
195 (and (eq_attr "cpu" "r5500")
196 (and (eq_attr "type" "frsqrt")
197 (eq_attr "mode" "SF")))
198 "vr55_mac")
199
200 (define_insn_reservation "ir_vr55_frsqrt_df" 118
201 (and (eq_attr "cpu" "r5500")
202 (and (eq_attr "type" "frsqrt")
203 (eq_attr "mode" "DF")))
204 "vr55_mac")
205
206 (define_insn_reservation "ir_vr55_multi" 1
207 (and (eq_attr "cpu" "r5500")
208 (eq_attr "type" "multi"))
209 "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru")