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comparison gcc/config/mips/mips-ps-3d.md @ 0:a06113de4d67

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author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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-1:000000000000 0:a06113de4d67
1 ;; MIPS Paired-Single Floating and MIPS-3D Instructions.
2 ;; Copyright (C) 2004, 2007 Free Software Foundation, Inc.
3 ;;
4 ;; This file is part of GCC.
5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
9 ;; any later version.
10 ;;
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
15 ;;
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
19
20 (define_insn "*movcc_v2sf_<mode>"
21 [(set (match_operand:V2SF 0 "register_operand" "=f,f")
22 (if_then_else:V2SF
23 (match_operator:GPR 4 "equality_operator"
24 [(match_operand:GPR 1 "register_operand" "d,d")
25 (const_int 0)])
26 (match_operand:V2SF 2 "register_operand" "f,0")
27 (match_operand:V2SF 3 "register_operand" "0,f")))]
28 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
29 "@
30 mov%T4.ps\t%0,%2,%1
31 mov%t4.ps\t%0,%3,%1"
32 [(set_attr "type" "condmove")
33 (set_attr "mode" "SF")])
34
35 (define_insn "mips_cond_move_tf_ps"
36 [(set (match_operand:V2SF 0 "register_operand" "=f,f")
37 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f,0")
38 (match_operand:V2SF 2 "register_operand" "0,f")
39 (match_operand:CCV2 3 "register_operand" "z,z")]
40 UNSPEC_MOVE_TF_PS))]
41 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
42 "@
43 movt.ps\t%0,%1,%3
44 movf.ps\t%0,%2,%3"
45 [(set_attr "type" "condmove")
46 (set_attr "mode" "SF")])
47
48 (define_expand "movv2sfcc"
49 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
50 (set (match_operand:V2SF 0 "register_operand")
51 (if_then_else:V2SF (match_dup 5)
52 (match_operand:V2SF 2 "register_operand")
53 (match_operand:V2SF 3 "register_operand")))]
54 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
55 {
56 /* We can only support MOVN.PS and MOVZ.PS.
57 NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and
58 MOVZ.PS. MOVT.PS and MOVF.PS depend on two CC values and move
59 each item independently. */
60
61 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
62 FAIL;
63
64 mips_expand_conditional_move (operands);
65 DONE;
66 })
67
68 ; pul.ps - Pair Upper Lower
69 (define_insn "mips_pul_ps"
70 [(set (match_operand:V2SF 0 "register_operand" "=f")
71 (vec_merge:V2SF
72 (match_operand:V2SF 1 "register_operand" "f")
73 (match_operand:V2SF 2 "register_operand" "f")
74 (const_int 2)))]
75 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
76 "pul.ps\t%0,%1,%2"
77 [(set_attr "type" "fmove")
78 (set_attr "mode" "SF")])
79
80 ; puu.ps - Pair upper upper
81 (define_insn "mips_puu_ps"
82 [(set (match_operand:V2SF 0 "register_operand" "=f")
83 (vec_merge:V2SF
84 (match_operand:V2SF 1 "register_operand" "f")
85 (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f")
86 (parallel [(const_int 1)
87 (const_int 0)]))
88 (const_int 2)))]
89 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
90 "puu.ps\t%0,%1,%2"
91 [(set_attr "type" "fmove")
92 (set_attr "mode" "SF")])
93
94 ; pll.ps - Pair Lower Lower
95 (define_insn "mips_pll_ps"
96 [(set (match_operand:V2SF 0 "register_operand" "=f")
97 (vec_merge:V2SF
98 (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f")
99 (parallel [(const_int 1)
100 (const_int 0)]))
101 (match_operand:V2SF 2 "register_operand" "f")
102 (const_int 2)))]
103 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
104 "pll.ps\t%0,%1,%2"
105 [(set_attr "type" "fmove")
106 (set_attr "mode" "SF")])
107
108 ; plu.ps - Pair Lower Upper
109 (define_insn "mips_plu_ps"
110 [(set (match_operand:V2SF 0 "register_operand" "=f")
111 (vec_merge:V2SF
112 (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f")
113 (parallel [(const_int 1)
114 (const_int 0)]))
115 (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f")
116 (parallel [(const_int 1)
117 (const_int 0)]))
118 (const_int 2)))]
119 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
120 "plu.ps\t%0,%1,%2"
121 [(set_attr "type" "fmove")
122 (set_attr "mode" "SF")])
123
124 ; vec_init
125 (define_expand "vec_initv2sf"
126 [(match_operand:V2SF 0 "register_operand")
127 (match_operand:V2SF 1 "")]
128 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
129 {
130 rtx op0 = force_reg (SFmode, XVECEXP (operands[1], 0, 0));
131 rtx op1 = force_reg (SFmode, XVECEXP (operands[1], 0, 1));
132 emit_insn (gen_vec_initv2sf_internal (operands[0], op0, op1));
133 DONE;
134 })
135
136 (define_insn "vec_initv2sf_internal"
137 [(set (match_operand:V2SF 0 "register_operand" "=f")
138 (vec_concat:V2SF
139 (match_operand:SF 1 "register_operand" "f")
140 (match_operand:SF 2 "register_operand" "f")))]
141 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
142 {
143 if (BYTES_BIG_ENDIAN)
144 return "cvt.ps.s\t%0,%1,%2";
145 else
146 return "cvt.ps.s\t%0,%2,%1";
147 }
148 [(set_attr "type" "fcvt")
149 (set_attr "mode" "SF")])
150
151 ;; ??? This is only generated if we perform a vector operation that has to be
152 ;; emulated. There is no other way to get a vector mode bitfield extract
153 ;; currently.
154
155 (define_insn "vec_extractv2sf"
156 [(set (match_operand:SF 0 "register_operand" "=f")
157 (vec_select:SF (match_operand:V2SF 1 "register_operand" "f")
158 (parallel
159 [(match_operand 2 "const_0_or_1_operand" "")])))]
160 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
161 {
162 if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN)
163 return "cvt.s.pu\t%0,%1";
164 else
165 return "cvt.s.pl\t%0,%1";
166 }
167 [(set_attr "type" "fcvt")
168 (set_attr "mode" "SF")])
169
170 ;; ??? This is only generated if we disable the vec_init pattern. There is
171 ;; no other way to get a vector mode bitfield store currently.
172
173 (define_expand "vec_setv2sf"
174 [(match_operand:V2SF 0 "register_operand")
175 (match_operand:SF 1 "register_operand")
176 (match_operand 2 "const_0_or_1_operand")]
177 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
178 {
179 rtx temp;
180
181 /* We don't have an insert instruction, so we duplicate the float, and
182 then use a PUL instruction. */
183 temp = gen_reg_rtx (V2SFmode);
184 emit_insn (gen_mips_cvt_ps_s (temp, operands[1], operands[1]));
185 if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN)
186 emit_insn (gen_mips_pul_ps (operands[0], temp, operands[0]));
187 else
188 emit_insn (gen_mips_pul_ps (operands[0], operands[0], temp));
189 DONE;
190 })
191
192 ; cvt.ps.s - Floating Point Convert Pair to Paired Single
193 (define_expand "mips_cvt_ps_s"
194 [(match_operand:V2SF 0 "register_operand")
195 (match_operand:SF 1 "register_operand")
196 (match_operand:SF 2 "register_operand")]
197 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
198 {
199 if (BYTES_BIG_ENDIAN)
200 emit_insn (gen_vec_initv2sf_internal (operands[0], operands[1],
201 operands[2]));
202 else
203 emit_insn (gen_vec_initv2sf_internal (operands[0], operands[2],
204 operands[1]));
205 DONE;
206 })
207
208 ; cvt.s.pl - Floating Point Convert Pair Lower to Single Floating Point
209 (define_expand "mips_cvt_s_pl"
210 [(set (match_operand:SF 0 "register_operand")
211 (vec_select:SF (match_operand:V2SF 1 "register_operand")
212 (parallel [(match_dup 2)])))]
213 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
214 { operands[2] = GEN_INT (BYTES_BIG_ENDIAN); })
215
216 ; cvt.s.pu - Floating Point Convert Pair Upper to Single Floating Point
217 (define_expand "mips_cvt_s_pu"
218 [(set (match_operand:SF 0 "register_operand")
219 (vec_select:SF (match_operand:V2SF 1 "register_operand")
220 (parallel [(match_dup 2)])))]
221 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
222 { operands[2] = GEN_INT (!BYTES_BIG_ENDIAN); })
223
224 ; alnv.ps - Floating Point Align Variable
225 (define_insn "mips_alnv_ps"
226 [(set (match_operand:V2SF 0 "register_operand" "=f")
227 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
228 (match_operand:V2SF 2 "register_operand" "f")
229 (match_operand:SI 3 "register_operand" "d")]
230 UNSPEC_ALNV_PS))]
231 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
232 "alnv.ps\t%0,%1,%2,%3"
233 [(set_attr "type" "fmove")
234 (set_attr "mode" "SF")])
235
236 ; addr.ps - Floating Point Reduction Add
237 (define_insn "mips_addr_ps"
238 [(set (match_operand:V2SF 0 "register_operand" "=f")
239 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
240 (match_operand:V2SF 2 "register_operand" "f")]
241 UNSPEC_ADDR_PS))]
242 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
243 "addr.ps\t%0,%1,%2"
244 [(set_attr "type" "fadd")
245 (set_attr "mode" "SF")])
246
247 ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word
248 (define_insn "mips_cvt_pw_ps"
249 [(set (match_operand:V2SF 0 "register_operand" "=f")
250 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
251 UNSPEC_CVT_PW_PS))]
252 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
253 "cvt.pw.ps\t%0,%1"
254 [(set_attr "type" "fcvt")
255 (set_attr "mode" "SF")])
256
257 ; cvt.ps.pw - Floating Point Convert Paired Word to Paired Single
258 (define_insn "mips_cvt_ps_pw"
259 [(set (match_operand:V2SF 0 "register_operand" "=f")
260 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
261 UNSPEC_CVT_PS_PW))]
262 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
263 "cvt.ps.pw\t%0,%1"
264 [(set_attr "type" "fcvt")
265 (set_attr "mode" "SF")])
266
267 ; mulr.ps - Floating Point Reduction Multiply
268 (define_insn "mips_mulr_ps"
269 [(set (match_operand:V2SF 0 "register_operand" "=f")
270 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
271 (match_operand:V2SF 2 "register_operand" "f")]
272 UNSPEC_MULR_PS))]
273 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
274 "mulr.ps\t%0,%1,%2"
275 [(set_attr "type" "fmul")
276 (set_attr "mode" "SF")])
277
278 ; abs.ps
279 (define_expand "mips_abs_ps"
280 [(set (match_operand:V2SF 0 "register_operand")
281 (unspec:V2SF [(match_operand:V2SF 1 "register_operand")]
282 UNSPEC_ABS_PS))]
283 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
284 {
285 /* If we can ignore NaNs, this operation is equivalent to the
286 rtl ABS code. */
287 if (!HONOR_NANS (V2SFmode))
288 {
289 emit_insn (gen_absv2sf2 (operands[0], operands[1]));
290 DONE;
291 }
292 })
293
294 (define_insn "*mips_abs_ps"
295 [(set (match_operand:V2SF 0 "register_operand" "=f")
296 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
297 UNSPEC_ABS_PS))]
298 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
299 "abs.ps\t%0,%1"
300 [(set_attr "type" "fabs")
301 (set_attr "mode" "SF")])
302
303 ;----------------------------------------------------------------------------
304 ; Floating Point Comparisons for Scalars
305 ;----------------------------------------------------------------------------
306
307 (define_insn "mips_cabs_cond_<fmt>"
308 [(set (match_operand:CC 0 "register_operand" "=z")
309 (unspec:CC [(match_operand:SCALARF 1 "register_operand" "f")
310 (match_operand:SCALARF 2 "register_operand" "f")
311 (match_operand 3 "const_int_operand" "")]
312 UNSPEC_CABS))]
313 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
314 "cabs.%Y3.<fmt>\t%0,%1,%2"
315 [(set_attr "type" "fcmp")
316 (set_attr "mode" "FPSW")])
317
318
319 ;----------------------------------------------------------------------------
320 ; Floating Point Comparisons for Four Singles
321 ;----------------------------------------------------------------------------
322
323 (define_insn_and_split "mips_c_cond_4s"
324 [(set (match_operand:CCV4 0 "register_operand" "=z")
325 (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f")
326 (match_operand:V2SF 2 "register_operand" "f")
327 (match_operand:V2SF 3 "register_operand" "f")
328 (match_operand:V2SF 4 "register_operand" "f")
329 (match_operand 5 "const_int_operand" "")]
330 UNSPEC_C))]
331 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
332 "#"
333 "&& reload_completed"
334 [(set (match_dup 6)
335 (unspec:CCV2 [(match_dup 1)
336 (match_dup 2)
337 (match_dup 5)]
338 UNSPEC_C))
339 (set (match_dup 7)
340 (unspec:CCV2 [(match_dup 3)
341 (match_dup 4)
342 (match_dup 5)]
343 UNSPEC_C))]
344 {
345 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0);
346 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
347 }
348 [(set_attr "type" "fcmp")
349 (set_attr "length" "8")
350 (set_attr "mode" "FPSW")])
351
352 (define_insn_and_split "mips_cabs_cond_4s"
353 [(set (match_operand:CCV4 0 "register_operand" "=z")
354 (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f")
355 (match_operand:V2SF 2 "register_operand" "f")
356 (match_operand:V2SF 3 "register_operand" "f")
357 (match_operand:V2SF 4 "register_operand" "f")
358 (match_operand 5 "const_int_operand" "")]
359 UNSPEC_CABS))]
360 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
361 "#"
362 "&& reload_completed"
363 [(set (match_dup 6)
364 (unspec:CCV2 [(match_dup 1)
365 (match_dup 2)
366 (match_dup 5)]
367 UNSPEC_CABS))
368 (set (match_dup 7)
369 (unspec:CCV2 [(match_dup 3)
370 (match_dup 4)
371 (match_dup 5)]
372 UNSPEC_CABS))]
373 {
374 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0);
375 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
376 }
377 [(set_attr "type" "fcmp")
378 (set_attr "length" "8")
379 (set_attr "mode" "FPSW")])
380
381
382 ;----------------------------------------------------------------------------
383 ; Floating Point Comparisons for Paired Singles
384 ;----------------------------------------------------------------------------
385
386 (define_insn "mips_c_cond_ps"
387 [(set (match_operand:CCV2 0 "register_operand" "=z")
388 (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f")
389 (match_operand:V2SF 2 "register_operand" "f")
390 (match_operand 3 "const_int_operand" "")]
391 UNSPEC_C))]
392 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
393 "c.%Y3.ps\t%0,%1,%2"
394 [(set_attr "type" "fcmp")
395 (set_attr "mode" "FPSW")])
396
397 (define_insn "mips_cabs_cond_ps"
398 [(set (match_operand:CCV2 0 "register_operand" "=z")
399 (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f")
400 (match_operand:V2SF 2 "register_operand" "f")
401 (match_operand 3 "const_int_operand" "")]
402 UNSPEC_CABS))]
403 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
404 "cabs.%Y3.ps\t%0,%1,%2"
405 [(set_attr "type" "fcmp")
406 (set_attr "mode" "FPSW")])
407
408 ;; An expander for generating an scc operation.
409 (define_expand "scc_ps"
410 [(set (match_operand:CCV2 0)
411 (unspec:CCV2 [(match_operand 1)] UNSPEC_SCC))])
412
413 (define_insn "s<code>_ps"
414 [(set (match_operand:CCV2 0 "register_operand" "=z")
415 (unspec:CCV2
416 [(fcond (match_operand:V2SF 1 "register_operand" "f")
417 (match_operand:V2SF 2 "register_operand" "f"))]
418 UNSPEC_SCC))]
419 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
420 "c.<fcond>.ps\t%0,%1,%2"
421 [(set_attr "type" "fcmp")
422 (set_attr "mode" "FPSW")])
423
424 (define_insn "s<code>_ps"
425 [(set (match_operand:CCV2 0 "register_operand" "=z")
426 (unspec:CCV2
427 [(swapped_fcond (match_operand:V2SF 1 "register_operand" "f")
428 (match_operand:V2SF 2 "register_operand" "f"))]
429 UNSPEC_SCC))]
430 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
431 "c.<swapped_fcond>.ps\t%0,%2,%1"
432 [(set_attr "type" "fcmp")
433 (set_attr "mode" "FPSW")])
434
435 ;----------------------------------------------------------------------------
436 ; Floating Point Branch Instructions.
437 ;----------------------------------------------------------------------------
438
439 ; Branch on Any of Four Floating Point Condition Codes True
440 (define_insn "bc1any4t"
441 [(set (pc)
442 (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z")
443 (const_int 0))
444 (label_ref (match_operand 1 "" ""))
445 (pc)))]
446 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
447 "%*bc1any4t\t%0,%1%/"
448 [(set_attr "type" "branch")
449 (set_attr "mode" "none")])
450
451 ; Branch on Any of Four Floating Point Condition Codes False
452 (define_insn "bc1any4f"
453 [(set (pc)
454 (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z")
455 (const_int -1))
456 (label_ref (match_operand 1 "" ""))
457 (pc)))]
458 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
459 "%*bc1any4f\t%0,%1%/"
460 [(set_attr "type" "branch")
461 (set_attr "mode" "none")])
462
463 ; Branch on Any of Two Floating Point Condition Codes True
464 (define_insn "bc1any2t"
465 [(set (pc)
466 (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z")
467 (const_int 0))
468 (label_ref (match_operand 1 "" ""))
469 (pc)))]
470 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
471 "%*bc1any2t\t%0,%1%/"
472 [(set_attr "type" "branch")
473 (set_attr "mode" "none")])
474
475 ; Branch on Any of Two Floating Point Condition Codes False
476 (define_insn "bc1any2f"
477 [(set (pc)
478 (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z")
479 (const_int -1))
480 (label_ref (match_operand 1 "" ""))
481 (pc)))]
482 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
483 "%*bc1any2f\t%0,%1%/"
484 [(set_attr "type" "branch")
485 (set_attr "mode" "none")])
486
487 ; Used to access one register in a CCV2 pair. Operand 0 is the register
488 ; pair and operand 1 is the index of the register we want (a CONST_INT).
489 (define_expand "single_cc"
490 [(ne (unspec:CC [(match_operand 0) (match_operand 1)] UNSPEC_SINGLE_CC)
491 (const_int 0))])
492
493 ; This is a normal floating-point branch pattern, but rather than check
494 ; a single CCmode register, it checks one register in a CCV2 pair.
495 ; Operand 2 is the register pair and operand 3 is the index of the
496 ; register we want.
497 (define_insn "*branch_upper_lower"
498 [(set (pc)
499 (if_then_else
500 (match_operator 0 "equality_operator"
501 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
502 (match_operand 3 "const_int_operand")]
503 UNSPEC_SINGLE_CC)
504 (const_int 0)])
505 (label_ref (match_operand 1 "" ""))
506 (pc)))]
507 "TARGET_HARD_FLOAT"
508 {
509 operands[2]
510 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
511 return mips_output_conditional_branch (insn, operands,
512 MIPS_BRANCH ("b%F0", "%2,%1"),
513 MIPS_BRANCH ("b%W0", "%2,%1"));
514 }
515 [(set_attr "type" "branch")
516 (set_attr "mode" "none")])
517
518 ; As above, but with the sense of the condition reversed.
519 (define_insn "*branch_upper_lower_inverted"
520 [(set (pc)
521 (if_then_else
522 (match_operator 0 "equality_operator"
523 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
524 (match_operand 3 "const_int_operand")]
525 UNSPEC_SINGLE_CC)
526 (const_int 0)])
527 (pc)
528 (label_ref (match_operand 1 "" ""))))]
529 "TARGET_HARD_FLOAT"
530 {
531 operands[2]
532 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
533 return mips_output_conditional_branch (insn, operands,
534 MIPS_BRANCH ("b%W0", "%2,%1"),
535 MIPS_BRANCH ("b%F0", "%2,%1"));
536 }
537 [(set_attr "type" "branch")
538 (set_attr "mode" "none")])
539
540 ;----------------------------------------------------------------------------
541 ; Floating Point Reduced Precision Reciprocal Square Root Instructions.
542 ;----------------------------------------------------------------------------
543
544 (define_insn "mips_rsqrt1_<fmt>"
545 [(set (match_operand:ANYF 0 "register_operand" "=f")
546 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
547 UNSPEC_RSQRT1))]
548 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
549 "rsqrt1.<fmt>\t%0,%1"
550 [(set_attr "type" "frsqrt1")
551 (set_attr "mode" "<UNITMODE>")])
552
553 (define_insn "mips_rsqrt2_<fmt>"
554 [(set (match_operand:ANYF 0 "register_operand" "=f")
555 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
556 (match_operand:ANYF 2 "register_operand" "f")]
557 UNSPEC_RSQRT2))]
558 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
559 "rsqrt2.<fmt>\t%0,%1,%2"
560 [(set_attr "type" "frsqrt2")
561 (set_attr "mode" "<UNITMODE>")])
562
563 (define_insn "mips_recip1_<fmt>"
564 [(set (match_operand:ANYF 0 "register_operand" "=f")
565 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
566 UNSPEC_RECIP1))]
567 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
568 "recip1.<fmt>\t%0,%1"
569 [(set_attr "type" "frdiv1")
570 (set_attr "mode" "<UNITMODE>")])
571
572 (define_insn "mips_recip2_<fmt>"
573 [(set (match_operand:ANYF 0 "register_operand" "=f")
574 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
575 (match_operand:ANYF 2 "register_operand" "f")]
576 UNSPEC_RECIP2))]
577 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
578 "recip2.<fmt>\t%0,%1,%2"
579 [(set_attr "type" "frdiv2")
580 (set_attr "mode" "<UNITMODE>")])
581
582 (define_expand "vcondv2sf"
583 [(set (match_operand:V2SF 0 "register_operand")
584 (if_then_else:V2SF
585 (match_operator 3 ""
586 [(match_operand:V2SF 4 "register_operand")
587 (match_operand:V2SF 5 "register_operand")])
588 (match_operand:V2SF 1 "register_operand")
589 (match_operand:V2SF 2 "register_operand")))]
590 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
591 {
592 mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
593 GET_CODE (operands[3]), operands[4], operands[5]);
594 DONE;
595 })
596
597 (define_expand "sminv2sf3"
598 [(set (match_operand:V2SF 0 "register_operand")
599 (smin:V2SF (match_operand:V2SF 1 "register_operand")
600 (match_operand:V2SF 2 "register_operand")))]
601 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
602 {
603 mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
604 LE, operands[1], operands[2]);
605 DONE;
606 })
607
608 (define_expand "smaxv2sf3"
609 [(set (match_operand:V2SF 0 "register_operand")
610 (smax:V2SF (match_operand:V2SF 1 "register_operand")
611 (match_operand:V2SF 2 "register_operand")))]
612 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
613 {
614 mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
615 LE, operands[2], operands[1]);
616 DONE;
617 })