Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/mips/sb1.md @ 0:a06113de4d67
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author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
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date | Fri, 17 Jul 2009 14:47:48 +0900 |
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children | 77e2b8dfacca |
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1 ;; | |
2 ;; DFA-based pipeline description for Broadcom SB-1 | |
3 ;; | |
4 | |
5 ;; The Broadcom SB-1 core is 4-way superscalar, in-order. It has 2 load/store | |
6 ;; pipes (one of which can support some ALU operations), 2 alu pipes, 2 FP | |
7 ;; pipes, and 1 MDMX pipes. It can issue 2 ls insns and 2 exe/fpu/mdmx insns | |
8 ;; each cycle. | |
9 | |
10 ;; We model the 4-way issue by ordering unit choices. The possible choices are | |
11 ;; {ex1,fp1}|{ex0,fp0}|ls1|ls0. Instructions issue to the first eligible unit | |
12 ;; in the list in most cases. Non-indexed load/stores issue to ls0 first. | |
13 ;; simple alu operations issue to ls1 if it is still available, and their | |
14 ;; operands are ready (no co-issue with loads), otherwise to the first | |
15 ;; available ex unit. | |
16 | |
17 ;; When exceptions are enabled, can only issue FP insns to fp1. This is | |
18 ;; to ensure that instructions complete in order. The -mfp-exceptions option | |
19 ;; can be used to specify whether the system has FP exceptions enabled or not. | |
20 | |
21 ;; In 32-bit mode, dependent FP can't co-issue with load, and only one FP exe | |
22 ;; insn can issue per cycle (fp1). | |
23 | |
24 ;; The A1 MDMX pipe is separate from the FP pipes, but uses the same register | |
25 ;; file. As a result, once an MDMX insn is issued, no FP insns can be issued | |
26 ;; for 3 cycles. When an FP insn is issued, no MDMX insn can be issued for | |
27 ;; 5 cycles. This is currently not handled because there is no MDMX insn | |
28 ;; support as yet. | |
29 | |
30 ;; | |
31 ;; We use two automata. sb1_cpu_div is for the integer divides, which are | |
32 ;; not pipelined. sb1_cpu is for everything else. | |
33 ;; | |
34 (define_automaton "sb1_cpu, sb1_cpu_div") | |
35 | |
36 ;; Load/store function units. | |
37 (define_cpu_unit "sb1_ls0" "sb1_cpu") | |
38 (define_cpu_unit "sb1_ls1" "sb1_cpu") | |
39 | |
40 ;; CPU function units. | |
41 (define_cpu_unit "sb1_ex0" "sb1_cpu") | |
42 (define_cpu_unit "sb1_ex1" "sb1_cpu") | |
43 | |
44 ;; The divide unit is not pipelined, and blocks hi/lo reads and writes. | |
45 (define_cpu_unit "sb1_div" "sb1_cpu_div") | |
46 ;; DMULT block any multiply from issuing in the next cycle. | |
47 (define_cpu_unit "sb1_mul" "sb1_cpu") | |
48 | |
49 ;; Floating-point units. | |
50 (define_cpu_unit "sb1_fp0" "sb1_cpu") | |
51 (define_cpu_unit "sb1_fp1" "sb1_cpu") | |
52 | |
53 ;; Can only issue to one of the ex and fp pipes at a time. | |
54 (exclusion_set "sb1_ex0" "sb1_fp0") | |
55 (exclusion_set "sb1_ex1" "sb1_fp1") | |
56 | |
57 ;; Define an SB-1 specific attribute to simplify some FP descriptions. | |
58 ;; We can use 2 FP pipes only if we have 64-bit FP code, and exceptions are | |
59 ;; disabled. | |
60 | |
61 (define_attr "sb1_fp_pipes" "one,two" | |
62 (cond [(and (ne (symbol_ref "TARGET_FLOAT64") (const_int 0)) | |
63 (eq (symbol_ref "TARGET_FP_EXCEPTIONS") (const_int 0))) | |
64 (const_string "two")] | |
65 (const_string "one"))) | |
66 | |
67 ;; Define reservations for common combinations. | |
68 | |
69 ;; For long cycle operations, the FPU has a 4 cycle pipeline that repeats, | |
70 ;; effectively re-issuing the operation every 4 cycles. This means that we | |
71 ;; can have at most 4 long-cycle operations per pipe. | |
72 | |
73 ;; ??? The fdiv operations should be e.g. | |
74 ;; sb1_fp1_4cycles*7" | "sb1_fp0_4cycle*7 | |
75 ;; but the DFA is too large when we do that. Perhaps have to use scheduler | |
76 ;; hooks here. | |
77 | |
78 ;; ??? Try limiting scheduler to 2 long latency operations, and see if this | |
79 ;; results in a usable DFA, and whether it helps code performance. | |
80 | |
81 ;;(define_reservation "sb1_fp0_4cycles" "sb1_fp0, nothing*3") | |
82 ;;(define_reservation "sb1_fp1_4cycles" "sb1_fp1, nothing*3") | |
83 | |
84 ;; | |
85 ;; The ordering of the instruction-execution-path/resource-usage | |
86 ;; descriptions (also known as reservation RTL) is roughly ordered | |
87 ;; based on the define attribute RTL for the "type" classification. | |
88 ;; When modifying, remember that the first test that matches is the | |
89 ;; reservation used! | |
90 ;; | |
91 | |
92 (define_insn_reservation "ir_sb1_unknown" 1 | |
93 (and (eq_attr "cpu" "sb1,sb1a") | |
94 (eq_attr "type" "unknown,multi")) | |
95 "sb1_ls0+sb1_ls1+sb1_ex0+sb1_ex1+sb1_fp0+sb1_fp1") | |
96 | |
97 ;; predicted taken branch causes 2 cycle ifetch bubble. predicted not | |
98 ;; taken branch causes 0 cycle ifetch bubble. mispredicted branch causes 8 | |
99 ;; cycle ifetch bubble. We assume all branches predicted not taken. | |
100 | |
101 ;; ??? This assumption that branches are predicated not taken should be | |
102 ;; investigated. Maybe using 2 here will give better results. | |
103 | |
104 (define_insn_reservation "ir_sb1_branch" 0 | |
105 (and (eq_attr "cpu" "sb1,sb1a") | |
106 (eq_attr "type" "branch,jump,call")) | |
107 "sb1_ex0") | |
108 | |
109 ;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data | |
110 ;; register as destination. | |
111 | |
112 ;; ??? SB-1 can co-issue a load with a dependent arith insn if it executes on | |
113 ;; an EX unit. Can not co-issue if the dependent insn executes on an LS unit. | |
114 ;; SB-1A can always co-issue here. | |
115 | |
116 ;; A load normally has a latency of zero cycles. In some cases, dependent | |
117 ;; insns can be issued in the same cycle. However, a value of 1 gives | |
118 ;; better performance in empirical testing. | |
119 | |
120 (define_insn_reservation "ir_sb1_load" 1 | |
121 (and (eq_attr "cpu" "sb1") | |
122 (eq_attr "type" "load,prefetch")) | |
123 "sb1_ls0 | sb1_ls1") | |
124 | |
125 (define_insn_reservation "ir_sb1a_load" 0 | |
126 (and (eq_attr "cpu" "sb1a") | |
127 (eq_attr "type" "load,prefetch")) | |
128 "sb1_ls0 | sb1_ls1") | |
129 | |
130 ;; Can not co-issue fpload with fp exe when in 32-bit mode. | |
131 | |
132 (define_insn_reservation "ir_sb1_fpload" 0 | |
133 (and (eq_attr "cpu" "sb1,sb1a") | |
134 (and (eq_attr "type" "fpload") | |
135 (ne (symbol_ref "TARGET_FLOAT64") | |
136 (const_int 0)))) | |
137 "sb1_ls0 | sb1_ls1") | |
138 | |
139 (define_insn_reservation "ir_sb1_fpload_32bitfp" 1 | |
140 (and (eq_attr "cpu" "sb1,sb1a") | |
141 (and (eq_attr "type" "fpload") | |
142 (eq (symbol_ref "TARGET_FLOAT64") | |
143 (const_int 0)))) | |
144 "sb1_ls0 | sb1_ls1") | |
145 | |
146 ;; Indexed loads can only execute on LS1 pipe. | |
147 | |
148 (define_insn_reservation "ir_sb1_fpidxload" 0 | |
149 (and (eq_attr "cpu" "sb1,sb1a") | |
150 (and (eq_attr "type" "fpidxload") | |
151 (ne (symbol_ref "TARGET_FLOAT64") | |
152 (const_int 0)))) | |
153 "sb1_ls1") | |
154 | |
155 (define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1 | |
156 (and (eq_attr "cpu" "sb1,sb1a") | |
157 (and (eq_attr "type" "fpidxload") | |
158 (eq (symbol_ref "TARGET_FLOAT64") | |
159 (const_int 0)))) | |
160 "sb1_ls1") | |
161 | |
162 ;; prefx can only execute on the ls1 pipe. | |
163 | |
164 (define_insn_reservation "ir_sb1_prefetchx" 0 | |
165 (and (eq_attr "cpu" "sb1,sb1a") | |
166 (eq_attr "type" "prefetchx")) | |
167 "sb1_ls1") | |
168 | |
169 ;; ??? There is a 4.5 cycle latency if a store is followed by a load, and | |
170 ;; there is a RAW dependency. | |
171 | |
172 (define_insn_reservation "ir_sb1_store" 1 | |
173 (and (eq_attr "cpu" "sb1,sb1a") | |
174 (eq_attr "type" "store")) | |
175 "sb1_ls0+sb1_ex1 | sb1_ls0+sb1_ex0 | sb1_ls1+sb1_ex1 | sb1_ls1+sb1_ex0") | |
176 | |
177 (define_insn_reservation "ir_sb1_fpstore" 1 | |
178 (and (eq_attr "cpu" "sb1,sb1a") | |
179 (eq_attr "type" "fpstore")) | |
180 "sb1_ls0+sb1_fp1 | sb1_ls0+sb1_fp0 | sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0") | |
181 | |
182 ;; Indexed stores can only execute on LS1 pipe. | |
183 | |
184 (define_insn_reservation "ir_sb1_fpidxstore" 1 | |
185 (and (eq_attr "cpu" "sb1,sb1a") | |
186 (eq_attr "type" "fpidxstore")) | |
187 "sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0") | |
188 | |
189 ;; Load latencies are 3 cycles for one load to another load or store (address | |
190 ;; only). This is 0 cycles for one load to a store using it as the data | |
191 ;; written. | |
192 | |
193 ;; This assumes that if a load is dependent on a previous insn, then it must | |
194 ;; be an address dependence. | |
195 | |
196 (define_bypass 3 | |
197 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, | |
198 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp" | |
199 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, | |
200 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") | |
201 | |
202 (define_bypass 3 | |
203 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, | |
204 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp" | |
205 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" | |
206 "mips_store_data_bypass_p") | |
207 | |
208 ;; On SB-1, simple alu instructions can execute on the LS1 unit. | |
209 | |
210 ;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX | |
211 ;; insn, to a store (for data), and to an xfer insn. It has 1 cycle latency to | |
212 ;; another LS insn (excluding store data). A simple alu insn issued on an EX | |
213 ;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding | |
214 ;; store data), otherwise a latency of 1 cycle. | |
215 | |
216 ;; ??? We cannot handle latencies properly for simple alu instructions | |
217 ;; within the DFA pipeline model. Latencies can be defined only from one | |
218 ;; insn reservation to another. We can't make them depend on which function | |
219 ;; unit was used. This isn't a DFA flaw. There is a conflict here, as we | |
220 ;; need to know the latency before we can determine which unit will be | |
221 ;; available, but we need to know which unit it is issued to before we can | |
222 ;; compute the latency. Perhaps this can be handled via scheduler hooks. | |
223 ;; This needs to be investigated. | |
224 | |
225 ;; ??? Optimal scheduling taking the LS units into account seems to require | |
226 ;; a pre-scheduling pass. We need to determine which instructions feed results | |
227 ;; into store/load addresses, and thus benefit most from being issued to the | |
228 ;; LS unit. Also, we need to prune the list to ensure we don't overschedule | |
229 ;; insns to the LS unit, and that we don't conflict with insns that need LS1 | |
230 ;; such as indexed loads. We then need to emit nops to ensure that simple | |
231 ;; alu instructions that are not supposed to be scheduled to LS1 don't | |
232 ;; accidentally end up there because LS1 is free when they are issued. This | |
233 ;; will be a lot of work, and it isn't clear how useful it will be. | |
234 | |
235 ;; Empirical testing shows that 2 gives the best result. | |
236 | |
237 (define_insn_reservation "ir_sb1_simple_alu" 2 | |
238 (and (eq_attr "cpu" "sb1") | |
239 (eq_attr "type" "const,arith,logical,move,signext")) | |
240 "sb1_ls1 | sb1_ex1 | sb1_ex0") | |
241 | |
242 ;; On SB-1A, simple alu instructions can not execute on the LS1 unit, and we | |
243 ;; have none of the above problems. | |
244 | |
245 (define_insn_reservation "ir_sb1a_simple_alu" 1 | |
246 (and (eq_attr "cpu" "sb1a") | |
247 (eq_attr "type" "const,arith,logical,move,signext")) | |
248 "sb1_ex1 | sb1_ex0") | |
249 | |
250 ;; ??? condmove also includes some FP instructions that execute on the FP | |
251 ;; units. This needs to be clarified. | |
252 | |
253 (define_insn_reservation "ir_sb1_alu" 1 | |
254 (and (eq_attr "cpu" "sb1,sb1a") | |
255 (eq_attr "type" "condmove,nop,shift")) | |
256 "sb1_ex1 | sb1_ex0") | |
257 | |
258 ;; These are type arith/darith that only execute on the EX0 unit. | |
259 | |
260 (define_insn_reservation "ir_sb1_alu_0" 1 | |
261 (and (eq_attr "cpu" "sb1,sb1a") | |
262 (eq_attr "type" "slt,clz,trap")) | |
263 "sb1_ex0") | |
264 | |
265 ;; An alu insn issued on an EX unit has a latency of 5 cycles when the | |
266 ;; result goes to a LS unit (excluding store data). | |
267 | |
268 ;; This assumes that if a load is dependent on a previous insn, then it must | |
269 ;; be an address dependence. | |
270 | |
271 (define_bypass 5 | |
272 "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo" | |
273 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, | |
274 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") | |
275 | |
276 (define_bypass 5 | |
277 "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo" | |
278 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" | |
279 "mips_store_data_bypass_p") | |
280 | |
281 ;; mf{hi,lo} is 1 cycle. | |
282 | |
283 (define_insn_reservation "ir_sb1_mfhi" 1 | |
284 (and (eq_attr "cpu" "sb1,sb1a") | |
285 (and (eq_attr "type" "mfhilo") | |
286 (not (match_operand 1 "lo_operand")))) | |
287 "sb1_ex1") | |
288 | |
289 (define_insn_reservation "ir_sb1_mflo" 1 | |
290 (and (eq_attr "cpu" "sb1,sb1a") | |
291 (and (eq_attr "type" "mfhilo") | |
292 (match_operand 1 "lo_operand"))) | |
293 "sb1_ex1") | |
294 | |
295 ;; mt{hi,lo} to mul/div is 4 cycles. | |
296 | |
297 (define_insn_reservation "ir_sb1_mthilo" 4 | |
298 (and (eq_attr "cpu" "sb1,sb1a") | |
299 (eq_attr "type" "mthilo")) | |
300 "sb1_ex1") | |
301 | |
302 ;; mt{hi,lo} to mf{hi,lo} is 3 cycles. | |
303 | |
304 (define_bypass 3 "ir_sb1_mthilo" "ir_sb1_mfhi,ir_sb1_mflo") | |
305 | |
306 ;; multiply latency to an EX operation is 3 cycles. | |
307 | |
308 ;; ??? Should check whether we need to make multiply conflict with moves | |
309 ;; to/from hilo registers. | |
310 | |
311 (define_insn_reservation "ir_sb1_mulsi" 3 | |
312 (and (eq_attr "cpu" "sb1,sb1a") | |
313 (and (eq_attr "type" "imul,imul3,imadd") | |
314 (eq_attr "mode" "SI"))) | |
315 "sb1_ex1+sb1_mul") | |
316 | |
317 ;; muldi to mfhi is 4 cycles. | |
318 ;; Blocks any other multiply insn issue for 1 cycle. | |
319 | |
320 (define_insn_reservation "ir_sb1_muldi" 4 | |
321 (and (eq_attr "cpu" "sb1,sb1a") | |
322 (and (eq_attr "type" "imul,imul3") | |
323 (eq_attr "mode" "DI"))) | |
324 "sb1_ex1+sb1_mul, sb1_mul") | |
325 | |
326 ;; muldi to mflo is 3 cycles. | |
327 | |
328 (define_bypass 3 "ir_sb1_muldi" "ir_sb1_mflo") | |
329 | |
330 ;; mul latency is 7 cycles if the result is used by any LS insn. | |
331 | |
332 ;; This assumes that if a load is dependent on a previous insn, then it must | |
333 ;; be an address dependence. | |
334 | |
335 (define_bypass 7 | |
336 "ir_sb1_mulsi,ir_sb1_muldi" | |
337 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, | |
338 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") | |
339 | |
340 (define_bypass 7 | |
341 "ir_sb1_mulsi,ir_sb1_muldi" | |
342 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" | |
343 "mips_store_data_bypass_p") | |
344 | |
345 ;; The divide unit is not pipelined. Divide busy is asserted in the 4th | |
346 ;; cycle, and then deasserted on the latency cycle. So only one divide at | |
347 ;; a time, but the first/last 4 cycles can overlap. | |
348 | |
349 ;; ??? All divides block writes to hi/lo regs. hi/lo regs are written 4 cycles | |
350 ;; after the latency cycle for divides (e.g. 40/72). dmult writes lo in | |
351 ;; cycle 7, and hi in cycle 8. All other insns write hi/lo regs in cycle 7. | |
352 ;; Default for output dependencies is the difference in latencies, which is | |
353 ;; only 1 cycle off here, e.g. div to mtlo stalls for 32 cycles, but should | |
354 ;; stall for 33 cycles. This does not seem significant enough to worry about. | |
355 | |
356 (define_insn_reservation "ir_sb1_divsi" 36 | |
357 (and (eq_attr "cpu" "sb1,sb1a") | |
358 (and (eq_attr "type" "idiv") | |
359 (eq_attr "mode" "SI"))) | |
360 "sb1_ex1, nothing*3, sb1_div*32") | |
361 | |
362 (define_insn_reservation "ir_sb1_divdi" 68 | |
363 (and (eq_attr "cpu" "sb1,sb1a") | |
364 (and (eq_attr "type" "idiv") | |
365 (eq_attr "mode" "DI"))) | |
366 "sb1_ex1, nothing*3, sb1_div*64") | |
367 | |
368 (define_insn_reservation "ir_sb1_fpu_2pipes" 4 | |
369 (and (eq_attr "cpu" "sb1,sb1a") | |
370 (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1") | |
371 (eq_attr "sb1_fp_pipes" "two"))) | |
372 "sb1_fp1 | sb1_fp0") | |
373 | |
374 (define_insn_reservation "ir_sb1_fpu_1pipe" 4 | |
375 (and (eq_attr "cpu" "sb1,sb1a") | |
376 (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1") | |
377 (eq_attr "sb1_fp_pipes" "one"))) | |
378 "sb1_fp1") | |
379 | |
380 (define_insn_reservation "ir_sb1_fpu_step2_2pipes" 8 | |
381 (and (eq_attr "cpu" "sb1,sb1a") | |
382 (and (eq_attr "type" "frdiv2,frsqrt2") | |
383 (eq_attr "sb1_fp_pipes" "two"))) | |
384 "sb1_fp1 | sb1_fp0") | |
385 | |
386 (define_insn_reservation "ir_sb1_fpu_step2_1pipe" 8 | |
387 (and (eq_attr "cpu" "sb1,sb1a") | |
388 (and (eq_attr "type" "frdiv2,frsqrt2") | |
389 (eq_attr "sb1_fp_pipes" "one"))) | |
390 "sb1_fp1") | |
391 | |
392 ;; ??? madd/msub 4-cycle latency to itself (same fr?), but 8 cycle latency | |
393 ;; otherwise. | |
394 | |
395 ;; ??? Blocks issue of another non-madd/msub after 4 cycles. | |
396 | |
397 (define_insn_reservation "ir_sb1_fmadd_2pipes" 8 | |
398 (and (eq_attr "cpu" "sb1,sb1a") | |
399 (and (eq_attr "type" "fmadd") | |
400 (eq_attr "sb1_fp_pipes" "two"))) | |
401 "sb1_fp1 | sb1_fp0") | |
402 | |
403 (define_insn_reservation "ir_sb1_fmadd_1pipe" 8 | |
404 (and (eq_attr "cpu" "sb1,sb1a") | |
405 (and (eq_attr "type" "fmadd") | |
406 (eq_attr "sb1_fp_pipes" "one"))) | |
407 "sb1_fp1") | |
408 | |
409 (define_insn_reservation "ir_sb1_fcmp" 4 | |
410 (and (eq_attr "cpu" "sb1,sb1a") | |
411 (eq_attr "type" "fcmp")) | |
412 "sb1_fp1") | |
413 | |
414 ;; mtc1 latency 5 cycles. | |
415 | |
416 (define_insn_reservation "ir_sb1_mtxfer" 5 | |
417 (and (eq_attr "cpu" "sb1,sb1a") | |
418 (eq_attr "type" "mtc")) | |
419 "sb1_fp0") | |
420 | |
421 ;; mfc1 latency 1 cycle. | |
422 | |
423 (define_insn_reservation "ir_sb1_mfxfer" 1 | |
424 (and (eq_attr "cpu" "sb1,sb1a") | |
425 (eq_attr "type" "mfc")) | |
426 "sb1_fp0") | |
427 | |
428 ;; ??? Can deliver at most 1 result per every 6 cycles because of issue | |
429 ;; restrictions. | |
430 | |
431 (define_insn_reservation "ir_sb1_divsf_2pipes" 24 | |
432 (and (eq_attr "cpu" "sb1,sb1a") | |
433 (and (eq_attr "type" "fdiv") | |
434 (and (eq_attr "mode" "SF") | |
435 (eq_attr "sb1_fp_pipes" "two")))) | |
436 "sb1_fp1 | sb1_fp0") | |
437 | |
438 (define_insn_reservation "ir_sb1_divsf_1pipe" 24 | |
439 (and (eq_attr "cpu" "sb1,sb1a") | |
440 (and (eq_attr "type" "fdiv") | |
441 (and (eq_attr "mode" "SF") | |
442 (eq_attr "sb1_fp_pipes" "one")))) | |
443 "sb1_fp1") | |
444 | |
445 ;; ??? Can deliver at most 1 result per every 8 cycles because of issue | |
446 ;; restrictions. | |
447 | |
448 (define_insn_reservation "ir_sb1_divdf_2pipes" 32 | |
449 (and (eq_attr "cpu" "sb1,sb1a") | |
450 (and (eq_attr "type" "fdiv") | |
451 (and (eq_attr "mode" "DF") | |
452 (eq_attr "sb1_fp_pipes" "two")))) | |
453 "sb1_fp1 | sb1_fp0") | |
454 | |
455 (define_insn_reservation "ir_sb1_divdf_1pipe" 32 | |
456 (and (eq_attr "cpu" "sb1,sb1a") | |
457 (and (eq_attr "type" "fdiv") | |
458 (and (eq_attr "mode" "DF") | |
459 (eq_attr "sb1_fp_pipes" "one")))) | |
460 "sb1_fp1") | |
461 | |
462 ;; ??? Can deliver at most 1 result per every 3 cycles because of issue | |
463 ;; restrictions. | |
464 | |
465 (define_insn_reservation "ir_sb1_recipsf_2pipes" 12 | |
466 (and (eq_attr "cpu" "sb1,sb1a") | |
467 (and (eq_attr "type" "frdiv") | |
468 (and (eq_attr "mode" "SF") | |
469 (eq_attr "sb1_fp_pipes" "two")))) | |
470 "sb1_fp1 | sb1_fp0") | |
471 | |
472 (define_insn_reservation "ir_sb1_recipsf_1pipe" 12 | |
473 (and (eq_attr "cpu" "sb1,sb1a") | |
474 (and (eq_attr "type" "frdiv") | |
475 (and (eq_attr "mode" "SF") | |
476 (eq_attr "sb1_fp_pipes" "one")))) | |
477 "sb1_fp1") | |
478 | |
479 ;; ??? Can deliver at most 1 result per every 5 cycles because of issue | |
480 ;; restrictions. | |
481 | |
482 (define_insn_reservation "ir_sb1_recipdf_2pipes" 20 | |
483 (and (eq_attr "cpu" "sb1,sb1a") | |
484 (and (eq_attr "type" "frdiv") | |
485 (and (eq_attr "mode" "DF") | |
486 (eq_attr "sb1_fp_pipes" "two")))) | |
487 "sb1_fp1 | sb1_fp0") | |
488 | |
489 (define_insn_reservation "ir_sb1_recipdf_1pipe" 20 | |
490 (and (eq_attr "cpu" "sb1,sb1a") | |
491 (and (eq_attr "type" "frdiv") | |
492 (and (eq_attr "mode" "DF") | |
493 (eq_attr "sb1_fp_pipes" "one")))) | |
494 "sb1_fp1") | |
495 | |
496 ;; ??? Can deliver at most 1 result per every 7 cycles because of issue | |
497 ;; restrictions. | |
498 | |
499 (define_insn_reservation "ir_sb1_sqrtsf_2pipes" 28 | |
500 (and (eq_attr "cpu" "sb1,sb1a") | |
501 (and (eq_attr "type" "fsqrt") | |
502 (and (eq_attr "mode" "SF") | |
503 (eq_attr "sb1_fp_pipes" "two")))) | |
504 "sb1_fp1 | sb1_fp0") | |
505 | |
506 (define_insn_reservation "ir_sb1_sqrtsf_1pipe" 28 | |
507 (and (eq_attr "cpu" "sb1,sb1a") | |
508 (and (eq_attr "type" "fsqrt") | |
509 (and (eq_attr "mode" "SF") | |
510 (eq_attr "sb1_fp_pipes" "one")))) | |
511 "sb1_fp1") | |
512 | |
513 ;; ??? Can deliver at most 1 result per every 10 cycles because of issue | |
514 ;; restrictions. | |
515 | |
516 (define_insn_reservation "ir_sb1_sqrtdf_2pipes" 40 | |
517 (and (eq_attr "cpu" "sb1,sb1a") | |
518 (and (eq_attr "type" "fsqrt") | |
519 (and (eq_attr "mode" "DF") | |
520 (eq_attr "sb1_fp_pipes" "two")))) | |
521 "sb1_fp1 | sb1_fp0") | |
522 | |
523 (define_insn_reservation "ir_sb1_sqrtdf_1pipe" 40 | |
524 (and (eq_attr "cpu" "sb1,sb1a") | |
525 (and (eq_attr "type" "fsqrt") | |
526 (and (eq_attr "mode" "DF") | |
527 (eq_attr "sb1_fp_pipes" "one")))) | |
528 "sb1_fp1") | |
529 | |
530 ;; ??? Can deliver at most 1 result per every 4 cycles because of issue | |
531 ;; restrictions. | |
532 | |
533 (define_insn_reservation "ir_sb1_rsqrtsf_2pipes" 16 | |
534 (and (eq_attr "cpu" "sb1,sb1a") | |
535 (and (eq_attr "type" "frsqrt") | |
536 (and (eq_attr "mode" "SF") | |
537 (eq_attr "sb1_fp_pipes" "two")))) | |
538 "sb1_fp1 | sb1_fp0") | |
539 | |
540 (define_insn_reservation "ir_sb1_rsqrtsf_1pipe" 16 | |
541 (and (eq_attr "cpu" "sb1,sb1a") | |
542 (and (eq_attr "type" "frsqrt") | |
543 (and (eq_attr "mode" "SF") | |
544 (eq_attr "sb1_fp_pipes" "one")))) | |
545 "sb1_fp1") | |
546 | |
547 ;; ??? Can deliver at most 1 result per every 7 cycles because of issue | |
548 ;; restrictions. | |
549 | |
550 (define_insn_reservation "ir_sb1_rsqrtdf_2pipes" 28 | |
551 (and (eq_attr "cpu" "sb1,sb1a") | |
552 (and (eq_attr "type" "frsqrt") | |
553 (and (eq_attr "mode" "DF") | |
554 (eq_attr "sb1_fp_pipes" "two")))) | |
555 "sb1_fp1 | sb1_fp0") | |
556 | |
557 (define_insn_reservation "ir_sb1_rsqrtdf_1pipe" 28 | |
558 (and (eq_attr "cpu" "sb1,sb1a") | |
559 (and (eq_attr "type" "frsqrt") | |
560 (and (eq_attr "mode" "DF") | |
561 (eq_attr "sb1_fp_pipes" "one")))) | |
562 "sb1_fp1") |