Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/picochip/picochip.h @ 0:a06113de4d67
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author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
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date | Fri, 17 Jul 2009 14:47:48 +0900 |
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children | 77e2b8dfacca |
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1 /* Definitions of target machine for GNU compiler for picoChip | |
2 Copyright (C) 2001, 2008 Free Software Foundation, Inc. | |
3 | |
4 Contributed by picoChip Designs Ltd. (http://www.picochip.com) | |
5 Maintained by Daniel Towner (daniel.towner@picochip.com) and | |
6 Hariharan Sandanagobalane (hariharan@picochip.com). | |
7 | |
8 This file is part of GCC. | |
9 | |
10 GCC is free software; you can redistribute it and/or modify | |
11 it under the terms of the GNU General Public License as published by | |
12 the Free Software Foundation; either version 3, or (at your option) | |
13 any later version. | |
14 | |
15 GCC is distributed in the hope that it will be useful, | |
16 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 GNU General Public License for more details. | |
19 | |
20 You should have received a copy of the GNU General Public License | |
21 along with GCC; see the file COPYING3. If not, see | |
22 <http://www.gnu.org/licenses/>. */ | |
23 | |
24 /* Which type of DFA scheduling to use - schedule for speed (VLIW), or | |
25 schedule for space. When scheduling for space, attempt to schedule | |
26 into stall cycles, but don't pack instructions. */ | |
27 | |
28 enum picochip_dfa_type | |
29 { | |
30 DFA_TYPE_NONE, | |
31 DFA_TYPE_SPACE, | |
32 DFA_TYPE_SPEED | |
33 }; | |
34 | |
35 extern enum picochip_dfa_type picochip_schedule_type; | |
36 | |
37 /* Controlling the Compilation Driver */ | |
38 | |
39 /* Pass through the save-temps command option. */ | |
40 #define LINK_SPEC " %{save-temps:--save-temps}" | |
41 | |
42 /* This is an embedded processor, and only supports a cut-down version of | |
43 * the standard C library. */ | |
44 #define LIB_SPEC "-lpicoC" | |
45 | |
46 /* The start file is automatically provided by the linker. */ | |
47 #define STARTFILE_SPEC "" | |
48 | |
49 /* Run-time Target Specification */ | |
50 | |
51 /* Define some additional pre-processor macros. */ | |
52 #define TARGET_CPU_CPP_BUILTINS() \ | |
53 do \ | |
54 { \ | |
55 builtin_define ("NO_TRAMPOLINES"); \ | |
56 builtin_define ("PICOCHIP"); \ | |
57 builtin_define ("__PICOCHIP__"); \ | |
58 } \ | |
59 while (0) | |
60 | |
61 /* Translate requests for particular AEs into their respective ISA | |
62 options. Note that byte access is enabled by default. */ | |
63 #define TARGET_OPTION_TRANSLATE_TABLE \ | |
64 { "-mae=ANY", "-mmul-type=none -mno-byte-access" }, \ | |
65 { "-mae=ANY2", "-mmul-type=none -mno-byte-access" }, \ | |
66 { "-mae=ANY3", "-mmul-type=none" }, \ | |
67 { "-mae=STAN", "-mmul-type=none -mno-byte-access" }, \ | |
68 { "-mae=STAN2", "-mmul-type=mac -mno-byte-access" }, \ | |
69 { "-mae=STAN3", "-mmul-type=mac " }, \ | |
70 { "-mae=MAC", "-mmul-type=mac -mno-byte-access" }, \ | |
71 { "-mae=MUL", "-mmul-type=mul" }, \ | |
72 { "-mae=MEM", "-mmul-type=mul" }, \ | |
73 { "-mae=MEM2", "-mmul-type=mul" }, \ | |
74 { "-mae=CTRL", "-mmul-type=mul" }, \ | |
75 { "-mae=CTRL2", "-mmul-type=mul" } | |
76 | |
77 /* Specify the default options, so that the multilib build doesn't | |
78 need to provide special cases for the defaults. */ | |
79 #define MULTILIB_DEFAULTS \ | |
80 { "mmul-type=mul", "mbyte-access"} | |
81 | |
82 #define TARGET_HAS_BYTE_ACCESS (picochip_has_byte_access) | |
83 #define TARGET_HAS_MUL_UNIT (picochip_has_mul_unit) | |
84 #define TARGET_HAS_MAC_UNIT (picochip_has_mac_unit) | |
85 #define TARGET_HAS_MULTIPLY (picochip_has_mac_unit || picochip_has_mul_unit) | |
86 | |
87 /* Allow some options to be overriden. In particular, the 2nd | |
88 scheduling pass option is switched off, and a machine dependent | |
89 reorganisation ensures that it is run later on, after the second | |
90 jump optimisation. */ | |
91 #define OVERRIDE_OPTIONS picochip_override_options() | |
92 | |
93 #define CAN_DEBUG_WITHOUT_FP 1 | |
94 | |
95 #define TARGET_VERSION fprintf(stderr, "(picoChip)"); | |
96 | |
97 /* Storage Layout */ | |
98 | |
99 /* picoChip processors are 16-bit machines, little endian. */ | |
100 | |
101 #define BITS_BIG_ENDIAN 0 | |
102 #define BYTES_BIG_ENDIAN 0 | |
103 #define WORDS_BIG_ENDIAN 0 | |
104 | |
105 #define BITS_PER_UNIT 8 | |
106 | |
107 #define BITS_PER_WORD 16 | |
108 #define UNITS_PER_WORD (BITS_PER_WORD / BITS_PER_UNIT) | |
109 | |
110 #define POINTER_SIZE BITS_PER_WORD | |
111 | |
112 /* Promote those modes that are smaller than an int, to int mode. */ | |
113 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
114 ((GET_MODE_CLASS (MODE) == MODE_INT \ | |
115 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
116 ? (MODE) = HImode : 0) | |
117 | |
118 /* All parameters are at least this aligned. Parameters are passed | |
119 one-per-register. */ | |
120 #define PARM_BOUNDARY BITS_PER_WORD | |
121 | |
122 /* The main stack pointer is guaranteed to be aligned to the most | |
123 strict data alignment. */ | |
124 #define STACK_BOUNDARY 32 | |
125 | |
126 /* Function entry point is byte aligned. */ | |
127 #define FUNCTION_BOUNDARY 8 | |
128 | |
129 /* This is the biggest alignment that can be allowed on this machine. | |
130 Since the STANs have only 256 byte memory, it doesnt make sense | |
131 to have alignments greater than 32 bytes. Hence the value */ | |
132 #define MAX_OFILE_ALIGNMENT 32*8 | |
133 | |
134 /* The strictest data object alignment, which repesents a register pair. */ | |
135 #define BIGGEST_ALIGNMENT 32 | |
136 | |
137 /* The hardware doesn't allow unaligned memory access. */ | |
138 #define STRICT_ALIGNMENT 1 | |
139 | |
140 /* We want the 'unix' style bitfield packing algorithm. */ | |
141 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
142 | |
143 /* Support up to 64-bit integers. */ | |
144 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode) | |
145 | |
146 /* We don't support floating point, but give it a sensible definition. */ | |
147 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT | |
148 | |
149 /* Layout of Source Language Data Types. */ | |
150 | |
151 #define INT_TYPE_SIZE BITS_PER_WORD | |
152 | |
153 /* The normal sizes for C scalar data. */ | |
154 #define CHAR_TYPE_SIZE 8 | |
155 #define SHORT_TYPE_SIZE 16 | |
156 #define LONG_TYPE_SIZE 32 | |
157 #define LONG_LONG_TYPE_SIZE 64 | |
158 | |
159 /* We don't support the following data types, but still give them | |
160 sensible values. */ | |
161 #define FLOAT_TYPE_SIZE 32 | |
162 #define DOUBLE_TYPE_SIZE 32 | |
163 #define LONG_DOUBLE_TYPE_SIZE 32 | |
164 | |
165 /* Plain `char' is a signed type, since the hardware sign-extends | |
166 bytes when loading them from memory into a register. */ | |
167 #define DEFAULT_SIGNED_CHAR 1 | |
168 | |
169 /* Note that the names of the types used in the following macros must | |
170 be precisely the same as those defined internally in gcc. For | |
171 example, `unsigned short' wouldn't work as a type string, since gcc | |
172 doesn't define any type with this exact string. The correct string | |
173 to use is `short unsigned int'. */ | |
174 | |
175 #define SIZE_TYPE "unsigned int" | |
176 | |
177 #define PTRDIFF_TYPE "int" | |
178 | |
179 #define WCHAR_TYPE "short unsigned int" | |
180 #define WCHAR_TYPE_SIZE 16 | |
181 | |
182 #define WINT_TYPE "unsigned int" | |
183 | |
184 /* Register Usage */ | |
185 | |
186 /* Picochip has 16 16-bit registers, a condition code register and an | |
187 (inaccessible) instruction pointer. One of these registers (r15) is | |
188 special, and is either used to load a constant anywhere a register | |
189 can normally be used, or is used to specify a dummy destination | |
190 (e.g., when setting condition flags). We also define some pseudo | |
191 registers to represent condition codes, the frame pointer and the | |
192 argument pointer. The latter two are eliminated wherever possible. | |
193 | |
194 Pairs of general registers may be combined to form 32-bit registers. | |
195 | |
196 The picoChip registers are as follows: | |
197 | |
198 0..1 - function return value | |
199 0..5 - first 6 function parameters | |
200 6..11 - General purpose | |
201 12 - link register | |
202 13 - stack pointer | |
203 14 - specialized pointer | |
204 15 - long constant or /dev/null | |
205 (16) acc0 | |
206 (17) pseudo condition code | |
207 (18) pseudo frame pointer | |
208 (19) pseudo arg pointer | |
209 | |
210 Registers 0..6, 12, 13, 14, 15 are caller save | |
211 Registers 0..12, 14 are available to the register allocator. | |
212 | |
213 In addition, the DSP variant of the ISA allows extra accumulator | |
214 registers to be accessed. These are special purpose registers, | |
215 which are not currently used by the compiler. | |
216 | |
217 */ | |
218 | |
219 /* Basic Characteristics of Registers */ | |
220 | |
221 /* We have 16 hard registers plus 3 pseudo hard registers and an accumulator. */ | |
222 #define FIRST_PSEUDO_REGISTER 20 | |
223 | |
224 /* The first non-hard register. Only used internally by the picoChip port. */ | |
225 #define FIRST_NONHARD_REGISTER 18 | |
226 | |
227 /* Cannot use SP, CST, CC, FP, AP */ | |
228 #define FIXED_REGISTERS {0,0,0,0,0,0,0,0, 0,0,0,0,0,1,0,1, 1,1,1,1} | |
229 | |
230 /* Those that are clobbered by a function call (includes pseudo-regs) */ | |
231 #define CALL_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,1, 1,1,1,1} | |
232 #define CALL_REALLY_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,0, 0,1,0,0} | |
233 | |
234 /* Define the number of the picoChip link and condition psuedo registers. */ | |
235 #define LINK_REGNUM 12 | |
236 #define CC_REGNUM 17 | |
237 #define ACC_REGNUM 16 | |
238 | |
239 /* Order of Allocation of Registers */ | |
240 | |
241 /* The registers are allocated starting with the caller-clobbered | |
242 registers, in reverse order. The registers are then listed in an | |
243 order which means that they are efficiently saved in pairs (i.e., | |
244 one 32-bit store can be used instead of two 16-bit stores to save | |
245 the registers into the stack). The exception to this is the use of | |
246 r14 (AP) register, which also appears early on. This is because the | |
247 AP register can be used to encode memory operations more | |
248 efficiently than other registers. Some code can be made more | |
249 compact as a result. */ | |
250 /* My current feeling is that r14 should go to the end and maybe even r12. | |
251 It seems like the overhead of store/load that will occur since we cant | |
252 pair anything up with r14 will be higher than the advantage of smaller | |
253 encoding. | |
254 Also r12 is put towards the end for leaf functions. Since leaf functions | |
255 do not have any calls, the prologue/epilogue for them wouldnt save up/ | |
256 restore its value. So, it doesnt make sense for us to use it in the middle, | |
257 if we can avoid it. */ | |
258 #define REG_ALLOC_ORDER {5,4,3,2,1,0,12,6,7,8,9,10,11,14,16,0,0,0,0,0} | |
259 #define LEAF_REG_ALLOC_ORDER {5,4,3,2,1,0,6,7,8,9,10,11,14,12,16,0,0,0,0,0} | |
260 | |
261 /* We can dynamically change the REG_ALLOC_ORDER using the following hook. | |
262 It would be desirable to change it for leaf functions so we can put | |
263 r12 at the end of this list.*/ | |
264 #define ORDER_REGS_FOR_LOCAL_ALLOC picochip_order_regs_for_local_alloc () | |
265 | |
266 /* How Values Fit in Registers */ | |
267 | |
268 /* Number of consecutive hard regs needed starting at reg REGNO | |
269 to hold something of mode MODE. */ | |
270 #define HARD_REGNO_NREGS(REGNO, MODE) picochip_regno_nregs((REGNO), (MODE)) | |
271 | |
272 /* Is it ok to place MODE in REGNO? Require that the register number | |
273 be aligned. */ | |
274 #define HARD_REGNO_MODE_OK(REGNO, MODE) picochip_hard_regno_mode_ok(REGNO, MODE) | |
275 | |
276 #define MODES_TIEABLE_P(MODE1,MODE2) 1 | |
277 | |
278 /* Don't copy the cc register ('cos you can't put it back). */ | |
279 #define AVOID_CCMODE_COPIES 1 | |
280 | |
281 /* Register Classes */ | |
282 | |
283 enum reg_class | |
284 { | |
285 NO_REGS, /* no registers in set */ | |
286 FRAME_REGS, /* registers with a long offset */ | |
287 PTR_REGS, /* registers without an offset */ | |
288 CONST_REGS, /* registers for long constants */ | |
289 NULL_REGS, /* registers which ignore writes */ | |
290 CC_REGS, /* condition code registers */ | |
291 ACC_REGS, /* Accumulator registers */ | |
292 TWIN_REGS, /* registers which can be paired */ | |
293 GR_REGS, /* general purpose registers */ | |
294 ALL_REGS, /* all registers */ | |
295 LIM_REG_CLASSES, /* max value + 1 */ | |
296 | |
297 /* Some aliases */ | |
298 GENERAL_REGS = GR_REGS | |
299 }; | |
300 | |
301 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
302 | |
303 /* The following macro defines cover classes for Integrated Register | |
304 Allocator. Cover classes is a set of non-intersected register | |
305 classes covering all hard registers used for register allocation | |
306 purpose. Any move between two registers of a cover class should be | |
307 cheaper than load or store of the registers. The macro value is | |
308 array of register classes with LIM_REG_CLASSES used as the end | |
309 marker. */ | |
310 | |
311 #define IRA_COVER_CLASSES \ | |
312 { \ | |
313 GR_REGS, LIM_REG_CLASSES \ | |
314 } | |
315 | |
316 | |
317 /* The names of the register classes */ | |
318 #define REG_CLASS_NAMES \ | |
319 { \ | |
320 "NO_REGS", \ | |
321 "FRAME_REGS", \ | |
322 "PTR_REGS", \ | |
323 "CONST_REGS", \ | |
324 "NULL_REGS", \ | |
325 "CC_REGS", \ | |
326 "ACC_REGS", \ | |
327 "TWIN_REGS", \ | |
328 "GR_REGS", \ | |
329 "ALL_REGS" \ | |
330 } | |
331 | |
332 /* Each reg class is an array of 32-bit integers. Each array must be | |
333 long enough to store one bit for every pseudo register. Thus in the | |
334 following code, each array only stores one 32-bit value. */ | |
335 #define REG_CLASS_CONTENTS \ | |
336 { \ | |
337 {0x00000000}, /* no registers */ \ | |
338 {0x00002000}, /* frame */ \ | |
339 {0x00004000}, /* pointer */ \ | |
340 {0x00008000}, /* const */ \ | |
341 {0x00008000}, /* null */ \ | |
342 {0x00020000}, /* cc */ \ | |
343 {0x00010000}, /* acc0 */ \ | |
344 {0x00000FFF}, /* twin */ \ | |
345 {0x000CFFFF}, /* general registers - includes pseudo-arg */ \ | |
346 {0x000FFFFF} /* all registers - includes pseudo-arg */ \ | |
347 } | |
348 | |
349 /* The earliest register class containing the given register. */ | |
350 extern const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
351 #define REGNO_REG_CLASS(REGNO) picochip_regno_reg_class[REGNO] | |
352 | |
353 /* Any register can be a base pointer. */ | |
354 #define BASE_REG_CLASS GR_REGS | |
355 | |
356 /* Any register can be an index. */ | |
357 #define INDEX_REG_CLASS GR_REGS | |
358 | |
359 #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
360 (REGNO_REG_CLASS (REGNO) != CC_REGS && REGNO_REG_CLASS (REGNO) != ACC_REGS) | |
361 | |
362 #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
363 | |
364 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS | |
365 | |
366 #define CLASS_MAX_NREGS(CLASS, MODE) picochip_class_max_nregs(CLASS, MODE) | |
367 | |
368 | |
369 /* Stack Layout and Calling Conventions */ | |
370 | |
371 #define STACK_GROWS_DOWNWARD 1 | |
372 | |
373 /* The frame pointer points to the outgoing argument area, so the | |
374 locals are above that. */ | |
375 #define STARTING_FRAME_OFFSET 0 | |
376 | |
377 #define FIRST_PARM_OFFSET(FNDECL) 0 | |
378 | |
379 /* Specify where the return address lives before entry to the | |
380 prologue. This is required to enable DWARF debug information to be | |
381 generated. */ | |
382 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM) | |
383 | |
384 #define RETURN_ADDR_RTX(count,frameaddr) picochip_return_addr_rtx(count,frameaddr) | |
385 | |
386 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNUM) | |
387 | |
388 /* Registers that Address the Stack Frame */ | |
389 | |
390 #define STACK_POINTER_REGNUM 13 | |
391 #define FRAME_POINTER_REGNUM 18 | |
392 #define ARG_POINTER_REGNUM 19 | |
393 | |
394 /* Static chain is used to pass the local variables of the enclosing function. | |
395 The static chain is passed in memory. The first long-word location | |
396 beneath the stack pointer is used. In the presence of pretend | |
397 arguments, which are written into that location, this mechanism | |
398 complicates matters. */ | |
399 | |
400 /* Location seen by the caller. */ | |
401 #define STATIC_CHAIN \ | |
402 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -2 * UNITS_PER_WORD)) | |
403 | |
404 /* Location seen by the callee. */ | |
405 #define STATIC_CHAIN_INCOMING \ | |
406 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, 0)) | |
407 | |
408 /* Eliminating Frame Pointer and Arg Pointer. The frame and argument | |
409 pointers are eliminated wherever possible, by replacing them with | |
410 offsets from the stack pointer. */ | |
411 | |
412 /* We want to get rid of the frame pointer. */ | |
413 #define FRAME_POINTER_REQUIRED 0 | |
414 | |
415 #define ELIMINABLE_REGS \ | |
416 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
417 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} | |
418 | |
419 #define CAN_ELIMINATE(FROM, TO) 1 | |
420 | |
421 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,OFFSET) \ | |
422 OFFSET = initial_elimination_offset(FROM, TO); | |
423 | |
424 #define ACCUMULATE_OUTGOING_ARGS 1 | |
425 | |
426 #define PUSH_ARGS 0 | |
427 | |
428 /* Functions don't pop their args. */ | |
429 #define RETURN_POPS_ARGS(FNDECL, FNTYPE, STACK) 0 | |
430 | |
431 /* Passing Arguments in Registers */ | |
432 | |
433 /* Store the offset of the next argument. */ | |
434 #define CUMULATIVE_ARGS unsigned | |
435 | |
436 /* Decide how function arguments are handled. */ | |
437 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
438 picochip_function_arg (CUM, MODE, TYPE, NAMED) | |
439 | |
440 /* Incoming arguments are always the same as normal arguments, except | |
441 for a function which uses variadic arguments, in which case all | |
442 arguments are effectively passed on the stack. */ | |
443 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
444 picochip_incoming_function_arg(CUM, MODE, TYPE, NAMED) | |
445 | |
446 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \ | |
447 ((CUM) = 0) | |
448 | |
449 #define FUNCTION_ARG_ADVANCE(CUM,MODE,TYPE,NAMED) \ | |
450 (CUM) = picochip_arg_advance (CUM, MODE, TYPE, NAMED) | |
451 | |
452 /* Originally this used TYPE_ALIGN to determine the | |
453 alignment. Unfortunately, this fails in some cases, because the | |
454 type is unknown (e.g., libcall's). Instead, use GET_MODE_ALIGNMENT | |
455 since the mode is always present. */ | |
456 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \ | |
457 picochip_get_function_arg_boundary(MODE) | |
458 | |
459 /* The first 6 registers can hold parameters. */ | |
460 #define FUNCTION_ARG_REGNO_P(REGNO) ((REGNO) < 6) | |
461 | |
462 /* How Scalar Function Values are Returned | |
463 Do we need this?? */ | |
464 #define FUNCTION_VALUE(VALTYPE,FUNC) picochip_function_value(VALTYPE, FUNC, 0) | |
465 | |
466 #define LIBCALL_VALUE(MODE) (gen_rtx_REG (MODE, 0)) | |
467 | |
468 /* Results are in register zero. If an SImode register is returned, | |
469 reg0 will suffice to mean R[0:1]. */ | |
470 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == 0) | |
471 | |
472 /* Don't automatically pass struct's in memory - use the | |
473 * RETURN_IN_MEMORY macro to determine when structs are returned in | |
474 * memory, and when in registers. */ | |
475 #define DEFAULT_PCC_STRUCT_RETURN 0 | |
476 | |
477 /* Function Entry and Exit */ | |
478 | |
479 /* The epilogue doesn't clobber anything. */ | |
480 #define EPILOGUE_USES(REGNO) 0 | |
481 | |
482 /* Generating Code for Profiling. No profiling implemented */ | |
483 | |
484 #define FUNCTION_PROFILER(FILE,LABELNO) | |
485 | |
486 /* Trampolines for Nested Functions */ | |
487 | |
488 /* No trampolines. */ | |
489 #define TRAMPOLINE_SIZE 0 | |
490 #define INITIALIZE_TRAMPOLINE(ADDR,FNADDR,CHAIN) | |
491 | |
492 /* Addressing Modes */ | |
493 | |
494 #define CONSTANT_ADDRESS_P(X) CONSTANT_P(X) | |
495 | |
496 #define MAX_REGS_PER_ADDRESS 1 | |
497 | |
498 #ifdef REG_OK_STRICT | |
499 | |
500 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ | |
501 if (picochip_legitimate_address_p (MODE, X, 1)) goto LABEL; | |
502 | |
503 #else /* REG_OK_STRICT */ | |
504 | |
505 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ | |
506 if (picochip_legitimate_address_p (MODE, X, 0)) goto LABEL; | |
507 | |
508 #endif /* !REG_OK_STRICT */ | |
509 | |
510 /* extern struct rtx_def *picochip_legitimize_address */ | |
511 /* PARAMS ((struct rtx_def *, struct rtx_def *, int)); */ | |
512 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN); | |
513 | |
514 /* Legitimize reload address tries machine dependent means of | |
515 reloading addresses. There seems to be a strange error in gcc, | |
516 which necessitates this macro. Consider: | |
517 | |
518 set (reg A) (symbol_ref) | |
519 set (reg B) (plus (reg A) (const_int)) | |
520 | |
521 A symbol_ref is a valid constant, so the symbol_ref is propagated | |
522 into the second instruction to generate the instruction: | |
523 | |
524 set (reg B) (plus (symbol_ref) (const_int)) | |
525 | |
526 This is an invalid address, and find_reloads_address correctly | |
527 determines this. However, that function doesn't generate a valid | |
528 replacement for the now invalid address, and the invalid address is | |
529 output into the assembly language. To fix the problem without | |
530 changing gcc itself, the following macro tests when such an invalid | |
531 address has been computed, and wraps it up inside a constant rtx. A | |
532 constant rtx can be correctly reloaded by the function, and hence | |
533 correct code is generated. */ | |
534 | |
535 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
536 if (picochip_symbol_offset(X)) { X = gen_rtx_CONST(MODE, X); } | |
537 | |
538 /* There are no mode dependent addresses. */ | |
539 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) do {} while (0) | |
540 | |
541 /* Nonzero if the constant rtx X is a legitimate general operand. X | |
542 satisfies CONSTANT_P. */ | |
543 | |
544 #define LEGITIMATE_CONSTANT_P(X) 1 | |
545 | |
546 | |
547 /* Condition Code Status */ | |
548 | |
549 #define CC_STATUS_MDEP unsigned | |
550 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) | |
551 | |
552 /* Describing Relative Costs of Operations */ | |
553 | |
554 /* Bytes are no faster than words. */ | |
555 #define SLOW_BYTE_ACCESS 1 | |
556 | |
557 /* The assembler is often able to optimise function call branches, so | |
558 don't try to CSE them in the compiler. This was the thinking before. | |
559 But now, we realise that the benefits from CSE would mostly outweigh | |
560 the disadvantages. */ | |
561 #define NO_FUNCTION_CSE | |
562 | |
563 | |
564 /* Dividing the Output into Sections */ | |
565 | |
566 #define TEXT_SECTION_ASM_OP ".section .text\n" | |
567 #define DATA_SECTION_ASM_OP ".section .data\n" | |
568 #define BSS_SECTION_ASM_OP ".section .bss\n" | |
569 /* picoChip is Harvard (separate data/instruction memories), so | |
570 read-only data must go into the data section. */ | |
571 #define READONLY_DATA_SECTION_ASM_OP ".section .data\n" | |
572 | |
573 /* Defining the Output Assembler Language */ | |
574 | |
575 /* The Overall Framework of an Assembler File */ | |
576 | |
577 #define ASM_FILE_COMMENT "// " | |
578 | |
579 #define ASM_APP_ON "// High-level ASM start\n" | |
580 #define ASM_APP_OFF "// High-level ASM end\n" | |
581 | |
582 #define ASM_OUTPUT_IDENT(STREAM,STRING) fprintf(STREAM, ".ident %s\n", STRING) | |
583 | |
584 /* Output of Data */ | |
585 | |
586 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) picochip_output_ascii(FILE, PTR, LEN); | |
587 | |
588 /* Output of Uninitialized Variables */ | |
589 #define ASM_OUTPUT_ALIGNED_COMMON(FILE,NAME,SIZE,ALIGN) \ | |
590 picochip_output_aligned_common(FILE, NAME, SIZE, ALIGN) | |
591 | |
592 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN) \ | |
593 picochip_output_aligned_local(FILE, NAME, SIZE, ALIGN) | |
594 | |
595 /* Output and Generation of Labels */ | |
596 | |
597 #define ASM_OUTPUT_LABEL(STREAM,NAME) \ | |
598 do { picochip_output_label(STREAM, NAME); } while (0); | |
599 | |
600 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ | |
601 { picochip_output_labelref(STREAM, NAME); } | |
602 | |
603 /* Format must match that of picochip_output_label. */ | |
604 #define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \ | |
605 picochip_generate_internal_label(STRING,PREFIX,(long)NUM) | |
606 | |
607 #define ASM_WEAKEN_LABEL(STREAM,NAME) picochip_weaken_label(STREAM,NAME); | |
608 | |
609 /* Store in OUTPUT a string (made with alloca) containing an | |
610 assembler-name for a local static variable named NAME. LABELNO is | |
611 an integer which is different for each call. The assembler can't | |
612 use periods to generate the name, so we use a ___ separator | |
613 instead. */ | |
614 | |
615 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
616 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 15), \ | |
617 sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) | |
618 | |
619 /* Macros Controlling Initialization Routines */ | |
620 | |
621 /* By defining this, the main function won't try to call `__main'. */ | |
622 #define HAS_INIT_SECTION | |
623 | |
624 /* Output of Assembler Instructions */ | |
625 | |
626 #define REGISTER_NAMES \ | |
627 {"R0", "R1", "R2", "R3", \ | |
628 "R4", "R5", "R6", "R7", \ | |
629 "R8", "R9", "R10", "R11", \ | |
630 "R12", "FP", "R14", "R15", \ | |
631 "acc0", "pseudoCC", "pseudoFP", "pseudoAP"} | |
632 | |
633 #define ADDITIONAL_REGISTER_NAMES \ | |
634 { \ | |
635 { "R0", 0}, \ | |
636 { "R1", 1}, \ | |
637 { "R2", 2}, \ | |
638 { "R3", 3}, \ | |
639 { "R4", 4}, \ | |
640 { "R5", 5}, \ | |
641 { "R6", 6}, \ | |
642 { "R7", 7}, \ | |
643 { "R8", 8}, \ | |
644 { "R9", 9}, \ | |
645 { "R10", 10}, \ | |
646 { "R11", 11}, \ | |
647 { "R12", 12}, \ | |
648 { "FP", 13}, \ | |
649 { "R14", 14}, \ | |
650 { "R15", 15}, \ | |
651 { "acc0", 16}, \ | |
652 { "sp", 12}, /* ABI stack pointer */ \ | |
653 { "ln", 13}, /* arch link register */ \ | |
654 { "ptr", 14}, /* arch constant pointer */ \ | |
655 { "rc", 15}, /* arch constant register */ \ | |
656 { "rz", 15}, /* arch zero */ \ | |
657 } | |
658 | |
659 /* Final prescan insn is called just before an instruction is | |
660 output. In our case, we use this to detect the VLIW slot to which | |
661 the instruction has been assigned, preparatory to generating the | |
662 VLIW output in ASM_OUTPUT_OPCODE. */ | |
663 #define FINAL_PRESCAN_INSN(insn, operand, nop) \ | |
664 picochip_final_prescan_insn (insn, operand,nop) | |
665 | |
666 #define ASM_OUTPUT_OPCODE(FILE,PTR) \ | |
667 { PTR = picochip_asm_output_opcode(FILE, PTR); } | |
668 | |
669 #define PRINT_OPERAND(STREAM,X,CODE) \ | |
670 picochip_print_operand(STREAM, X, CODE) | |
671 | |
672 #define PRINT_OPERAND_PUNCT_VALID_P(code) \ | |
673 (((code) == '|') || ((code) == '#') || ((code) == '>')) | |
674 | |
675 #define PRINT_OPERAND_ADDRESS(STREAM,X) \ | |
676 picochip_print_operand_address(STREAM,X) | |
677 | |
678 /* Output of Dispatch Tables */ | |
679 | |
680 /* Initialise a data memory location to an absolute code label. Used | |
681 for building switch statement jump tables. Note - the format of the | |
682 label must match that of the function picochip_output_label. */ | |
683 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \ | |
684 fprintf (stream, ".initWord _L%d\n", value); | |
685 | |
686 /* Assembler Commands for Alignment */ | |
687 | |
688 #define ASM_OUTPUT_SKIP(STREAM,BYTES) \ | |
689 fprintf(STREAM, ".skip %u\n", BYTES); | |
690 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \ | |
691 fprintf(STREAM, ".align %u\n", 1 << POWER); | |
692 | |
693 /* The elaborator doesn't output zero bytes in the text section. */ | |
694 #define ASM_NO_SKIP_IN_TEXT 1 | |
695 | |
696 /* Controlling Debugging Information Format */ | |
697 | |
698 /* Macros Affecting All Debugging Formats */ | |
699 | |
700 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
701 | |
702 #define DWARF2_DEBUGGING_INFO | |
703 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
704 #define DWARF2_FRAME_INFO 1 | |
705 | |
706 /* Generate .file/.loc directives, so that the assembler generates the | |
707 line table. */ | |
708 #define DWARF2_ASM_LINE_DEBUG_INFO 1 | |
709 | |
710 /* Miscellaneous Parameters */ | |
711 | |
712 #define CASE_VECTOR_MODE HImode | |
713 #define WORD_REGISTER_OPERATIONS | |
714 #define LOAD_EXTEND_OP(MODE) ((MODE) == QImode ? SIGN_EXTEND : ZERO_EXTEND) | |
715 #define MOVE_MAX 4 | |
716 #define SHIFT_COUNT_TRUNCATED 1 | |
717 #define Pmode HImode | |
718 #define FUNCTION_MODE QImode | |
719 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 | |
720 | |
721 #define ASM_LONG ":TODO:.word\t" | |
722 | |
723 /* Define builtins for selected special-purpose instructions. */ | |
724 enum picochip_builtins | |
725 { | |
726 PICOCHIP_BUILTIN_SBC, | |
727 PICOCHIP_BUILTIN_PUT, | |
728 PICOCHIP_BUILTIN_GET, | |
729 PICOCHIP_BUILTIN_TESTPORT, | |
730 PICOCHIP_BUILTIN_COPYSW, | |
731 PICOCHIP_BUILTIN_ADDS, | |
732 PICOCHIP_BUILTIN_SUBS, | |
733 PICOCHIP_BUILTIN_BREV, | |
734 PICOCHIP_BUILTIN_BYTESWAP, | |
735 PICOCHIP_BUILTIN_GET_ARRAY, | |
736 PICOCHIP_BUILTIN_PUT_ARRAY, | |
737 PICOCHIP_BUILTIN_TESTPORT_ARRAY, | |
738 PICOCHIP_BUILTIN_ASRI, | |
739 PICOCHIP_BUILTIN_HALT | |
740 }; | |
741 | |
742 #define NO_DOT_IN_LABEL 1 | |
743 | |
744 /* The assembler does support LEB128, despite the auto-configure test | |
745 not detecting this. */ | |
746 #define HAVE_AS_LEB128 1 | |
747 | |
748 /* The End */ |