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comparison gcc/config/rs6000/altivec.md @ 0:a06113de4d67

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author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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-1:000000000000 0:a06113de4d67
1 ;; AltiVec patterns.
2 ;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
5
6 ;; This file is part of GCC.
7
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
12
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
17
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
21
22 (define_constants
23 [(UNSPEC_VCMPBFP 50)
24 (UNSPEC_VCMPEQUB 51)
25 (UNSPEC_VCMPEQUH 52)
26 (UNSPEC_VCMPEQUW 53)
27 (UNSPEC_VCMPEQFP 54)
28 (UNSPEC_VCMPGEFP 55)
29 (UNSPEC_VCMPGTUB 56)
30 (UNSPEC_VCMPGTSB 57)
31 (UNSPEC_VCMPGTUH 58)
32 (UNSPEC_VCMPGTSH 59)
33 (UNSPEC_VCMPGTUW 60)
34 (UNSPEC_VCMPGTSW 61)
35 (UNSPEC_VCMPGTFP 62)
36 (UNSPEC_VMSUMU 65)
37 (UNSPEC_VMSUMM 66)
38 (UNSPEC_VMSUMSHM 68)
39 (UNSPEC_VMSUMUHS 69)
40 (UNSPEC_VMSUMSHS 70)
41 (UNSPEC_VMHADDSHS 71)
42 (UNSPEC_VMHRADDSHS 72)
43 (UNSPEC_VMLADDUHM 73)
44 (UNSPEC_VADDCUW 75)
45 (UNSPEC_VADDU 76)
46 (UNSPEC_VADDS 77)
47 (UNSPEC_VAVGU 80)
48 (UNSPEC_VAVGS 81)
49 (UNSPEC_VMULEUB 83)
50 (UNSPEC_VMULESB 84)
51 (UNSPEC_VMULEUH 85)
52 (UNSPEC_VMULESH 86)
53 (UNSPEC_VMULOUB 87)
54 (UNSPEC_VMULOSB 88)
55 (UNSPEC_VMULOUH 89)
56 (UNSPEC_VMULOSH 90)
57 (UNSPEC_VPKUHUM 93)
58 (UNSPEC_VPKUWUM 94)
59 (UNSPEC_VPKPX 95)
60 (UNSPEC_VPKSHSS 97)
61 (UNSPEC_VPKSWSS 99)
62 (UNSPEC_VPKUHUS 100)
63 (UNSPEC_VPKSHUS 101)
64 (UNSPEC_VPKUWUS 102)
65 (UNSPEC_VPKSWUS 103)
66 (UNSPEC_VRL 104)
67 (UNSPEC_VSLV4SI 110)
68 (UNSPEC_VSLO 111)
69 (UNSPEC_VSR 118)
70 (UNSPEC_VSRO 119)
71 (UNSPEC_VSUBCUW 124)
72 (UNSPEC_VSUBU 125)
73 (UNSPEC_VSUBS 126)
74 (UNSPEC_VSUM4UBS 131)
75 (UNSPEC_VSUM4S 132)
76 (UNSPEC_VSUM2SWS 134)
77 (UNSPEC_VSUMSWS 135)
78 (UNSPEC_VPERM 144)
79 (UNSPEC_VRFIP 148)
80 (UNSPEC_VRFIN 149)
81 (UNSPEC_VRFIM 150)
82 (UNSPEC_VCFUX 151)
83 (UNSPEC_VCFSX 152)
84 (UNSPEC_VCTUXS 153)
85 (UNSPEC_VCTSXS 154)
86 (UNSPEC_VLOGEFP 155)
87 (UNSPEC_VEXPTEFP 156)
88 (UNSPEC_VRSQRTEFP 157)
89 (UNSPEC_VREFP 158)
90 (UNSPEC_VSEL4SI 159)
91 (UNSPEC_VSEL4SF 160)
92 (UNSPEC_VSEL8HI 161)
93 (UNSPEC_VSEL16QI 162)
94 (UNSPEC_VLSDOI 163)
95 (UNSPEC_VUPKHSB 167)
96 (UNSPEC_VUPKHPX 168)
97 (UNSPEC_VUPKHSH 169)
98 (UNSPEC_VUPKLSB 170)
99 (UNSPEC_VUPKLPX 171)
100 (UNSPEC_VUPKLSH 172)
101 (UNSPEC_PREDICATE 173)
102 (UNSPEC_DST 190)
103 (UNSPEC_DSTT 191)
104 (UNSPEC_DSTST 192)
105 (UNSPEC_DSTSTT 193)
106 (UNSPEC_LVSL 194)
107 (UNSPEC_LVSR 195)
108 (UNSPEC_LVE 196)
109 (UNSPEC_STVX 201)
110 (UNSPEC_STVXL 202)
111 (UNSPEC_STVE 203)
112 (UNSPEC_SET_VSCR 213)
113 (UNSPEC_GET_VRSAVE 214)
114 (UNSPEC_REALIGN_LOAD 215)
115 (UNSPEC_REDUC_PLUS 217)
116 (UNSPEC_VECSH 219)
117 (UNSPEC_EXTEVEN_V4SI 220)
118 (UNSPEC_EXTEVEN_V8HI 221)
119 (UNSPEC_EXTEVEN_V16QI 222)
120 (UNSPEC_EXTEVEN_V4SF 223)
121 (UNSPEC_EXTODD_V4SI 224)
122 (UNSPEC_EXTODD_V8HI 225)
123 (UNSPEC_EXTODD_V16QI 226)
124 (UNSPEC_EXTODD_V4SF 227)
125 (UNSPEC_INTERHI_V4SI 228)
126 (UNSPEC_INTERHI_V8HI 229)
127 (UNSPEC_INTERHI_V16QI 230)
128 (UNSPEC_INTERHI_V4SF 231)
129 (UNSPEC_INTERLO_V4SI 232)
130 (UNSPEC_INTERLO_V8HI 233)
131 (UNSPEC_INTERLO_V16QI 234)
132 (UNSPEC_INTERLO_V4SF 235)
133 (UNSPEC_LVLX 236)
134 (UNSPEC_LVLXL 237)
135 (UNSPEC_LVRX 238)
136 (UNSPEC_LVRXL 239)
137 (UNSPEC_STVLX 240)
138 (UNSPEC_STVLXL 241)
139 (UNSPEC_STVRX 242)
140 (UNSPEC_STVRXL 243)
141 (UNSPEC_VMULWHUB 308)
142 (UNSPEC_VMULWLUB 309)
143 (UNSPEC_VMULWHSB 310)
144 (UNSPEC_VMULWLSB 311)
145 (UNSPEC_VMULWHUH 312)
146 (UNSPEC_VMULWLUH 313)
147 (UNSPEC_VMULWHSH 314)
148 (UNSPEC_VMULWLSH 315)
149 (UNSPEC_VUPKHUB 316)
150 (UNSPEC_VUPKHUH 317)
151 (UNSPEC_VUPKLUB 318)
152 (UNSPEC_VUPKLUH 319)
153 (UNSPEC_VPERMSI 320)
154 (UNSPEC_VPERMHI 321)
155 (UNSPEC_INTERHI 322)
156 (UNSPEC_INTERLO 323)
157 (UNSPEC_VUPKHS_V4SF 324)
158 (UNSPEC_VUPKLS_V4SF 325)
159 (UNSPEC_VUPKHU_V4SF 326)
160 (UNSPEC_VUPKLU_V4SF 327)
161 ])
162
163 (define_constants
164 [(UNSPECV_SET_VRSAVE 30)
165 (UNSPECV_MTVSCR 186)
166 (UNSPECV_MFVSCR 187)
167 (UNSPECV_DSSALL 188)
168 (UNSPECV_DSS 189)
169 ])
170
171 ;; Vec int modes
172 (define_mode_iterator VI [V4SI V8HI V16QI])
173 ;; Short vec in modes
174 (define_mode_iterator VIshort [V8HI V16QI])
175 ;; Vec float modes
176 (define_mode_iterator VF [V4SF])
177 ;; Vec modes, pity mode iterators are not composable
178 (define_mode_iterator V [V4SI V8HI V16QI V4SF])
179
180 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
181
182 ;; Generic LVX load instruction.
183 (define_insn "altivec_lvx_<mode>"
184 [(set (match_operand:V 0 "altivec_register_operand" "=v")
185 (match_operand:V 1 "memory_operand" "Z"))]
186 "TARGET_ALTIVEC"
187 "lvx %0,%y1"
188 [(set_attr "type" "vecload")])
189
190 ;; Generic STVX store instruction.
191 (define_insn "altivec_stvx_<mode>"
192 [(set (match_operand:V 0 "memory_operand" "=Z")
193 (match_operand:V 1 "altivec_register_operand" "v"))]
194 "TARGET_ALTIVEC"
195 "stvx %1,%y0"
196 [(set_attr "type" "vecstore")])
197
198 ;; Vector move instructions.
199 (define_expand "mov<mode>"
200 [(set (match_operand:V 0 "nonimmediate_operand" "")
201 (match_operand:V 1 "any_operand" ""))]
202 "TARGET_ALTIVEC"
203 {
204 rs6000_emit_move (operands[0], operands[1], <MODE>mode);
205 DONE;
206 })
207
208 (define_insn "*mov<mode>_internal"
209 [(set (match_operand:V 0 "nonimmediate_operand" "=Z,v,v,o,r,r,v")
210 (match_operand:V 1 "input_operand" "v,Z,v,r,o,r,W"))]
211 "TARGET_ALTIVEC
212 && (register_operand (operands[0], <MODE>mode)
213 || register_operand (operands[1], <MODE>mode))"
214 {
215 switch (which_alternative)
216 {
217 case 0: return "stvx %1,%y0";
218 case 1: return "lvx %0,%y1";
219 case 2: return "vor %0,%1,%1";
220 case 3: return "#";
221 case 4: return "#";
222 case 5: return "#";
223 case 6: return output_vec_const_move (operands);
224 default: gcc_unreachable ();
225 }
226 }
227 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
228
229 (define_split
230 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
231 (match_operand:V4SI 1 "input_operand" ""))]
232 "TARGET_ALTIVEC && reload_completed
233 && gpr_or_gpr_p (operands[0], operands[1])"
234 [(pc)]
235 {
236 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
237 })
238
239 (define_split
240 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
241 (match_operand:V8HI 1 "input_operand" ""))]
242 "TARGET_ALTIVEC && reload_completed
243 && gpr_or_gpr_p (operands[0], operands[1])"
244 [(pc)]
245 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
246
247 (define_split
248 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
249 (match_operand:V16QI 1 "input_operand" ""))]
250 "TARGET_ALTIVEC && reload_completed
251 && gpr_or_gpr_p (operands[0], operands[1])"
252 [(pc)]
253 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
254
255 (define_split
256 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
257 (match_operand:V4SF 1 "input_operand" ""))]
258 "TARGET_ALTIVEC && reload_completed
259 && gpr_or_gpr_p (operands[0], operands[1])"
260 [(pc)]
261 {
262 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
263 })
264
265 (define_split
266 [(set (match_operand:V 0 "altivec_register_operand" "")
267 (match_operand:V 1 "easy_vector_constant_add_self" ""))]
268 "TARGET_ALTIVEC && reload_completed"
269 [(set (match_dup 0) (match_dup 3))
270 (set (match_dup 0) (match_dup 4))]
271 {
272 rtx dup = gen_easy_altivec_constant (operands[1]);
273 rtx const_vec;
274 enum machine_mode op_mode = <MODE>mode;
275
276 /* Divide the operand of the resulting VEC_DUPLICATE, and use
277 simplify_rtx to make a CONST_VECTOR. */
278 XEXP (dup, 0) = simplify_const_binary_operation (ASHIFTRT, QImode,
279 XEXP (dup, 0), const1_rtx);
280 const_vec = simplify_rtx (dup);
281
282 if (op_mode == V4SFmode)
283 {
284 op_mode = V4SImode;
285 operands[0] = gen_lowpart (op_mode, operands[0]);
286 }
287 if (GET_MODE (const_vec) == op_mode)
288 operands[3] = const_vec;
289 else
290 operands[3] = gen_lowpart (op_mode, const_vec);
291 operands[4] = gen_rtx_PLUS (op_mode, operands[0], operands[0]);
292 })
293
294 (define_insn "get_vrsave_internal"
295 [(set (match_operand:SI 0 "register_operand" "=r")
296 (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
297 "TARGET_ALTIVEC"
298 {
299 if (TARGET_MACHO)
300 return "mfspr %0,256";
301 else
302 return "mfvrsave %0";
303 }
304 [(set_attr "type" "*")])
305
306 (define_insn "*set_vrsave_internal"
307 [(match_parallel 0 "vrsave_operation"
308 [(set (reg:SI 109)
309 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
310 (reg:SI 109)] UNSPECV_SET_VRSAVE))])]
311 "TARGET_ALTIVEC"
312 {
313 if (TARGET_MACHO)
314 return "mtspr 256,%1";
315 else
316 return "mtvrsave %1";
317 }
318 [(set_attr "type" "*")])
319
320 (define_insn "*save_world"
321 [(match_parallel 0 "save_world_operation"
322 [(clobber (reg:SI 65))
323 (use (match_operand:SI 1 "call_operand" "s"))])]
324 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
325 "bl %z1"
326 [(set_attr "type" "branch")
327 (set_attr "length" "4")])
328
329 (define_insn "*restore_world"
330 [(match_parallel 0 "restore_world_operation"
331 [(return)
332 (use (reg:SI 65))
333 (use (match_operand:SI 1 "call_operand" "s"))
334 (clobber (match_operand:SI 2 "gpc_reg_operand" "=r"))])]
335 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
336 "b %z1")
337
338 ;; Simple binary operations.
339
340 ;; add
341 (define_insn "add<mode>3"
342 [(set (match_operand:VI 0 "register_operand" "=v")
343 (plus:VI (match_operand:VI 1 "register_operand" "v")
344 (match_operand:VI 2 "register_operand" "v")))]
345 "TARGET_ALTIVEC"
346 "vaddu<VI_char>m %0,%1,%2"
347 [(set_attr "type" "vecsimple")])
348
349 (define_insn "addv4sf3"
350 [(set (match_operand:V4SF 0 "register_operand" "=v")
351 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
352 (match_operand:V4SF 2 "register_operand" "v")))]
353 "TARGET_ALTIVEC"
354 "vaddfp %0,%1,%2"
355 [(set_attr "type" "vecfloat")])
356
357 (define_insn "altivec_vaddcuw"
358 [(set (match_operand:V4SI 0 "register_operand" "=v")
359 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
360 (match_operand:V4SI 2 "register_operand" "v")]
361 UNSPEC_VADDCUW))]
362 "TARGET_ALTIVEC"
363 "vaddcuw %0,%1,%2"
364 [(set_attr "type" "vecsimple")])
365
366 (define_insn "altivec_vaddu<VI_char>s"
367 [(set (match_operand:VI 0 "register_operand" "=v")
368 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
369 (match_operand:VI 2 "register_operand" "v")]
370 UNSPEC_VADDU))
371 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
372 "TARGET_ALTIVEC"
373 "vaddu<VI_char>s %0,%1,%2"
374 [(set_attr "type" "vecsimple")])
375
376 (define_insn "altivec_vadds<VI_char>s"
377 [(set (match_operand:VI 0 "register_operand" "=v")
378 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
379 (match_operand:VI 2 "register_operand" "v")]
380 UNSPEC_VADDS))
381 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
382 "TARGET_ALTIVEC"
383 "vadds<VI_char>s %0,%1,%2"
384 [(set_attr "type" "vecsimple")])
385
386 ;; sub
387 (define_insn "sub<mode>3"
388 [(set (match_operand:VI 0 "register_operand" "=v")
389 (minus:VI (match_operand:VI 1 "register_operand" "v")
390 (match_operand:VI 2 "register_operand" "v")))]
391 "TARGET_ALTIVEC"
392 "vsubu<VI_char>m %0,%1,%2"
393 [(set_attr "type" "vecsimple")])
394
395 (define_insn "subv4sf3"
396 [(set (match_operand:V4SF 0 "register_operand" "=v")
397 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
398 (match_operand:V4SF 2 "register_operand" "v")))]
399 "TARGET_ALTIVEC"
400 "vsubfp %0,%1,%2"
401 [(set_attr "type" "vecfloat")])
402
403 (define_insn "altivec_vsubcuw"
404 [(set (match_operand:V4SI 0 "register_operand" "=v")
405 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
406 (match_operand:V4SI 2 "register_operand" "v")]
407 UNSPEC_VSUBCUW))]
408 "TARGET_ALTIVEC"
409 "vsubcuw %0,%1,%2"
410 [(set_attr "type" "vecsimple")])
411
412 (define_insn "altivec_vsubu<VI_char>s"
413 [(set (match_operand:VI 0 "register_operand" "=v")
414 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
415 (match_operand:VI 2 "register_operand" "v")]
416 UNSPEC_VSUBU))
417 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
418 "TARGET_ALTIVEC"
419 "vsubu<VI_char>s %0,%1,%2"
420 [(set_attr "type" "vecsimple")])
421
422 (define_insn "altivec_vsubs<VI_char>s"
423 [(set (match_operand:VI 0 "register_operand" "=v")
424 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
425 (match_operand:VI 2 "register_operand" "v")]
426 UNSPEC_VSUBS))
427 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
428 "TARGET_ALTIVEC"
429 "vsubs<VI_char>s %0,%1,%2"
430 [(set_attr "type" "vecsimple")])
431
432 ;;
433 (define_insn "altivec_vavgu<VI_char>"
434 [(set (match_operand:VI 0 "register_operand" "=v")
435 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
436 (match_operand:VI 2 "register_operand" "v")]
437 UNSPEC_VAVGU))]
438 "TARGET_ALTIVEC"
439 "vavgu<VI_char> %0,%1,%2"
440 [(set_attr "type" "vecsimple")])
441
442 (define_insn "altivec_vavgs<VI_char>"
443 [(set (match_operand:VI 0 "register_operand" "=v")
444 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
445 (match_operand:VI 2 "register_operand" "v")]
446 UNSPEC_VAVGS))]
447 "TARGET_ALTIVEC"
448 "vavgs<VI_char> %0,%1,%2"
449 [(set_attr "type" "vecsimple")])
450
451 (define_insn "altivec_vcmpbfp"
452 [(set (match_operand:V4SI 0 "register_operand" "=v")
453 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
454 (match_operand:V4SF 2 "register_operand" "v")]
455 UNSPEC_VCMPBFP))]
456 "TARGET_ALTIVEC"
457 "vcmpbfp %0,%1,%2"
458 [(set_attr "type" "veccmp")])
459
460 (define_insn "altivec_vcmpequb"
461 [(set (match_operand:V16QI 0 "register_operand" "=v")
462 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
463 (match_operand:V16QI 2 "register_operand" "v")]
464 UNSPEC_VCMPEQUB))]
465 "TARGET_ALTIVEC"
466 "vcmpequb %0,%1,%2"
467 [(set_attr "type" "vecsimple")])
468
469 (define_insn "altivec_vcmpequh"
470 [(set (match_operand:V8HI 0 "register_operand" "=v")
471 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
472 (match_operand:V8HI 2 "register_operand" "v")]
473 UNSPEC_VCMPEQUH))]
474 "TARGET_ALTIVEC"
475 "vcmpequh %0,%1,%2"
476 [(set_attr "type" "vecsimple")])
477
478 (define_insn "altivec_vcmpequw"
479 [(set (match_operand:V4SI 0 "register_operand" "=v")
480 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
481 (match_operand:V4SI 2 "register_operand" "v")]
482 UNSPEC_VCMPEQUW))]
483 "TARGET_ALTIVEC"
484 "vcmpequw %0,%1,%2"
485 [(set_attr "type" "vecsimple")])
486
487 (define_insn "altivec_vcmpeqfp"
488 [(set (match_operand:V4SI 0 "register_operand" "=v")
489 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
490 (match_operand:V4SF 2 "register_operand" "v")]
491 UNSPEC_VCMPEQFP))]
492 "TARGET_ALTIVEC"
493 "vcmpeqfp %0,%1,%2"
494 [(set_attr "type" "veccmp")])
495
496 (define_insn "altivec_vcmpgefp"
497 [(set (match_operand:V4SI 0 "register_operand" "=v")
498 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
499 (match_operand:V4SF 2 "register_operand" "v")]
500 UNSPEC_VCMPGEFP))]
501 "TARGET_ALTIVEC"
502 "vcmpgefp %0,%1,%2"
503 [(set_attr "type" "veccmp")])
504
505 (define_insn "altivec_vcmpgtub"
506 [(set (match_operand:V16QI 0 "register_operand" "=v")
507 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
508 (match_operand:V16QI 2 "register_operand" "v")]
509 UNSPEC_VCMPGTUB))]
510 "TARGET_ALTIVEC"
511 "vcmpgtub %0,%1,%2"
512 [(set_attr "type" "vecsimple")])
513
514 (define_insn "altivec_vcmpgtsb"
515 [(set (match_operand:V16QI 0 "register_operand" "=v")
516 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
517 (match_operand:V16QI 2 "register_operand" "v")]
518 UNSPEC_VCMPGTSB))]
519 "TARGET_ALTIVEC"
520 "vcmpgtsb %0,%1,%2"
521 [(set_attr "type" "vecsimple")])
522
523 (define_insn "altivec_vcmpgtuh"
524 [(set (match_operand:V8HI 0 "register_operand" "=v")
525 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
526 (match_operand:V8HI 2 "register_operand" "v")]
527 UNSPEC_VCMPGTUH))]
528 "TARGET_ALTIVEC"
529 "vcmpgtuh %0,%1,%2"
530 [(set_attr "type" "vecsimple")])
531
532 (define_insn "altivec_vcmpgtsh"
533 [(set (match_operand:V8HI 0 "register_operand" "=v")
534 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
535 (match_operand:V8HI 2 "register_operand" "v")]
536 UNSPEC_VCMPGTSH))]
537 "TARGET_ALTIVEC"
538 "vcmpgtsh %0,%1,%2"
539 [(set_attr "type" "vecsimple")])
540
541 (define_insn "altivec_vcmpgtuw"
542 [(set (match_operand:V4SI 0 "register_operand" "=v")
543 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
544 (match_operand:V4SI 2 "register_operand" "v")]
545 UNSPEC_VCMPGTUW))]
546 "TARGET_ALTIVEC"
547 "vcmpgtuw %0,%1,%2"
548 [(set_attr "type" "vecsimple")])
549
550 (define_insn "altivec_vcmpgtsw"
551 [(set (match_operand:V4SI 0 "register_operand" "=v")
552 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
553 (match_operand:V4SI 2 "register_operand" "v")]
554 UNSPEC_VCMPGTSW))]
555 "TARGET_ALTIVEC"
556 "vcmpgtsw %0,%1,%2"
557 [(set_attr "type" "vecsimple")])
558
559 (define_insn "altivec_vcmpgtfp"
560 [(set (match_operand:V4SI 0 "register_operand" "=v")
561 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
562 (match_operand:V4SF 2 "register_operand" "v")]
563 UNSPEC_VCMPGTFP))]
564 "TARGET_ALTIVEC"
565 "vcmpgtfp %0,%1,%2"
566 [(set_attr "type" "veccmp")])
567
568 ;; Fused multiply add
569 (define_insn "altivec_vmaddfp"
570 [(set (match_operand:V4SF 0 "register_operand" "=v")
571 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
572 (match_operand:V4SF 2 "register_operand" "v"))
573 (match_operand:V4SF 3 "register_operand" "v")))]
574 "TARGET_ALTIVEC"
575 "vmaddfp %0,%1,%2,%3"
576 [(set_attr "type" "vecfloat")])
577
578 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
579
580 (define_expand "mulv4sf3"
581 [(use (match_operand:V4SF 0 "register_operand" ""))
582 (use (match_operand:V4SF 1 "register_operand" ""))
583 (use (match_operand:V4SF 2 "register_operand" ""))]
584 "TARGET_ALTIVEC && TARGET_FUSED_MADD"
585 "
586 {
587 rtx neg0;
588
589 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
590 neg0 = gen_reg_rtx (V4SImode);
591 emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
592 emit_insn (gen_vashlv4si3 (neg0, neg0, neg0));
593
594 /* Use the multiply-add. */
595 emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
596 gen_lowpart (V4SFmode, neg0)));
597 DONE;
598 }")
599
600 ;; 32-bit integer multiplication
601 ;; A_high = Operand_0 & 0xFFFF0000 >> 16
602 ;; A_low = Operand_0 & 0xFFFF
603 ;; B_high = Operand_1 & 0xFFFF0000 >> 16
604 ;; B_low = Operand_1 & 0xFFFF
605 ;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
606
607 ;; (define_insn "mulv4si3"
608 ;; [(set (match_operand:V4SI 0 "register_operand" "=v")
609 ;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
610 ;; (match_operand:V4SI 2 "register_operand" "v")))]
611 (define_expand "mulv4si3"
612 [(use (match_operand:V4SI 0 "register_operand" ""))
613 (use (match_operand:V4SI 1 "register_operand" ""))
614 (use (match_operand:V4SI 2 "register_operand" ""))]
615 "TARGET_ALTIVEC"
616 "
617 {
618 rtx zero;
619 rtx swap;
620 rtx small_swap;
621 rtx sixteen;
622 rtx one;
623 rtx two;
624 rtx low_product;
625 rtx high_product;
626
627 zero = gen_reg_rtx (V4SImode);
628 emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
629
630 sixteen = gen_reg_rtx (V4SImode);
631 emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode, -16)));
632
633 swap = gen_reg_rtx (V4SImode);
634 emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
635
636 one = gen_reg_rtx (V8HImode);
637 convert_move (one, operands[1], 0);
638
639 two = gen_reg_rtx (V8HImode);
640 convert_move (two, operands[2], 0);
641
642 small_swap = gen_reg_rtx (V8HImode);
643 convert_move (small_swap, swap, 0);
644
645 low_product = gen_reg_rtx (V4SImode);
646 emit_insn (gen_altivec_vmulouh (low_product, one, two));
647
648 high_product = gen_reg_rtx (V4SImode);
649 emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
650
651 emit_insn (gen_vashlv4si3 (high_product, high_product, sixteen));
652
653 emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
654
655 DONE;
656 }")
657
658 (define_expand "mulv8hi3"
659 [(use (match_operand:V8HI 0 "register_operand" ""))
660 (use (match_operand:V8HI 1 "register_operand" ""))
661 (use (match_operand:V8HI 2 "register_operand" ""))]
662 "TARGET_ALTIVEC"
663 "
664 {
665 rtx odd = gen_reg_rtx (V4SImode);
666 rtx even = gen_reg_rtx (V4SImode);
667 rtx high = gen_reg_rtx (V4SImode);
668 rtx low = gen_reg_rtx (V4SImode);
669
670 emit_insn (gen_altivec_vmulesh (even, operands[1], operands[2]));
671 emit_insn (gen_altivec_vmulosh (odd, operands[1], operands[2]));
672
673 emit_insn (gen_altivec_vmrghw (high, even, odd));
674 emit_insn (gen_altivec_vmrglw (low, even, odd));
675
676 emit_insn (gen_altivec_vpkuwum (operands[0], high, low));
677
678 DONE;
679 }")
680
681 ;; Fused multiply subtract
682 (define_insn "altivec_vnmsubfp"
683 [(set (match_operand:V4SF 0 "register_operand" "=v")
684 (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
685 (match_operand:V4SF 2 "register_operand" "v"))
686 (match_operand:V4SF 3 "register_operand" "v"))))]
687 "TARGET_ALTIVEC"
688 "vnmsubfp %0,%1,%2,%3"
689 [(set_attr "type" "vecfloat")])
690
691 (define_insn "altivec_vmsumu<VI_char>m"
692 [(set (match_operand:V4SI 0 "register_operand" "=v")
693 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
694 (match_operand:VIshort 2 "register_operand" "v")
695 (match_operand:V4SI 3 "register_operand" "v")]
696 UNSPEC_VMSUMU))]
697 "TARGET_ALTIVEC"
698 "vmsumu<VI_char>m %0,%1,%2,%3"
699 [(set_attr "type" "veccomplex")])
700
701 (define_insn "altivec_vmsumm<VI_char>m"
702 [(set (match_operand:V4SI 0 "register_operand" "=v")
703 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
704 (match_operand:VIshort 2 "register_operand" "v")
705 (match_operand:V4SI 3 "register_operand" "v")]
706 UNSPEC_VMSUMM))]
707 "TARGET_ALTIVEC"
708 "vmsumm<VI_char>m %0,%1,%2,%3"
709 [(set_attr "type" "veccomplex")])
710
711 (define_insn "altivec_vmsumshm"
712 [(set (match_operand:V4SI 0 "register_operand" "=v")
713 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
714 (match_operand:V8HI 2 "register_operand" "v")
715 (match_operand:V4SI 3 "register_operand" "v")]
716 UNSPEC_VMSUMSHM))]
717 "TARGET_ALTIVEC"
718 "vmsumshm %0,%1,%2,%3"
719 [(set_attr "type" "veccomplex")])
720
721 (define_insn "altivec_vmsumuhs"
722 [(set (match_operand:V4SI 0 "register_operand" "=v")
723 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
724 (match_operand:V8HI 2 "register_operand" "v")
725 (match_operand:V4SI 3 "register_operand" "v")]
726 UNSPEC_VMSUMUHS))
727 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
728 "TARGET_ALTIVEC"
729 "vmsumuhs %0,%1,%2,%3"
730 [(set_attr "type" "veccomplex")])
731
732 (define_insn "altivec_vmsumshs"
733 [(set (match_operand:V4SI 0 "register_operand" "=v")
734 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
735 (match_operand:V8HI 2 "register_operand" "v")
736 (match_operand:V4SI 3 "register_operand" "v")]
737 UNSPEC_VMSUMSHS))
738 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
739 "TARGET_ALTIVEC"
740 "vmsumshs %0,%1,%2,%3"
741 [(set_attr "type" "veccomplex")])
742
743 ;; max
744
745 (define_insn "umax<mode>3"
746 [(set (match_operand:VI 0 "register_operand" "=v")
747 (umax:VI (match_operand:VI 1 "register_operand" "v")
748 (match_operand:VI 2 "register_operand" "v")))]
749 "TARGET_ALTIVEC"
750 "vmaxu<VI_char> %0,%1,%2"
751 [(set_attr "type" "vecsimple")])
752
753 (define_insn "smax<mode>3"
754 [(set (match_operand:VI 0 "register_operand" "=v")
755 (smax:VI (match_operand:VI 1 "register_operand" "v")
756 (match_operand:VI 2 "register_operand" "v")))]
757 "TARGET_ALTIVEC"
758 "vmaxs<VI_char> %0,%1,%2"
759 [(set_attr "type" "vecsimple")])
760
761 (define_insn "smaxv4sf3"
762 [(set (match_operand:V4SF 0 "register_operand" "=v")
763 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
764 (match_operand:V4SF 2 "register_operand" "v")))]
765 "TARGET_ALTIVEC"
766 "vmaxfp %0,%1,%2"
767 [(set_attr "type" "veccmp")])
768
769 (define_insn "umin<mode>3"
770 [(set (match_operand:VI 0 "register_operand" "=v")
771 (umin:VI (match_operand:VI 1 "register_operand" "v")
772 (match_operand:VI 2 "register_operand" "v")))]
773 "TARGET_ALTIVEC"
774 "vminu<VI_char> %0,%1,%2"
775 [(set_attr "type" "vecsimple")])
776
777 (define_insn "smin<mode>3"
778 [(set (match_operand:VI 0 "register_operand" "=v")
779 (smin:VI (match_operand:VI 1 "register_operand" "v")
780 (match_operand:VI 2 "register_operand" "v")))]
781 "TARGET_ALTIVEC"
782 "vmins<VI_char> %0,%1,%2"
783 [(set_attr "type" "vecsimple")])
784
785 (define_insn "sminv4sf3"
786 [(set (match_operand:V4SF 0 "register_operand" "=v")
787 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
788 (match_operand:V4SF 2 "register_operand" "v")))]
789 "TARGET_ALTIVEC"
790 "vminfp %0,%1,%2"
791 [(set_attr "type" "veccmp")])
792
793 (define_insn "altivec_vmhaddshs"
794 [(set (match_operand:V8HI 0 "register_operand" "=v")
795 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
796 (match_operand:V8HI 2 "register_operand" "v")
797 (match_operand:V8HI 3 "register_operand" "v")]
798 UNSPEC_VMHADDSHS))
799 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
800 "TARGET_ALTIVEC"
801 "vmhaddshs %0,%1,%2,%3"
802 [(set_attr "type" "veccomplex")])
803
804 (define_insn "altivec_vmhraddshs"
805 [(set (match_operand:V8HI 0 "register_operand" "=v")
806 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
807 (match_operand:V8HI 2 "register_operand" "v")
808 (match_operand:V8HI 3 "register_operand" "v")]
809 UNSPEC_VMHRADDSHS))
810 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
811 "TARGET_ALTIVEC"
812 "vmhraddshs %0,%1,%2,%3"
813 [(set_attr "type" "veccomplex")])
814
815 (define_insn "altivec_vmladduhm"
816 [(set (match_operand:V8HI 0 "register_operand" "=v")
817 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
818 (match_operand:V8HI 2 "register_operand" "v")
819 (match_operand:V8HI 3 "register_operand" "v")]
820 UNSPEC_VMLADDUHM))]
821 "TARGET_ALTIVEC"
822 "vmladduhm %0,%1,%2,%3"
823 [(set_attr "type" "veccomplex")])
824
825 (define_insn "altivec_vmrghb"
826 [(set (match_operand:V16QI 0 "register_operand" "=v")
827 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
828 (parallel [(const_int 0)
829 (const_int 8)
830 (const_int 1)
831 (const_int 9)
832 (const_int 2)
833 (const_int 10)
834 (const_int 3)
835 (const_int 11)
836 (const_int 4)
837 (const_int 12)
838 (const_int 5)
839 (const_int 13)
840 (const_int 6)
841 (const_int 14)
842 (const_int 7)
843 (const_int 15)]))
844 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
845 (parallel [(const_int 8)
846 (const_int 0)
847 (const_int 9)
848 (const_int 1)
849 (const_int 10)
850 (const_int 2)
851 (const_int 11)
852 (const_int 3)
853 (const_int 12)
854 (const_int 4)
855 (const_int 13)
856 (const_int 5)
857 (const_int 14)
858 (const_int 6)
859 (const_int 15)
860 (const_int 7)]))
861 (const_int 21845)))]
862 "TARGET_ALTIVEC"
863 "vmrghb %0,%1,%2"
864 [(set_attr "type" "vecperm")])
865
866 (define_insn "altivec_vmrghh"
867 [(set (match_operand:V8HI 0 "register_operand" "=v")
868 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
869 (parallel [(const_int 0)
870 (const_int 4)
871 (const_int 1)
872 (const_int 5)
873 (const_int 2)
874 (const_int 6)
875 (const_int 3)
876 (const_int 7)]))
877 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
878 (parallel [(const_int 4)
879 (const_int 0)
880 (const_int 5)
881 (const_int 1)
882 (const_int 6)
883 (const_int 2)
884 (const_int 7)
885 (const_int 3)]))
886 (const_int 85)))]
887 "TARGET_ALTIVEC"
888 "vmrghh %0,%1,%2"
889 [(set_attr "type" "vecperm")])
890
891 (define_insn "altivec_vmrghw"
892 [(set (match_operand:V4SI 0 "register_operand" "=v")
893 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
894 (parallel [(const_int 0)
895 (const_int 2)
896 (const_int 1)
897 (const_int 3)]))
898 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
899 (parallel [(const_int 2)
900 (const_int 0)
901 (const_int 3)
902 (const_int 1)]))
903 (const_int 5)))]
904 "TARGET_ALTIVEC"
905 "vmrghw %0,%1,%2"
906 [(set_attr "type" "vecperm")])
907
908 (define_insn "altivec_vmrghsf"
909 [(set (match_operand:V4SF 0 "register_operand" "=v")
910 (vec_merge:V4SF (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
911 (parallel [(const_int 0)
912 (const_int 2)
913 (const_int 1)
914 (const_int 3)]))
915 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
916 (parallel [(const_int 2)
917 (const_int 0)
918 (const_int 3)
919 (const_int 1)]))
920 (const_int 5)))]
921 "TARGET_ALTIVEC"
922 "vmrghw %0,%1,%2"
923 [(set_attr "type" "vecperm")])
924
925 (define_insn "altivec_vmrglb"
926 [(set (match_operand:V16QI 0 "register_operand" "=v")
927 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
928 (parallel [(const_int 8)
929 (const_int 0)
930 (const_int 9)
931 (const_int 1)
932 (const_int 10)
933 (const_int 2)
934 (const_int 11)
935 (const_int 3)
936 (const_int 12)
937 (const_int 4)
938 (const_int 13)
939 (const_int 5)
940 (const_int 14)
941 (const_int 6)
942 (const_int 15)
943 (const_int 7)]))
944 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
945 (parallel [(const_int 0)
946 (const_int 8)
947 (const_int 1)
948 (const_int 9)
949 (const_int 2)
950 (const_int 10)
951 (const_int 3)
952 (const_int 11)
953 (const_int 4)
954 (const_int 12)
955 (const_int 5)
956 (const_int 13)
957 (const_int 6)
958 (const_int 14)
959 (const_int 7)
960 (const_int 15)]))
961 (const_int 21845)))]
962 "TARGET_ALTIVEC"
963 "vmrglb %0,%1,%2"
964 [(set_attr "type" "vecperm")])
965
966 (define_insn "altivec_vmrglh"
967 [(set (match_operand:V8HI 0 "register_operand" "=v")
968 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
969 (parallel [(const_int 4)
970 (const_int 0)
971 (const_int 5)
972 (const_int 1)
973 (const_int 6)
974 (const_int 2)
975 (const_int 7)
976 (const_int 3)]))
977 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
978 (parallel [(const_int 0)
979 (const_int 4)
980 (const_int 1)
981 (const_int 5)
982 (const_int 2)
983 (const_int 6)
984 (const_int 3)
985 (const_int 7)]))
986 (const_int 85)))]
987 "TARGET_ALTIVEC"
988 "vmrglh %0,%1,%2"
989 [(set_attr "type" "vecperm")])
990
991 (define_insn "altivec_vmrglw"
992 [(set (match_operand:V4SI 0 "register_operand" "=v")
993 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
994 (parallel [(const_int 2)
995 (const_int 0)
996 (const_int 3)
997 (const_int 1)]))
998 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
999 (parallel [(const_int 0)
1000 (const_int 2)
1001 (const_int 1)
1002 (const_int 3)]))
1003 (const_int 5)))]
1004 "TARGET_ALTIVEC"
1005 "vmrglw %0,%1,%2"
1006 [(set_attr "type" "vecperm")])
1007
1008 (define_insn "altivec_vmrglsf"
1009 [(set (match_operand:V4SF 0 "register_operand" "=v")
1010 (vec_merge:V4SF (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
1011 (parallel [(const_int 2)
1012 (const_int 0)
1013 (const_int 3)
1014 (const_int 1)]))
1015 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
1016 (parallel [(const_int 0)
1017 (const_int 2)
1018 (const_int 1)
1019 (const_int 3)]))
1020 (const_int 5)))]
1021 "TARGET_ALTIVEC"
1022 "vmrglw %0,%1,%2"
1023 [(set_attr "type" "vecperm")])
1024
1025 (define_insn "altivec_vmuleub"
1026 [(set (match_operand:V8HI 0 "register_operand" "=v")
1027 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1028 (match_operand:V16QI 2 "register_operand" "v")]
1029 UNSPEC_VMULEUB))]
1030 "TARGET_ALTIVEC"
1031 "vmuleub %0,%1,%2"
1032 [(set_attr "type" "veccomplex")])
1033
1034 (define_insn "altivec_vmulesb"
1035 [(set (match_operand:V8HI 0 "register_operand" "=v")
1036 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1037 (match_operand:V16QI 2 "register_operand" "v")]
1038 UNSPEC_VMULESB))]
1039 "TARGET_ALTIVEC"
1040 "vmulesb %0,%1,%2"
1041 [(set_attr "type" "veccomplex")])
1042
1043 (define_insn "altivec_vmuleuh"
1044 [(set (match_operand:V4SI 0 "register_operand" "=v")
1045 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1046 (match_operand:V8HI 2 "register_operand" "v")]
1047 UNSPEC_VMULEUH))]
1048 "TARGET_ALTIVEC"
1049 "vmuleuh %0,%1,%2"
1050 [(set_attr "type" "veccomplex")])
1051
1052 (define_insn "altivec_vmulesh"
1053 [(set (match_operand:V4SI 0 "register_operand" "=v")
1054 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1055 (match_operand:V8HI 2 "register_operand" "v")]
1056 UNSPEC_VMULESH))]
1057 "TARGET_ALTIVEC"
1058 "vmulesh %0,%1,%2"
1059 [(set_attr "type" "veccomplex")])
1060
1061 (define_insn "altivec_vmuloub"
1062 [(set (match_operand:V8HI 0 "register_operand" "=v")
1063 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1064 (match_operand:V16QI 2 "register_operand" "v")]
1065 UNSPEC_VMULOUB))]
1066 "TARGET_ALTIVEC"
1067 "vmuloub %0,%1,%2"
1068 [(set_attr "type" "veccomplex")])
1069
1070 (define_insn "altivec_vmulosb"
1071 [(set (match_operand:V8HI 0 "register_operand" "=v")
1072 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1073 (match_operand:V16QI 2 "register_operand" "v")]
1074 UNSPEC_VMULOSB))]
1075 "TARGET_ALTIVEC"
1076 "vmulosb %0,%1,%2"
1077 [(set_attr "type" "veccomplex")])
1078
1079 (define_insn "altivec_vmulouh"
1080 [(set (match_operand:V4SI 0 "register_operand" "=v")
1081 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1082 (match_operand:V8HI 2 "register_operand" "v")]
1083 UNSPEC_VMULOUH))]
1084 "TARGET_ALTIVEC"
1085 "vmulouh %0,%1,%2"
1086 [(set_attr "type" "veccomplex")])
1087
1088 (define_insn "altivec_vmulosh"
1089 [(set (match_operand:V4SI 0 "register_operand" "=v")
1090 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1091 (match_operand:V8HI 2 "register_operand" "v")]
1092 UNSPEC_VMULOSH))]
1093 "TARGET_ALTIVEC"
1094 "vmulosh %0,%1,%2"
1095 [(set_attr "type" "veccomplex")])
1096
1097
1098 ;; logical ops
1099
1100 (define_insn "and<mode>3"
1101 [(set (match_operand:VI 0 "register_operand" "=v")
1102 (and:VI (match_operand:VI 1 "register_operand" "v")
1103 (match_operand:VI 2 "register_operand" "v")))]
1104 "TARGET_ALTIVEC"
1105 "vand %0,%1,%2"
1106 [(set_attr "type" "vecsimple")])
1107
1108 (define_insn "ior<mode>3"
1109 [(set (match_operand:VI 0 "register_operand" "=v")
1110 (ior:VI (match_operand:VI 1 "register_operand" "v")
1111 (match_operand:VI 2 "register_operand" "v")))]
1112 "TARGET_ALTIVEC"
1113 "vor %0,%1,%2"
1114 [(set_attr "type" "vecsimple")])
1115
1116 (define_insn "xor<mode>3"
1117 [(set (match_operand:VI 0 "register_operand" "=v")
1118 (xor:VI (match_operand:VI 1 "register_operand" "v")
1119 (match_operand:VI 2 "register_operand" "v")))]
1120 "TARGET_ALTIVEC"
1121 "vxor %0,%1,%2"
1122 [(set_attr "type" "vecsimple")])
1123
1124 (define_insn "xorv4sf3"
1125 [(set (match_operand:V4SF 0 "register_operand" "=v")
1126 (xor:V4SF (match_operand:V4SF 1 "register_operand" "v")
1127 (match_operand:V4SF 2 "register_operand" "v")))]
1128 "TARGET_ALTIVEC"
1129 "vxor %0,%1,%2"
1130 [(set_attr "type" "vecsimple")])
1131
1132 (define_insn "one_cmpl<mode>2"
1133 [(set (match_operand:VI 0 "register_operand" "=v")
1134 (not:VI (match_operand:VI 1 "register_operand" "v")))]
1135 "TARGET_ALTIVEC"
1136 "vnor %0,%1,%1"
1137 [(set_attr "type" "vecsimple")])
1138
1139 (define_insn "altivec_nor<mode>3"
1140 [(set (match_operand:VI 0 "register_operand" "=v")
1141 (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
1142 (match_operand:VI 2 "register_operand" "v"))))]
1143 "TARGET_ALTIVEC"
1144 "vnor %0,%1,%2"
1145 [(set_attr "type" "vecsimple")])
1146
1147 (define_insn "andc<mode>3"
1148 [(set (match_operand:VI 0 "register_operand" "=v")
1149 (and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
1150 (match_operand:VI 1 "register_operand" "v")))]
1151 "TARGET_ALTIVEC"
1152 "vandc %0,%1,%2"
1153 [(set_attr "type" "vecsimple")])
1154
1155 (define_insn "*andc3_v4sf"
1156 [(set (match_operand:V4SF 0 "register_operand" "=v")
1157 (and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v"))
1158 (match_operand:V4SF 1 "register_operand" "v")))]
1159 "TARGET_ALTIVEC"
1160 "vandc %0,%1,%2"
1161 [(set_attr "type" "vecsimple")])
1162
1163 (define_insn "altivec_vpkuhum"
1164 [(set (match_operand:V16QI 0 "register_operand" "=v")
1165 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1166 (match_operand:V8HI 2 "register_operand" "v")]
1167 UNSPEC_VPKUHUM))]
1168 "TARGET_ALTIVEC"
1169 "vpkuhum %0,%1,%2"
1170 [(set_attr "type" "vecperm")])
1171
1172 (define_insn "altivec_vpkuwum"
1173 [(set (match_operand:V8HI 0 "register_operand" "=v")
1174 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1175 (match_operand:V4SI 2 "register_operand" "v")]
1176 UNSPEC_VPKUWUM))]
1177 "TARGET_ALTIVEC"
1178 "vpkuwum %0,%1,%2"
1179 [(set_attr "type" "vecperm")])
1180
1181 (define_insn "altivec_vpkpx"
1182 [(set (match_operand:V8HI 0 "register_operand" "=v")
1183 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1184 (match_operand:V4SI 2 "register_operand" "v")]
1185 UNSPEC_VPKPX))]
1186 "TARGET_ALTIVEC"
1187 "vpkpx %0,%1,%2"
1188 [(set_attr "type" "vecperm")])
1189
1190 (define_insn "altivec_vpkshss"
1191 [(set (match_operand:V16QI 0 "register_operand" "=v")
1192 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1193 (match_operand:V8HI 2 "register_operand" "v")]
1194 UNSPEC_VPKSHSS))
1195 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1196 "TARGET_ALTIVEC"
1197 "vpkshss %0,%1,%2"
1198 [(set_attr "type" "vecperm")])
1199
1200 (define_insn "altivec_vpkswss"
1201 [(set (match_operand:V8HI 0 "register_operand" "=v")
1202 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1203 (match_operand:V4SI 2 "register_operand" "v")]
1204 UNSPEC_VPKSWSS))
1205 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1206 "TARGET_ALTIVEC"
1207 "vpkswss %0,%1,%2"
1208 [(set_attr "type" "vecperm")])
1209
1210 (define_insn "altivec_vpkuhus"
1211 [(set (match_operand:V16QI 0 "register_operand" "=v")
1212 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1213 (match_operand:V8HI 2 "register_operand" "v")]
1214 UNSPEC_VPKUHUS))
1215 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1216 "TARGET_ALTIVEC"
1217 "vpkuhus %0,%1,%2"
1218 [(set_attr "type" "vecperm")])
1219
1220 (define_insn "altivec_vpkshus"
1221 [(set (match_operand:V16QI 0 "register_operand" "=v")
1222 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1223 (match_operand:V8HI 2 "register_operand" "v")]
1224 UNSPEC_VPKSHUS))
1225 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1226 "TARGET_ALTIVEC"
1227 "vpkshus %0,%1,%2"
1228 [(set_attr "type" "vecperm")])
1229
1230 (define_insn "altivec_vpkuwus"
1231 [(set (match_operand:V8HI 0 "register_operand" "=v")
1232 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1233 (match_operand:V4SI 2 "register_operand" "v")]
1234 UNSPEC_VPKUWUS))
1235 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1236 "TARGET_ALTIVEC"
1237 "vpkuwus %0,%1,%2"
1238 [(set_attr "type" "vecperm")])
1239
1240 (define_insn "altivec_vpkswus"
1241 [(set (match_operand:V8HI 0 "register_operand" "=v")
1242 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1243 (match_operand:V4SI 2 "register_operand" "v")]
1244 UNSPEC_VPKSWUS))
1245 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1246 "TARGET_ALTIVEC"
1247 "vpkswus %0,%1,%2"
1248 [(set_attr "type" "vecperm")])
1249
1250 (define_insn "altivec_vrl<VI_char>"
1251 [(set (match_operand:VI 0 "register_operand" "=v")
1252 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1253 (match_operand:VI 2 "register_operand" "v")]
1254 UNSPEC_VRL))]
1255 "TARGET_ALTIVEC"
1256 "vrl<VI_char> %0,%1,%2"
1257 [(set_attr "type" "vecsimple")])
1258
1259 (define_insn "altivec_vsl"
1260 [(set (match_operand:V4SI 0 "register_operand" "=v")
1261 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1262 (match_operand:V4SI 2 "register_operand" "v")]
1263 UNSPEC_VSLV4SI))]
1264 "TARGET_ALTIVEC"
1265 "vsl %0,%1,%2"
1266 [(set_attr "type" "vecperm")])
1267
1268 (define_insn "altivec_vslo"
1269 [(set (match_operand:V4SI 0 "register_operand" "=v")
1270 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1271 (match_operand:V4SI 2 "register_operand" "v")]
1272 UNSPEC_VSLO))]
1273 "TARGET_ALTIVEC"
1274 "vslo %0,%1,%2"
1275 [(set_attr "type" "vecperm")])
1276
1277 (define_insn "vashl<mode>3"
1278 [(set (match_operand:VI 0 "register_operand" "=v")
1279 (ashift:VI (match_operand:VI 1 "register_operand" "v")
1280 (match_operand:VI 2 "register_operand" "v") ))]
1281 "TARGET_ALTIVEC"
1282 "vsl<VI_char> %0,%1,%2"
1283 [(set_attr "type" "vecsimple")])
1284
1285 (define_insn "vlshr<mode>3"
1286 [(set (match_operand:VI 0 "register_operand" "=v")
1287 (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
1288 (match_operand:VI 2 "register_operand" "v") ))]
1289 "TARGET_ALTIVEC"
1290 "vsr<VI_char> %0,%1,%2"
1291 [(set_attr "type" "vecsimple")])
1292
1293 (define_insn "vashr<mode>3"
1294 [(set (match_operand:VI 0 "register_operand" "=v")
1295 (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
1296 (match_operand:VI 2 "register_operand" "v") ))]
1297 "TARGET_ALTIVEC"
1298 "vsra<VI_char> %0,%1,%2"
1299 [(set_attr "type" "vecsimple")])
1300
1301 (define_insn "altivec_vsr"
1302 [(set (match_operand:V4SI 0 "register_operand" "=v")
1303 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1304 (match_operand:V4SI 2 "register_operand" "v")]
1305 UNSPEC_VSR))]
1306 "TARGET_ALTIVEC"
1307 "vsr %0,%1,%2"
1308 [(set_attr "type" "vecperm")])
1309
1310 (define_insn "altivec_vsro"
1311 [(set (match_operand:V4SI 0 "register_operand" "=v")
1312 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1313 (match_operand:V4SI 2 "register_operand" "v")]
1314 UNSPEC_VSRO))]
1315 "TARGET_ALTIVEC"
1316 "vsro %0,%1,%2"
1317 [(set_attr "type" "vecperm")])
1318
1319 (define_insn "altivec_vsum4ubs"
1320 [(set (match_operand:V4SI 0 "register_operand" "=v")
1321 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1322 (match_operand:V4SI 2 "register_operand" "v")]
1323 UNSPEC_VSUM4UBS))
1324 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1325 "TARGET_ALTIVEC"
1326 "vsum4ubs %0,%1,%2"
1327 [(set_attr "type" "veccomplex")])
1328
1329 (define_insn "altivec_vsum4s<VI_char>s"
1330 [(set (match_operand:V4SI 0 "register_operand" "=v")
1331 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1332 (match_operand:V4SI 2 "register_operand" "v")]
1333 UNSPEC_VSUM4S))
1334 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1335 "TARGET_ALTIVEC"
1336 "vsum4s<VI_char>s %0,%1,%2"
1337 [(set_attr "type" "veccomplex")])
1338
1339 (define_insn "altivec_vsum2sws"
1340 [(set (match_operand:V4SI 0 "register_operand" "=v")
1341 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1342 (match_operand:V4SI 2 "register_operand" "v")]
1343 UNSPEC_VSUM2SWS))
1344 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1345 "TARGET_ALTIVEC"
1346 "vsum2sws %0,%1,%2"
1347 [(set_attr "type" "veccomplex")])
1348
1349 (define_insn "altivec_vsumsws"
1350 [(set (match_operand:V4SI 0 "register_operand" "=v")
1351 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1352 (match_operand:V4SI 2 "register_operand" "v")]
1353 UNSPEC_VSUMSWS))
1354 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1355 "TARGET_ALTIVEC"
1356 "vsumsws %0,%1,%2"
1357 [(set_attr "type" "veccomplex")])
1358
1359 (define_insn "altivec_vspltb"
1360 [(set (match_operand:V16QI 0 "register_operand" "=v")
1361 (vec_duplicate:V16QI
1362 (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1363 (parallel
1364 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1365 "TARGET_ALTIVEC"
1366 "vspltb %0,%1,%2"
1367 [(set_attr "type" "vecperm")])
1368
1369 (define_insn "altivec_vsplth"
1370 [(set (match_operand:V8HI 0 "register_operand" "=v")
1371 (vec_duplicate:V8HI
1372 (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1373 (parallel
1374 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1375 "TARGET_ALTIVEC"
1376 "vsplth %0,%1,%2"
1377 [(set_attr "type" "vecperm")])
1378
1379 (define_insn "altivec_vspltw"
1380 [(set (match_operand:V4SI 0 "register_operand" "=v")
1381 (vec_duplicate:V4SI
1382 (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1383 (parallel
1384 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1385 "TARGET_ALTIVEC"
1386 "vspltw %0,%1,%2"
1387 [(set_attr "type" "vecperm")])
1388
1389 (define_insn "*altivec_vspltsf"
1390 [(set (match_operand:V4SF 0 "register_operand" "=v")
1391 (vec_duplicate:V4SF
1392 (vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
1393 (parallel
1394 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1395 "TARGET_ALTIVEC"
1396 "vspltw %0,%1,%2"
1397 [(set_attr "type" "vecperm")])
1398
1399 (define_insn "altivec_vspltis<VI_char>"
1400 [(set (match_operand:VI 0 "register_operand" "=v")
1401 (vec_duplicate:VI
1402 (match_operand:QI 1 "s5bit_cint_operand" "i")))]
1403 "TARGET_ALTIVEC"
1404 "vspltis<VI_char> %0,%1"
1405 [(set_attr "type" "vecperm")])
1406
1407 (define_insn "ftruncv4sf2"
1408 [(set (match_operand:V4SF 0 "register_operand" "=v")
1409 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1410 "TARGET_ALTIVEC"
1411 "vrfiz %0,%1"
1412 [(set_attr "type" "vecfloat")])
1413
1414 (define_insn "altivec_vperm_<mode>"
1415 [(set (match_operand:V 0 "register_operand" "=v")
1416 (unspec:V [(match_operand:V 1 "register_operand" "v")
1417 (match_operand:V 2 "register_operand" "v")
1418 (match_operand:V16QI 3 "register_operand" "v")]
1419 UNSPEC_VPERM))]
1420 "TARGET_ALTIVEC"
1421 "vperm %0,%1,%2,%3"
1422 [(set_attr "type" "vecperm")])
1423
1424 (define_insn "altivec_vrfip"
1425 [(set (match_operand:V4SF 0 "register_operand" "=v")
1426 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1427 UNSPEC_VRFIP))]
1428 "TARGET_ALTIVEC"
1429 "vrfip %0,%1"
1430 [(set_attr "type" "vecfloat")])
1431
1432 (define_insn "altivec_vrfin"
1433 [(set (match_operand:V4SF 0 "register_operand" "=v")
1434 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1435 UNSPEC_VRFIN))]
1436 "TARGET_ALTIVEC"
1437 "vrfin %0,%1"
1438 [(set_attr "type" "vecfloat")])
1439
1440 (define_insn "altivec_vrfim"
1441 [(set (match_operand:V4SF 0 "register_operand" "=v")
1442 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1443 UNSPEC_VRFIM))]
1444 "TARGET_ALTIVEC"
1445 "vrfim %0,%1"
1446 [(set_attr "type" "vecfloat")])
1447
1448 (define_insn "altivec_vcfux"
1449 [(set (match_operand:V4SF 0 "register_operand" "=v")
1450 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1451 (match_operand:QI 2 "immediate_operand" "i")]
1452 UNSPEC_VCFUX))]
1453 "TARGET_ALTIVEC"
1454 "vcfux %0,%1,%2"
1455 [(set_attr "type" "vecfloat")])
1456
1457 (define_insn "altivec_vcfsx"
1458 [(set (match_operand:V4SF 0 "register_operand" "=v")
1459 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1460 (match_operand:QI 2 "immediate_operand" "i")]
1461 UNSPEC_VCFSX))]
1462 "TARGET_ALTIVEC"
1463 "vcfsx %0,%1,%2"
1464 [(set_attr "type" "vecfloat")])
1465
1466 (define_insn "altivec_vctuxs"
1467 [(set (match_operand:V4SI 0 "register_operand" "=v")
1468 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1469 (match_operand:QI 2 "immediate_operand" "i")]
1470 UNSPEC_VCTUXS))
1471 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1472 "TARGET_ALTIVEC"
1473 "vctuxs %0,%1,%2"
1474 [(set_attr "type" "vecfloat")])
1475
1476 (define_insn "altivec_vctsxs"
1477 [(set (match_operand:V4SI 0 "register_operand" "=v")
1478 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1479 (match_operand:QI 2 "immediate_operand" "i")]
1480 UNSPEC_VCTSXS))
1481 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1482 "TARGET_ALTIVEC"
1483 "vctsxs %0,%1,%2"
1484 [(set_attr "type" "vecfloat")])
1485
1486 (define_insn "altivec_vlogefp"
1487 [(set (match_operand:V4SF 0 "register_operand" "=v")
1488 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1489 UNSPEC_VLOGEFP))]
1490 "TARGET_ALTIVEC"
1491 "vlogefp %0,%1"
1492 [(set_attr "type" "vecfloat")])
1493
1494 (define_insn "altivec_vexptefp"
1495 [(set (match_operand:V4SF 0 "register_operand" "=v")
1496 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1497 UNSPEC_VEXPTEFP))]
1498 "TARGET_ALTIVEC"
1499 "vexptefp %0,%1"
1500 [(set_attr "type" "vecfloat")])
1501
1502 (define_insn "altivec_vrsqrtefp"
1503 [(set (match_operand:V4SF 0 "register_operand" "=v")
1504 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1505 UNSPEC_VRSQRTEFP))]
1506 "TARGET_ALTIVEC"
1507 "vrsqrtefp %0,%1"
1508 [(set_attr "type" "vecfloat")])
1509
1510 (define_insn "altivec_vrefp"
1511 [(set (match_operand:V4SF 0 "register_operand" "=v")
1512 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1513 UNSPEC_VREFP))]
1514 "TARGET_ALTIVEC"
1515 "vrefp %0,%1"
1516 [(set_attr "type" "vecfloat")])
1517
1518 (define_expand "vcondv4si"
1519 [(set (match_operand:V4SI 0 "register_operand" "=v")
1520 (if_then_else:V4SI
1521 (match_operator 3 "comparison_operator"
1522 [(match_operand:V4SI 4 "register_operand" "v")
1523 (match_operand:V4SI 5 "register_operand" "v")])
1524 (match_operand:V4SI 1 "register_operand" "v")
1525 (match_operand:V4SI 2 "register_operand" "v")))]
1526 "TARGET_ALTIVEC"
1527 "
1528 {
1529 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1530 operands[3], operands[4], operands[5]))
1531 DONE;
1532 else
1533 FAIL;
1534 }
1535 ")
1536
1537 (define_expand "vconduv4si"
1538 [(set (match_operand:V4SI 0 "register_operand" "=v")
1539 (if_then_else:V4SI
1540 (match_operator 3 "comparison_operator"
1541 [(match_operand:V4SI 4 "register_operand" "v")
1542 (match_operand:V4SI 5 "register_operand" "v")])
1543 (match_operand:V4SI 1 "register_operand" "v")
1544 (match_operand:V4SI 2 "register_operand" "v")))]
1545 "TARGET_ALTIVEC"
1546 "
1547 {
1548 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1549 operands[3], operands[4], operands[5]))
1550 DONE;
1551 else
1552 FAIL;
1553 }
1554 ")
1555
1556 (define_expand "vcondv4sf"
1557 [(set (match_operand:V4SF 0 "register_operand" "=v")
1558 (if_then_else:V4SF
1559 (match_operator 3 "comparison_operator"
1560 [(match_operand:V4SF 4 "register_operand" "v")
1561 (match_operand:V4SF 5 "register_operand" "v")])
1562 (match_operand:V4SF 1 "register_operand" "v")
1563 (match_operand:V4SF 2 "register_operand" "v")))]
1564 "TARGET_ALTIVEC"
1565 "
1566 {
1567 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1568 operands[3], operands[4], operands[5]))
1569 DONE;
1570 else
1571 FAIL;
1572 }
1573 ")
1574
1575 (define_expand "vcondv8hi"
1576 [(set (match_operand:V8HI 0 "register_operand" "=v")
1577 (if_then_else:V8HI
1578 (match_operator 3 "comparison_operator"
1579 [(match_operand:V8HI 4 "register_operand" "v")
1580 (match_operand:V8HI 5 "register_operand" "v")])
1581 (match_operand:V8HI 1 "register_operand" "v")
1582 (match_operand:V8HI 2 "register_operand" "v")))]
1583 "TARGET_ALTIVEC"
1584 "
1585 {
1586 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1587 operands[3], operands[4], operands[5]))
1588 DONE;
1589 else
1590 FAIL;
1591 }
1592 ")
1593
1594 (define_expand "vconduv8hi"
1595 [(set (match_operand:V8HI 0 "register_operand" "=v")
1596 (if_then_else:V8HI
1597 (match_operator 3 "comparison_operator"
1598 [(match_operand:V8HI 4 "register_operand" "v")
1599 (match_operand:V8HI 5 "register_operand" "v")])
1600 (match_operand:V8HI 1 "register_operand" "v")
1601 (match_operand:V8HI 2 "register_operand" "v")))]
1602 "TARGET_ALTIVEC"
1603 "
1604 {
1605 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1606 operands[3], operands[4], operands[5]))
1607 DONE;
1608 else
1609 FAIL;
1610 }
1611 ")
1612
1613 (define_expand "vcondv16qi"
1614 [(set (match_operand:V16QI 0 "register_operand" "=v")
1615 (if_then_else:V16QI
1616 (match_operator 3 "comparison_operator"
1617 [(match_operand:V16QI 4 "register_operand" "v")
1618 (match_operand:V16QI 5 "register_operand" "v")])
1619 (match_operand:V16QI 1 "register_operand" "v")
1620 (match_operand:V16QI 2 "register_operand" "v")))]
1621 "TARGET_ALTIVEC"
1622 "
1623 {
1624 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1625 operands[3], operands[4], operands[5]))
1626 DONE;
1627 else
1628 FAIL;
1629 }
1630 ")
1631
1632 (define_expand "vconduv16qi"
1633 [(set (match_operand:V16QI 0 "register_operand" "=v")
1634 (if_then_else:V16QI
1635 (match_operator 3 "comparison_operator"
1636 [(match_operand:V16QI 4 "register_operand" "v")
1637 (match_operand:V16QI 5 "register_operand" "v")])
1638 (match_operand:V16QI 1 "register_operand" "v")
1639 (match_operand:V16QI 2 "register_operand" "v")))]
1640 "TARGET_ALTIVEC"
1641 "
1642 {
1643 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1644 operands[3], operands[4], operands[5]))
1645 DONE;
1646 else
1647 FAIL;
1648 }
1649 ")
1650
1651
1652 (define_insn "altivec_vsel_v4si"
1653 [(set (match_operand:V4SI 0 "register_operand" "=v")
1654 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1655 (match_operand:V4SI 2 "register_operand" "v")
1656 (match_operand:V4SI 3 "register_operand" "v")]
1657 UNSPEC_VSEL4SI))]
1658 "TARGET_ALTIVEC"
1659 "vsel %0,%1,%2,%3"
1660 [(set_attr "type" "vecperm")])
1661
1662 (define_insn "altivec_vsel_v4sf"
1663 [(set (match_operand:V4SF 0 "register_operand" "=v")
1664 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1665 (match_operand:V4SF 2 "register_operand" "v")
1666 (match_operand:V4SI 3 "register_operand" "v")]
1667 UNSPEC_VSEL4SF))]
1668 "TARGET_ALTIVEC"
1669 "vsel %0,%1,%2,%3"
1670 [(set_attr "type" "vecperm")])
1671
1672 (define_insn "altivec_vsel_v8hi"
1673 [(set (match_operand:V8HI 0 "register_operand" "=v")
1674 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1675 (match_operand:V8HI 2 "register_operand" "v")
1676 (match_operand:V8HI 3 "register_operand" "v")]
1677 UNSPEC_VSEL8HI))]
1678 "TARGET_ALTIVEC"
1679 "vsel %0,%1,%2,%3"
1680 [(set_attr "type" "vecperm")])
1681
1682 (define_insn "altivec_vsel_v16qi"
1683 [(set (match_operand:V16QI 0 "register_operand" "=v")
1684 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1685 (match_operand:V16QI 2 "register_operand" "v")
1686 (match_operand:V16QI 3 "register_operand" "v")]
1687 UNSPEC_VSEL16QI))]
1688 "TARGET_ALTIVEC"
1689 "vsel %0,%1,%2,%3"
1690 [(set_attr "type" "vecperm")])
1691
1692 (define_insn "altivec_vsldoi_<mode>"
1693 [(set (match_operand:V 0 "register_operand" "=v")
1694 (unspec:V [(match_operand:V 1 "register_operand" "v")
1695 (match_operand:V 2 "register_operand" "v")
1696 (match_operand:QI 3 "immediate_operand" "i")]
1697 UNSPEC_VLSDOI))]
1698 "TARGET_ALTIVEC"
1699 "vsldoi %0,%1,%2,%3"
1700 [(set_attr "type" "vecperm")])
1701
1702 (define_insn "altivec_vupkhsb"
1703 [(set (match_operand:V8HI 0 "register_operand" "=v")
1704 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1705 UNSPEC_VUPKHSB))]
1706 "TARGET_ALTIVEC"
1707 "vupkhsb %0,%1"
1708 [(set_attr "type" "vecperm")])
1709
1710 (define_insn "altivec_vupkhpx"
1711 [(set (match_operand:V4SI 0 "register_operand" "=v")
1712 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1713 UNSPEC_VUPKHPX))]
1714 "TARGET_ALTIVEC"
1715 "vupkhpx %0,%1"
1716 [(set_attr "type" "vecperm")])
1717
1718 (define_insn "altivec_vupkhsh"
1719 [(set (match_operand:V4SI 0 "register_operand" "=v")
1720 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1721 UNSPEC_VUPKHSH))]
1722 "TARGET_ALTIVEC"
1723 "vupkhsh %0,%1"
1724 [(set_attr "type" "vecperm")])
1725
1726 (define_insn "altivec_vupklsb"
1727 [(set (match_operand:V8HI 0 "register_operand" "=v")
1728 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1729 UNSPEC_VUPKLSB))]
1730 "TARGET_ALTIVEC"
1731 "vupklsb %0,%1"
1732 [(set_attr "type" "vecperm")])
1733
1734 (define_insn "altivec_vupklpx"
1735 [(set (match_operand:V4SI 0 "register_operand" "=v")
1736 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1737 UNSPEC_VUPKLPX))]
1738 "TARGET_ALTIVEC"
1739 "vupklpx %0,%1"
1740 [(set_attr "type" "vecperm")])
1741
1742 (define_insn "altivec_vupklsh"
1743 [(set (match_operand:V4SI 0 "register_operand" "=v")
1744 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1745 UNSPEC_VUPKLSH))]
1746 "TARGET_ALTIVEC"
1747 "vupklsh %0,%1"
1748 [(set_attr "type" "vecperm")])
1749
1750 ;; AltiVec predicates.
1751
1752 (define_expand "cr6_test_for_zero"
1753 [(set (match_operand:SI 0 "register_operand" "=r")
1754 (eq:SI (reg:CC 74)
1755 (const_int 0)))]
1756 "TARGET_ALTIVEC"
1757 "")
1758
1759 (define_expand "cr6_test_for_zero_reverse"
1760 [(set (match_operand:SI 0 "register_operand" "=r")
1761 (eq:SI (reg:CC 74)
1762 (const_int 0)))
1763 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1764 "TARGET_ALTIVEC"
1765 "")
1766
1767 (define_expand "cr6_test_for_lt"
1768 [(set (match_operand:SI 0 "register_operand" "=r")
1769 (lt:SI (reg:CC 74)
1770 (const_int 0)))]
1771 "TARGET_ALTIVEC"
1772 "")
1773
1774 (define_expand "cr6_test_for_lt_reverse"
1775 [(set (match_operand:SI 0 "register_operand" "=r")
1776 (lt:SI (reg:CC 74)
1777 (const_int 0)))
1778 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1779 "TARGET_ALTIVEC"
1780 "")
1781
1782 ;; We can get away with generating the opcode on the fly (%3 below)
1783 ;; because all the predicates have the same scheduling parameters.
1784
1785 (define_insn "altivec_predicate_<mode>"
1786 [(set (reg:CC 74)
1787 (unspec:CC [(match_operand:V 1 "register_operand" "v")
1788 (match_operand:V 2 "register_operand" "v")
1789 (match_operand 3 "any_operand" "")] UNSPEC_PREDICATE))
1790 (clobber (match_scratch:V 0 "=v"))]
1791 "TARGET_ALTIVEC"
1792 "%3 %0,%1,%2"
1793 [(set_attr "type" "veccmp")])
1794
1795 (define_insn "altivec_mtvscr"
1796 [(set (reg:SI 110)
1797 (unspec_volatile:SI
1798 [(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
1799 "TARGET_ALTIVEC"
1800 "mtvscr %0"
1801 [(set_attr "type" "vecsimple")])
1802
1803 (define_insn "altivec_mfvscr"
1804 [(set (match_operand:V8HI 0 "register_operand" "=v")
1805 (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
1806 "TARGET_ALTIVEC"
1807 "mfvscr %0"
1808 [(set_attr "type" "vecsimple")])
1809
1810 (define_insn "altivec_dssall"
1811 [(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)]
1812 "TARGET_ALTIVEC"
1813 "dssall"
1814 [(set_attr "type" "vecsimple")])
1815
1816 (define_insn "altivec_dss"
1817 [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")]
1818 UNSPECV_DSS)]
1819 "TARGET_ALTIVEC"
1820 "dss %0"
1821 [(set_attr "type" "vecsimple")])
1822
1823 (define_insn "altivec_dst"
1824 [(unspec [(match_operand 0 "register_operand" "b")
1825 (match_operand:SI 1 "register_operand" "r")
1826 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)]
1827 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1828 "dst %0,%1,%2"
1829 [(set_attr "type" "vecsimple")])
1830
1831 (define_insn "altivec_dstt"
1832 [(unspec [(match_operand 0 "register_operand" "b")
1833 (match_operand:SI 1 "register_operand" "r")
1834 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)]
1835 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1836 "dstt %0,%1,%2"
1837 [(set_attr "type" "vecsimple")])
1838
1839 (define_insn "altivec_dstst"
1840 [(unspec [(match_operand 0 "register_operand" "b")
1841 (match_operand:SI 1 "register_operand" "r")
1842 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)]
1843 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1844 "dstst %0,%1,%2"
1845 [(set_attr "type" "vecsimple")])
1846
1847 (define_insn "altivec_dststt"
1848 [(unspec [(match_operand 0 "register_operand" "b")
1849 (match_operand:SI 1 "register_operand" "r")
1850 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)]
1851 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1852 "dststt %0,%1,%2"
1853 [(set_attr "type" "vecsimple")])
1854
1855 (define_insn "altivec_lvsl"
1856 [(set (match_operand:V16QI 0 "register_operand" "=v")
1857 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))]
1858 "TARGET_ALTIVEC"
1859 "lvsl %0,%y1"
1860 [(set_attr "type" "vecload")])
1861
1862 (define_insn "altivec_lvsr"
1863 [(set (match_operand:V16QI 0 "register_operand" "=v")
1864 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))]
1865 "TARGET_ALTIVEC"
1866 "lvsr %0,%y1"
1867 [(set_attr "type" "vecload")])
1868
1869 (define_expand "build_vector_mask_for_load"
1870 [(set (match_operand:V16QI 0 "register_operand" "")
1871 (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
1872 "TARGET_ALTIVEC"
1873 "
1874 {
1875 rtx addr;
1876 rtx temp;
1877
1878 gcc_assert (GET_CODE (operands[1]) == MEM);
1879
1880 addr = XEXP (operands[1], 0);
1881 temp = gen_reg_rtx (GET_MODE (addr));
1882 emit_insn (gen_rtx_SET (VOIDmode, temp,
1883 gen_rtx_NEG (GET_MODE (addr), addr)));
1884 emit_insn (gen_altivec_lvsr (operands[0],
1885 replace_equiv_address (operands[1], temp)));
1886 DONE;
1887 }")
1888
1889 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1890 ;; identical rtl but different instructions-- and gcc gets confused.
1891
1892 (define_insn "altivec_lve<VI_char>x"
1893 [(parallel
1894 [(set (match_operand:VI 0 "register_operand" "=v")
1895 (match_operand:VI 1 "memory_operand" "Z"))
1896 (unspec [(const_int 0)] UNSPEC_LVE)])]
1897 "TARGET_ALTIVEC"
1898 "lve<VI_char>x %0,%y1"
1899 [(set_attr "type" "vecload")])
1900
1901 (define_insn "*altivec_lvesfx"
1902 [(parallel
1903 [(set (match_operand:V4SF 0 "register_operand" "=v")
1904 (match_operand:V4SF 1 "memory_operand" "Z"))
1905 (unspec [(const_int 0)] UNSPEC_LVE)])]
1906 "TARGET_ALTIVEC"
1907 "lvewx %0,%y1"
1908 [(set_attr "type" "vecload")])
1909
1910 (define_insn "altivec_lvxl"
1911 [(parallel
1912 [(set (match_operand:V4SI 0 "register_operand" "=v")
1913 (match_operand:V4SI 1 "memory_operand" "Z"))
1914 (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
1915 "TARGET_ALTIVEC"
1916 "lvxl %0,%y1"
1917 [(set_attr "type" "vecload")])
1918
1919 (define_insn "altivec_lvx"
1920 [(set (match_operand:V4SI 0 "register_operand" "=v")
1921 (match_operand:V4SI 1 "memory_operand" "Z"))]
1922 "TARGET_ALTIVEC"
1923 "lvx %0,%y1"
1924 [(set_attr "type" "vecload")])
1925
1926 (define_insn "altivec_stvx"
1927 [(parallel
1928 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1929 (match_operand:V4SI 1 "register_operand" "v"))
1930 (unspec [(const_int 0)] UNSPEC_STVX)])]
1931 "TARGET_ALTIVEC"
1932 "stvx %1,%y0"
1933 [(set_attr "type" "vecstore")])
1934
1935 (define_insn "altivec_stvxl"
1936 [(parallel
1937 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1938 (match_operand:V4SI 1 "register_operand" "v"))
1939 (unspec [(const_int 0)] UNSPEC_STVXL)])]
1940 "TARGET_ALTIVEC"
1941 "stvxl %1,%y0"
1942 [(set_attr "type" "vecstore")])
1943
1944 (define_insn "altivec_stve<VI_char>x"
1945 [(parallel
1946 [(set (match_operand:VI 0 "memory_operand" "=Z")
1947 (match_operand:VI 1 "register_operand" "v"))
1948 (unspec [(const_int 0)] UNSPEC_STVE)])]
1949 "TARGET_ALTIVEC"
1950 "stve<VI_char>x %1,%y0"
1951 [(set_attr "type" "vecstore")])
1952
1953 (define_insn "*altivec_stvesfx"
1954 [(parallel
1955 [(set (match_operand:V4SF 0 "memory_operand" "=Z")
1956 (match_operand:V4SF 1 "register_operand" "v"))
1957 (unspec [(const_int 0)] UNSPEC_STVE)])]
1958 "TARGET_ALTIVEC"
1959 "stvewx %1,%y0"
1960 [(set_attr "type" "vecstore")])
1961
1962 (define_expand "vec_init<mode>"
1963 [(match_operand:V 0 "register_operand" "")
1964 (match_operand 1 "" "")]
1965 "TARGET_ALTIVEC"
1966 {
1967 rs6000_expand_vector_init (operands[0], operands[1]);
1968 DONE;
1969 })
1970
1971 (define_expand "vec_setv4si"
1972 [(match_operand:V4SI 0 "register_operand" "")
1973 (match_operand:SI 1 "register_operand" "")
1974 (match_operand 2 "const_int_operand" "")]
1975 "TARGET_ALTIVEC"
1976 {
1977 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1978 DONE;
1979 })
1980
1981 (define_expand "vec_setv8hi"
1982 [(match_operand:V8HI 0 "register_operand" "")
1983 (match_operand:HI 1 "register_operand" "")
1984 (match_operand 2 "const_int_operand" "")]
1985 "TARGET_ALTIVEC"
1986 {
1987 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1988 DONE;
1989 })
1990
1991 (define_expand "vec_setv16qi"
1992 [(match_operand:V16QI 0 "register_operand" "")
1993 (match_operand:QI 1 "register_operand" "")
1994 (match_operand 2 "const_int_operand" "")]
1995 "TARGET_ALTIVEC"
1996 {
1997 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1998 DONE;
1999 })
2000
2001 (define_expand "vec_setv4sf"
2002 [(match_operand:V4SF 0 "register_operand" "")
2003 (match_operand:SF 1 "register_operand" "")
2004 (match_operand 2 "const_int_operand" "")]
2005 "TARGET_ALTIVEC"
2006 {
2007 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
2008 DONE;
2009 })
2010
2011 (define_expand "vec_extractv4si"
2012 [(match_operand:SI 0 "register_operand" "")
2013 (match_operand:V4SI 1 "register_operand" "")
2014 (match_operand 2 "const_int_operand" "")]
2015 "TARGET_ALTIVEC"
2016 {
2017 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2018 DONE;
2019 })
2020
2021 (define_expand "vec_extractv8hi"
2022 [(match_operand:HI 0 "register_operand" "")
2023 (match_operand:V8HI 1 "register_operand" "")
2024 (match_operand 2 "const_int_operand" "")]
2025 "TARGET_ALTIVEC"
2026 {
2027 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2028 DONE;
2029 })
2030
2031 (define_expand "vec_extractv16qi"
2032 [(match_operand:QI 0 "register_operand" "")
2033 (match_operand:V16QI 1 "register_operand" "")
2034 (match_operand 2 "const_int_operand" "")]
2035 "TARGET_ALTIVEC"
2036 {
2037 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2038 DONE;
2039 })
2040
2041 (define_expand "vec_extractv4sf"
2042 [(match_operand:SF 0 "register_operand" "")
2043 (match_operand:V4SF 1 "register_operand" "")
2044 (match_operand 2 "const_int_operand" "")]
2045 "TARGET_ALTIVEC"
2046 {
2047 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2048 DONE;
2049 })
2050
2051 ;; Generate
2052 ;; vspltis? SCRATCH0,0
2053 ;; vsubu?m SCRATCH2,SCRATCH1,%1
2054 ;; vmaxs? %0,%1,SCRATCH2"
2055 (define_expand "abs<mode>2"
2056 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
2057 (set (match_dup 3)
2058 (minus:VI (match_dup 2)
2059 (match_operand:VI 1 "register_operand" "v")))
2060 (set (match_operand:VI 0 "register_operand" "=v")
2061 (smax:VI (match_dup 1) (match_dup 3)))]
2062 "TARGET_ALTIVEC"
2063 {
2064 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
2065 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
2066 })
2067
2068 ;; Generate
2069 ;; vspltisw SCRATCH1,-1
2070 ;; vslw SCRATCH2,SCRATCH1,SCRATCH1
2071 ;; vandc %0,%1,SCRATCH2
2072 (define_expand "absv4sf2"
2073 [(set (match_dup 2)
2074 (vec_duplicate:V4SI (const_int -1)))
2075 (set (match_dup 3)
2076 (ashift:V4SI (match_dup 2) (match_dup 2)))
2077 (set (match_operand:V4SF 0 "register_operand" "=v")
2078 (and:V4SF (not:V4SF (subreg:V4SF (match_dup 3) 0))
2079 (match_operand:V4SF 1 "register_operand" "v")))]
2080 "TARGET_ALTIVEC"
2081 {
2082 operands[2] = gen_reg_rtx (V4SImode);
2083 operands[3] = gen_reg_rtx (V4SImode);
2084 })
2085
2086 ;; Generate
2087 ;; vspltis? SCRATCH0,0
2088 ;; vsubs?s SCRATCH2,SCRATCH1,%1
2089 ;; vmaxs? %0,%1,SCRATCH2"
2090 (define_expand "altivec_abss_<mode>"
2091 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
2092 (parallel [(set (match_dup 3)
2093 (unspec:VI [(match_dup 2)
2094 (match_operand:VI 1 "register_operand" "v")]
2095 UNSPEC_VSUBS))
2096 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
2097 (set (match_operand:VI 0 "register_operand" "=v")
2098 (smax:VI (match_dup 1) (match_dup 3)))]
2099 "TARGET_ALTIVEC"
2100 {
2101 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
2102 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
2103 })
2104
2105 ;; Vector shift left in bits. Currently supported ony for shift
2106 ;; amounts that can be expressed as byte shifts (divisible by 8).
2107 ;; General shift amounts can be supported using vslo + vsl. We're
2108 ;; not expecting to see these yet (the vectorizer currently
2109 ;; generates only shifts divisible by byte_size).
2110 (define_expand "vec_shl_<mode>"
2111 [(set (match_operand:V 0 "register_operand" "=v")
2112 (unspec:V [(match_operand:V 1 "register_operand" "v")
2113 (match_operand:QI 2 "reg_or_short_operand" "")]
2114 UNSPEC_VECSH))]
2115 "TARGET_ALTIVEC"
2116 "
2117 {
2118 rtx bitshift = operands[2];
2119 rtx byteshift = gen_reg_rtx (QImode);
2120 HOST_WIDE_INT bitshift_val;
2121 HOST_WIDE_INT byteshift_val;
2122
2123 if (! CONSTANT_P (bitshift))
2124 FAIL;
2125 bitshift_val = INTVAL (bitshift);
2126 if (bitshift_val & 0x7)
2127 FAIL;
2128 byteshift_val = bitshift_val >> 3;
2129 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2130 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2131 byteshift));
2132 DONE;
2133 }")
2134
2135 ;; Vector shift left in bits. Currently supported ony for shift
2136 ;; amounts that can be expressed as byte shifts (divisible by 8).
2137 ;; General shift amounts can be supported using vsro + vsr. We're
2138 ;; not expecting to see these yet (the vectorizer currently
2139 ;; generates only shifts divisible by byte_size).
2140 (define_expand "vec_shr_<mode>"
2141 [(set (match_operand:V 0 "register_operand" "=v")
2142 (unspec:V [(match_operand:V 1 "register_operand" "v")
2143 (match_operand:QI 2 "reg_or_short_operand" "")]
2144 UNSPEC_VECSH))]
2145 "TARGET_ALTIVEC"
2146 "
2147 {
2148 rtx bitshift = operands[2];
2149 rtx byteshift = gen_reg_rtx (QImode);
2150 HOST_WIDE_INT bitshift_val;
2151 HOST_WIDE_INT byteshift_val;
2152
2153 if (! CONSTANT_P (bitshift))
2154 FAIL;
2155 bitshift_val = INTVAL (bitshift);
2156 if (bitshift_val & 0x7)
2157 FAIL;
2158 byteshift_val = 16 - (bitshift_val >> 3);
2159 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2160 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2161 byteshift));
2162 DONE;
2163 }")
2164
2165 (define_insn "altivec_vsumsws_nomode"
2166 [(set (match_operand 0 "register_operand" "=v")
2167 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
2168 (match_operand:V4SI 2 "register_operand" "v")]
2169 UNSPEC_VSUMSWS))
2170 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
2171 "TARGET_ALTIVEC"
2172 "vsumsws %0,%1,%2"
2173 [(set_attr "type" "veccomplex")])
2174
2175 (define_expand "reduc_splus_<mode>"
2176 [(set (match_operand:VIshort 0 "register_operand" "=v")
2177 (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
2178 UNSPEC_REDUC_PLUS))]
2179 "TARGET_ALTIVEC"
2180 "
2181 {
2182 rtx vzero = gen_reg_rtx (V4SImode);
2183 rtx vtmp1 = gen_reg_rtx (V4SImode);
2184
2185 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2186 emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
2187 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2188 DONE;
2189 }")
2190
2191 (define_expand "reduc_uplus_v16qi"
2192 [(set (match_operand:V16QI 0 "register_operand" "=v")
2193 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
2194 UNSPEC_REDUC_PLUS))]
2195 "TARGET_ALTIVEC"
2196 "
2197 {
2198 rtx vzero = gen_reg_rtx (V4SImode);
2199 rtx vtmp1 = gen_reg_rtx (V4SImode);
2200
2201 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2202 emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
2203 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2204 DONE;
2205 }")
2206
2207 (define_insn "vec_realign_load_<mode>"
2208 [(set (match_operand:V 0 "register_operand" "=v")
2209 (unspec:V [(match_operand:V 1 "register_operand" "v")
2210 (match_operand:V 2 "register_operand" "v")
2211 (match_operand:V16QI 3 "register_operand" "v")]
2212 UNSPEC_REALIGN_LOAD))]
2213 "TARGET_ALTIVEC"
2214 "vperm %0,%1,%2,%3"
2215 [(set_attr "type" "vecperm")])
2216
2217 (define_expand "neg<mode>2"
2218 [(use (match_operand:VI 0 "register_operand" ""))
2219 (use (match_operand:VI 1 "register_operand" ""))]
2220 "TARGET_ALTIVEC"
2221 "
2222 {
2223 rtx vzero;
2224
2225 vzero = gen_reg_rtx (GET_MODE (operands[0]));
2226 emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx));
2227 emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
2228
2229 DONE;
2230 }")
2231
2232 (define_expand "udot_prod<mode>"
2233 [(set (match_operand:V4SI 0 "register_operand" "=v")
2234 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
2235 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
2236 (match_operand:VIshort 2 "register_operand" "v")]
2237 UNSPEC_VMSUMU)))]
2238 "TARGET_ALTIVEC"
2239 "
2240 {
2241 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3]));
2242 DONE;
2243 }")
2244
2245 (define_expand "sdot_prodv8hi"
2246 [(set (match_operand:V4SI 0 "register_operand" "=v")
2247 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
2248 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2249 (match_operand:V8HI 2 "register_operand" "v")]
2250 UNSPEC_VMSUMSHM)))]
2251 "TARGET_ALTIVEC"
2252 "
2253 {
2254 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
2255 DONE;
2256 }")
2257
2258 (define_expand "widen_usum<mode>3"
2259 [(set (match_operand:V4SI 0 "register_operand" "=v")
2260 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2261 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
2262 UNSPEC_VMSUMU)))]
2263 "TARGET_ALTIVEC"
2264 "
2265 {
2266 rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
2267
2268 emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx));
2269 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2]));
2270 DONE;
2271 }")
2272
2273 (define_expand "widen_ssumv16qi3"
2274 [(set (match_operand:V4SI 0 "register_operand" "=v")
2275 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2276 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
2277 UNSPEC_VMSUMM)))]
2278 "TARGET_ALTIVEC"
2279 "
2280 {
2281 rtx vones = gen_reg_rtx (V16QImode);
2282
2283 emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
2284 emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
2285 DONE;
2286 }")
2287
2288 (define_expand "widen_ssumv8hi3"
2289 [(set (match_operand:V4SI 0 "register_operand" "=v")
2290 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2291 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2292 UNSPEC_VMSUMSHM)))]
2293 "TARGET_ALTIVEC"
2294 "
2295 {
2296 rtx vones = gen_reg_rtx (V8HImode);
2297
2298 emit_insn (gen_altivec_vspltish (vones, const1_rtx));
2299 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
2300 DONE;
2301 }")
2302
2303 (define_expand "vec_unpacks_hi_v16qi"
2304 [(set (match_operand:V8HI 0 "register_operand" "=v")
2305 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2306 UNSPEC_VUPKHSB))]
2307 "TARGET_ALTIVEC"
2308 "
2309 {
2310 emit_insn (gen_altivec_vupkhsb (operands[0], operands[1]));
2311 DONE;
2312 }")
2313
2314 (define_expand "vec_unpacks_hi_v8hi"
2315 [(set (match_operand:V4SI 0 "register_operand" "=v")
2316 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2317 UNSPEC_VUPKHSH))]
2318 "TARGET_ALTIVEC"
2319 "
2320 {
2321 emit_insn (gen_altivec_vupkhsh (operands[0], operands[1]));
2322 DONE;
2323 }")
2324
2325 (define_expand "vec_unpacks_lo_v16qi"
2326 [(set (match_operand:V8HI 0 "register_operand" "=v")
2327 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2328 UNSPEC_VUPKLSB))]
2329 "TARGET_ALTIVEC"
2330 "
2331 {
2332 emit_insn (gen_altivec_vupklsb (operands[0], operands[1]));
2333 DONE;
2334 }")
2335
2336 (define_expand "vec_unpacks_lo_v8hi"
2337 [(set (match_operand:V4SI 0 "register_operand" "=v")
2338 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2339 UNSPEC_VUPKLSH))]
2340 "TARGET_ALTIVEC"
2341 "
2342 {
2343 emit_insn (gen_altivec_vupklsh (operands[0], operands[1]));
2344 DONE;
2345 }")
2346
2347 (define_insn "vperm_v8hiv4si"
2348 [(set (match_operand:V4SI 0 "register_operand" "=v")
2349 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2350 (match_operand:V4SI 2 "register_operand" "v")
2351 (match_operand:V16QI 3 "register_operand" "v")]
2352 UNSPEC_VPERMSI))]
2353 "TARGET_ALTIVEC"
2354 "vperm %0,%1,%2,%3"
2355 [(set_attr "type" "vecperm")])
2356
2357 (define_insn "vperm_v16qiv8hi"
2358 [(set (match_operand:V8HI 0 "register_operand" "=v")
2359 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2360 (match_operand:V8HI 2 "register_operand" "v")
2361 (match_operand:V16QI 3 "register_operand" "v")]
2362 UNSPEC_VPERMHI))]
2363 "TARGET_ALTIVEC"
2364 "vperm %0,%1,%2,%3"
2365 [(set_attr "type" "vecperm")])
2366
2367
2368 (define_expand "vec_unpacku_hi_v16qi"
2369 [(set (match_operand:V8HI 0 "register_operand" "=v")
2370 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2371 UNSPEC_VUPKHUB))]
2372 "TARGET_ALTIVEC"
2373 "
2374 {
2375 rtx vzero = gen_reg_rtx (V8HImode);
2376 rtx mask = gen_reg_rtx (V16QImode);
2377 rtvec v = rtvec_alloc (16);
2378
2379 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2380
2381 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2382 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0);
2383 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2384 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2385 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2386 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2);
2387 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2388 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2389 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2390 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4);
2391 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2392 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2393 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2394 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6);
2395 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2396 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2397
2398 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2399 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2400 DONE;
2401 }")
2402
2403 (define_expand "vec_unpacku_hi_v8hi"
2404 [(set (match_operand:V4SI 0 "register_operand" "=v")
2405 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2406 UNSPEC_VUPKHUH))]
2407 "TARGET_ALTIVEC"
2408 "
2409 {
2410 rtx vzero = gen_reg_rtx (V4SImode);
2411 rtx mask = gen_reg_rtx (V16QImode);
2412 rtvec v = rtvec_alloc (16);
2413
2414 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2415
2416 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2417 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2418 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0);
2419 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2420 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2421 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2422 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2);
2423 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2424 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2425 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2426 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4);
2427 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2428 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2429 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2430 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6);
2431 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2432
2433 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2434 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2435 DONE;
2436 }")
2437
2438 (define_expand "vec_unpacku_lo_v16qi"
2439 [(set (match_operand:V8HI 0 "register_operand" "=v")
2440 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2441 UNSPEC_VUPKLUB))]
2442 "TARGET_ALTIVEC"
2443 "
2444 {
2445 rtx vzero = gen_reg_rtx (V8HImode);
2446 rtx mask = gen_reg_rtx (V16QImode);
2447 rtvec v = rtvec_alloc (16);
2448
2449 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2450
2451 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2452 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8);
2453 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2454 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2455 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2456 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2457 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2458 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2459 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2460 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12);
2461 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2462 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2463 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2464 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14);
2465 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2466 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2467
2468 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2469 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2470 DONE;
2471 }")
2472
2473 (define_expand "vec_unpacku_lo_v8hi"
2474 [(set (match_operand:V4SI 0 "register_operand" "=v")
2475 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2476 UNSPEC_VUPKLUH))]
2477 "TARGET_ALTIVEC"
2478 "
2479 {
2480 rtx vzero = gen_reg_rtx (V4SImode);
2481 rtx mask = gen_reg_rtx (V16QImode);
2482 rtvec v = rtvec_alloc (16);
2483
2484 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2485
2486 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2487 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2488 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8);
2489 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2490 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2491 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2492 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2493 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2494 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2495 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2496 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12);
2497 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2498 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2499 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2500 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14);
2501 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2502
2503 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2504 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2505 DONE;
2506 }")
2507
2508 (define_expand "vec_widen_umult_hi_v16qi"
2509 [(set (match_operand:V8HI 0 "register_operand" "=v")
2510 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2511 (match_operand:V16QI 2 "register_operand" "v")]
2512 UNSPEC_VMULWHUB))]
2513 "TARGET_ALTIVEC"
2514 "
2515 {
2516 rtx ve = gen_reg_rtx (V8HImode);
2517 rtx vo = gen_reg_rtx (V8HImode);
2518
2519 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2520 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2521 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2522 DONE;
2523 }")
2524
2525 (define_expand "vec_widen_umult_lo_v16qi"
2526 [(set (match_operand:V8HI 0 "register_operand" "=v")
2527 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2528 (match_operand:V16QI 2 "register_operand" "v")]
2529 UNSPEC_VMULWLUB))]
2530 "TARGET_ALTIVEC"
2531 "
2532 {
2533 rtx ve = gen_reg_rtx (V8HImode);
2534 rtx vo = gen_reg_rtx (V8HImode);
2535
2536 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2537 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2538 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2539 DONE;
2540 }")
2541
2542 (define_expand "vec_widen_smult_hi_v16qi"
2543 [(set (match_operand:V8HI 0 "register_operand" "=v")
2544 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2545 (match_operand:V16QI 2 "register_operand" "v")]
2546 UNSPEC_VMULWHSB))]
2547 "TARGET_ALTIVEC"
2548 "
2549 {
2550 rtx ve = gen_reg_rtx (V8HImode);
2551 rtx vo = gen_reg_rtx (V8HImode);
2552
2553 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2554 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2555 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2556 DONE;
2557 }")
2558
2559 (define_expand "vec_widen_smult_lo_v16qi"
2560 [(set (match_operand:V8HI 0 "register_operand" "=v")
2561 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2562 (match_operand:V16QI 2 "register_operand" "v")]
2563 UNSPEC_VMULWLSB))]
2564 "TARGET_ALTIVEC"
2565 "
2566 {
2567 rtx ve = gen_reg_rtx (V8HImode);
2568 rtx vo = gen_reg_rtx (V8HImode);
2569
2570 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2571 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2572 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2573 DONE;
2574 }")
2575
2576 (define_expand "vec_widen_umult_hi_v8hi"
2577 [(set (match_operand:V4SI 0 "register_operand" "=v")
2578 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2579 (match_operand:V8HI 2 "register_operand" "v")]
2580 UNSPEC_VMULWHUH))]
2581 "TARGET_ALTIVEC"
2582 "
2583 {
2584 rtx ve = gen_reg_rtx (V4SImode);
2585 rtx vo = gen_reg_rtx (V4SImode);
2586
2587 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2588 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2589 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2590 DONE;
2591 }")
2592
2593 (define_expand "vec_widen_umult_lo_v8hi"
2594 [(set (match_operand:V4SI 0 "register_operand" "=v")
2595 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2596 (match_operand:V8HI 2 "register_operand" "v")]
2597 UNSPEC_VMULWLUH))]
2598 "TARGET_ALTIVEC"
2599 "
2600 {
2601 rtx ve = gen_reg_rtx (V4SImode);
2602 rtx vo = gen_reg_rtx (V4SImode);
2603
2604 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2605 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2606 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2607 DONE;
2608 }")
2609
2610 (define_expand "vec_widen_smult_hi_v8hi"
2611 [(set (match_operand:V4SI 0 "register_operand" "=v")
2612 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2613 (match_operand:V8HI 2 "register_operand" "v")]
2614 UNSPEC_VMULWHSH))]
2615 "TARGET_ALTIVEC"
2616 "
2617 {
2618 rtx ve = gen_reg_rtx (V4SImode);
2619 rtx vo = gen_reg_rtx (V4SImode);
2620
2621 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2622 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2623 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2624 DONE;
2625 }")
2626
2627 (define_expand "vec_widen_smult_lo_v8hi"
2628 [(set (match_operand:V4SI 0 "register_operand" "=v")
2629 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2630 (match_operand:V8HI 2 "register_operand" "v")]
2631 UNSPEC_VMULWLSH))]
2632 "TARGET_ALTIVEC"
2633 "
2634 {
2635 rtx ve = gen_reg_rtx (V4SImode);
2636 rtx vo = gen_reg_rtx (V4SImode);
2637
2638 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2639 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2640 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2641 DONE;
2642 }")
2643
2644 (define_expand "vec_pack_trunc_v8hi"
2645 [(set (match_operand:V16QI 0 "register_operand" "=v")
2646 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
2647 (match_operand:V8HI 2 "register_operand" "v")]
2648 UNSPEC_VPKUHUM))]
2649 "TARGET_ALTIVEC"
2650 "
2651 {
2652 emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2]));
2653 DONE;
2654 }")
2655
2656 (define_expand "vec_pack_trunc_v4si"
2657 [(set (match_operand:V8HI 0 "register_operand" "=v")
2658 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
2659 (match_operand:V4SI 2 "register_operand" "v")]
2660 UNSPEC_VPKUWUM))]
2661 "TARGET_ALTIVEC"
2662 "
2663 {
2664 emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2]));
2665 DONE;
2666 }")
2667
2668 (define_expand "negv4sf2"
2669 [(use (match_operand:V4SF 0 "register_operand" ""))
2670 (use (match_operand:V4SF 1 "register_operand" ""))]
2671 "TARGET_ALTIVEC"
2672 "
2673 {
2674 rtx neg0;
2675
2676 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
2677 neg0 = gen_reg_rtx (V4SImode);
2678 emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
2679 emit_insn (gen_vashlv4si3 (neg0, neg0, neg0));
2680
2681 /* XOR */
2682 emit_insn (gen_xorv4sf3 (operands[0],
2683 gen_lowpart (V4SFmode, neg0), operands[1]));
2684
2685 DONE;
2686 }")
2687
2688 ;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL,
2689 ;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell.
2690 (define_insn "altivec_lvlx"
2691 [(set (match_operand:V16QI 0 "register_operand" "=v")
2692 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2693 UNSPEC_LVLX))]
2694 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2695 "lvlx %0,%y1"
2696 [(set_attr "type" "vecload")])
2697
2698 (define_insn "altivec_lvlxl"
2699 [(set (match_operand:V16QI 0 "register_operand" "=v")
2700 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2701 UNSPEC_LVLXL))]
2702 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2703 "lvlxl %0,%y1"
2704 [(set_attr "type" "vecload")])
2705
2706 (define_insn "altivec_lvrx"
2707 [(set (match_operand:V16QI 0 "register_operand" "=v")
2708 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2709 UNSPEC_LVRX))]
2710 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2711 "lvrx %0,%y1"
2712 [(set_attr "type" "vecload")])
2713
2714 (define_insn "altivec_lvrxl"
2715 [(set (match_operand:V16QI 0 "register_operand" "=v")
2716 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2717 UNSPEC_LVRXL))]
2718 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2719 "lvrxl %0,%y1"
2720 [(set_attr "type" "vecload")])
2721
2722 (define_insn "altivec_stvlx"
2723 [(parallel
2724 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2725 (match_operand:V4SI 1 "register_operand" "v"))
2726 (unspec [(const_int 0)] UNSPEC_STVLX)])]
2727 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2728 "stvlx %1,%y0"
2729 [(set_attr "type" "vecstore")])
2730
2731 (define_insn "altivec_stvlxl"
2732 [(parallel
2733 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2734 (match_operand:V4SI 1 "register_operand" "v"))
2735 (unspec [(const_int 0)] UNSPEC_STVLXL)])]
2736 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2737 "stvlxl %1,%y0"
2738 [(set_attr "type" "vecstore")])
2739
2740 (define_insn "altivec_stvrx"
2741 [(parallel
2742 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2743 (match_operand:V4SI 1 "register_operand" "v"))
2744 (unspec [(const_int 0)] UNSPEC_STVRX)])]
2745 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2746 "stvrx %1,%y0"
2747 [(set_attr "type" "vecstore")])
2748
2749 (define_insn "altivec_stvrxl"
2750 [(parallel
2751 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2752 (match_operand:V4SI 1 "register_operand" "v"))
2753 (unspec [(const_int 0)] UNSPEC_STVRXL)])]
2754 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2755 "stvrxl %1,%y0"
2756 [(set_attr "type" "vecstore")])
2757
2758 (define_expand "vec_extract_evenv4si"
2759 [(set (match_operand:V4SI 0 "register_operand" "")
2760 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2761 (match_operand:V4SI 2 "register_operand" "")]
2762 UNSPEC_EXTEVEN_V4SI))]
2763 "TARGET_ALTIVEC"
2764 "
2765 {
2766 rtx mask = gen_reg_rtx (V16QImode);
2767 rtvec v = rtvec_alloc (16);
2768
2769 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2770 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2771 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2772 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2773 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2774 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2775 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2776 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2777 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2778 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2779 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2780 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2781 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2782 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2783 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2784 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2785 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2786 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2787
2788 DONE;
2789 }")
2790
2791 (define_expand "vec_extract_evenv4sf"
2792 [(set (match_operand:V4SF 0 "register_operand" "")
2793 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2794 (match_operand:V4SF 2 "register_operand" "")]
2795 UNSPEC_EXTEVEN_V4SF))]
2796 "TARGET_ALTIVEC"
2797 "
2798 {
2799 rtx mask = gen_reg_rtx (V16QImode);
2800 rtvec v = rtvec_alloc (16);
2801
2802 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2803 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2804 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2805 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2806 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2807 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2808 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2809 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2810 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2811 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2812 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2813 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2814 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2815 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2816 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2817 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2818 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2819 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
2820
2821 DONE;
2822 }")
2823
2824 (define_expand "vec_extract_evenv8hi"
2825 [(set (match_operand:V4SI 0 "register_operand" "")
2826 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
2827 (match_operand:V8HI 2 "register_operand" "")]
2828 UNSPEC_EXTEVEN_V8HI))]
2829 "TARGET_ALTIVEC"
2830 "
2831 {
2832 rtx mask = gen_reg_rtx (V16QImode);
2833 rtvec v = rtvec_alloc (16);
2834
2835 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2836 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2837 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2838 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 5);
2839 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2840 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2841 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2842 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 13);
2843 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2844 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2845 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2846 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 21);
2847 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2848 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2849 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2850 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 29);
2851 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2852 emit_insn (gen_altivec_vperm_v8hi (operands[0], operands[1], operands[2], mask));
2853
2854 DONE;
2855 }")
2856
2857 (define_expand "vec_extract_evenv16qi"
2858 [(set (match_operand:V4SI 0 "register_operand" "")
2859 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "")
2860 (match_operand:V16QI 2 "register_operand" "")]
2861 UNSPEC_EXTEVEN_V16QI))]
2862 "TARGET_ALTIVEC"
2863 "
2864 {
2865 rtx mask = gen_reg_rtx (V16QImode);
2866 rtvec v = rtvec_alloc (16);
2867
2868 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2869 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 2);
2870 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2871 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 6);
2872 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2873 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2874 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2875 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 14);
2876 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2877 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 18);
2878 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2879 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 22);
2880 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2881 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 26);
2882 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2883 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 30);
2884 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2885 emit_insn (gen_altivec_vperm_v16qi (operands[0], operands[1], operands[2], mask));
2886
2887 DONE;
2888 }")
2889
2890 (define_expand "vec_extract_oddv4si"
2891 [(set (match_operand:V4SI 0 "register_operand" "")
2892 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2893 (match_operand:V4SI 2 "register_operand" "")]
2894 UNSPEC_EXTODD_V4SI))]
2895 "TARGET_ALTIVEC"
2896 "
2897 {
2898 rtx mask = gen_reg_rtx (V16QImode);
2899 rtvec v = rtvec_alloc (16);
2900
2901 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2902 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2903 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2904 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2905 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2906 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2907 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2908 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2909 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2910 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2911 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2912 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2913 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2914 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2915 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
2916 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
2917 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2918 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2919
2920 DONE;
2921 }")
2922
2923 (define_expand "vec_extract_oddv4sf"
2924 [(set (match_operand:V4SF 0 "register_operand" "")
2925 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2926 (match_operand:V4SF 2 "register_operand" "")]
2927 UNSPEC_EXTODD_V4SF))]
2928 "TARGET_ALTIVEC"
2929 "
2930 {
2931 rtx mask = gen_reg_rtx (V16QImode);
2932 rtvec v = rtvec_alloc (16);
2933
2934 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2935 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2936 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2937 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2938 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2939 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2940 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2941 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2942 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2943 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2944 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2945 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2946 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2947 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2948 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
2949 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
2950 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2951 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
2952
2953 DONE;
2954 }")
2955
2956 (define_insn "vpkuhum_nomode"
2957 [(set (match_operand:V16QI 0 "register_operand" "=v")
2958 (unspec:V16QI [(match_operand 1 "register_operand" "v")
2959 (match_operand 2 "register_operand" "v")]
2960 UNSPEC_VPKUHUM))]
2961 "TARGET_ALTIVEC"
2962 "vpkuhum %0,%1,%2"
2963 [(set_attr "type" "vecperm")])
2964
2965 (define_insn "vpkuwum_nomode"
2966 [(set (match_operand:V8HI 0 "register_operand" "=v")
2967 (unspec:V8HI [(match_operand 1 "register_operand" "v")
2968 (match_operand 2 "register_operand" "v")]
2969 UNSPEC_VPKUWUM))]
2970 "TARGET_ALTIVEC"
2971 "vpkuwum %0,%1,%2"
2972 [(set_attr "type" "vecperm")])
2973
2974 (define_expand "vec_extract_oddv8hi"
2975 [(set (match_operand:V8HI 0 "register_operand" "")
2976 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
2977 (match_operand:V8HI 2 "register_operand" "")]
2978 UNSPEC_EXTODD_V8HI))]
2979 "TARGET_ALTIVEC"
2980 "
2981 {
2982 emit_insn (gen_vpkuwum_nomode (operands[0], operands[1], operands[2]));
2983 DONE;
2984 }")
2985
2986 (define_expand "vec_extract_oddv16qi"
2987 [(set (match_operand:V16QI 0 "register_operand" "")
2988 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
2989 (match_operand:V16QI 2 "register_operand" "")]
2990 UNSPEC_EXTODD_V16QI))]
2991 "TARGET_ALTIVEC"
2992 "
2993 {
2994 emit_insn (gen_vpkuhum_nomode (operands[0], operands[1], operands[2]));
2995 DONE;
2996 }")
2997 (define_expand "vec_interleave_highv4sf"
2998 [(set (match_operand:V4SF 0 "register_operand" "")
2999 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
3000 (match_operand:V4SF 2 "register_operand" "")]
3001 UNSPEC_INTERHI_V4SF))]
3002 "TARGET_ALTIVEC"
3003 "
3004 {
3005 emit_insn (gen_altivec_vmrghsf (operands[0], operands[1], operands[2]));
3006 DONE;
3007 }")
3008
3009 (define_expand "vec_interleave_lowv4sf"
3010 [(set (match_operand:V4SF 0 "register_operand" "")
3011 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
3012 (match_operand:V4SF 2 "register_operand" "")]
3013 UNSPEC_INTERLO_V4SF))]
3014 "TARGET_ALTIVEC"
3015 "
3016 {
3017 emit_insn (gen_altivec_vmrglsf (operands[0], operands[1], operands[2]));
3018 DONE;
3019 }")
3020
3021 (define_expand "vec_interleave_high<mode>"
3022 [(set (match_operand:VI 0 "register_operand" "")
3023 (unspec:VI [(match_operand:VI 1 "register_operand" "")
3024 (match_operand:VI 2 "register_operand" "")]
3025 UNSPEC_INTERHI))]
3026 "TARGET_ALTIVEC"
3027 "
3028 {
3029 emit_insn (gen_altivec_vmrgh<VI_char> (operands[0], operands[1], operands[2]));
3030 DONE;
3031 }")
3032
3033 (define_expand "vec_interleave_low<mode>"
3034 [(set (match_operand:VI 0 "register_operand" "")
3035 (unspec:VI [(match_operand:VI 1 "register_operand" "")
3036 (match_operand:VI 2 "register_operand" "")]
3037 UNSPEC_INTERLO))]
3038 "TARGET_ALTIVEC"
3039 "
3040 {
3041 emit_insn (gen_altivec_vmrgl<VI_char> (operands[0], operands[1], operands[2]));
3042 DONE;
3043 }")
3044
3045 (define_expand "vec_unpacks_float_hi_v8hi"
3046 [(set (match_operand:V4SF 0 "register_operand" "")
3047 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
3048 UNSPEC_VUPKHS_V4SF))]
3049 "TARGET_ALTIVEC"
3050 "
3051 {
3052 rtx tmp = gen_reg_rtx (V4SImode);
3053
3054 emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
3055 emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
3056 DONE;
3057 }")
3058
3059 (define_expand "vec_unpacks_float_lo_v8hi"
3060 [(set (match_operand:V4SF 0 "register_operand" "")
3061 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
3062 UNSPEC_VUPKLS_V4SF))]
3063 "TARGET_ALTIVEC"
3064 "
3065 {
3066 rtx tmp = gen_reg_rtx (V4SImode);
3067
3068 emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
3069 emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
3070 DONE;
3071 }")
3072
3073 (define_expand "vec_unpacku_float_hi_v8hi"
3074 [(set (match_operand:V4SF 0 "register_operand" "")
3075 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
3076 UNSPEC_VUPKHU_V4SF))]
3077 "TARGET_ALTIVEC"
3078 "
3079 {
3080 rtx tmp = gen_reg_rtx (V4SImode);
3081
3082 emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
3083 emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
3084 DONE;
3085 }")
3086
3087 (define_expand "vec_unpacku_float_lo_v8hi"
3088 [(set (match_operand:V4SF 0 "register_operand" "")
3089 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
3090 UNSPEC_VUPKLU_V4SF))]
3091 "TARGET_ALTIVEC"
3092 "
3093 {
3094 rtx tmp = gen_reg_rtx (V4SImode);
3095
3096 emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
3097 emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
3098 DONE;
3099 }")