Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/rs6000/rs64.md @ 0:a06113de4d67
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author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
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date | Fri, 17 Jul 2009 14:47:48 +0900 |
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children | 77e2b8dfacca |
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1 ;; Scheduling description for IBM RS64 processors. | |
2 ;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. | |
3 ;; | |
4 ;; This file is part of GCC. | |
5 | |
6 ;; GCC is free software; you can redistribute it and/or modify it | |
7 ;; under the terms of the GNU General Public License as published | |
8 ;; by the Free Software Foundation; either version 3, or (at your | |
9 ;; option) any later version. | |
10 | |
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 ;; License for more details. | |
15 | |
16 ;; You should have received a copy of the GNU General Public License | |
17 ;; along with GCC; see the file COPYING3. If not see | |
18 ;; <http://www.gnu.org/licenses/>. | |
19 | |
20 (define_automaton "rs64,rs64fp") | |
21 (define_cpu_unit "iu_rs64" "rs64") | |
22 (define_cpu_unit "mciu_rs64" "rs64") | |
23 (define_cpu_unit "fpu_rs64" "rs64fp") | |
24 (define_cpu_unit "lsu_rs64,bpu_rs64" "rs64") | |
25 | |
26 ;; RS64a 64-bit IU, LSU, FPU, BPU | |
27 | |
28 (define_insn_reservation "rs64a-load" 2 | |
29 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") | |
30 (eq_attr "cpu" "rs64a")) | |
31 "lsu_rs64") | |
32 | |
33 (define_insn_reservation "rs64a-store" 2 | |
34 (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") | |
35 (eq_attr "cpu" "rs64a")) | |
36 "lsu_rs64") | |
37 | |
38 (define_insn_reservation "rs64a-fpload" 3 | |
39 (and (eq_attr "type" "fpload,fpload_ux,fpload_u") | |
40 (eq_attr "cpu" "rs64a")) | |
41 "lsu_rs64") | |
42 | |
43 (define_insn_reservation "rs64a-llsc" 2 | |
44 (and (eq_attr "type" "load_l,store_c") | |
45 (eq_attr "cpu" "rs64a")) | |
46 "lsu_rs64") | |
47 | |
48 (define_insn_reservation "rs64a-integer" 1 | |
49 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ | |
50 var_shift_rotate,cntlz,exts") | |
51 (eq_attr "cpu" "rs64a")) | |
52 "iu_rs64") | |
53 | |
54 (define_insn_reservation "rs64a-two" 1 | |
55 (and (eq_attr "type" "two") | |
56 (eq_attr "cpu" "rs64a")) | |
57 "iu_rs64,iu_rs64") | |
58 | |
59 (define_insn_reservation "rs64a-three" 1 | |
60 (and (eq_attr "type" "three") | |
61 (eq_attr "cpu" "rs64a")) | |
62 "iu_rs64,iu_rs64,iu_rs64") | |
63 | |
64 (define_insn_reservation "rs64a-imul" 20 | |
65 (and (eq_attr "type" "imul,imul_compare") | |
66 (eq_attr "cpu" "rs64a")) | |
67 "mciu_rs64*13") | |
68 | |
69 (define_insn_reservation "rs64a-imul2" 12 | |
70 (and (eq_attr "type" "imul2") | |
71 (eq_attr "cpu" "rs64a")) | |
72 "mciu_rs64*5") | |
73 | |
74 (define_insn_reservation "rs64a-imul3" 8 | |
75 (and (eq_attr "type" "imul3") | |
76 (eq_attr "cpu" "rs64a")) | |
77 "mciu_rs64*2") | |
78 | |
79 (define_insn_reservation "rs64a-lmul" 34 | |
80 (and (eq_attr "type" "lmul,lmul_compare") | |
81 (eq_attr "cpu" "rs64a")) | |
82 "mciu_rs64*34") | |
83 | |
84 (define_insn_reservation "rs64a-idiv" 66 | |
85 (and (eq_attr "type" "idiv") | |
86 (eq_attr "cpu" "rs64a")) | |
87 "mciu_rs64*66") | |
88 | |
89 (define_insn_reservation "rs64a-ldiv" 66 | |
90 (and (eq_attr "type" "ldiv") | |
91 (eq_attr "cpu" "rs64a")) | |
92 "mciu_rs64*66") | |
93 | |
94 (define_insn_reservation "rs64a-compare" 3 | |
95 (and (eq_attr "type" "cmp,fast_compare,compare,\ | |
96 delayed_compare,var_delayed_compare") | |
97 (eq_attr "cpu" "rs64a")) | |
98 "iu_rs64,nothing,bpu_rs64") | |
99 | |
100 (define_insn_reservation "rs64a-fpcompare" 5 | |
101 (and (eq_attr "type" "fpcompare") | |
102 (eq_attr "cpu" "rs64a")) | |
103 "mciu_rs64,fpu_rs64,bpu_rs64") | |
104 | |
105 (define_insn_reservation "rs64a-fp" 4 | |
106 (and (eq_attr "type" "fp,dmul") | |
107 (eq_attr "cpu" "rs64a")) | |
108 "mciu_rs64,fpu_rs64") | |
109 | |
110 (define_insn_reservation "rs64a-sdiv" 31 | |
111 (and (eq_attr "type" "sdiv,ddiv") | |
112 (eq_attr "cpu" "rs64a")) | |
113 "mciu_rs64,fpu_rs64*31") | |
114 | |
115 (define_insn_reservation "rs64a-sqrt" 49 | |
116 (and (eq_attr "type" "ssqrt,dsqrt") | |
117 (eq_attr "cpu" "rs64a")) | |
118 "mciu_rs64,fpu_rs64*49") | |
119 | |
120 (define_insn_reservation "rs64a-mfcr" 2 | |
121 (and (eq_attr "type" "mfcr") | |
122 (eq_attr "cpu" "rs64a")) | |
123 "lsu_rs64") | |
124 | |
125 (define_insn_reservation "rs64a-mtcr" 3 | |
126 (and (eq_attr "type" "mtcr") | |
127 (eq_attr "cpu" "rs64a")) | |
128 "lsu_rs64") | |
129 | |
130 (define_insn_reservation "rs64a-mtjmpr" 3 | |
131 (and (eq_attr "type" "mtjmpr") | |
132 (eq_attr "cpu" "rs64a")) | |
133 "lsu_rs64") | |
134 | |
135 (define_insn_reservation "rs64a-mfjmpr" 2 | |
136 (and (eq_attr "type" "mfjmpr") | |
137 (eq_attr "cpu" "rs64a")) | |
138 "lsu_rs64") | |
139 | |
140 (define_insn_reservation "rs64a-jmpreg" 1 | |
141 (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr") | |
142 (eq_attr "cpu" "rs64a")) | |
143 "bpu_rs64") | |
144 | |
145 (define_insn_reservation "rs64a-isync" 6 | |
146 (and (eq_attr "type" "isync") | |
147 (eq_attr "cpu" "rs64a")) | |
148 "bpu_rs64") | |
149 | |
150 (define_insn_reservation "rs64a-sync" 1 | |
151 (and (eq_attr "type" "sync") | |
152 (eq_attr "cpu" "rs64a")) | |
153 "lsu_rs64") | |
154 |