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comparison gcc/config/s390/2097.md @ 0:a06113de4d67

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author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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-1:000000000000 0:a06113de4d67
1 ;; Scheduling description for z10 (cpu 2097).
2 ;; Copyright (C) 2008 Free Software Foundation, Inc.
3 ;; Contributed by Wolfgang Gellerich (gellerich@de.ibm.com).
4
5
6 ; General naming conventions used in this file:
7 ; - The two pipelines are called S and T, respectively.
8 ; - A name ending "_S" or "_T" indicates that something happens in
9 ; (or belongs to) this pipeline.
10 ; - A name ending "_ANY" indicates that something happens in (or belongs
11 ; to) either of the two pipelines.
12 ; - A name ending "_BOTH" indicates that something happens in (or belongs
13 ; to) both pipelines.
14
15
16 ;; Automaton and components.
17
18 (define_automaton "z10_cpu")
19
20 (define_cpu_unit "z10_e1_S, z10_e1_T" "z10_cpu")
21 (define_reservation "z10_e1_ANY" "(z10_e1_S | z10_e1_T)")
22 (define_reservation "z10_e1_BOTH" "(z10_e1_S + z10_e1_T)")
23
24
25 ; Both pipelines can execute a branch instruction, and branch
26 ; instructions can be grouped with all other groupable instructions
27 ; but not with a second branch instruction.
28
29 (define_cpu_unit "z10_branch_ANY" "z10_cpu")
30
31 (define_insn_reservation "z10_branch" 4
32 (and (eq_attr "cpu" "z10")
33 (eq_attr "type" "branch"))
34 "z10_branch_ANY + z10_e1_ANY, z10_Gate_ANY")
35
36
37 ; Z10 operand and result forwarding.
38
39 ; Instructions marked with the attributes as z10_fwd or z10_fr can
40 ; forward a value they load from one of their operants into a register
41 ; if the instruction in the second pipeline reads the same register.
42 ; The second operation must be superscalar. Instructions marked as
43 ; z10_rec or z10_fr can receive a value they read from a register is
44 ; this register gets updated by an instruction in the first pipeline.
45 ; The first instruction must be superscalar.
46
47
48 ; Forwarding from z10_fwd and z10_fr to z10_super.
49
50 (define_bypass 0 "z10_la_fwd, z10_la_fwd_A1, z10_larl_fwd, z10_larl_fwd_A3, \
51 z10_load_fwd, z10_load_fwd_A3, \
52 z10_other_fwd, z10_other_fwd_A1, z10_other_fwd_A3, \
53 z10_other_fr, z10_other_fr_A3, z10_other_fr_E1, \
54 z10_other_fwd_E1, z10_lr_fr, z10_lr_fr_E1, \
55 z10_int_fwd, z10_int_fwd_A1, z10_int_fwd_A3, \
56 z10_int_fwd_E1, z10_int_fr, z10_int_fr_E1, \
57 z10_int_fr_A3"
58 "z10_other_super, z10_other_super_c_E1, z10_other_super_E1, \
59 z10_int_super, z10_int_super_E1, \
60 z10_lr, z10_store_super")
61
62
63 ; Forwarding from z10_super to frz10_ and z10_rec.
64
65 (define_bypass 0 "z10_other_super, z10_other_super_E1, z10_other_super_c_E1, \
66 z10_int_super, z10_int_super_E1, \
67 z10_larl_super_E1, z10_larl_super, \
68 z10_store_super"
69 "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \
70 z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \
71 z10_other_fr_E1, z10_store_rec")
72
73
74 ; Forwarding from z10_fwd and z10_fr to z10_rec and z10_fr.
75
76 (define_bypass 0 "z10_la_fwd, z10_la_fwd_A1, z10_larl_fwd, z10_larl_fwd_A3, \
77 z10_load_fwd, z10_load_fwd_A3, \
78 z10_other_fwd, z10_other_fwd_A1, z10_other_fwd_A3, \
79 z10_other_fr, z10_other_fr_A3, z10_other_fr_E1, \
80 z10_other_fwd_E1, \
81 z10_lr_fr, z10_lr_fr_E1, \
82 z10_int_fwd, z10_int_fwd_A1, z10_int_fwd_A3, \
83 z10_int_fwd_E1, z10_int_fr, z10_int_fr_E1, \
84 z10_int_fr_A3"
85 "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \
86 z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \
87 z10_other_fr_E1, z10_store_rec")
88
89
90 ;
91 ; Simple insns
92 ;
93
94 ; Here is the cycle diagram for FXU-executed instructions:
95 ; ... A1 A2 A3 E1 P1 P2 P3 R0 ...
96 ; ^ ^ ^
97 ; | | updated GPR is available
98 ; | write to GPR
99 ; instruction reads GPR during this cycle
100
101
102 ; Variants of z10_int follow.
103
104 (define_insn_reservation "z10_int" 6
105 (and (and (eq_attr "cpu" "z10")
106 (eq_attr "type" "integer"))
107 (and (eq_attr "atype" "reg")
108 (and (and (eq_attr "z10prop" "!z10_super")
109 (eq_attr "z10prop" "!z10_super_c"))
110 (and (and (and (and (eq_attr "z10prop" "!z10_super_E1")
111 (eq_attr "z10prop" "!z10_super_c_E1"))
112 (eq_attr "z10prop" "!z10_fwd"))
113 (and (eq_attr "z10prop" "!z10_fwd_A1")
114 (eq_attr "z10prop" "!z10_fwd_A3")))
115 (and (and (eq_attr "z10prop" "!z10_fwd_E1")
116 (eq_attr "z10prop" "!z10_fr"))
117 (and (eq_attr "z10prop" "!z10_fr_E1")
118 (eq_attr "z10prop" "!z10_fr_A3")))))))
119 "z10_e1_ANY, z10_Gate_ANY")
120
121 (define_insn_reservation "z10_int_super" 6
122 (and (eq_attr "cpu" "z10")
123 (and (eq_attr "type" "integer")
124 (and (eq_attr "atype" "reg")
125 (ior (eq_attr "z10prop" "z10_super")
126 (eq_attr "z10prop" "z10_super_c")))))
127 "z10_e1_ANY, z10_Gate_ANY")
128
129 (define_insn_reservation "z10_int_super_E1" 6
130 (and (eq_attr "cpu" "z10")
131 (and (eq_attr "type" "integer")
132 (and (eq_attr "atype" "reg")
133 (ior (eq_attr "z10prop" "z10_super_E1")
134 (eq_attr "z10prop" "z10_super_c_E1")))))
135 "z10_e1_ANY, z10_Gate_ANY")
136
137 (define_insn_reservation "z10_int_fwd" 6
138 (and (eq_attr "cpu" "z10")
139 (and (eq_attr "type" "integer")
140 (and (eq_attr "atype" "reg")
141 (eq_attr "z10prop" "z10_fwd"))))
142 "z10_e1_ANY, z10_Gate_ANY")
143
144 (define_insn_reservation "z10_int_fwd_A1" 6
145 (and (eq_attr "cpu" "z10")
146 (and (eq_attr "type" "integer")
147 (and (eq_attr "atype" "reg")
148 (eq_attr "z10prop" "z10_fwd_A1"))))
149 "z10_e1_ANY, z10_Gate_ANY")
150
151 (define_insn_reservation "z10_int_fwd_A3" 6
152 (and (eq_attr "cpu" "z10")
153 (and (eq_attr "type" "integer")
154 (and (eq_attr "atype" "reg")
155 (eq_attr "z10prop" "z10_fwd_A3"))))
156 "z10_e1_ANY, z10_Gate_ANY")
157
158 (define_insn_reservation "z10_int_fwd_E1" 6
159 (and (eq_attr "cpu" "z10")
160 (and (eq_attr "type" "integer")
161 (and (eq_attr "atype" "reg")
162 (eq_attr "z10prop" "z10_fwd_E1"))))
163 "z10_e1_ANY, z10_Gate_ANY")
164
165 (define_insn_reservation "z10_int_fr" 6
166 (and (eq_attr "cpu" "z10")
167 (and (eq_attr "type" "integer")
168 (and (eq_attr "atype" "reg")
169 (eq_attr "z10prop" "z10_fr"))))
170 "z10_e1_ANY, z10_Gate_ANY")
171
172 (define_insn_reservation "z10_int_fr_E1" 6
173 (and (eq_attr "cpu" "z10")
174 (and (eq_attr "type" "integer")
175 (and (eq_attr "atype" "reg")
176 (eq_attr "z10prop" "z10_fr_E1"))))
177 "z10_e1_ANY, z10_Gate_ANY")
178
179 (define_insn_reservation "z10_int_fr_A3" 6
180 (and (eq_attr "cpu" "z10")
181 (and (eq_attr "type" "integer")
182 (and (eq_attr "atype" "reg")
183 (eq_attr "z10prop" "z10_fr_A3"))))
184 "z10_e1_ANY, z10_Gate_ANY")
185
186 ; END of z10_int variants
187
188
189 (define_insn_reservation "z10_agen" 6
190 (and (eq_attr "cpu" "z10")
191 (and (eq_attr "type" "integer")
192 (eq_attr "atype" "agen")))
193 "z10_e1_ANY, z10_Gate_ANY")
194
195
196 (define_insn_reservation "z10_lr" 6
197 (and (eq_attr "cpu" "z10")
198 (and (eq_attr "type" "lr")
199 (and (eq_attr "z10prop" "!z10_fr")
200 (eq_attr "z10prop" "!z10_fr_E1"))))
201 "z10_e1_ANY, z10_Gate_ANY")
202
203 (define_insn_reservation "z10_lr_fr" 6
204 (and (eq_attr "cpu" "z10")
205 (and (eq_attr "type" "lr")
206 (eq_attr "z10prop" "z10_fr")))
207 "z10_e1_ANY, z10_Gate_ANY")
208 ; "z10_e1_ANY")
209
210 (define_insn_reservation "z10_lr_fr_E1" 6
211 (and (eq_attr "cpu" "z10")
212 (and (eq_attr "type" "lr")
213 (eq_attr "z10prop" "z10_fr_E1")))
214 "z10_e1_ANY, z10_Gate_ANY")
215 ; "z10_e1_ANY")
216
217
218 (define_insn_reservation "z10_la" 6
219 (and (eq_attr "cpu" "z10")
220 (and (eq_attr "type" "la")
221 (and (eq_attr "z10prop" "!z10_fwd")
222 (eq_attr "z10prop" "!z10_fwd_A1"))))
223 "z10_e1_ANY, z10_Gate_ANY")
224
225 (define_insn_reservation "z10_la_fwd" 6
226 (and (eq_attr "cpu" "z10")
227 (and (eq_attr "type" "la")
228 (eq_attr "z10prop" "z10_fwd")))
229 "z10_e1_ANY, z10_Gate_ANY")
230 ; "z10_e1_ANY")
231
232 (define_insn_reservation "z10_la_fwd_A1" 6
233 (and (eq_attr "cpu" "z10")
234 (and (eq_attr "type" "la")
235 (eq_attr "z10prop" "z10_fwd_A1")))
236 "z10_e1_ANY, z10_Gate_ANY")
237 ; "z10_e1_ANY")
238
239
240 ; larl-type instructions
241
242 (define_insn_reservation "z10_larl" 6
243 (and (eq_attr "cpu" "z10")
244 (and (eq_attr "type" "larl")
245 (and (eq_attr "z10prop" "!z10_super_A1")
246 (and (eq_attr "z10prop" "!z10_fwd")
247 (and (eq_attr "z10prop" "!z10_fwd_A3")
248 (and (eq_attr "z10prop" "!z10_super")
249 (eq_attr "z10prop" "!z10_super_c"))
250 (and (eq_attr "z10prop" "!z10_super_E1")
251 (eq_attr "z10prop" "!z10_super_c_E1")))))))
252 "z10_e1_ANY, z10_Gate_ANY")
253
254 (define_insn_reservation "z10_larl_super" 6
255 (and (eq_attr "cpu" "z10")
256 (and (eq_attr "type" "larl")
257 (and (eq_attr "z10prop" "z10_super")
258 (eq_attr "z10prop" "z10_super_c"))))
259 "z10_e1_ANY, z10_Gate_ANY")
260
261 (define_insn_reservation "z10_larl_fwd" 6
262 (and (eq_attr "cpu" "z10")
263 (and (eq_attr "type" "larl")
264 (eq_attr "z10prop" "z10_fwd")))
265 "z10_e1_ANY, z10_Gate_ANY")
266
267 (define_insn_reservation "z10_larl_fwd_A3" 6
268 (and (eq_attr "cpu" "z10")
269 (and (eq_attr "type" "larl")
270 (eq_attr "z10prop" "z10_fwd_A3")))
271 "z10_e1_ANY, z10_Gate_ANY")
272
273
274 (define_insn_reservation "z10_larl_A1" 6
275 (and (eq_attr "cpu" "z10")
276 (and (eq_attr "type" "larl")
277 (eq_attr "z10prop" "z10_super_A1")))
278 "z10_e1_ANY, z10_Gate_ANY")
279 ; "z10_e1_ANY")
280
281 (define_insn_reservation "z10_larl_super_E1" 6
282 (and (eq_attr "cpu" "z10")
283 (and (eq_attr "type" "larl")
284 (ior (eq_attr "z10prop" "z10_super_E1")
285 (eq_attr "z10prop" "z10_super_c_E1"))))
286 "z10_e1_ANY, z10_Gate_ANY")
287 ; "z10_e1_ANY")
288
289
290 (define_insn_reservation "z10_load" 6
291 (and (eq_attr "cpu" "z10")
292 (and (eq_attr "type" "load")
293 (and (eq_attr "z10prop" "!z10_fwd")
294 (eq_attr "z10prop" "!z10_fwd_A3"))))
295 "z10_e1_ANY, z10_Gate_ANY")
296
297 (define_insn_reservation "z10_load_fwd" 6
298 (and (eq_attr "cpu" "z10")
299 (and (eq_attr "type" "load")
300 (eq_attr "z10prop" "z10_fwd")))
301 "z10_e1_ANY, z10_Gate_ANY")
302 ; "z10_e1_ANY")
303
304 (define_insn_reservation "z10_load_fwd_A3" 6
305 (and (eq_attr "cpu" "z10")
306 (and (eq_attr "type" "load")
307 (eq_attr "z10prop" "z10_fwd_A3")))
308 "z10_e1_ANY, z10_Gate_ANY")
309 ; "z10_e1_ANY")
310
311 (define_insn_reservation "z10_store" 6
312 (and (eq_attr "cpu" "z10")
313 (and (eq_attr "type" "store")
314 (and (eq_attr "z10prop" "!z10_rec")
315 (and (eq_attr "z10prop" "!z10_super")
316 (eq_attr "z10prop" "!z10_super_c")))))
317 "z10_e1_ANY, z10_Gate_ANY")
318
319 (define_insn_reservation "z10_store_super" 6
320 (and (eq_attr "cpu" "z10")
321 (and (eq_attr "type" "store")
322 (ior (eq_attr "z10prop" "z10_super")
323 (eq_attr "z10prop" "z10_super_c"))))
324 "z10_e1_ANY, z10_Gate_ANY")
325
326 (define_insn_reservation "z10_store_rec" 6
327 (and (eq_attr "cpu" "z10")
328 (and (eq_attr "type" "store")
329 (eq_attr "z10prop" "z10_rec")))
330 "z10_e1_ANY, z10_Gate_ANY")
331
332 ; The default_latency is chosen to drain off the pipeline.
333 (define_insn_reservation "z10_call" 14
334 (and (eq_attr "cpu" "z10")
335 (eq_attr "type" "jsr"))
336 "z10_e1_BOTH*4, z10_Gate_BOTH")
337
338 ; The default latency is for worst case. CS and CSG take one
339 ; cycle only (i.e. latency would be 6).
340 (define_insn_reservation "z10_sem" 9
341 (and (eq_attr "cpu" "z10")
342 (eq_attr "type" "sem"))
343 "z10_e1_BOTH*5, z10_Gate_ANY")
344
345 (define_insn_reservation "z10_cs" 6
346 (and (eq_attr "cpu" "z10")
347 (eq_attr "type" "cs"))
348 "z10_e1_BOTH, z10_Gate_BOTH")
349
350 (define_insn_reservation "z10_vs" 6
351 (and (eq_attr "cpu" "z10")
352 (eq_attr "type" "vs"))
353 "z10_e1_BOTH*4, z10_Gate_BOTH")
354
355 ; Load and store multiple. Actual number of cycles
356 ; in unknown at compile.time.
357 (define_insn_reservation "z10_stm" 10
358 (and (eq_attr "cpu" "z10")
359 (ior (eq_attr "type" "stm")
360 (eq_attr "type" "lm")))
361 "z10_e1_BOTH*4, z10_Gate_BOTH")
362
363
364 ; Subsets of z10_other follow.
365
366 (define_insn_reservation "z10_other" 6
367 (and (and (eq_attr "cpu" "z10")
368 (eq_attr "type" "other"))
369 (and (and (eq_attr "z10prop" "!z10_fwd")
370 (eq_attr "z10prop" "!z10_fwd_A1"))
371 (and (and (and (eq_attr "z10prop" "!z10_fr_A3")
372 (eq_attr "z10prop" "!z10_fwd_A3"))
373 (and (eq_attr "z10prop" "!z10_fr")
374 (eq_attr "z10prop" "!z10_fr_E1")))
375 (and (and (and (eq_attr "z10prop" "!z10_super")
376 (eq_attr "z10prop" "!z10_super_c"))
377 (eq_attr "z10prop" "!z10_super_c_E1"))
378 (and (eq_attr "z10prop" "!z10_super_E1")
379 (eq_attr "z10prop" "!z10_fwd_E1"))))))
380 "z10_e1_BOTH, z10_Gate_BOTH")
381
382 (define_insn_reservation "z10_other_fr_E1" 6
383 (and (eq_attr "cpu" "z10")
384 (and (eq_attr "type" "other")
385 (eq_attr "z10prop" "z10_fr_E1")))
386 "z10_e1_BOTH, z10_Gate_BOTH")
387
388 (define_insn_reservation "z10_other_super_c_E1" 6
389 (and (eq_attr "cpu" "z10")
390 (and (eq_attr "type" "other")
391 (eq_attr "z10prop" "z10_super_c_E1")))
392 "z10_e1_BOTH, z10_Gate_BOTH")
393
394 (define_insn_reservation "z10_other_super_E1" 6
395 (and (eq_attr "cpu" "z10")
396 (and (eq_attr "type" "other")
397 (eq_attr "z10prop" "z10_super_E1")))
398 "z10_e1_BOTH, z10_Gate_BOTH")
399
400 (define_insn_reservation "z10_other_fwd_E1" 6
401 (and (eq_attr "cpu" "z10")
402 (and (eq_attr "type" "other")
403 (eq_attr "z10prop" "z10_fwd_E1")))
404 "z10_e1_BOTH, z10_Gate_BOTH")
405
406 (define_insn_reservation "z10_other_fwd" 6
407 (and (eq_attr "cpu" "z10")
408 (and (eq_attr "type" "other")
409 (eq_attr "z10prop" "z10_fwd")))
410 "z10_e1_BOTH, z10_Gate_BOTH")
411
412 (define_insn_reservation "z10_other_fwd_A3" 6
413 (and (eq_attr "cpu" "z10")
414 (and (eq_attr "type" "other")
415 (eq_attr "z10prop" "z10_fwd_A3")))
416 "z10_e1_BOTH, z10_Gate_BOTH")
417
418 (define_insn_reservation "z10_other_fwd_A1" 6
419 (and (eq_attr "cpu" "z10")
420 (and (eq_attr "type" "other")
421 (eq_attr "z10prop" "z10_fwd_A1")))
422 "z10_e1_BOTH, z10_Gate_BOTH")
423
424 (define_insn_reservation "z10_other_fr" 6
425 (and (eq_attr "cpu" "z10")
426 (and (eq_attr "type" "other")
427 (eq_attr "z10prop" "z10_fr")))
428 "z10_e1_BOTH, z10_Gate_BOTH")
429
430 (define_insn_reservation "z10_other_fr_A3" 6
431 (and (eq_attr "cpu" "z10")
432 (and (eq_attr "type" "other")
433 (eq_attr "z10prop" "z10_fr_A3")))
434 "z10_e1_BOTH, z10_Gate_BOTH")
435
436 (define_insn_reservation "z10_other_super" 6
437 (and (eq_attr "cpu" "z10")
438 (and (eq_attr "type" "other")
439 (ior (eq_attr "z10prop" "z10_super")
440 (eq_attr "z10prop" "z10_super_c"))))
441 "z10_e1_BOTH, z10_Gate_BOTH")
442
443 ; END of z10_other subsets.
444
445
446 ;
447 ; Floating point insns
448 ;
449
450 ; Z10 executes the following integer operations in the BFU pipeline.
451
452 (define_insn_reservation "z10_mul_sidi" 12
453 (and (eq_attr "cpu" "z10")
454 (eq_attr "type" "imulsi,imuldi,imulhi"))
455 "z10_e1_BOTH, z10_Gate_FP")
456
457 ; Some variants take fewer cycles, but that is not relevant here.
458 (define_insn_reservation "z10_div" 162
459 (and (eq_attr "cpu" "z10")
460 (eq_attr "type" "idiv"))
461 "z10_e1_BOTH*4, z10_Gate_FP")
462
463
464 ; BFP multiplication and general instructions
465
466 (define_insn_reservation "z10_fsimpdf" 12
467 (and (eq_attr "cpu" "z10")
468 (eq_attr "type" "fsimpdf,fmuldf"))
469 "z10_e1_BOTH, z10_Gate_FP")
470 ; Wg "z10_e1_T, z10_Gate_FP")
471
472 (define_insn_reservation "z10_fsimpsf" 12
473 (and (eq_attr "cpu" "z10")
474 (eq_attr "type" "fsimpsf,fmulsf"))
475 "z10_e1_BOTH, z10_Gate_FP")
476 ; Wg "z10_e1_T, z10_Gate_FP")
477
478 (define_insn_reservation "z10_fmultf" 52
479 (and (eq_attr "cpu" "z10")
480 (eq_attr "type" "fmultf"))
481 "z10_e1_BOTH*4, z10_Gate_FP")
482 ; Wg "z10_e1_T*4, z10_Gate_FP")
483
484 (define_insn_reservation "z10_fsimptf" 14
485 (and (eq_attr "cpu" "z10")
486 (eq_attr "type" "fsimptf"))
487 "z10_e1_BOTH*2, z10_Gate_FP")
488 ; Wg "z10_e1_T*2, z10_Gate_FP")
489
490
491 ; BFP division
492
493 (define_insn_reservation "z10_fdivtf" 113
494 (and (eq_attr "cpu" "z10")
495 (eq_attr "type" "fdivtf"))
496 "z10_e1_T*4, z10_Gate_FP")
497
498 (define_insn_reservation "z10_fdivdf" 41
499 (and (eq_attr "cpu" "z10")
500 (eq_attr "type" "fdivdf"))
501 "z10_e1_T*4, z10_Gate_FP")
502
503 (define_insn_reservation "z10_fdivsf" 34
504 (and (eq_attr "cpu" "z10")
505 (eq_attr "type" "fdivsf"))
506 "z10_e1_T*4, z10_Gate_FP")
507
508
509 ; BFP sqrt
510
511 (define_insn_reservation "z10_fsqrtsf" 41
512 (and (eq_attr "cpu" "z10")
513 (eq_attr "type" "fsqrtsf"))
514 "z10_e1_T*4, z10_Gate_FP")
515
516 (define_insn_reservation "z10_fsqrtdf" 54
517 (and (eq_attr "cpu" "z10")
518 (eq_attr "type" "fsqrtdf"))
519 "z10_e1_T*4, z10_Gate_FP")
520
521 (define_insn_reservation "z10_fsqrtf" 122
522 (and (eq_attr "cpu" "z10")
523 (eq_attr "type" "fsqrttf"))
524 "z10_e1_T*4, z10_Gate_FP")
525
526
527 ; BFP load and store
528
529 (define_insn_reservation "z10_floadtf" 12
530 (and (eq_attr "cpu" "z10")
531 (eq_attr "type" "floadtf"))
532 "z10_e1_T, z10_Gate_FP")
533
534 (define_insn_reservation "z10_floaddf" 12
535 (and (eq_attr "cpu" "z10")
536 (eq_attr "type" "floaddf"))
537 "z10_e1_T, z10_Gate_FP")
538
539 (define_insn_reservation "z10_floadsf" 12
540 (and (eq_attr "cpu" "z10")
541 (eq_attr "type" "floadsf"))
542 "z10_e1_T, z10_Gate_FP")
543
544 (define_insn_reservation "z10_fstoredf" 12
545 (and (eq_attr "cpu" "z10")
546 (eq_attr "type" "fstoredf,fstoredd"))
547 "z10_e1_T, z10_Gate_FP")
548
549 (define_insn_reservation "z10_fstoresf" 12
550 (and (eq_attr "cpu" "z10")
551 (eq_attr "type" "fstoresf,fstoresd"))
552 "z10_e1_T, z10_Gate_FP")
553
554
555 ; BFP truncate
556 (define_insn_reservation "z10_ftrunctf" 12
557 (and (eq_attr "cpu" "z10")
558 (eq_attr "type" "ftrunctf"))
559 "z10_e1_T, z10_Gate_FP")
560
561 (define_insn_reservation "z10_ftruncdf" 16
562 (and (eq_attr "cpu" "z10")
563 (eq_attr "type" "ftruncdf"))
564 "z10_e1_T, z10_Gate_FP")
565
566
567 ; Conversion between BFP and int.
568 (define_insn_reservation "z10_ftoi" 13
569 (and (eq_attr "cpu" "z10")
570 (eq_attr "type" "ftoi"))
571 "z10_e1_T, z10_Gate_FP")
572
573 (define_insn_reservation "z10_itoftf" 14
574 (and (eq_attr "cpu" "z10")
575 (eq_attr "type" "itoftf"))
576 "z10_e1_T*2, z10_Gate_FP")
577
578 (define_insn_reservation "z10_itofsfdf" 12
579 (and (eq_attr "cpu" "z10")
580 (eq_attr "type" "itofdf,itofsf"))
581 "z10_e1_T, z10_Gate_FP")
582
583
584
585 ; BFP-related bypasses. There is no bypass for extended mode.
586 (define_bypass 1 "z10_fsimpdf" "z10_fstoredf")
587 (define_bypass 1 "z10_fsimpsf" "z10_fstoresf")
588 (define_bypass 1 "z10_floaddf" "z10_fsimpdf, z10_fstoredf, z10_floaddf")
589 (define_bypass 1 "z10_floadsf" "z10_fsimpsf, z10_fstoresf, z10_floadsf")
590
591
592 ;
593 ; insn_reservations for DFP instructions.
594 ;
595
596 ; Exact number of cycles is not known at compile-time.
597 (define_insn_reservation "z10_fdivddtd" 40
598 (and (eq_attr "cpu" "z10")
599 (eq_attr "type" "fdivdd,fdivtd"))
600 "z10_e1_BOTH,z10_Gate_DFU")
601
602 (define_insn_reservation "z10_ftruncsd" 38
603 (and (eq_attr "cpu" "z10")
604 (eq_attr "type" "ftruncsd"))
605 "z10_e1_BOTH*4,z10_Gate_DFU")
606
607 (define_insn_reservation "z10_ftruncdd" 340
608 (and (eq_attr "cpu" "z10")
609 (eq_attr "type" "ftruncsd"))
610 "z10_e1_BOTH*4,z10_Gate_DFU")
611
612 (define_insn_reservation "z10_floaddd" 12
613 (and (eq_attr "cpu" "z10")
614 (eq_attr "type" "floaddd"))
615 "z10_e1_BOTH,z10_Gate_DFU")
616
617 (define_insn_reservation "z10_floadsd" 12
618 (and (eq_attr "cpu" "z10")
619 (eq_attr "type" "floadsd"))
620 "z10_e1_BOTH,z10_Gate_DFU")
621
622 ; Exact number of cycles is not known at compile-time.
623 (define_insn_reservation "z10_fmulddtd" 35
624 (and (eq_attr "cpu" "z10")
625 (eq_attr "type" "fmuldd,fmultd"))
626 "z10_e1_BOTH,z10_Gate_DFU")
627
628 (define_insn_reservation "z10_fsimpdd" 17
629 (and (eq_attr "cpu" "z10")
630 (eq_attr "type" "fsimpdd"))
631 "z10_e1_BOTH,z10_Gate_DFU")
632
633 (define_insn_reservation "z10_fsimpsd" 17
634 (and (eq_attr "cpu" "z10")
635 (eq_attr "type" "fsimpsd"))
636 "z10_e1_BOTH,z10_Gate_DFU")
637
638 (define_insn_reservation "z10_fsimptd" 18
639 (and (eq_attr "cpu" "z10")
640 (eq_attr "type" "fsimptd"))
641 "z10_e1_BOTH,z10_Gate_DFU")
642
643 (define_insn_reservation "z10_itofdd" 36
644 (and (eq_attr "cpu" "z10")
645 (eq_attr "type" "itofdd"))
646 "z10_e1_BOTH*3,z10_Gate_DFU")
647
648 (define_insn_reservation "z10_itoftd" 49
649 (and (eq_attr "cpu" "z10")
650 (eq_attr "type" "itoftd"))
651 "z10_e1_BOTH*3,z10_Gate_DFU")
652
653 ; Exact number of cycles is not known at compile-time.
654 (define_insn_reservation "z10_ftoidfp" 30
655 (and (eq_attr "cpu" "z10")
656 (eq_attr "type" "ftoidfp"))
657 "z10_e1_BOTH*3,z10_Gate_DFU")
658
659
660 ;
661 ; Address-related bypasses
662 ;
663
664 ; Here is the cycle diagram for Address-related bypasses:
665 ; ... G1 G2 G3 A0 A1 A2 A3 E1 P1 P2 P3 R0 ...
666 ; ^ ^ ^ ^ ^
667 ; | | | | E1-type bypasses provide the new addr AFTER this cycle
668 ; | | | A3-type bypasses provide the new addr AFTER this cycle
669 ; | | A1-type bypasses provide the new addr AFTER this cycle
670 ; | AGI resolution, actual USE of address is DURING this cycle
671 ; AGI detection
672
673 (define_bypass 3 "z10_larl_A1, z10_la_fwd_A1, z10_other_fwd_A1, \
674 z10_int_fwd_A1"
675 "z10_agen, z10_la, z10_branch, z10_call, z10_load, \
676 z10_store, \
677 z10_cs, z10_stm, z10_other"
678 "s390_agen_dep_p")
679
680
681 (define_bypass 5 "z10_larl_fwd_A3, z10_load_fwd_A3, z10_other_fwd_A3, \
682 z10_other_fr_A3, z10_int_fwd_A3, z10_int_fr_A3"
683 "z10_agen, z10_la, z10_branch, z10_call, z10_load, \
684 z10_store, \
685 z10_cs, z10_stm, z10_other"
686 "s390_agen_dep_p")
687
688 (define_bypass 6 "z10_other_fr_E1, z10_other_super_c_E1, z10_other_super_E1, \
689 z10_other_fwd_E1, \
690 z10_lr_fr_E1, z10_larl_super_E1, \
691 z10_int_super_E1, z10_int_fwd_E1, z10_int_fr_E1"
692 "z10_agen, z10_la, z10_branch, z10_call, z10_load, \
693 z10_store, \
694 z10_cs, z10_stm, z10_other"
695 "s390_agen_dep_p")
696
697
698
699 ;
700 ; Try to avoid transitions between DFU-, BFU- and FXU-executed instructions as there is a
701 ; dispatch delay required.
702 ;
703
704
705 ; Declaration for some pseudo-pipeline stages that reflect the
706 ; dispatch gap when issueing an INT/FXU/BFU-executed instruction after
707 ; an instruction executed by a different unit has been executed. The
708 ; approach is that we pretend a pipelined execution of BFU operations
709 ; with as many stages as the gap is long and request that none of
710 ; these stages is busy when issueing a FXU- or DFU-executed
711 ; instruction. Similar for FXU- and DFU-executed instructions.
712
713 ; Declaration for FPU stages.
714 (define_cpu_unit "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, \
715 z10_f7, z10_f8, z10_f9, z10_f10, z10_f11, z10_f12" "z10_cpu")
716 (define_reservation "z10_FP_PP" "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, \
717 z10_f5, z10_f6, z10_f7, z10_f8, z10_f9, z10_f10, z10_f11, \
718 z10_f12")
719
720 ; Declaration for FXU stages.
721 (define_cpu_unit "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6" "z10_cpu")
722 (define_cpu_unit "z10_T1, z10_T2, z10_T3, z10_T4, z10_T5, z10_T6" "z10_cpu")
723 (define_reservation "z10_INT_PP" "z10_S1 | z10_T1, z10_S2 | z10_T2, z10_S3 \
724 | z10_T3, z10_S4 | z10_T4, z10_S5 | \
725 z10_T5, z10_S6 | z10_T6")
726
727 ; Declaration for DFU stages.
728 (define_cpu_unit "z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6"
729 "z10_cpu")
730 (define_reservation "z10_DFU_PP" "z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, \
731 z10_d5, z10_d6")
732
733
734 ; Pseudo-units representing whether the respective unit is available
735 ; in the sense that using it does not cause a dispatch delay.
736
737 (define_cpu_unit "z10_S_avail, z10_T_avail, z10_FP_avail, z10_DFU_avail"
738 "z10_cpu")
739
740 (absence_set "z10_FP_avail"
741 "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6, z10_T1, z10_T2, z10_T3, z10_T4, \
742 z10_T5, z10_T6, \
743 z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6")
744
745 (absence_set "z10_S_avail,z10_T_avail"
746 "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, z10_f7, \
747 z10_f8, z10_f9, z10_f10, z10_f11, z10_f12, \
748 z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6")
749
750 (absence_set "z10_DFU_avail"
751 "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6, z10_T1, z10_T2, z10_T3, z10_T4, \
752 z10_T5, z10_T6, \
753 z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, z10_f7, \
754 z10_f8, z10_f9, z10_f10, z10_f11, z10_f12")
755
756
757 ; Pseudo-units to be used in insn_reservations.
758
759 (define_reservation "z10_Gate_ANY" "((z10_S_avail | z10_T_avail), z10_INT_PP)")
760 (define_reservation "z10_Gate_BOTH" "((z10_S_avail + z10_T_avail), z10_INT_PP)")
761
762 (define_reservation "z10_Gate_FP" "z10_FP_avail, z10_FP_PP")
763
764 (define_reservation "z10_Gate_DFU" "z10_DFU_avail, z10_DFU_PP")