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comparison gcc/config/s390/s390.md @ 0:a06113de4d67
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author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
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date | Fri, 17 Jul 2009 14:47:48 +0900 |
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children | 58ad6c70ea60 |
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1 ;;- Machine description for GNU compiler -- S/390 / zSeries version. | |
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, | |
3 ;; 2009 Free Software Foundation, Inc. | |
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and | |
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and | |
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
7 | |
8 ;; This file is part of GCC. | |
9 | |
10 ;; GCC is free software; you can redistribute it and/or modify it under | |
11 ;; the terms of the GNU General Public License as published by the Free | |
12 ;; Software Foundation; either version 3, or (at your option) any later | |
13 ;; version. | |
14 | |
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 ;; for more details. | |
19 | |
20 ;; You should have received a copy of the GNU General Public License | |
21 ;; along with GCC; see the file COPYING3. If not see | |
22 ;; <http://www.gnu.org/licenses/>. | |
23 | |
24 ;; | |
25 ;; See constraints.md for a description of constraints specific to s390. | |
26 ;; | |
27 | |
28 ;; Special formats used for outputting 390 instructions. | |
29 ;; | |
30 ;; %C: print opcode suffix for branch condition. | |
31 ;; %D: print opcode suffix for inverse branch condition. | |
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
33 ;; %G: print the size of the operand in bytes. | |
34 ;; %O: print only the displacement of a memory reference. | |
35 ;; %R: print only the base register of a memory reference. | |
36 ;; %S: print S-type memory reference (base+displacement). | |
37 ;; %N: print the second word of a DImode operand. | |
38 ;; %M: print the second word of a TImode operand. | |
39 ;; %Y: print shift count operand. | |
40 ;; | |
41 ;; %b: print integer X as if it's an unsigned byte. | |
42 ;; %c: print integer X as if it's an signed byte. | |
43 ;; %x: print integer X as if it's an unsigned halfword. | |
44 ;; %h: print integer X as if it's a signed halfword. | |
45 ;; %i: print the first nonzero HImode part of X. | |
46 ;; %j: print the first HImode part unequal to -1 of X. | |
47 ;; %k: print the first nonzero SImode part of X. | |
48 ;; %m: print the first SImode part unequal to -1 of X. | |
49 ;; %o: print integer X as if it's an unsigned 32bit word. | |
50 ;; | |
51 ;; We have a special constraint for pattern matching. | |
52 ;; | |
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
54 ;; | |
55 | |
56 ;; | |
57 ;; UNSPEC usage | |
58 ;; | |
59 | |
60 (define_constants | |
61 [; Miscellaneous | |
62 (UNSPEC_ROUND 1) | |
63 (UNSPEC_CCU_TO_INT 2) | |
64 (UNSPEC_CCZ_TO_INT 3) | |
65 (UNSPEC_ICM 10) | |
66 (UNSPEC_TIE 11) | |
67 | |
68 ; GOT/PLT and lt-relative accesses | |
69 (UNSPEC_LTREL_OFFSET 100) | |
70 (UNSPEC_LTREL_BASE 101) | |
71 (UNSPEC_POOL_OFFSET 102) | |
72 (UNSPEC_GOTENT 110) | |
73 (UNSPEC_GOT 111) | |
74 (UNSPEC_GOTOFF 112) | |
75 (UNSPEC_PLT 113) | |
76 (UNSPEC_PLTOFF 114) | |
77 | |
78 ; Literal pool | |
79 (UNSPEC_RELOAD_BASE 210) | |
80 (UNSPEC_MAIN_BASE 211) | |
81 (UNSPEC_LTREF 212) | |
82 (UNSPEC_INSN 213) | |
83 (UNSPEC_EXECUTE 214) | |
84 | |
85 ; Atomic Support | |
86 (UNSPEC_MB 400) | |
87 | |
88 ; TLS relocation specifiers | |
89 (UNSPEC_TLSGD 500) | |
90 (UNSPEC_TLSLDM 501) | |
91 (UNSPEC_NTPOFF 502) | |
92 (UNSPEC_DTPOFF 503) | |
93 (UNSPEC_GOTNTPOFF 504) | |
94 (UNSPEC_INDNTPOFF 505) | |
95 | |
96 ; TLS support | |
97 (UNSPEC_TLSLDM_NTPOFF 511) | |
98 (UNSPEC_TLS_LOAD 512) | |
99 | |
100 ; String Functions | |
101 (UNSPEC_SRST 600) | |
102 (UNSPEC_MVST 601) | |
103 | |
104 ; Stack Smashing Protector | |
105 (UNSPEC_SP_SET 700) | |
106 (UNSPEC_SP_TEST 701) | |
107 | |
108 ; Copy sign instructions | |
109 (UNSPEC_COPYSIGN 800) | |
110 | |
111 ; Test Data Class (TDC) | |
112 (UNSPEC_TDC_INSN 900) | |
113 ]) | |
114 | |
115 ;; | |
116 ;; UNSPEC_VOLATILE usage | |
117 ;; | |
118 | |
119 (define_constants | |
120 [; Blockage | |
121 (UNSPECV_BLOCKAGE 0) | |
122 | |
123 ; TPF Support | |
124 (UNSPECV_TPF_PROLOGUE 20) | |
125 (UNSPECV_TPF_EPILOGUE 21) | |
126 | |
127 ; Literal pool | |
128 (UNSPECV_POOL 200) | |
129 (UNSPECV_POOL_SECTION 201) | |
130 (UNSPECV_POOL_ALIGN 202) | |
131 (UNSPECV_POOL_ENTRY 203) | |
132 (UNSPECV_MAIN_POOL 300) | |
133 | |
134 ; TLS support | |
135 (UNSPECV_SET_TP 500) | |
136 | |
137 ; Atomic Support | |
138 (UNSPECV_CAS 700) | |
139 ]) | |
140 | |
141 ;; | |
142 ;; Registers | |
143 ;; | |
144 | |
145 ; Registers with special meaning | |
146 | |
147 (define_constants | |
148 [ | |
149 ; Sibling call register. | |
150 (SIBCALL_REGNUM 1) | |
151 ; Literal pool base register. | |
152 (BASE_REGNUM 13) | |
153 ; Return address register. | |
154 (RETURN_REGNUM 14) | |
155 ; Condition code register. | |
156 (CC_REGNUM 33) | |
157 ; Thread local storage pointer register. | |
158 (TP_REGNUM 36) | |
159 ]) | |
160 | |
161 ; Hardware register names | |
162 | |
163 (define_constants | |
164 [ | |
165 ; General purpose registers | |
166 (GPR0_REGNUM 0) | |
167 ; Floating point registers. | |
168 (FPR0_REGNUM 16) | |
169 (FPR2_REGNUM 18) | |
170 ]) | |
171 | |
172 ;; | |
173 ;; PFPO GPR0 argument format | |
174 ;; | |
175 | |
176 (define_constants | |
177 [ | |
178 ; PFPO operation type | |
179 (PFPO_CONVERT 0x1000000) | |
180 ; PFPO operand types | |
181 (PFPO_OP_TYPE_SF 0x5) | |
182 (PFPO_OP_TYPE_DF 0x6) | |
183 (PFPO_OP_TYPE_TF 0x7) | |
184 (PFPO_OP_TYPE_SD 0x8) | |
185 (PFPO_OP_TYPE_DD 0x9) | |
186 (PFPO_OP_TYPE_TD 0xa) | |
187 ; Bitposition of operand types | |
188 (PFPO_OP0_TYPE_SHIFT 16) | |
189 (PFPO_OP1_TYPE_SHIFT 8) | |
190 ]) | |
191 | |
192 | |
193 ;; Instruction operand type as used in the Principles of Operation. | |
194 ;; Used to determine defaults for length and other attribute values. | |
195 | |
196 (define_attr "op_type" | |
197 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS" | |
198 (const_string "NN")) | |
199 | |
200 ;; Instruction type attribute used for scheduling. | |
201 | |
202 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, | |
203 cs,vs,store,sem,idiv, | |
204 imulhi,imulsi,imuldi, | |
205 branch,jsr,fsimptf,fsimpdf,fsimpsf, | |
206 floadtf,floaddf,floadsf,fstoredf,fstoresf, | |
207 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
208 ftoi,fsqrttf,fsqrtdf,fsqrtsf, | |
209 ftrunctf,ftruncdf, ftruncsd, ftruncdd, | |
210 itoftf, itofdf, itofsf, itofdd, itoftd, | |
211 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
212 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
213 ftoidfp, other" | |
214 (cond [(eq_attr "op_type" "NN") (const_string "other") | |
215 (eq_attr "op_type" "SS") (const_string "cs")] | |
216 (const_string "integer"))) | |
217 | |
218 ;; Another attribute used for scheduling purposes: | |
219 ;; agen: Instruction uses the address generation unit | |
220 ;; reg: Instruction does not use the agen unit | |
221 | |
222 (define_attr "atype" "agen,reg" | |
223 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE") | |
224 (const_string "reg") | |
225 (const_string "agen"))) | |
226 | |
227 ;; Properties concerning Z10 execution grouping and value forwarding. | |
228 ;; z10_super: instruction is superscalar. | |
229 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
230 ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
231 ;; target register. It can forward this value to a second instruction that reads | |
232 ;; the same register if that second instruction is issued in the same group. | |
233 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
234 ;; instruction in the S pipe writes to the register, then the T instruction | |
235 ;; can immediately read the new value. | |
236 ;; z10_fr: union of Z10_fwd and z10_rec. | |
237 ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
238 ;; | |
239 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
240 | |
241 | |
242 (define_attr "z10prop" "none, | |
243 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
244 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
245 z10_rec, | |
246 z10_fr, z10_fr_A3, z10_fr_E1, | |
247 z10_c" | |
248 (const_string "none")) | |
249 | |
250 | |
251 ;; Length in bytes. | |
252 | |
253 (define_attr "length" "" | |
254 (cond [(eq_attr "op_type" "E,RR") (const_int 2) | |
255 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] | |
256 (const_int 6))) | |
257 | |
258 | |
259 ;; Processor type. This attribute must exactly match the processor_type | |
260 ;; enumeration in s390.h. The current machine description does not | |
261 ;; distinguish between g5 and g6, but there are differences between the two | |
262 ;; CPUs could in theory be modeled. | |
263 | |
264 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10" | |
265 (const (symbol_ref "s390_tune"))) | |
266 | |
267 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10" | |
268 (const_string "standard")) | |
269 | |
270 (define_attr "enabled" "" | |
271 (cond [(eq_attr "cpu_facility" "standard") | |
272 (const_int 1) | |
273 | |
274 (and (eq_attr "cpu_facility" "ieee") | |
275 (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0))) | |
276 (const_int 1) | |
277 | |
278 (and (eq_attr "cpu_facility" "zarch") | |
279 (ne (symbol_ref "TARGET_ZARCH") (const_int 0))) | |
280 (const_int 1) | |
281 | |
282 (and (eq_attr "cpu_facility" "longdisp") | |
283 (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0))) | |
284 (const_int 1) | |
285 | |
286 (and (eq_attr "cpu_facility" "extimm") | |
287 (ne (symbol_ref "TARGET_EXTIMM") (const_int 0))) | |
288 (const_int 1) | |
289 | |
290 (and (eq_attr "cpu_facility" "dfp") | |
291 (ne (symbol_ref "TARGET_DFP") (const_int 0))) | |
292 (const_int 1) | |
293 | |
294 (and (eq_attr "cpu_facility" "z10") | |
295 (ne (symbol_ref "TARGET_Z10") (const_int 0))) | |
296 (const_int 1)] | |
297 (const_int 0))) | |
298 | |
299 ;; Pipeline description for z900. For lack of anything better, | |
300 ;; this description is also used for the g5 and g6. | |
301 (include "2064.md") | |
302 | |
303 ;; Pipeline description for z990, z9-109 and z9-ec. | |
304 (include "2084.md") | |
305 | |
306 ;; Pipeline description for z10 | |
307 (include "2097.md") | |
308 | |
309 ;; Predicates | |
310 (include "predicates.md") | |
311 | |
312 ;; Constraint definitions | |
313 (include "constraints.md") | |
314 | |
315 ;; Other includes | |
316 (include "tpf.md") | |
317 | |
318 ;; Iterators | |
319 | |
320 ;; These mode iterators allow floating point patterns to be generated from the | |
321 ;; same template. | |
322 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") | |
323 (SD "TARGET_HARD_DFP")]) | |
324 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) | |
325 (define_mode_iterator FPALL [TF DF SF TD DD SD]) | |
326 (define_mode_iterator BFP [TF DF SF]) | |
327 (define_mode_iterator DFP [TD DD]) | |
328 (define_mode_iterator DFP_ALL [TD DD SD]) | |
329 (define_mode_iterator DSF [DF SF]) | |
330 (define_mode_iterator SD_SF [SF SD]) | |
331 (define_mode_iterator DD_DF [DF DD]) | |
332 (define_mode_iterator TD_TF [TF TD]) | |
333 | |
334 ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated | |
335 ;; from the same template. | |
336 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI]) | |
337 | |
338 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated | |
339 ;; from the same template. | |
340 (define_mode_iterator GPR [(DI "TARGET_64BIT") SI]) | |
341 (define_mode_iterator DSI [DI SI]) | |
342 | |
343 ;; These mode iterators allow :P to be used for patterns that operate on | |
344 ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
345 (define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")]) | |
346 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) | |
347 | |
348 ;; This mode iterator allows the QI and HI patterns to be defined from | |
349 ;; the same template. | |
350 (define_mode_iterator HQI [HI QI]) | |
351 | |
352 ;; This mode iterator allows the integer patterns to be defined from the | |
353 ;; same template. | |
354 (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI]) | |
355 (define_mode_iterator INTALL [TI DI SI HI QI]) | |
356 | |
357 ;; This iterator allows to unify all 'bCOND' expander patterns. | |
358 (define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered | |
359 ordered uneq unlt ungt unle unge ltgt]) | |
360 | |
361 ;; This iterator allows to unify all 'sCOND' patterns. | |
362 (define_code_iterator SCOND [ltu gtu leu geu]) | |
363 | |
364 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from | |
365 ;; the same template. | |
366 (define_code_iterator SHIFT [ashift lshiftrt]) | |
367 | |
368 ;; This iterator and attribute allow to combine most atomic operations. | |
369 (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
370 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") | |
371 (plus "add") (minus "sub") (mult "nand")]) | |
372 | |
373 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in | |
374 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. | |
375 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
376 | |
377 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in | |
378 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
379 ;; SDmode. | |
380 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
381 | |
382 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. | |
383 ;; Likewise for "<RXe>". | |
384 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
385 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
386 | |
387 ;; The decimal floating point variants of add, sub, div and mul support 3 | |
388 ;; fp register operands. The following attributes allow to merge the bfp and | |
389 ;; dfp variants in a single insn definition. | |
390 | |
391 ;; This attribute is used to set op_type accordingly. | |
392 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") | |
393 (DD "RRR") (SD "RRR")]) | |
394 | |
395 ;; This attribute is used in the operand constraint list in order to have the | |
396 ;; first and the second operand match for bfp modes. | |
397 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) | |
398 | |
399 ;; This attribute is used in the operand list of the instruction to have an | |
400 ;; additional operand for the dfp instructions. | |
401 (define_mode_attr op1 [(TF "") (DF "") (SF "") | |
402 (TD "%1,") (DD "%1,") (SD "%1,")]) | |
403 | |
404 | |
405 ;; This attribute is used in the operand constraint list | |
406 ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
407 ;; TFmode values are represented by a fp register pair. Since the | |
408 ;; sign bit instructions only handle single source and target fp registers | |
409 ;; these instructions can only be used for TFmode values if the source and | |
410 ;; target operand uses the same fp register. | |
411 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
412 | |
413 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. | |
414 ;; This is used to disable the memory alternative in TFmode patterns. | |
415 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) | |
416 | |
417 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used | |
418 ;; within instruction mnemonics. | |
419 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
420 | |
421 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp | |
422 ;; modes and to an empty string for bfp modes. | |
423 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
424 | |
425 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode | |
426 ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
427 ;; version only operates on one register. | |
428 (define_mode_attr d0 [(DI "d") (SI "0")]) | |
429 | |
430 ;; In combination with d0 this allows to combine instructions of which the 31bit | |
431 ;; version only operates on one register. The DImode version needs an additional | |
432 ;; register for the assembler output. | |
433 (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
434 | |
435 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
436 ;; 'ashift' and "srdl" in 'lshiftrt'. | |
437 (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
438 | |
439 ;; In SHIFT templates, this attribute holds the correct standard name for the | |
440 ;; pattern itself and the corresponding function calls. | |
441 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) | |
442 | |
443 ;; This attribute handles differences in the instruction 'type' and will result | |
444 ;; in "RRE" for DImode and "RR" for SImode. | |
445 (define_mode_attr E [(DI "E") (SI "")]) | |
446 | |
447 ;; This attribute handles differences in the instruction 'type' and makes RX<Y> | |
448 ;; to result in "RXY" for DImode and "RX" for SImode. | |
449 (define_mode_attr Y [(DI "Y") (SI "")]) | |
450 | |
451 ;; This attribute handles differences in the instruction 'type' and will result | |
452 ;; in "RSE" for TImode and "RS" for DImode. | |
453 (define_mode_attr TE [(TI "E") (DI "")]) | |
454 | |
455 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode | |
456 ;; and "lcr" in SImode. | |
457 (define_mode_attr g [(DI "g") (SI "")]) | |
458 | |
459 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode | |
460 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
461 ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
462 ;; variant for long displacements. | |
463 (define_mode_attr y [(DI "g") (SI "y")]) | |
464 | |
465 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode | |
466 ;; and "cds" in DImode. | |
467 (define_mode_attr tg [(TI "g") (DI "")]) | |
468 | |
469 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode | |
470 ;; and "cfdbr" in SImode. | |
471 (define_mode_attr gf [(DI "g") (SI "f")]) | |
472 | |
473 ;; ICM mask required to load MODE value into the lowest subreg | |
474 ;; of a SImode register. | |
475 (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
476 | |
477 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in | |
478 ;; HImode and "llgc" in QImode. | |
479 (define_mode_attr hc [(HI "h") (QI "c")]) | |
480 | |
481 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" | |
482 ;; in SImode. | |
483 (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
484 | |
485 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is | |
486 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
487 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
488 | |
489 ;; Maximum unsigned integer that fits in MODE. | |
490 (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
491 | |
492 ;; | |
493 ;;- Compare instructions. | |
494 ;; | |
495 | |
496 (define_expand "cmp<mode>" | |
497 [(set (reg:CC CC_REGNUM) | |
498 (compare:CC (match_operand:GPR 0 "register_operand" "") | |
499 (match_operand:GPR 1 "general_operand" "")))] | |
500 "" | |
501 { | |
502 s390_compare_op0 = operands[0]; | |
503 s390_compare_op1 = operands[1]; | |
504 DONE; | |
505 }) | |
506 | |
507 (define_expand "cmp<mode>" | |
508 [(set (reg:CC CC_REGNUM) | |
509 (compare:CC (match_operand:FP 0 "register_operand" "") | |
510 (match_operand:FP 1 "general_operand" "")))] | |
511 "TARGET_HARD_FLOAT" | |
512 { | |
513 s390_compare_op0 = operands[0]; | |
514 s390_compare_op1 = operands[1]; | |
515 DONE; | |
516 }) | |
517 | |
518 | |
519 ; Test-under-Mask instructions | |
520 | |
521 (define_insn "*tmqi_mem" | |
522 [(set (reg CC_REGNUM) | |
523 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") | |
524 (match_operand:QI 1 "immediate_operand" "n,n")) | |
525 (match_operand:QI 2 "immediate_operand" "n,n")))] | |
526 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" | |
527 "@ | |
528 tm\t%S0,%b1 | |
529 tmy\t%S0,%b1" | |
530 [(set_attr "op_type" "SI,SIY") | |
531 (set_attr "z10prop" "z10_super,z10_super")]) | |
532 | |
533 (define_insn "*tmdi_reg" | |
534 [(set (reg CC_REGNUM) | |
535 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") | |
536 (match_operand:DI 1 "immediate_operand" | |
537 "N0HD0,N1HD0,N2HD0,N3HD0")) | |
538 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
539 "TARGET_64BIT | |
540 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) | |
541 && s390_single_part (operands[1], DImode, HImode, 0) >= 0" | |
542 "@ | |
543 tmhh\t%0,%i1 | |
544 tmhl\t%0,%i1 | |
545 tmlh\t%0,%i1 | |
546 tmll\t%0,%i1" | |
547 [(set_attr "op_type" "RI") | |
548 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
549 | |
550 (define_insn "*tmsi_reg" | |
551 [(set (reg CC_REGNUM) | |
552 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") | |
553 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
554 (match_operand:SI 2 "immediate_operand" "n,n")))] | |
555 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) | |
556 && s390_single_part (operands[1], SImode, HImode, 0) >= 0" | |
557 "@ | |
558 tmh\t%0,%i1 | |
559 tml\t%0,%i1" | |
560 [(set_attr "op_type" "RI") | |
561 (set_attr "z10prop" "z10_super,z10_super")]) | |
562 | |
563 (define_insn "*tm<mode>_full" | |
564 [(set (reg CC_REGNUM) | |
565 (compare (match_operand:HQI 0 "register_operand" "d") | |
566 (match_operand:HQI 1 "immediate_operand" "n")))] | |
567 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" | |
568 "tml\t%0,<max_uint>" | |
569 [(set_attr "op_type" "RI") | |
570 (set_attr "z10prop" "z10_super")]) | |
571 | |
572 | |
573 ; | |
574 ; Load-and-Test instructions | |
575 ; | |
576 | |
577 ; tst(di|si) instruction pattern(s). | |
578 | |
579 (define_insn "*tstdi_sign" | |
580 [(set (reg CC_REGNUM) | |
581 (compare | |
582 (ashiftrt:DI | |
583 (ashift:DI | |
584 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
585 (const_int 32)) (const_int 32)) | |
586 (match_operand:DI 1 "const0_operand" ""))) | |
587 (set (match_operand:DI 2 "register_operand" "=d,d") | |
588 (sign_extend:DI (match_dup 0)))] | |
589 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
590 "ltgfr\t%2,%0 | |
591 ltgf\t%2,%0" | |
592 [(set_attr "op_type" "RRE,RXY") | |
593 (set_attr "cpu_facility" "*,z10") | |
594 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
595 | |
596 ; ltr, lt, ltgr, ltg | |
597 (define_insn "*tst<mode>_extimm" | |
598 [(set (reg CC_REGNUM) | |
599 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") | |
600 (match_operand:GPR 1 "const0_operand" ""))) | |
601 (set (match_operand:GPR 2 "register_operand" "=d,d") | |
602 (match_dup 0))] | |
603 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
604 "@ | |
605 lt<g>r\t%2,%0 | |
606 lt<g>\t%2,%0" | |
607 [(set_attr "op_type" "RR<E>,RXY") | |
608 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) | |
609 | |
610 ; ltr, lt, ltgr, ltg | |
611 (define_insn "*tst<mode>_cconly_extimm" | |
612 [(set (reg CC_REGNUM) | |
613 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") | |
614 (match_operand:GPR 1 "const0_operand" ""))) | |
615 (clobber (match_scratch:GPR 2 "=X,d"))] | |
616 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
617 "@ | |
618 lt<g>r\t%0,%0 | |
619 lt<g>\t%2,%0" | |
620 [(set_attr "op_type" "RR<E>,RXY") | |
621 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) | |
622 | |
623 (define_insn "*tstdi" | |
624 [(set (reg CC_REGNUM) | |
625 (compare (match_operand:DI 0 "register_operand" "d") | |
626 (match_operand:DI 1 "const0_operand" ""))) | |
627 (set (match_operand:DI 2 "register_operand" "=d") | |
628 (match_dup 0))] | |
629 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" | |
630 "ltgr\t%2,%0" | |
631 [(set_attr "op_type" "RRE") | |
632 (set_attr "z10prop" "z10_fr_E1")]) | |
633 | |
634 (define_insn "*tstsi" | |
635 [(set (reg CC_REGNUM) | |
636 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") | |
637 (match_operand:SI 1 "const0_operand" ""))) | |
638 (set (match_operand:SI 2 "register_operand" "=d,d,d") | |
639 (match_dup 0))] | |
640 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" | |
641 "@ | |
642 ltr\t%2,%0 | |
643 icm\t%2,15,%S0 | |
644 icmy\t%2,15,%S0" | |
645 [(set_attr "op_type" "RR,RS,RSY") | |
646 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
647 | |
648 (define_insn "*tstsi_cconly" | |
649 [(set (reg CC_REGNUM) | |
650 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") | |
651 (match_operand:SI 1 "const0_operand" ""))) | |
652 (clobber (match_scratch:SI 2 "=X,d,d"))] | |
653 "s390_match_ccmode(insn, CCSmode)" | |
654 "@ | |
655 ltr\t%0,%0 | |
656 icm\t%2,15,%S0 | |
657 icmy\t%2,15,%S0" | |
658 [(set_attr "op_type" "RR,RS,RSY") | |
659 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
660 | |
661 (define_insn "*tstdi_cconly_31" | |
662 [(set (reg CC_REGNUM) | |
663 (compare (match_operand:DI 0 "register_operand" "d") | |
664 (match_operand:DI 1 "const0_operand" "")))] | |
665 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
666 "srda\t%0,0" | |
667 [(set_attr "op_type" "RS") | |
668 (set_attr "atype" "reg")]) | |
669 | |
670 ; ltr, ltgr | |
671 (define_insn "*tst<mode>_cconly2" | |
672 [(set (reg CC_REGNUM) | |
673 (compare (match_operand:GPR 0 "register_operand" "d") | |
674 (match_operand:GPR 1 "const0_operand" "")))] | |
675 "s390_match_ccmode(insn, CCSmode)" | |
676 "lt<g>r\t%0,%0" | |
677 [(set_attr "op_type" "RR<E>") | |
678 (set_attr "z10prop" "z10_fr_E1")]) | |
679 | |
680 ; tst(hi|qi) instruction pattern(s). | |
681 | |
682 (define_insn "*tst<mode>CCT" | |
683 [(set (reg CC_REGNUM) | |
684 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") | |
685 (match_operand:HQI 1 "const0_operand" ""))) | |
686 (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
687 (match_dup 0))] | |
688 "s390_match_ccmode(insn, CCTmode)" | |
689 "@ | |
690 icm\t%2,<icm_lo>,%S0 | |
691 icmy\t%2,<icm_lo>,%S0 | |
692 tml\t%0,<max_uint>" | |
693 [(set_attr "op_type" "RS,RSY,RI") | |
694 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
695 | |
696 (define_insn "*tsthiCCT_cconly" | |
697 [(set (reg CC_REGNUM) | |
698 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") | |
699 (match_operand:HI 1 "const0_operand" ""))) | |
700 (clobber (match_scratch:HI 2 "=d,d,X"))] | |
701 "s390_match_ccmode(insn, CCTmode)" | |
702 "@ | |
703 icm\t%2,3,%S0 | |
704 icmy\t%2,3,%S0 | |
705 tml\t%0,65535" | |
706 [(set_attr "op_type" "RS,RSY,RI") | |
707 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
708 | |
709 (define_insn "*tstqiCCT_cconly" | |
710 [(set (reg CC_REGNUM) | |
711 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") | |
712 (match_operand:QI 1 "const0_operand" "")))] | |
713 "s390_match_ccmode(insn, CCTmode)" | |
714 "@ | |
715 cli\t%S0,0 | |
716 cliy\t%S0,0 | |
717 tml\t%0,255" | |
718 [(set_attr "op_type" "SI,SIY,RI") | |
719 (set_attr "z10prop" "z10_super,z10_super,z10_super")]) | |
720 | |
721 (define_insn "*tst<mode>" | |
722 [(set (reg CC_REGNUM) | |
723 (compare (match_operand:HQI 0 "s_operand" "Q,S") | |
724 (match_operand:HQI 1 "const0_operand" ""))) | |
725 (set (match_operand:HQI 2 "register_operand" "=d,d") | |
726 (match_dup 0))] | |
727 "s390_match_ccmode(insn, CCSmode)" | |
728 "@ | |
729 icm\t%2,<icm_lo>,%S0 | |
730 icmy\t%2,<icm_lo>,%S0" | |
731 [(set_attr "op_type" "RS,RSY") | |
732 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
733 | |
734 (define_insn "*tst<mode>_cconly" | |
735 [(set (reg CC_REGNUM) | |
736 (compare (match_operand:HQI 0 "s_operand" "Q,S") | |
737 (match_operand:HQI 1 "const0_operand" ""))) | |
738 (clobber (match_scratch:HQI 2 "=d,d"))] | |
739 "s390_match_ccmode(insn, CCSmode)" | |
740 "@ | |
741 icm\t%2,<icm_lo>,%S0 | |
742 icmy\t%2,<icm_lo>,%S0" | |
743 [(set_attr "op_type" "RS,RSY") | |
744 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
745 | |
746 | |
747 ; Compare (equality) instructions | |
748 | |
749 (define_insn "*cmpdi_cct" | |
750 [(set (reg CC_REGNUM) | |
751 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") | |
752 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] | |
753 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" | |
754 "@ | |
755 cgr\t%0,%1 | |
756 cghi\t%0,%h1 | |
757 cgfi\t%0,%1 | |
758 cg\t%0,%1 | |
759 #" | |
760 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") | |
761 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
762 | |
763 (define_insn "*cmpsi_cct" | |
764 [(set (reg CC_REGNUM) | |
765 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") | |
766 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
767 "s390_match_ccmode (insn, CCTmode)" | |
768 "@ | |
769 cr\t%0,%1 | |
770 chi\t%0,%h1 | |
771 cfi\t%0,%1 | |
772 c\t%0,%1 | |
773 cy\t%0,%1 | |
774 #" | |
775 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") | |
776 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) | |
777 | |
778 ; Compare (signed) instructions | |
779 | |
780 (define_insn "*cmpdi_ccs_sign" | |
781 [(set (reg CC_REGNUM) | |
782 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" | |
783 "d,RT,b")) | |
784 (match_operand:DI 0 "register_operand" "d, d,d")))] | |
785 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
786 "@ | |
787 cgfr\t%0,%1 | |
788 cgf\t%0,%1 | |
789 cgfrl\t%0,%1" | |
790 [(set_attr "op_type" "RRE,RXY,RIL") | |
791 (set_attr "z10prop" "z10_c,*,*") | |
792 (set_attr "type" "*,*,larl")]) | |
793 | |
794 | |
795 | |
796 (define_insn "*cmpsi_ccs_sign" | |
797 [(set (reg CC_REGNUM) | |
798 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) | |
799 (match_operand:SI 0 "register_operand" "d,d,d")))] | |
800 "s390_match_ccmode(insn, CCSRmode)" | |
801 "@ | |
802 ch\t%0,%1 | |
803 chy\t%0,%1 | |
804 chrl\t%0,%1" | |
805 [(set_attr "op_type" "RX,RXY,RIL") | |
806 (set_attr "cpu_facility" "*,*,z10") | |
807 (set_attr "type" "*,*,larl")]) | |
808 | |
809 (define_insn "*cmphi_ccs_z10" | |
810 [(set (reg CC_REGNUM) | |
811 (compare (match_operand:HI 0 "s_operand" "Q") | |
812 (match_operand:HI 1 "immediate_operand" "K")))] | |
813 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
814 "chhsi\t%0,%1" | |
815 [(set_attr "op_type" "SIL")]) | |
816 | |
817 (define_insn "*cmpdi_ccs_signhi_rl" | |
818 [(set (reg CC_REGNUM) | |
819 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
820 (match_operand:GPR 0 "register_operand" "d,d")))] | |
821 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
822 "@ | |
823 cgh\t%0,%1 | |
824 cghrl\t%0,%1" | |
825 [(set_attr "op_type" "RXY,RIL") | |
826 (set_attr "type" "*,larl")]) | |
827 | |
828 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl | |
829 (define_insn "*cmp<mode>_ccs" | |
830 [(set (reg CC_REGNUM) | |
831 (compare (match_operand:GPR 0 "nonimmediate_operand" | |
832 "d,d,Q, d,d,d,d") | |
833 (match_operand:GPR 1 "general_operand" | |
834 "d,K,K,Os,R,T,b")))] | |
835 "s390_match_ccmode(insn, CCSmode)" | |
836 "@ | |
837 c<g>r\t%0,%1 | |
838 c<g>hi\t%0,%h1 | |
839 c<g>hsi\t%0,%h1 | |
840 c<g>fi\t%0,%1 | |
841 c<g>\t%0,%1 | |
842 c<y>\t%0,%1 | |
843 c<g>rl\t%0,%1" | |
844 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
845 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
846 (set_attr "type" "*,*,*,*,*,*,larl") | |
847 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
848 | |
849 | |
850 ; Compare (unsigned) instructions | |
851 | |
852 (define_insn "*cmpsi_ccu_zerohi_rlsi" | |
853 [(set (reg CC_REGNUM) | |
854 (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
855 "larl_operand" "X"))) | |
856 (match_operand:SI 0 "register_operand" "d")))] | |
857 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
858 "clhrl\t%0,%1" | |
859 [(set_attr "op_type" "RIL") | |
860 (set_attr "type" "larl") | |
861 (set_attr "z10prop" "z10_super")]) | |
862 | |
863 ; clhrl, clghrl | |
864 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
865 [(set (reg CC_REGNUM) | |
866 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
867 "larl_operand" "X"))) | |
868 (match_operand:GPR 0 "register_operand" "d")))] | |
869 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
870 "cl<g>hrl\t%0,%1" | |
871 [(set_attr "op_type" "RIL") | |
872 (set_attr "type" "larl") | |
873 (set_attr "z10prop" "z10_super")]) | |
874 | |
875 (define_insn "*cmpdi_ccu_zero" | |
876 [(set (reg CC_REGNUM) | |
877 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" | |
878 "d,RT,b")) | |
879 (match_operand:DI 0 "register_operand" "d, d,d")))] | |
880 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" | |
881 "@ | |
882 clgfr\t%0,%1 | |
883 clgf\t%0,%1 | |
884 clgfrl\t%0,%1" | |
885 [(set_attr "op_type" "RRE,RXY,RIL") | |
886 (set_attr "cpu_facility" "*,*,z10") | |
887 (set_attr "type" "*,*,larl") | |
888 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
889 | |
890 (define_insn "*cmpdi_ccu" | |
891 [(set (reg CC_REGNUM) | |
892 (compare (match_operand:DI 0 "nonimmediate_operand" | |
893 "d, d,d,Q, d, Q,BQ") | |
894 (match_operand:DI 1 "general_operand" | |
895 "d,Op,b,D,RT,BQ,Q")))] | |
896 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" | |
897 "@ | |
898 clgr\t%0,%1 | |
899 clgfi\t%0,%1 | |
900 clgrl\t%0,%1 | |
901 clghsi\t%0,%x1 | |
902 clg\t%0,%1 | |
903 # | |
904 #" | |
905 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") | |
906 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
907 (set_attr "type" "*,*,larl,*,*,*,*") | |
908 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
909 | |
910 (define_insn "*cmpsi_ccu" | |
911 [(set (reg CC_REGNUM) | |
912 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") | |
913 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
914 "s390_match_ccmode (insn, CCUmode)" | |
915 "@ | |
916 clr\t%0,%1 | |
917 clfi\t%0,%o1 | |
918 clrl\t%0,%1 | |
919 clfhsi\t%0,%x1 | |
920 cl\t%0,%1 | |
921 cly\t%0,%1 | |
922 # | |
923 #" | |
924 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") | |
925 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
926 (set_attr "type" "*,*,larl,*,*,*,*,*") | |
927 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
928 | |
929 (define_insn "*cmphi_ccu" | |
930 [(set (reg CC_REGNUM) | |
931 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") | |
932 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
933 "s390_match_ccmode (insn, CCUmode) | |
934 && !register_operand (operands[1], HImode)" | |
935 "@ | |
936 clm\t%0,3,%S1 | |
937 clmy\t%0,3,%S1 | |
938 clhhsi\t%0,%1 | |
939 # | |
940 #" | |
941 [(set_attr "op_type" "RS,RSY,SIL,SS,SS") | |
942 (set_attr "cpu_facility" "*,*,z10,*,*") | |
943 (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
944 | |
945 (define_insn "*cmpqi_ccu" | |
946 [(set (reg CC_REGNUM) | |
947 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") | |
948 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
949 "s390_match_ccmode (insn, CCUmode) | |
950 && !register_operand (operands[1], QImode)" | |
951 "@ | |
952 clm\t%0,1,%S1 | |
953 clmy\t%0,1,%S1 | |
954 cli\t%S0,%b1 | |
955 cliy\t%S0,%b1 | |
956 # | |
957 #" | |
958 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") | |
959 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
960 | |
961 | |
962 ; Block compare (CLC) instruction patterns. | |
963 | |
964 (define_insn "*clc" | |
965 [(set (reg CC_REGNUM) | |
966 (compare (match_operand:BLK 0 "memory_operand" "Q") | |
967 (match_operand:BLK 1 "memory_operand" "Q"))) | |
968 (use (match_operand 2 "const_int_operand" "n"))] | |
969 "s390_match_ccmode (insn, CCUmode) | |
970 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
971 "clc\t%O0(%2,%R0),%S1" | |
972 [(set_attr "op_type" "SS")]) | |
973 | |
974 (define_split | |
975 [(set (reg CC_REGNUM) | |
976 (compare (match_operand 0 "memory_operand" "") | |
977 (match_operand 1 "memory_operand" "")))] | |
978 "reload_completed | |
979 && s390_match_ccmode (insn, CCUmode) | |
980 && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
981 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
982 [(parallel | |
983 [(set (match_dup 0) (match_dup 1)) | |
984 (use (match_dup 2))])] | |
985 { | |
986 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
987 operands[0] = adjust_address (operands[0], BLKmode, 0); | |
988 operands[1] = adjust_address (operands[1], BLKmode, 0); | |
989 | |
990 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
991 operands[0], operands[1]); | |
992 operands[0] = SET_DEST (PATTERN (curr_insn)); | |
993 }) | |
994 | |
995 | |
996 ; (TF|DF|SF|TD|DD|SD) instructions | |
997 | |
998 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr | |
999 (define_insn "*cmp<mode>_ccs_0" | |
1000 [(set (reg CC_REGNUM) | |
1001 (compare (match_operand:FP 0 "register_operand" "f") | |
1002 (match_operand:FP 1 "const0_operand" "")))] | |
1003 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" | |
1004 "lt<xde><bt>r\t%0,%0" | |
1005 [(set_attr "op_type" "RRE") | |
1006 (set_attr "type" "fsimp<mode>")]) | |
1007 | |
1008 ; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr | |
1009 (define_insn "*cmp<mode>_ccs" | |
1010 [(set (reg CC_REGNUM) | |
1011 (compare (match_operand:FP 0 "register_operand" "f,f") | |
1012 (match_operand:FP 1 "general_operand" "f,<Rf>")))] | |
1013 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" | |
1014 "@ | |
1015 c<xde><bt>r\t%0,%1 | |
1016 c<xde>b\t%0,%1" | |
1017 [(set_attr "op_type" "RRE,RXE") | |
1018 (set_attr "type" "fsimp<mode>")]) | |
1019 | |
1020 | |
1021 ; Compare and Branch instructions | |
1022 | |
1023 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1024 ; The following instructions do a complementary access of their second | |
1025 ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1026 (define_insn "*cmp_and_br_signed_<mode>" | |
1027 [(set (pc) | |
1028 (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1029 [(match_operand:GPR 1 "register_operand" "d,d") | |
1030 (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1031 (label_ref (match_operand 3 "" "")) | |
1032 (pc))) | |
1033 (clobber (reg:CC CC_REGNUM))] | |
1034 "TARGET_Z10" | |
1035 { | |
1036 if (get_attr_length (insn) == 6) | |
1037 return which_alternative ? | |
1038 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1039 else | |
1040 return which_alternative ? | |
1041 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1042 } | |
1043 [(set_attr "op_type" "RIE") | |
1044 (set_attr "type" "branch") | |
1045 (set_attr "z10prop" "z10_super_c,z10_super") | |
1046 (set (attr "length") | |
1047 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1048 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1049 ; 10 byte for cgr/jg | |
1050 | |
1051 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1052 ; The following instructions do a complementary access of their second | |
1053 ; operand (z10 only): clrj, clgrj, clr, clgr | |
1054 (define_insn "*cmp_and_br_unsigned_<mode>" | |
1055 [(set (pc) | |
1056 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1057 [(match_operand:GPR 1 "register_operand" "d,d") | |
1058 (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1059 (label_ref (match_operand 3 "" "")) | |
1060 (pc))) | |
1061 (clobber (reg:CC CC_REGNUM))] | |
1062 "TARGET_Z10" | |
1063 { | |
1064 if (get_attr_length (insn) == 6) | |
1065 return which_alternative ? | |
1066 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1067 else | |
1068 return which_alternative ? | |
1069 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1070 } | |
1071 [(set_attr "op_type" "RIE") | |
1072 (set_attr "type" "branch") | |
1073 (set_attr "z10prop" "z10_super_c,z10_super") | |
1074 (set (attr "length") | |
1075 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1076 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1077 ; 10 byte for clgr/jg | |
1078 | |
1079 ;; | |
1080 ;;- Move instructions. | |
1081 ;; | |
1082 | |
1083 ; | |
1084 ; movti instruction pattern(s). | |
1085 ; | |
1086 | |
1087 (define_insn "movti" | |
1088 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o") | |
1089 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))] | |
1090 "TARGET_64BIT" | |
1091 "@ | |
1092 lmg\t%0,%N0,%S1 | |
1093 stmg\t%1,%N1,%S0 | |
1094 # | |
1095 #" | |
1096 [(set_attr "op_type" "RSY,RSY,*,*") | |
1097 (set_attr "type" "lm,stm,*,*")]) | |
1098 | |
1099 (define_split | |
1100 [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1101 (match_operand:TI 1 "general_operand" ""))] | |
1102 "TARGET_64BIT && reload_completed | |
1103 && s390_split_ok_p (operands[0], operands[1], TImode, 0)" | |
1104 [(set (match_dup 2) (match_dup 4)) | |
1105 (set (match_dup 3) (match_dup 5))] | |
1106 { | |
1107 operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1108 operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1109 operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1110 operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1111 }) | |
1112 | |
1113 (define_split | |
1114 [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1115 (match_operand:TI 1 "general_operand" ""))] | |
1116 "TARGET_64BIT && reload_completed | |
1117 && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
1118 [(set (match_dup 2) (match_dup 4)) | |
1119 (set (match_dup 3) (match_dup 5))] | |
1120 { | |
1121 operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1122 operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1123 operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1124 operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1125 }) | |
1126 | |
1127 (define_split | |
1128 [(set (match_operand:TI 0 "register_operand" "") | |
1129 (match_operand:TI 1 "memory_operand" ""))] | |
1130 "TARGET_64BIT && reload_completed | |
1131 && !s_operand (operands[1], VOIDmode)" | |
1132 [(set (match_dup 0) (match_dup 1))] | |
1133 { | |
1134 rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
1135 s390_load_address (addr, XEXP (operands[1], 0)); | |
1136 operands[1] = replace_equiv_address (operands[1], addr); | |
1137 }) | |
1138 | |
1139 | |
1140 ; | |
1141 ; Patterns used for secondary reloads | |
1142 ; | |
1143 | |
1144 ; z10 provides move instructions accepting larl memory operands. | |
1145 ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1146 ; These patterns are also used for unaligned SI and DI accesses. | |
1147 | |
1148 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10" | |
1149 [(parallel [(match_operand:INTALL 0 "memory_operand" "") | |
1150 (match_operand:INTALL 1 "register_operand" "=d") | |
1151 (match_operand:P 2 "register_operand" "=&a")])] | |
1152 "TARGET_Z10" | |
1153 { | |
1154 s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1155 DONE; | |
1156 }) | |
1157 | |
1158 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10" | |
1159 [(parallel [(match_operand:INTALL 0 "register_operand" "=d") | |
1160 (match_operand:INTALL 1 "memory_operand" "") | |
1161 (match_operand:P 2 "register_operand" "=a")])] | |
1162 "TARGET_Z10" | |
1163 { | |
1164 s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1165 DONE; | |
1166 }) | |
1167 | |
1168 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10" | |
1169 [(parallel [(match_operand:FPALL 0 "memory_operand" "") | |
1170 (match_operand:FPALL 1 "register_operand" "=d") | |
1171 (match_operand:P 2 "register_operand" "=&a")])] | |
1172 "TARGET_Z10" | |
1173 { | |
1174 s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1175 DONE; | |
1176 }) | |
1177 | |
1178 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10" | |
1179 [(parallel [(match_operand:FPALL 0 "register_operand" "=d") | |
1180 (match_operand:FPALL 1 "memory_operand" "") | |
1181 (match_operand:P 2 "register_operand" "=a")])] | |
1182 "TARGET_Z10" | |
1183 { | |
1184 s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1185 DONE; | |
1186 }) | |
1187 | |
1188 (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1189 [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1190 (match_operand:P 1 "larl_operand" "") | |
1191 (match_operand:P 2 "register_operand" "=a")])] | |
1192 "TARGET_Z10" | |
1193 { | |
1194 s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1195 DONE; | |
1196 }) | |
1197 | |
1198 ; Handles loading a PLUS (load address) expression | |
1199 | |
1200 (define_expand "reload<mode>_plus" | |
1201 [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1202 (match_operand:P 1 "s390_plus_operand" "") | |
1203 (match_operand:P 2 "register_operand" "=&a")])] | |
1204 "" | |
1205 { | |
1206 s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1207 DONE; | |
1208 }) | |
1209 | |
1210 ; Handles assessing a non-offsetable memory address | |
1211 | |
1212 (define_expand "reload<mode>_nonoffmem_in" | |
1213 [(parallel [(match_operand 0 "register_operand" "") | |
1214 (match_operand 1 "" "") | |
1215 (match_operand:P 2 "register_operand" "=&a")])] | |
1216 "" | |
1217 { | |
1218 gcc_assert (MEM_P (operands[1])); | |
1219 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1220 operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1221 emit_move_insn (operands[0], operands[1]); | |
1222 DONE; | |
1223 }) | |
1224 | |
1225 (define_expand "reload<mode>_nonoffmem_out" | |
1226 [(parallel [(match_operand 0 "" "") | |
1227 (match_operand 1 "register_operand" "") | |
1228 (match_operand:P 2 "register_operand" "=&a")])] | |
1229 "" | |
1230 { | |
1231 gcc_assert (MEM_P (operands[0])); | |
1232 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); | |
1233 operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1234 emit_move_insn (operands[0], operands[1]); | |
1235 DONE; | |
1236 }) | |
1237 | |
1238 (define_expand "reload<mode>_PIC_addr" | |
1239 [(parallel [(match_operand 0 "register_operand" "=d") | |
1240 (match_operand 1 "larl_operand" "") | |
1241 (match_operand:P 2 "register_operand" "=a")])] | |
1242 "" | |
1243 { | |
1244 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); | |
1245 emit_move_insn (operands[0], new_rtx); | |
1246 }) | |
1247 | |
1248 ; | |
1249 ; movdi instruction pattern(s). | |
1250 ; | |
1251 | |
1252 (define_expand "movdi" | |
1253 [(set (match_operand:DI 0 "general_operand" "") | |
1254 (match_operand:DI 1 "general_operand" ""))] | |
1255 "" | |
1256 { | |
1257 /* Handle symbolic constants. */ | |
1258 if (TARGET_64BIT | |
1259 && (SYMBOLIC_CONST (operands[1]) | |
1260 || (GET_CODE (operands[1]) == PLUS | |
1261 && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1262 && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
1263 emit_symbolic_move (operands); | |
1264 }) | |
1265 | |
1266 (define_insn "*movdi_larl" | |
1267 [(set (match_operand:DI 0 "register_operand" "=d") | |
1268 (match_operand:DI 1 "larl_operand" "X"))] | |
1269 "TARGET_64BIT | |
1270 && !FP_REG_P (operands[0])" | |
1271 "larl\t%0,%1" | |
1272 [(set_attr "op_type" "RIL") | |
1273 (set_attr "type" "larl") | |
1274 (set_attr "z10prop" "z10_super_A1")]) | |
1275 | |
1276 (define_insn "*movdi_64" | |
1277 [(set (match_operand:DI 0 "nonimmediate_operand" | |
1278 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d, | |
1279 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t") | |
1280 (match_operand:DI 1 "general_operand" | |
1281 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, | |
1282 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))] | |
1283 "TARGET_64BIT" | |
1284 "@ | |
1285 lghi\t%0,%h1 | |
1286 llihh\t%0,%i1 | |
1287 llihl\t%0,%i1 | |
1288 llilh\t%0,%i1 | |
1289 llill\t%0,%i1 | |
1290 lgfi\t%0,%1 | |
1291 llihf\t%0,%k1 | |
1292 llilf\t%0,%k1 | |
1293 ldgr\t%0,%1 | |
1294 lgdr\t%0,%1 | |
1295 lay\t%0,%a1 | |
1296 lgrl\t%0,%1 | |
1297 lgr\t%0,%1 | |
1298 lg\t%0,%1 | |
1299 stg\t%1,%0 | |
1300 ldr\t%0,%1 | |
1301 ld\t%0,%1 | |
1302 ldy\t%0,%1 | |
1303 std\t%1,%0 | |
1304 stdy\t%1,%0 | |
1305 stgrl\t%1,%0 | |
1306 mvghi\t%0,%1 | |
1307 # | |
1308 # | |
1309 stam\t%1,%N1,%S0 | |
1310 lam\t%0,%N0,%S1" | |
1311 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, | |
1312 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS") | |
1313 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, | |
1314 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*, | |
1315 *,*") | |
1316 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, | |
1317 z10,*,*,*,*,*,longdisp,*,longdisp, | |
1318 z10,z10,*,*,*,*") | |
1319 (set_attr "z10prop" "z10_fwd_A1, | |
1320 z10_fwd_E1, | |
1321 z10_fwd_E1, | |
1322 z10_fwd_E1, | |
1323 z10_fwd_E1, | |
1324 z10_fwd_A1, | |
1325 z10_fwd_E1, | |
1326 z10_fwd_E1, | |
1327 *, | |
1328 *, | |
1329 z10_fwd_A1, | |
1330 z10_fwd_A3, | |
1331 z10_fr_E1, | |
1332 z10_fwd_A3, | |
1333 z10_rec, | |
1334 *, | |
1335 *, | |
1336 *, | |
1337 *, | |
1338 *, | |
1339 z10_rec, | |
1340 z10_super, | |
1341 *, | |
1342 *, | |
1343 *, | |
1344 *") | |
1345 ]) | |
1346 | |
1347 (define_split | |
1348 [(set (match_operand:DI 0 "register_operand" "") | |
1349 (match_operand:DI 1 "register_operand" ""))] | |
1350 "TARGET_64BIT && ACCESS_REG_P (operands[1])" | |
1351 [(set (match_dup 2) (match_dup 3)) | |
1352 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1353 (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1354 "operands[2] = gen_lowpart (SImode, operands[0]); | |
1355 s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1356 | |
1357 (define_split | |
1358 [(set (match_operand:DI 0 "register_operand" "") | |
1359 (match_operand:DI 1 "register_operand" ""))] | |
1360 "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1361 && dead_or_set_p (insn, operands[1])" | |
1362 [(set (match_dup 3) (match_dup 2)) | |
1363 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1364 (set (match_dup 4) (match_dup 2))] | |
1365 "operands[2] = gen_lowpart (SImode, operands[1]); | |
1366 s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1367 | |
1368 (define_split | |
1369 [(set (match_operand:DI 0 "register_operand" "") | |
1370 (match_operand:DI 1 "register_operand" ""))] | |
1371 "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1372 && !dead_or_set_p (insn, operands[1])" | |
1373 [(set (match_dup 3) (match_dup 2)) | |
1374 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1375 (set (match_dup 4) (match_dup 2)) | |
1376 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1377 "operands[2] = gen_lowpart (SImode, operands[1]); | |
1378 s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1379 | |
1380 (define_insn "*movdi_31" | |
1381 [(set (match_operand:DI 0 "nonimmediate_operand" | |
1382 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") | |
1383 (match_operand:DI 1 "general_operand" | |
1384 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] | |
1385 "!TARGET_64BIT" | |
1386 "@ | |
1387 lm\t%0,%N0,%S1 | |
1388 lmy\t%0,%N0,%S1 | |
1389 stm\t%1,%N1,%S0 | |
1390 stmy\t%1,%N1,%S0 | |
1391 # | |
1392 # | |
1393 ldr\t%0,%1 | |
1394 ld\t%0,%1 | |
1395 ldy\t%0,%1 | |
1396 std\t%1,%0 | |
1397 stdy\t%1,%0 | |
1398 #" | |
1399 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") | |
1400 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1401 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
1402 | |
1403 ; For a load from a symbol ref we can use one of the target registers | |
1404 ; together with larl to load the address. | |
1405 (define_split | |
1406 [(set (match_operand:DI 0 "register_operand" "") | |
1407 (match_operand:DI 1 "memory_operand" ""))] | |
1408 "!TARGET_64BIT && reload_completed && TARGET_Z10 | |
1409 && larl_operand (XEXP (operands[1], 0), SImode)" | |
1410 [(set (match_dup 2) (match_dup 3)) | |
1411 (set (match_dup 0) (match_dup 1))] | |
1412 { | |
1413 operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1414 operands[3] = XEXP (operands[1], 0); | |
1415 operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1416 }) | |
1417 | |
1418 (define_split | |
1419 [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1420 (match_operand:DI 1 "general_operand" ""))] | |
1421 "!TARGET_64BIT && reload_completed | |
1422 && s390_split_ok_p (operands[0], operands[1], DImode, 0)" | |
1423 [(set (match_dup 2) (match_dup 4)) | |
1424 (set (match_dup 3) (match_dup 5))] | |
1425 { | |
1426 operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
1427 operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1428 operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1429 operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1430 }) | |
1431 | |
1432 (define_split | |
1433 [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1434 (match_operand:DI 1 "general_operand" ""))] | |
1435 "!TARGET_64BIT && reload_completed | |
1436 && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
1437 [(set (match_dup 2) (match_dup 4)) | |
1438 (set (match_dup 3) (match_dup 5))] | |
1439 { | |
1440 operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1441 operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1442 operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1443 operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1444 }) | |
1445 | |
1446 (define_split | |
1447 [(set (match_operand:DI 0 "register_operand" "") | |
1448 (match_operand:DI 1 "memory_operand" ""))] | |
1449 "!TARGET_64BIT && reload_completed | |
1450 && !FP_REG_P (operands[0]) | |
1451 && !s_operand (operands[1], VOIDmode)" | |
1452 [(set (match_dup 0) (match_dup 1))] | |
1453 { | |
1454 rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1455 s390_load_address (addr, XEXP (operands[1], 0)); | |
1456 operands[1] = replace_equiv_address (operands[1], addr); | |
1457 }) | |
1458 | |
1459 (define_peephole2 | |
1460 [(set (match_operand:DI 0 "register_operand" "") | |
1461 (mem:DI (match_operand 1 "address_operand" "")))] | |
1462 "TARGET_64BIT | |
1463 && !FP_REG_P (operands[0]) | |
1464 && GET_CODE (operands[1]) == SYMBOL_REF | |
1465 && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1466 && get_pool_mode (operands[1]) == DImode | |
1467 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1468 [(set (match_dup 0) (match_dup 2))] | |
1469 "operands[2] = get_pool_constant (operands[1]);") | |
1470 | |
1471 (define_insn "*la_64" | |
1472 [(set (match_operand:DI 0 "register_operand" "=d,d") | |
1473 (match_operand:QI 1 "address_operand" "U,W"))] | |
1474 "TARGET_64BIT" | |
1475 "@ | |
1476 la\t%0,%a1 | |
1477 lay\t%0,%a1" | |
1478 [(set_attr "op_type" "RX,RXY") | |
1479 (set_attr "type" "la") | |
1480 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
1481 | |
1482 (define_peephole2 | |
1483 [(parallel | |
1484 [(set (match_operand:DI 0 "register_operand" "") | |
1485 (match_operand:QI 1 "address_operand" "")) | |
1486 (clobber (reg:CC CC_REGNUM))])] | |
1487 "TARGET_64BIT | |
1488 && preferred_la_operand_p (operands[1], const0_rtx)" | |
1489 [(set (match_dup 0) (match_dup 1))] | |
1490 "") | |
1491 | |
1492 (define_peephole2 | |
1493 [(set (match_operand:DI 0 "register_operand" "") | |
1494 (match_operand:DI 1 "register_operand" "")) | |
1495 (parallel | |
1496 [(set (match_dup 0) | |
1497 (plus:DI (match_dup 0) | |
1498 (match_operand:DI 2 "nonmemory_operand" ""))) | |
1499 (clobber (reg:CC CC_REGNUM))])] | |
1500 "TARGET_64BIT | |
1501 && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
1502 && preferred_la_operand_p (operands[1], operands[2])" | |
1503 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] | |
1504 "") | |
1505 | |
1506 ; | |
1507 ; movsi instruction pattern(s). | |
1508 ; | |
1509 | |
1510 (define_expand "movsi" | |
1511 [(set (match_operand:SI 0 "general_operand" "") | |
1512 (match_operand:SI 1 "general_operand" ""))] | |
1513 "" | |
1514 { | |
1515 /* Handle symbolic constants. */ | |
1516 if (!TARGET_64BIT | |
1517 && (SYMBOLIC_CONST (operands[1]) | |
1518 || (GET_CODE (operands[1]) == PLUS | |
1519 && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1520 && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
1521 emit_symbolic_move (operands); | |
1522 }) | |
1523 | |
1524 (define_insn "*movsi_larl" | |
1525 [(set (match_operand:SI 0 "register_operand" "=d") | |
1526 (match_operand:SI 1 "larl_operand" "X"))] | |
1527 "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1528 && !FP_REG_P (operands[0])" | |
1529 "larl\t%0,%1" | |
1530 [(set_attr "op_type" "RIL") | |
1531 (set_attr "type" "larl") | |
1532 (set_attr "z10prop" "z10_fwd_A1")]) | |
1533 | |
1534 (define_insn "*movsi_zarch" | |
1535 [(set (match_operand:SI 0 "nonimmediate_operand" | |
1536 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t") | |
1537 (match_operand:SI 1 "general_operand" | |
1538 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))] | |
1539 "TARGET_ZARCH" | |
1540 "@ | |
1541 lhi\t%0,%h1 | |
1542 llilh\t%0,%i1 | |
1543 llill\t%0,%i1 | |
1544 iilf\t%0,%o1 | |
1545 lay\t%0,%a1 | |
1546 lrl\t%0,%1 | |
1547 lr\t%0,%1 | |
1548 l\t%0,%1 | |
1549 ly\t%0,%1 | |
1550 st\t%1,%0 | |
1551 sty\t%1,%0 | |
1552 ler\t%0,%1 | |
1553 le\t%0,%1 | |
1554 ley\t%0,%1 | |
1555 ste\t%1,%0 | |
1556 stey\t%1,%0 | |
1557 ear\t%0,%1 | |
1558 sar\t%0,%1 | |
1559 stam\t%1,%1,%S0 | |
1560 strl\t%1,%0 | |
1561 mvhi\t%0,%1 | |
1562 lam\t%0,%0,%S1" | |
1563 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, | |
1564 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS") | |
1565 (set_attr "type" "*, | |
1566 *, | |
1567 *, | |
1568 *, | |
1569 la, | |
1570 larl, | |
1571 lr, | |
1572 load, | |
1573 load, | |
1574 store, | |
1575 store, | |
1576 floadsf, | |
1577 floadsf, | |
1578 floadsf, | |
1579 fstoresf, | |
1580 fstoresf, | |
1581 *, | |
1582 *, | |
1583 *, | |
1584 larl, | |
1585 *, | |
1586 *") | |
1587 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, | |
1588 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*") | |
1589 (set_attr "z10prop" "z10_fwd_A1, | |
1590 z10_fwd_E1, | |
1591 z10_fwd_E1, | |
1592 z10_fwd_A1, | |
1593 z10_fwd_A1, | |
1594 z10_fwd_A3, | |
1595 z10_fr_E1, | |
1596 z10_fwd_A3, | |
1597 z10_fwd_A3, | |
1598 z10_rec, | |
1599 z10_rec, | |
1600 *, | |
1601 *, | |
1602 *, | |
1603 *, | |
1604 *, | |
1605 z10_super_E1, | |
1606 z10_super, | |
1607 *, | |
1608 z10_rec, | |
1609 z10_super, | |
1610 *")]) | |
1611 | |
1612 (define_insn "*movsi_esa" | |
1613 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t") | |
1614 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))] | |
1615 "!TARGET_ZARCH" | |
1616 "@ | |
1617 lhi\t%0,%h1 | |
1618 lr\t%0,%1 | |
1619 l\t%0,%1 | |
1620 st\t%1,%0 | |
1621 ler\t%0,%1 | |
1622 le\t%0,%1 | |
1623 ste\t%1,%0 | |
1624 ear\t%0,%1 | |
1625 sar\t%0,%1 | |
1626 stam\t%1,%1,%S0 | |
1627 lam\t%0,%0,%S1" | |
1628 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS") | |
1629 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*") | |
1630 (set_attr "z10prop" "z10_fwd_A1, | |
1631 z10_fr_E1, | |
1632 z10_fwd_A3, | |
1633 z10_rec, | |
1634 *, | |
1635 *, | |
1636 *, | |
1637 z10_super_E1, | |
1638 z10_super, | |
1639 *, | |
1640 *") | |
1641 ]) | |
1642 | |
1643 (define_peephole2 | |
1644 [(set (match_operand:SI 0 "register_operand" "") | |
1645 (mem:SI (match_operand 1 "address_operand" "")))] | |
1646 "!FP_REG_P (operands[0]) | |
1647 && GET_CODE (operands[1]) == SYMBOL_REF | |
1648 && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1649 && get_pool_mode (operands[1]) == SImode | |
1650 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1651 [(set (match_dup 0) (match_dup 2))] | |
1652 "operands[2] = get_pool_constant (operands[1]);") | |
1653 | |
1654 (define_insn "*la_31" | |
1655 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1656 (match_operand:QI 1 "address_operand" "U,W"))] | |
1657 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
1658 "@ | |
1659 la\t%0,%a1 | |
1660 lay\t%0,%a1" | |
1661 [(set_attr "op_type" "RX,RXY") | |
1662 (set_attr "type" "la") | |
1663 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
1664 | |
1665 (define_peephole2 | |
1666 [(parallel | |
1667 [(set (match_operand:SI 0 "register_operand" "") | |
1668 (match_operand:QI 1 "address_operand" "")) | |
1669 (clobber (reg:CC CC_REGNUM))])] | |
1670 "!TARGET_64BIT | |
1671 && preferred_la_operand_p (operands[1], const0_rtx)" | |
1672 [(set (match_dup 0) (match_dup 1))] | |
1673 "") | |
1674 | |
1675 (define_peephole2 | |
1676 [(set (match_operand:SI 0 "register_operand" "") | |
1677 (match_operand:SI 1 "register_operand" "")) | |
1678 (parallel | |
1679 [(set (match_dup 0) | |
1680 (plus:SI (match_dup 0) | |
1681 (match_operand:SI 2 "nonmemory_operand" ""))) | |
1682 (clobber (reg:CC CC_REGNUM))])] | |
1683 "!TARGET_64BIT | |
1684 && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
1685 && preferred_la_operand_p (operands[1], operands[2])" | |
1686 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] | |
1687 "") | |
1688 | |
1689 (define_insn "*la_31_and" | |
1690 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1691 (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
1692 (const_int 2147483647)))] | |
1693 "!TARGET_64BIT" | |
1694 "@ | |
1695 la\t%0,%a1 | |
1696 lay\t%0,%a1" | |
1697 [(set_attr "op_type" "RX,RXY") | |
1698 (set_attr "type" "la") | |
1699 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
1700 | |
1701 (define_insn_and_split "*la_31_and_cc" | |
1702 [(set (match_operand:SI 0 "register_operand" "=d") | |
1703 (and:SI (match_operand:QI 1 "address_operand" "p") | |
1704 (const_int 2147483647))) | |
1705 (clobber (reg:CC CC_REGNUM))] | |
1706 "!TARGET_64BIT" | |
1707 "#" | |
1708 "&& reload_completed" | |
1709 [(set (match_dup 0) | |
1710 (and:SI (match_dup 1) (const_int 2147483647)))] | |
1711 "" | |
1712 [(set_attr "op_type" "RX") | |
1713 (set_attr "type" "la")]) | |
1714 | |
1715 (define_insn "force_la_31" | |
1716 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1717 (match_operand:QI 1 "address_operand" "U,W")) | |
1718 (use (const_int 0))] | |
1719 "!TARGET_64BIT" | |
1720 "@ | |
1721 la\t%0,%a1 | |
1722 lay\t%0,%a1" | |
1723 [(set_attr "op_type" "RX") | |
1724 (set_attr "type" "la") | |
1725 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
1726 | |
1727 ; | |
1728 ; movhi instruction pattern(s). | |
1729 ; | |
1730 | |
1731 (define_expand "movhi" | |
1732 [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1733 (match_operand:HI 1 "general_operand" ""))] | |
1734 "" | |
1735 { | |
1736 /* Make it explicit that loading a register from memory | |
1737 always sign-extends (at least) to SImode. */ | |
1738 if (optimize && can_create_pseudo_p () | |
1739 && register_operand (operands[0], VOIDmode) | |
1740 && GET_CODE (operands[1]) == MEM) | |
1741 { | |
1742 rtx tmp = gen_reg_rtx (SImode); | |
1743 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1744 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1745 operands[1] = gen_lowpart (HImode, tmp); | |
1746 } | |
1747 }) | |
1748 | |
1749 (define_insn "*movhi" | |
1750 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q") | |
1751 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))] | |
1752 "" | |
1753 "@ | |
1754 lr\t%0,%1 | |
1755 lhi\t%0,%h1 | |
1756 lh\t%0,%1 | |
1757 lhy\t%0,%1 | |
1758 lhrl\t%0,%1 | |
1759 sth\t%1,%0 | |
1760 sthy\t%1,%0 | |
1761 sthrl\t%1,%0 | |
1762 mvhhi\t%0,%1" | |
1763 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL") | |
1764 (set_attr "type" "lr,*,*,*,larl,store,store,store,*") | |
1765 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10") | |
1766 (set_attr "z10prop" "z10_fr_E1, | |
1767 z10_fwd_A1, | |
1768 z10_super_E1, | |
1769 z10_super_E1, | |
1770 z10_super_E1, | |
1771 z10_rec, | |
1772 z10_rec, | |
1773 z10_rec, | |
1774 z10_super")]) | |
1775 | |
1776 (define_peephole2 | |
1777 [(set (match_operand:HI 0 "register_operand" "") | |
1778 (mem:HI (match_operand 1 "address_operand" "")))] | |
1779 "GET_CODE (operands[1]) == SYMBOL_REF | |
1780 && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1781 && get_pool_mode (operands[1]) == HImode | |
1782 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1783 [(set (match_dup 0) (match_dup 2))] | |
1784 "operands[2] = get_pool_constant (operands[1]);") | |
1785 | |
1786 ; | |
1787 ; movqi instruction pattern(s). | |
1788 ; | |
1789 | |
1790 (define_expand "movqi" | |
1791 [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1792 (match_operand:QI 1 "general_operand" ""))] | |
1793 "" | |
1794 { | |
1795 /* On z/Architecture, zero-extending from memory to register | |
1796 is just as fast as a QImode load. */ | |
1797 if (TARGET_ZARCH && optimize && can_create_pseudo_p () | |
1798 && register_operand (operands[0], VOIDmode) | |
1799 && GET_CODE (operands[1]) == MEM) | |
1800 { | |
1801 rtx tmp = gen_reg_rtx (word_mode); | |
1802 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
1803 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1804 operands[1] = gen_lowpart (QImode, tmp); | |
1805 } | |
1806 }) | |
1807 | |
1808 (define_insn "*movqi" | |
1809 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S") | |
1810 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))] | |
1811 "" | |
1812 "@ | |
1813 lr\t%0,%1 | |
1814 lhi\t%0,%b1 | |
1815 ic\t%0,%1 | |
1816 icy\t%0,%1 | |
1817 stc\t%1,%0 | |
1818 stcy\t%1,%0 | |
1819 mvi\t%S0,%b1 | |
1820 mviy\t%S0,%b1" | |
1821 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY") | |
1822 (set_attr "type" "lr,*,*,*,store,store,store,store") | |
1823 (set_attr "z10prop" "z10_fr_E1, | |
1824 z10_fwd_A1, | |
1825 z10_super_E1, | |
1826 z10_super_E1, | |
1827 z10_rec, | |
1828 z10_rec, | |
1829 z10_super, | |
1830 z10_super")]) | |
1831 | |
1832 (define_peephole2 | |
1833 [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1834 (mem:QI (match_operand 1 "address_operand" "")))] | |
1835 "GET_CODE (operands[1]) == SYMBOL_REF | |
1836 && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1837 && get_pool_mode (operands[1]) == QImode | |
1838 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1839 [(set (match_dup 0) (match_dup 2))] | |
1840 "operands[2] = get_pool_constant (operands[1]);") | |
1841 | |
1842 ; | |
1843 ; movstrictqi instruction pattern(s). | |
1844 ; | |
1845 | |
1846 (define_insn "*movstrictqi" | |
1847 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) | |
1848 (match_operand:QI 1 "memory_operand" "R,T"))] | |
1849 "" | |
1850 "@ | |
1851 ic\t%0,%1 | |
1852 icy\t%0,%1" | |
1853 [(set_attr "op_type" "RX,RXY") | |
1854 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
1855 | |
1856 ; | |
1857 ; movstricthi instruction pattern(s). | |
1858 ; | |
1859 | |
1860 (define_insn "*movstricthi" | |
1861 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) | |
1862 (match_operand:HI 1 "memory_operand" "Q,S")) | |
1863 (clobber (reg:CC CC_REGNUM))] | |
1864 "" | |
1865 "@ | |
1866 icm\t%0,3,%S1 | |
1867 icmy\t%0,3,%S1" | |
1868 [(set_attr "op_type" "RS,RSY") | |
1869 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
1870 | |
1871 ; | |
1872 ; movstrictsi instruction pattern(s). | |
1873 ; | |
1874 | |
1875 (define_insn "movstrictsi" | |
1876 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) | |
1877 (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
1878 "TARGET_64BIT" | |
1879 "@ | |
1880 lr\t%0,%1 | |
1881 l\t%0,%1 | |
1882 ly\t%0,%1 | |
1883 ear\t%0,%1" | |
1884 [(set_attr "op_type" "RR,RX,RXY,RRE") | |
1885 (set_attr "type" "lr,load,load,*") | |
1886 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
1887 | |
1888 ; | |
1889 ; mov(tf|td) instruction pattern(s). | |
1890 ; | |
1891 | |
1892 (define_expand "mov<mode>" | |
1893 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
1894 (match_operand:TD_TF 1 "general_operand" ""))] | |
1895 "" | |
1896 "") | |
1897 | |
1898 (define_insn "*mov<mode>_64" | |
1899 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") | |
1900 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
1901 "TARGET_64BIT" | |
1902 "@ | |
1903 lzxr\t%0 | |
1904 lxr\t%0,%1 | |
1905 # | |
1906 # | |
1907 lmg\t%0,%N0,%S1 | |
1908 stmg\t%1,%N1,%S0 | |
1909 # | |
1910 #" | |
1911 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") | |
1912 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")]) | |
1913 | |
1914 (define_insn "*mov<mode>_31" | |
1915 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") | |
1916 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
1917 "!TARGET_64BIT" | |
1918 "@ | |
1919 lzxr\t%0 | |
1920 lxr\t%0,%1 | |
1921 # | |
1922 #" | |
1923 [(set_attr "op_type" "RRE,RRE,*,*") | |
1924 (set_attr "type" "fsimptf,fsimptf,*,*")]) | |
1925 | |
1926 ; TFmode in GPRs splitters | |
1927 | |
1928 (define_split | |
1929 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
1930 (match_operand:TD_TF 1 "general_operand" ""))] | |
1931 "TARGET_64BIT && reload_completed | |
1932 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" | |
1933 [(set (match_dup 2) (match_dup 4)) | |
1934 (set (match_dup 3) (match_dup 5))] | |
1935 { | |
1936 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
1937 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
1938 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
1939 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
1940 }) | |
1941 | |
1942 (define_split | |
1943 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
1944 (match_operand:TD_TF 1 "general_operand" ""))] | |
1945 "TARGET_64BIT && reload_completed | |
1946 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" | |
1947 [(set (match_dup 2) (match_dup 4)) | |
1948 (set (match_dup 3) (match_dup 5))] | |
1949 { | |
1950 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
1951 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
1952 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
1953 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
1954 }) | |
1955 | |
1956 (define_split | |
1957 [(set (match_operand:TD_TF 0 "register_operand" "") | |
1958 (match_operand:TD_TF 1 "memory_operand" ""))] | |
1959 "TARGET_64BIT && reload_completed | |
1960 && !FP_REG_P (operands[0]) | |
1961 && !s_operand (operands[1], VOIDmode)" | |
1962 [(set (match_dup 0) (match_dup 1))] | |
1963 { | |
1964 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); | |
1965 s390_load_address (addr, XEXP (operands[1], 0)); | |
1966 operands[1] = replace_equiv_address (operands[1], addr); | |
1967 }) | |
1968 | |
1969 ; TFmode in BFPs splitters | |
1970 | |
1971 (define_split | |
1972 [(set (match_operand:TD_TF 0 "register_operand" "") | |
1973 (match_operand:TD_TF 1 "memory_operand" ""))] | |
1974 "reload_completed && offsettable_memref_p (operands[1]) | |
1975 && FP_REG_P (operands[0])" | |
1976 [(set (match_dup 2) (match_dup 4)) | |
1977 (set (match_dup 3) (match_dup 5))] | |
1978 { | |
1979 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
1980 <MODE>mode, 0); | |
1981 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
1982 <MODE>mode, 8); | |
1983 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
1984 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
1985 }) | |
1986 | |
1987 (define_split | |
1988 [(set (match_operand:TD_TF 0 "memory_operand" "") | |
1989 (match_operand:TD_TF 1 "register_operand" ""))] | |
1990 "reload_completed && offsettable_memref_p (operands[0]) | |
1991 && FP_REG_P (operands[1])" | |
1992 [(set (match_dup 2) (match_dup 4)) | |
1993 (set (match_dup 3) (match_dup 5))] | |
1994 { | |
1995 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); | |
1996 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
1997 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
1998 <MODE>mode, 0); | |
1999 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2000 <MODE>mode, 8); | |
2001 }) | |
2002 | |
2003 ; | |
2004 ; mov(df|dd) instruction pattern(s). | |
2005 ; | |
2006 | |
2007 (define_expand "mov<mode>" | |
2008 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2009 (match_operand:DD_DF 1 "general_operand" ""))] | |
2010 "" | |
2011 "") | |
2012 | |
2013 (define_insn "*mov<mode>_64dfp" | |
2014 [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
2015 "=f,f,f,d,f,f,R,T,d, d,RT") | |
2016 (match_operand:DD_DF 1 "general_operand" | |
2017 " G,f,d,f,R,T,f,f,d,RT, d"))] | |
2018 "TARGET_64BIT && TARGET_DFP" | |
2019 "@ | |
2020 lzdr\t%0 | |
2021 ldr\t%0,%1 | |
2022 ldgr\t%0,%1 | |
2023 lgdr\t%0,%1 | |
2024 ld\t%0,%1 | |
2025 ldy\t%0,%1 | |
2026 std\t%1,%0 | |
2027 stdy\t%1,%0 | |
2028 lgr\t%0,%1 | |
2029 lg\t%0,%1 | |
2030 stg\t%1,%0" | |
2031 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY") | |
2032 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, | |
2033 fstoredf,fstoredf,lr,load,store") | |
2034 (set_attr "z10prop" "*, | |
2035 *, | |
2036 *, | |
2037 *, | |
2038 *, | |
2039 *, | |
2040 *, | |
2041 *, | |
2042 z10_fr_E1, | |
2043 z10_fwd_A3, | |
2044 z10_rec") | |
2045 ]) | |
2046 | |
2047 (define_insn "*mov<mode>_64" | |
2048 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT") | |
2049 (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))] | |
2050 "TARGET_64BIT" | |
2051 "@ | |
2052 lzdr\t%0 | |
2053 ldr\t%0,%1 | |
2054 ld\t%0,%1 | |
2055 ldy\t%0,%1 | |
2056 std\t%1,%0 | |
2057 stdy\t%1,%0 | |
2058 lgr\t%0,%1 | |
2059 lg\t%0,%1 | |
2060 stg\t%1,%0" | |
2061 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY") | |
2062 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, | |
2063 fstore<mode>,fstore<mode>,lr,load,store") | |
2064 (set_attr "z10prop" "*, | |
2065 *, | |
2066 *, | |
2067 *, | |
2068 *, | |
2069 *, | |
2070 z10_fr_E1, | |
2071 z10_fwd_A3, | |
2072 z10_rec")]) | |
2073 | |
2074 (define_insn "*mov<mode>_31" | |
2075 [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
2076 "=f,f,f,f,R,T,d,d,Q,S, d,o") | |
2077 (match_operand:DD_DF 1 "general_operand" | |
2078 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] | |
2079 "!TARGET_64BIT" | |
2080 "@ | |
2081 lzdr\t%0 | |
2082 ldr\t%0,%1 | |
2083 ld\t%0,%1 | |
2084 ldy\t%0,%1 | |
2085 std\t%1,%0 | |
2086 stdy\t%1,%0 | |
2087 lm\t%0,%N0,%S1 | |
2088 lmy\t%0,%N0,%S1 | |
2089 stm\t%1,%N1,%S0 | |
2090 stmy\t%1,%N1,%S0 | |
2091 # | |
2092 #" | |
2093 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") | |
2094 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, | |
2095 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")]) | |
2096 | |
2097 (define_split | |
2098 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2099 (match_operand:DD_DF 1 "general_operand" ""))] | |
2100 "!TARGET_64BIT && reload_completed | |
2101 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" | |
2102 [(set (match_dup 2) (match_dup 4)) | |
2103 (set (match_dup 3) (match_dup 5))] | |
2104 { | |
2105 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2106 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2107 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2108 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2109 }) | |
2110 | |
2111 (define_split | |
2112 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2113 (match_operand:DD_DF 1 "general_operand" ""))] | |
2114 "!TARGET_64BIT && reload_completed | |
2115 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" | |
2116 [(set (match_dup 2) (match_dup 4)) | |
2117 (set (match_dup 3) (match_dup 5))] | |
2118 { | |
2119 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2120 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2121 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2122 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2123 }) | |
2124 | |
2125 (define_split | |
2126 [(set (match_operand:DD_DF 0 "register_operand" "") | |
2127 (match_operand:DD_DF 1 "memory_operand" ""))] | |
2128 "!TARGET_64BIT && reload_completed | |
2129 && !FP_REG_P (operands[0]) | |
2130 && !s_operand (operands[1], VOIDmode)" | |
2131 [(set (match_dup 0) (match_dup 1))] | |
2132 { | |
2133 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2134 s390_load_address (addr, XEXP (operands[1], 0)); | |
2135 operands[1] = replace_equiv_address (operands[1], addr); | |
2136 }) | |
2137 | |
2138 ; | |
2139 ; mov(sf|sd) instruction pattern(s). | |
2140 ; | |
2141 | |
2142 (define_insn "mov<mode>" | |
2143 [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
2144 "=f,f,f,f,R,T,d,d,d,R,T") | |
2145 (match_operand:SD_SF 1 "general_operand" | |
2146 " G,f,R,T,f,f,d,R,T,d,d"))] | |
2147 "" | |
2148 "@ | |
2149 lzer\t%0 | |
2150 ler\t%0,%1 | |
2151 le\t%0,%1 | |
2152 ley\t%0,%1 | |
2153 ste\t%1,%0 | |
2154 stey\t%1,%0 | |
2155 lr\t%0,%1 | |
2156 l\t%0,%1 | |
2157 ly\t%0,%1 | |
2158 st\t%1,%0 | |
2159 sty\t%1,%0" | |
2160 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY") | |
2161 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, | |
2162 fstore<mode>,fstore<mode>,lr,load,load,store,store") | |
2163 (set_attr "z10prop" "*, | |
2164 *, | |
2165 *, | |
2166 *, | |
2167 *, | |
2168 *, | |
2169 z10_fr_E1, | |
2170 z10_fwd_A3, | |
2171 z10_fwd_A3, | |
2172 z10_rec, | |
2173 z10_rec")]) | |
2174 | |
2175 ; | |
2176 ; movcc instruction pattern | |
2177 ; | |
2178 | |
2179 (define_insn "movcc" | |
2180 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
2181 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
2182 "" | |
2183 "@ | |
2184 lr\t%0,%1 | |
2185 tmh\t%1,12288 | |
2186 ipm\t%0 | |
2187 st\t%0,%1 | |
2188 sty\t%0,%1 | |
2189 l\t%1,%0 | |
2190 ly\t%1,%0" | |
2191 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") | |
2192 (set_attr "type" "lr,*,*,store,store,load,load") | |
2193 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")]) | |
2194 | |
2195 ; | |
2196 ; Block move (MVC) patterns. | |
2197 ; | |
2198 | |
2199 (define_insn "*mvc" | |
2200 [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2201 (match_operand:BLK 1 "memory_operand" "Q")) | |
2202 (use (match_operand 2 "const_int_operand" "n"))] | |
2203 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
2204 "mvc\t%O0(%2,%R0),%S1" | |
2205 [(set_attr "op_type" "SS")]) | |
2206 | |
2207 (define_peephole2 | |
2208 [(parallel | |
2209 [(set (match_operand:BLK 0 "memory_operand" "") | |
2210 (match_operand:BLK 1 "memory_operand" "")) | |
2211 (use (match_operand 2 "const_int_operand" ""))]) | |
2212 (parallel | |
2213 [(set (match_operand:BLK 3 "memory_operand" "") | |
2214 (match_operand:BLK 4 "memory_operand" "")) | |
2215 (use (match_operand 5 "const_int_operand" ""))])] | |
2216 "s390_offset_p (operands[0], operands[3], operands[2]) | |
2217 && s390_offset_p (operands[1], operands[4], operands[2]) | |
2218 && !s390_overlap_p (operands[0], operands[1], | |
2219 INTVAL (operands[2]) + INTVAL (operands[5])) | |
2220 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
2221 [(parallel | |
2222 [(set (match_dup 6) (match_dup 7)) | |
2223 (use (match_dup 8))])] | |
2224 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2225 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2226 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2227 | |
2228 | |
2229 ; | |
2230 ; load_multiple pattern(s). | |
2231 ; | |
2232 ; ??? Due to reload problems with replacing registers inside match_parallel | |
2233 ; we currently support load_multiple/store_multiple only after reload. | |
2234 ; | |
2235 | |
2236 (define_expand "load_multiple" | |
2237 [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2238 (match_operand 1 "" "")) | |
2239 (use (match_operand 2 "" ""))])] | |
2240 "reload_completed" | |
2241 { | |
2242 enum machine_mode mode; | |
2243 int regno; | |
2244 int count; | |
2245 rtx from; | |
2246 int i, off; | |
2247 | |
2248 /* Support only loading a constant number of fixed-point registers from | |
2249 memory and only bother with this if more than two */ | |
2250 if (GET_CODE (operands[2]) != CONST_INT | |
2251 || INTVAL (operands[2]) < 2 | |
2252 || INTVAL (operands[2]) > 16 | |
2253 || GET_CODE (operands[1]) != MEM | |
2254 || GET_CODE (operands[0]) != REG | |
2255 || REGNO (operands[0]) >= 16) | |
2256 FAIL; | |
2257 | |
2258 count = INTVAL (operands[2]); | |
2259 regno = REGNO (operands[0]); | |
2260 mode = GET_MODE (operands[0]); | |
2261 if (mode != SImode && mode != word_mode) | |
2262 FAIL; | |
2263 | |
2264 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
2265 if (!can_create_pseudo_p ()) | |
2266 { | |
2267 if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2268 { | |
2269 from = XEXP (operands[1], 0); | |
2270 off = 0; | |
2271 } | |
2272 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2273 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2274 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2275 { | |
2276 from = XEXP (XEXP (operands[1], 0), 0); | |
2277 off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2278 } | |
2279 else | |
2280 FAIL; | |
2281 } | |
2282 else | |
2283 { | |
2284 from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2285 off = 0; | |
2286 } | |
2287 | |
2288 for (i = 0; i < count; i++) | |
2289 XVECEXP (operands[3], 0, i) | |
2290 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), | |
2291 change_address (operands[1], mode, | |
2292 plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
2293 }) | |
2294 | |
2295 (define_insn "*load_multiple_di" | |
2296 [(match_parallel 0 "load_multiple_operation" | |
2297 [(set (match_operand:DI 1 "register_operand" "=r") | |
2298 (match_operand:DI 2 "s_operand" "QS"))])] | |
2299 "reload_completed && word_mode == DImode" | |
2300 { | |
2301 int words = XVECLEN (operands[0], 0); | |
2302 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); | |
2303 return "lmg\t%1,%0,%S2"; | |
2304 } | |
2305 [(set_attr "op_type" "RSY") | |
2306 (set_attr "type" "lm")]) | |
2307 | |
2308 (define_insn "*load_multiple_si" | |
2309 [(match_parallel 0 "load_multiple_operation" | |
2310 [(set (match_operand:SI 1 "register_operand" "=r,r") | |
2311 (match_operand:SI 2 "s_operand" "Q,S"))])] | |
2312 "reload_completed" | |
2313 { | |
2314 int words = XVECLEN (operands[0], 0); | |
2315 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); | |
2316 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; | |
2317 } | |
2318 [(set_attr "op_type" "RS,RSY") | |
2319 (set_attr "type" "lm")]) | |
2320 | |
2321 ; | |
2322 ; store multiple pattern(s). | |
2323 ; | |
2324 | |
2325 (define_expand "store_multiple" | |
2326 [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2327 (match_operand 1 "" "")) | |
2328 (use (match_operand 2 "" ""))])] | |
2329 "reload_completed" | |
2330 { | |
2331 enum machine_mode mode; | |
2332 int regno; | |
2333 int count; | |
2334 rtx to; | |
2335 int i, off; | |
2336 | |
2337 /* Support only storing a constant number of fixed-point registers to | |
2338 memory and only bother with this if more than two. */ | |
2339 if (GET_CODE (operands[2]) != CONST_INT | |
2340 || INTVAL (operands[2]) < 2 | |
2341 || INTVAL (operands[2]) > 16 | |
2342 || GET_CODE (operands[0]) != MEM | |
2343 || GET_CODE (operands[1]) != REG | |
2344 || REGNO (operands[1]) >= 16) | |
2345 FAIL; | |
2346 | |
2347 count = INTVAL (operands[2]); | |
2348 regno = REGNO (operands[1]); | |
2349 mode = GET_MODE (operands[1]); | |
2350 if (mode != SImode && mode != word_mode) | |
2351 FAIL; | |
2352 | |
2353 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
2354 | |
2355 if (!can_create_pseudo_p ()) | |
2356 { | |
2357 if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2358 { | |
2359 to = XEXP (operands[0], 0); | |
2360 off = 0; | |
2361 } | |
2362 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2363 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2364 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2365 { | |
2366 to = XEXP (XEXP (operands[0], 0), 0); | |
2367 off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2368 } | |
2369 else | |
2370 FAIL; | |
2371 } | |
2372 else | |
2373 { | |
2374 to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2375 off = 0; | |
2376 } | |
2377 | |
2378 for (i = 0; i < count; i++) | |
2379 XVECEXP (operands[3], 0, i) | |
2380 = gen_rtx_SET (VOIDmode, | |
2381 change_address (operands[0], mode, | |
2382 plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
2383 gen_rtx_REG (mode, regno + i)); | |
2384 }) | |
2385 | |
2386 (define_insn "*store_multiple_di" | |
2387 [(match_parallel 0 "store_multiple_operation" | |
2388 [(set (match_operand:DI 1 "s_operand" "=QS") | |
2389 (match_operand:DI 2 "register_operand" "r"))])] | |
2390 "reload_completed && word_mode == DImode" | |
2391 { | |
2392 int words = XVECLEN (operands[0], 0); | |
2393 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); | |
2394 return "stmg\t%2,%0,%S1"; | |
2395 } | |
2396 [(set_attr "op_type" "RSY") | |
2397 (set_attr "type" "stm")]) | |
2398 | |
2399 | |
2400 (define_insn "*store_multiple_si" | |
2401 [(match_parallel 0 "store_multiple_operation" | |
2402 [(set (match_operand:SI 1 "s_operand" "=Q,S") | |
2403 (match_operand:SI 2 "register_operand" "r,r"))])] | |
2404 "reload_completed" | |
2405 { | |
2406 int words = XVECLEN (operands[0], 0); | |
2407 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); | |
2408 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; | |
2409 } | |
2410 [(set_attr "op_type" "RS,RSY") | |
2411 (set_attr "type" "stm")]) | |
2412 | |
2413 ;; | |
2414 ;; String instructions. | |
2415 ;; | |
2416 | |
2417 (define_insn "*execute_rl" | |
2418 [(match_parallel 0 "" | |
2419 [(unspec [(match_operand 1 "register_operand" "a") | |
2420 (match_operand 2 "" "") | |
2421 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2422 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2423 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2424 "exrl\t%1,%3" | |
2425 [(set_attr "op_type" "RIL") | |
2426 (set_attr "type" "cs")]) | |
2427 | |
2428 (define_insn "*execute" | |
2429 [(match_parallel 0 "" | |
2430 [(unspec [(match_operand 1 "register_operand" "a") | |
2431 (match_operand:BLK 2 "memory_operand" "R") | |
2432 (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2433 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2434 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2435 "ex\t%1,%2" | |
2436 [(set_attr "op_type" "RX") | |
2437 (set_attr "type" "cs")]) | |
2438 | |
2439 | |
2440 ; | |
2441 ; strlenM instruction pattern(s). | |
2442 ; | |
2443 | |
2444 (define_expand "strlen<mode>" | |
2445 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) | |
2446 (parallel | |
2447 [(set (match_dup 4) | |
2448 (unspec:P [(const_int 0) | |
2449 (match_operand:BLK 1 "memory_operand" "") | |
2450 (reg:SI 0) | |
2451 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
2452 (clobber (scratch:P)) | |
2453 (clobber (reg:CC CC_REGNUM))]) | |
2454 (parallel | |
2455 [(set (match_operand:P 0 "register_operand" "") | |
2456 (minus:P (match_dup 4) (match_dup 5))) | |
2457 (clobber (reg:CC CC_REGNUM))])] | |
2458 "" | |
2459 { | |
2460 operands[4] = gen_reg_rtx (Pmode); | |
2461 operands[5] = gen_reg_rtx (Pmode); | |
2462 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2463 operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2464 }) | |
2465 | |
2466 (define_insn "*strlen<mode>" | |
2467 [(set (match_operand:P 0 "register_operand" "=a") | |
2468 (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2469 (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
2470 (reg:SI 0) | |
2471 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
2472 (clobber (match_scratch:P 1 "=a")) | |
2473 (clobber (reg:CC CC_REGNUM))] | |
2474 "" | |
2475 "srst\t%0,%1\;jo\t.-4" | |
2476 [(set_attr "length" "8") | |
2477 (set_attr "type" "vs")]) | |
2478 | |
2479 ; | |
2480 ; cmpstrM instruction pattern(s). | |
2481 ; | |
2482 | |
2483 (define_expand "cmpstrsi" | |
2484 [(set (reg:SI 0) (const_int 0)) | |
2485 (parallel | |
2486 [(clobber (match_operand 3 "" "")) | |
2487 (clobber (match_dup 4)) | |
2488 (set (reg:CCU CC_REGNUM) | |
2489 (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2490 (match_operand:BLK 2 "memory_operand" ""))) | |
2491 (use (reg:SI 0))]) | |
2492 (parallel | |
2493 [(set (match_operand:SI 0 "register_operand" "=d") | |
2494 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT)) | |
2495 (clobber (reg:CC CC_REGNUM))])] | |
2496 "" | |
2497 { | |
2498 /* As the result of CMPINT is inverted compared to what we need, | |
2499 we have to swap the operands. */ | |
2500 rtx op1 = operands[2]; | |
2501 rtx op2 = operands[1]; | |
2502 rtx addr1 = gen_reg_rtx (Pmode); | |
2503 rtx addr2 = gen_reg_rtx (Pmode); | |
2504 | |
2505 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2506 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2507 operands[1] = replace_equiv_address_nv (op1, addr1); | |
2508 operands[2] = replace_equiv_address_nv (op2, addr2); | |
2509 operands[3] = addr1; | |
2510 operands[4] = addr2; | |
2511 }) | |
2512 | |
2513 (define_insn "*cmpstr<mode>" | |
2514 [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2515 (clobber (match_operand:P 1 "register_operand" "=d")) | |
2516 (set (reg:CCU CC_REGNUM) | |
2517 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2518 (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2519 (use (reg:SI 0))] | |
2520 "" | |
2521 "clst\t%0,%1\;jo\t.-4" | |
2522 [(set_attr "length" "8") | |
2523 (set_attr "type" "vs")]) | |
2524 | |
2525 ; | |
2526 ; movstr instruction pattern. | |
2527 ; | |
2528 | |
2529 (define_expand "movstr" | |
2530 [(set (reg:SI 0) (const_int 0)) | |
2531 (parallel | |
2532 [(clobber (match_dup 3)) | |
2533 (set (match_operand:BLK 1 "memory_operand" "") | |
2534 (match_operand:BLK 2 "memory_operand" "")) | |
2535 (set (match_operand 0 "register_operand" "") | |
2536 (unspec [(match_dup 1) | |
2537 (match_dup 2) | |
2538 (reg:SI 0)] UNSPEC_MVST)) | |
2539 (clobber (reg:CC CC_REGNUM))])] | |
2540 "" | |
2541 { | |
2542 rtx addr1 = gen_reg_rtx (Pmode); | |
2543 rtx addr2 = gen_reg_rtx (Pmode); | |
2544 | |
2545 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2546 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2547 operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2548 operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2549 operands[3] = addr2; | |
2550 }) | |
2551 | |
2552 (define_insn "*movstr" | |
2553 [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2554 (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2555 (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2556 (set (match_operand:P 0 "register_operand" "=d") | |
2557 (unspec [(mem:BLK (match_dup 1)) | |
2558 (mem:BLK (match_dup 3)) | |
2559 (reg:SI 0)] UNSPEC_MVST)) | |
2560 (clobber (reg:CC CC_REGNUM))] | |
2561 "" | |
2562 "mvst\t%1,%2\;jo\t.-4" | |
2563 [(set_attr "length" "8") | |
2564 (set_attr "type" "vs")]) | |
2565 | |
2566 | |
2567 ; | |
2568 ; movmemM instruction pattern(s). | |
2569 ; | |
2570 | |
2571 (define_expand "movmem<mode>" | |
2572 [(set (match_operand:BLK 0 "memory_operand" "") ; destination | |
2573 (match_operand:BLK 1 "memory_operand" "")) ; source | |
2574 (use (match_operand:GPR 2 "general_operand" "")) ; count | |
2575 (match_operand 3 "" "")] | |
2576 "" | |
2577 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") | |
2578 | |
2579 ; Move a block that is up to 256 bytes in length. | |
2580 ; The block length is taken as (operands[2] % 256) + 1. | |
2581 | |
2582 (define_expand "movmem_short" | |
2583 [(parallel | |
2584 [(set (match_operand:BLK 0 "memory_operand" "") | |
2585 (match_operand:BLK 1 "memory_operand" "")) | |
2586 (use (match_operand 2 "nonmemory_operand" "")) | |
2587 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2588 (clobber (match_dup 3))])] | |
2589 "" | |
2590 "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
2591 | |
2592 (define_insn "*movmem_short" | |
2593 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") | |
2594 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
2595 (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2596 (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
2597 (clobber (match_scratch 4 "=X,X,X,&a"))] | |
2598 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) | |
2599 && GET_MODE (operands[4]) == Pmode" | |
2600 "#" | |
2601 [(set_attr "type" "cs") | |
2602 (set_attr "cpu_facility" "*,*,z10,*")]) | |
2603 | |
2604 (define_split | |
2605 [(set (match_operand:BLK 0 "memory_operand" "") | |
2606 (match_operand:BLK 1 "memory_operand" "")) | |
2607 (use (match_operand 2 "const_int_operand" "")) | |
2608 (use (match_operand 3 "immediate_operand" "")) | |
2609 (clobber (scratch))] | |
2610 "reload_completed" | |
2611 [(parallel | |
2612 [(set (match_dup 0) (match_dup 1)) | |
2613 (use (match_dup 2))])] | |
2614 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
2615 | |
2616 (define_split | |
2617 [(set (match_operand:BLK 0 "memory_operand" "") | |
2618 (match_operand:BLK 1 "memory_operand" "")) | |
2619 (use (match_operand 2 "register_operand" "")) | |
2620 (use (match_operand 3 "memory_operand" "")) | |
2621 (clobber (scratch))] | |
2622 "reload_completed" | |
2623 [(parallel | |
2624 [(unspec [(match_dup 2) (match_dup 3) | |
2625 (const_int 0)] UNSPEC_EXECUTE) | |
2626 (set (match_dup 0) (match_dup 1)) | |
2627 (use (const_int 1))])] | |
2628 "") | |
2629 | |
2630 (define_split | |
2631 [(set (match_operand:BLK 0 "memory_operand" "") | |
2632 (match_operand:BLK 1 "memory_operand" "")) | |
2633 (use (match_operand 2 "register_operand" "")) | |
2634 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2635 (clobber (scratch))] | |
2636 "TARGET_Z10 && reload_completed" | |
2637 [(parallel | |
2638 [(unspec [(match_dup 2) (const_int 0) | |
2639 (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2640 (set (match_dup 0) (match_dup 1)) | |
2641 (use (const_int 1))])] | |
2642 "operands[3] = gen_label_rtx ();") | |
2643 | |
2644 (define_split | |
2645 [(set (match_operand:BLK 0 "memory_operand" "") | |
2646 (match_operand:BLK 1 "memory_operand" "")) | |
2647 (use (match_operand 2 "register_operand" "")) | |
2648 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2649 (clobber (match_operand 3 "register_operand" ""))] | |
2650 "reload_completed && TARGET_CPU_ZARCH" | |
2651 [(set (match_dup 3) (label_ref (match_dup 4))) | |
2652 (parallel | |
2653 [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
2654 (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
2655 (set (match_dup 0) (match_dup 1)) | |
2656 (use (const_int 1))])] | |
2657 "operands[4] = gen_label_rtx ();") | |
2658 | |
2659 ; Move a block of arbitrary length. | |
2660 | |
2661 (define_expand "movmem_long" | |
2662 [(parallel | |
2663 [(clobber (match_dup 2)) | |
2664 (clobber (match_dup 3)) | |
2665 (set (match_operand:BLK 0 "memory_operand" "") | |
2666 (match_operand:BLK 1 "memory_operand" "")) | |
2667 (use (match_operand 2 "general_operand" "")) | |
2668 (use (match_dup 3)) | |
2669 (clobber (reg:CC CC_REGNUM))])] | |
2670 "" | |
2671 { | |
2672 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2673 rtx reg0 = gen_reg_rtx (dword_mode); | |
2674 rtx reg1 = gen_reg_rtx (dword_mode); | |
2675 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2676 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2677 rtx len0 = gen_lowpart (Pmode, reg0); | |
2678 rtx len1 = gen_lowpart (Pmode, reg1); | |
2679 | |
2680 emit_clobber (reg0); | |
2681 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2682 emit_move_insn (len0, operands[2]); | |
2683 | |
2684 emit_clobber (reg1); | |
2685 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2686 emit_move_insn (len1, operands[2]); | |
2687 | |
2688 operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2689 operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2690 operands[2] = reg0; | |
2691 operands[3] = reg1; | |
2692 }) | |
2693 | |
2694 (define_insn "*movmem_long" | |
2695 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2696 (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
2697 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
2698 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
2699 (use (match_dup 2)) | |
2700 (use (match_dup 3)) | |
2701 (clobber (reg:CC CC_REGNUM))] | |
2702 "" | |
2703 "mvcle\t%0,%1,0\;jo\t.-4" | |
2704 [(set_attr "length" "8") | |
2705 (set_attr "type" "vs")]) | |
2706 | |
2707 | |
2708 ; | |
2709 ; Test data class. | |
2710 ; | |
2711 | |
2712 (define_expand "signbit<mode>2" | |
2713 [(set (reg:CCZ CC_REGNUM) | |
2714 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") | |
2715 (match_dup 2)] | |
2716 UNSPEC_TDC_INSN)) | |
2717 (set (match_operand:SI 0 "register_operand" "=d") | |
2718 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
2719 "TARGET_HARD_FLOAT" | |
2720 { | |
2721 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
2722 }) | |
2723 | |
2724 (define_expand "isinf<mode>2" | |
2725 [(set (reg:CCZ CC_REGNUM) | |
2726 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") | |
2727 (match_dup 2)] | |
2728 UNSPEC_TDC_INSN)) | |
2729 (set (match_operand:SI 0 "register_operand" "=d") | |
2730 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
2731 "TARGET_HARD_FLOAT" | |
2732 { | |
2733 operands[2] = GEN_INT (S390_TDC_INFINITY); | |
2734 }) | |
2735 | |
2736 ; This insn is used to generate all variants of the Test Data Class | |
2737 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
2738 ; is the register to be tested and the second one is the bit mask | |
2739 ; specifying the required test(s). | |
2740 ; | |
2741 (define_insn "*TDC_insn_<mode>" | |
2742 [(set (reg:CCZ CC_REGNUM) | |
2743 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") | |
2744 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] | |
2745 "TARGET_HARD_FLOAT" | |
2746 "t<_d>c<xde><bt>\t%0,%1" | |
2747 [(set_attr "op_type" "RXE") | |
2748 (set_attr "type" "fsimp<mode>")]) | |
2749 | |
2750 (define_insn_and_split "*ccz_to_int" | |
2751 [(set (match_operand:SI 0 "register_operand" "=d") | |
2752 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")] | |
2753 UNSPEC_CCZ_TO_INT))] | |
2754 "" | |
2755 "#" | |
2756 "reload_completed" | |
2757 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
2758 | |
2759 | |
2760 ; | |
2761 ; setmemM instruction pattern(s). | |
2762 ; | |
2763 | |
2764 (define_expand "setmem<mode>" | |
2765 [(set (match_operand:BLK 0 "memory_operand" "") | |
2766 (match_operand:QI 2 "general_operand" "")) | |
2767 (use (match_operand:GPR 1 "general_operand" "")) | |
2768 (match_operand 3 "" "")] | |
2769 "" | |
2770 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") | |
2771 | |
2772 ; Clear a block that is up to 256 bytes in length. | |
2773 ; The block length is taken as (operands[1] % 256) + 1. | |
2774 | |
2775 (define_expand "clrmem_short" | |
2776 [(parallel | |
2777 [(set (match_operand:BLK 0 "memory_operand" "") | |
2778 (const_int 0)) | |
2779 (use (match_operand 1 "nonmemory_operand" "")) | |
2780 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2781 (clobber (match_dup 2)) | |
2782 (clobber (reg:CC CC_REGNUM))])] | |
2783 "" | |
2784 "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
2785 | |
2786 (define_insn "*clrmem_short" | |
2787 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") | |
2788 (const_int 0)) | |
2789 (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) | |
2790 (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
2791 (clobber (match_scratch 3 "=X,X,X,&a")) | |
2792 (clobber (reg:CC CC_REGNUM))] | |
2793 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) | |
2794 && GET_MODE (operands[3]) == Pmode" | |
2795 "#" | |
2796 [(set_attr "type" "cs") | |
2797 (set_attr "cpu_facility" "*,*,z10,*")]) | |
2798 | |
2799 (define_split | |
2800 [(set (match_operand:BLK 0 "memory_operand" "") | |
2801 (const_int 0)) | |
2802 (use (match_operand 1 "const_int_operand" "")) | |
2803 (use (match_operand 2 "immediate_operand" "")) | |
2804 (clobber (scratch)) | |
2805 (clobber (reg:CC CC_REGNUM))] | |
2806 "reload_completed" | |
2807 [(parallel | |
2808 [(set (match_dup 0) (const_int 0)) | |
2809 (use (match_dup 1)) | |
2810 (clobber (reg:CC CC_REGNUM))])] | |
2811 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") | |
2812 | |
2813 (define_split | |
2814 [(set (match_operand:BLK 0 "memory_operand" "") | |
2815 (const_int 0)) | |
2816 (use (match_operand 1 "register_operand" "")) | |
2817 (use (match_operand 2 "memory_operand" "")) | |
2818 (clobber (scratch)) | |
2819 (clobber (reg:CC CC_REGNUM))] | |
2820 "reload_completed" | |
2821 [(parallel | |
2822 [(unspec [(match_dup 1) (match_dup 2) | |
2823 (const_int 0)] UNSPEC_EXECUTE) | |
2824 (set (match_dup 0) (const_int 0)) | |
2825 (use (const_int 1)) | |
2826 (clobber (reg:CC CC_REGNUM))])] | |
2827 "") | |
2828 | |
2829 (define_split | |
2830 [(set (match_operand:BLK 0 "memory_operand" "") | |
2831 (const_int 0)) | |
2832 (use (match_operand 1 "register_operand" "")) | |
2833 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2834 (clobber (scratch)) | |
2835 (clobber (reg:CC CC_REGNUM))] | |
2836 "TARGET_Z10 && reload_completed" | |
2837 [(parallel | |
2838 [(unspec [(match_dup 1) (const_int 0) | |
2839 (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2840 (set (match_dup 0) (const_int 0)) | |
2841 (use (const_int 1)) | |
2842 (clobber (reg:CC CC_REGNUM))])] | |
2843 "operands[3] = gen_label_rtx ();") | |
2844 | |
2845 (define_split | |
2846 [(set (match_operand:BLK 0 "memory_operand" "") | |
2847 (const_int 0)) | |
2848 (use (match_operand 1 "register_operand" "")) | |
2849 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2850 (clobber (match_operand 2 "register_operand" "")) | |
2851 (clobber (reg:CC CC_REGNUM))] | |
2852 "reload_completed && TARGET_CPU_ZARCH" | |
2853 [(set (match_dup 2) (label_ref (match_dup 3))) | |
2854 (parallel | |
2855 [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) | |
2856 (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2857 (set (match_dup 0) (const_int 0)) | |
2858 (use (const_int 1)) | |
2859 (clobber (reg:CC CC_REGNUM))])] | |
2860 "operands[3] = gen_label_rtx ();") | |
2861 | |
2862 ; Initialize a block of arbitrary length with (operands[2] % 256). | |
2863 | |
2864 (define_expand "setmem_long" | |
2865 [(parallel | |
2866 [(clobber (match_dup 1)) | |
2867 (set (match_operand:BLK 0 "memory_operand" "") | |
2868 (match_operand 2 "shift_count_or_setmem_operand" "")) | |
2869 (use (match_operand 1 "general_operand" "")) | |
2870 (use (match_dup 3)) | |
2871 (clobber (reg:CC CC_REGNUM))])] | |
2872 "" | |
2873 { | |
2874 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2875 rtx reg0 = gen_reg_rtx (dword_mode); | |
2876 rtx reg1 = gen_reg_rtx (dword_mode); | |
2877 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2878 rtx len0 = gen_lowpart (Pmode, reg0); | |
2879 | |
2880 emit_clobber (reg0); | |
2881 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2882 emit_move_insn (len0, operands[1]); | |
2883 | |
2884 emit_move_insn (reg1, const0_rtx); | |
2885 | |
2886 operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2887 operands[1] = reg0; | |
2888 operands[3] = reg1; | |
2889 }) | |
2890 | |
2891 (define_insn "*setmem_long" | |
2892 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2893 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
2894 (match_operand 2 "shift_count_or_setmem_operand" "Y")) | |
2895 (use (match_dup 3)) | |
2896 (use (match_operand:<DBL> 1 "register_operand" "d")) | |
2897 (clobber (reg:CC CC_REGNUM))] | |
2898 "" | |
2899 "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
2900 [(set_attr "length" "8") | |
2901 (set_attr "type" "vs")]) | |
2902 | |
2903 (define_insn "*setmem_long_and" | |
2904 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2905 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
2906 (and (match_operand 2 "shift_count_or_setmem_operand" "Y") | |
2907 (match_operand 4 "const_int_operand" "n"))) | |
2908 (use (match_dup 3)) | |
2909 (use (match_operand:<DBL> 1 "register_operand" "d")) | |
2910 (clobber (reg:CC CC_REGNUM))] | |
2911 "(INTVAL (operands[4]) & 255) == 255" | |
2912 "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
2913 [(set_attr "length" "8") | |
2914 (set_attr "type" "vs")]) | |
2915 ; | |
2916 ; cmpmemM instruction pattern(s). | |
2917 ; | |
2918 | |
2919 (define_expand "cmpmemsi" | |
2920 [(set (match_operand:SI 0 "register_operand" "") | |
2921 (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2922 (match_operand:BLK 2 "memory_operand" "") ) ) | |
2923 (use (match_operand:SI 3 "general_operand" "")) | |
2924 (use (match_operand:SI 4 "" ""))] | |
2925 "" | |
2926 "s390_expand_cmpmem (operands[0], operands[1], | |
2927 operands[2], operands[3]); DONE;") | |
2928 | |
2929 ; Compare a block that is up to 256 bytes in length. | |
2930 ; The block length is taken as (operands[2] % 256) + 1. | |
2931 | |
2932 (define_expand "cmpmem_short" | |
2933 [(parallel | |
2934 [(set (reg:CCU CC_REGNUM) | |
2935 (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2936 (match_operand:BLK 1 "memory_operand" ""))) | |
2937 (use (match_operand 2 "nonmemory_operand" "")) | |
2938 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2939 (clobber (match_dup 3))])] | |
2940 "" | |
2941 "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
2942 | |
2943 (define_insn "*cmpmem_short" | |
2944 [(set (reg:CCU CC_REGNUM) | |
2945 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") | |
2946 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
2947 (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2948 (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
2949 (clobber (match_scratch 4 "=X,X,X,&a"))] | |
2950 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) | |
2951 && GET_MODE (operands[4]) == Pmode" | |
2952 "#" | |
2953 [(set_attr "type" "cs") | |
2954 (set_attr "cpu_facility" "*,*,z10,*")]) | |
2955 | |
2956 (define_split | |
2957 [(set (reg:CCU CC_REGNUM) | |
2958 (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2959 (match_operand:BLK 1 "memory_operand" ""))) | |
2960 (use (match_operand 2 "const_int_operand" "")) | |
2961 (use (match_operand 3 "immediate_operand" "")) | |
2962 (clobber (scratch))] | |
2963 "reload_completed" | |
2964 [(parallel | |
2965 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
2966 (use (match_dup 2))])] | |
2967 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
2968 | |
2969 (define_split | |
2970 [(set (reg:CCU CC_REGNUM) | |
2971 (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2972 (match_operand:BLK 1 "memory_operand" ""))) | |
2973 (use (match_operand 2 "register_operand" "")) | |
2974 (use (match_operand 3 "memory_operand" "")) | |
2975 (clobber (scratch))] | |
2976 "reload_completed" | |
2977 [(parallel | |
2978 [(unspec [(match_dup 2) (match_dup 3) | |
2979 (const_int 0)] UNSPEC_EXECUTE) | |
2980 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
2981 (use (const_int 1))])] | |
2982 "") | |
2983 | |
2984 (define_split | |
2985 [(set (reg:CCU CC_REGNUM) | |
2986 (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2987 (match_operand:BLK 1 "memory_operand" ""))) | |
2988 (use (match_operand 2 "register_operand" "")) | |
2989 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2990 (clobber (scratch))] | |
2991 "TARGET_Z10 && reload_completed" | |
2992 [(parallel | |
2993 [(unspec [(match_dup 2) (const_int 0) | |
2994 (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
2995 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
2996 (use (const_int 1))])] | |
2997 "operands[4] = gen_label_rtx ();") | |
2998 | |
2999 (define_split | |
3000 [(set (reg:CCU CC_REGNUM) | |
3001 (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3002 (match_operand:BLK 1 "memory_operand" ""))) | |
3003 (use (match_operand 2 "register_operand" "")) | |
3004 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3005 (clobber (match_operand 3 "register_operand" ""))] | |
3006 "reload_completed && TARGET_CPU_ZARCH" | |
3007 [(set (match_dup 3) (label_ref (match_dup 4))) | |
3008 (parallel | |
3009 [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
3010 (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3011 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3012 (use (const_int 1))])] | |
3013 "operands[4] = gen_label_rtx ();") | |
3014 | |
3015 ; Compare a block of arbitrary length. | |
3016 | |
3017 (define_expand "cmpmem_long" | |
3018 [(parallel | |
3019 [(clobber (match_dup 2)) | |
3020 (clobber (match_dup 3)) | |
3021 (set (reg:CCU CC_REGNUM) | |
3022 (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3023 (match_operand:BLK 1 "memory_operand" ""))) | |
3024 (use (match_operand 2 "general_operand" "")) | |
3025 (use (match_dup 3))])] | |
3026 "" | |
3027 { | |
3028 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
3029 rtx reg0 = gen_reg_rtx (dword_mode); | |
3030 rtx reg1 = gen_reg_rtx (dword_mode); | |
3031 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
3032 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
3033 rtx len0 = gen_lowpart (Pmode, reg0); | |
3034 rtx len1 = gen_lowpart (Pmode, reg1); | |
3035 | |
3036 emit_clobber (reg0); | |
3037 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
3038 emit_move_insn (len0, operands[2]); | |
3039 | |
3040 emit_clobber (reg1); | |
3041 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
3042 emit_move_insn (len1, operands[2]); | |
3043 | |
3044 operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3045 operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3046 operands[2] = reg0; | |
3047 operands[3] = reg1; | |
3048 }) | |
3049 | |
3050 (define_insn "*cmpmem_long" | |
3051 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3052 (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3053 (set (reg:CCU CC_REGNUM) | |
3054 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3055 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
3056 (use (match_dup 2)) | |
3057 (use (match_dup 3))] | |
3058 "" | |
3059 "clcle\t%0,%1,0\;jo\t.-4" | |
3060 [(set_attr "length" "8") | |
3061 (set_attr "type" "vs")]) | |
3062 | |
3063 ; Convert CCUmode condition code to integer. | |
3064 ; Result is zero if EQ, positive if LTU, negative if GTU. | |
3065 | |
3066 (define_insn_and_split "cmpint" | |
3067 [(set (match_operand:SI 0 "register_operand" "=d") | |
3068 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
3069 UNSPEC_CCU_TO_INT)) | |
3070 (clobber (reg:CC CC_REGNUM))] | |
3071 "" | |
3072 "#" | |
3073 "reload_completed" | |
3074 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3075 (parallel | |
3076 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
3077 (clobber (reg:CC CC_REGNUM))])]) | |
3078 | |
3079 (define_insn_and_split "*cmpint_cc" | |
3080 [(set (reg CC_REGNUM) | |
3081 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
3082 UNSPEC_CCU_TO_INT) | |
3083 (const_int 0))) | |
3084 (set (match_operand:SI 0 "register_operand" "=d") | |
3085 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))] | |
3086 "s390_match_ccmode (insn, CCSmode)" | |
3087 "#" | |
3088 "&& reload_completed" | |
3089 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3090 (parallel | |
3091 [(set (match_dup 2) (match_dup 3)) | |
3092 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
3093 { | |
3094 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); | |
3095 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3096 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3097 }) | |
3098 | |
3099 (define_insn_and_split "*cmpint_sign" | |
3100 [(set (match_operand:DI 0 "register_operand" "=d") | |
3101 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
3102 UNSPEC_CCU_TO_INT))) | |
3103 (clobber (reg:CC CC_REGNUM))] | |
3104 "TARGET_64BIT" | |
3105 "#" | |
3106 "&& reload_completed" | |
3107 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3108 (parallel | |
3109 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
3110 (clobber (reg:CC CC_REGNUM))])]) | |
3111 | |
3112 (define_insn_and_split "*cmpint_sign_cc" | |
3113 [(set (reg CC_REGNUM) | |
3114 (compare (ashiftrt:DI (ashift:DI (subreg:DI | |
3115 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
3116 UNSPEC_CCU_TO_INT) 0) | |
3117 (const_int 32)) (const_int 32)) | |
3118 (const_int 0))) | |
3119 (set (match_operand:DI 0 "register_operand" "=d") | |
3120 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))] | |
3121 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" | |
3122 "#" | |
3123 "&& reload_completed" | |
3124 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3125 (parallel | |
3126 [(set (match_dup 2) (match_dup 3)) | |
3127 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
3128 { | |
3129 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); | |
3130 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3131 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3132 }) | |
3133 | |
3134 | |
3135 ;; | |
3136 ;;- Conversion instructions. | |
3137 ;; | |
3138 | |
3139 (define_insn "*sethighpartsi" | |
3140 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3141 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") | |
3142 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
3143 (clobber (reg:CC CC_REGNUM))] | |
3144 "" | |
3145 "@ | |
3146 icm\t%0,%2,%S1 | |
3147 icmy\t%0,%2,%S1" | |
3148 [(set_attr "op_type" "RS,RSY") | |
3149 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3150 | |
3151 (define_insn "*sethighpartdi_64" | |
3152 [(set (match_operand:DI 0 "register_operand" "=d") | |
3153 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") | |
3154 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
3155 (clobber (reg:CC CC_REGNUM))] | |
3156 "TARGET_64BIT" | |
3157 "icmh\t%0,%2,%S1" | |
3158 [(set_attr "op_type" "RSY") | |
3159 (set_attr "z10prop" "z10_super")]) | |
3160 | |
3161 (define_insn "*sethighpartdi_31" | |
3162 [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3163 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") | |
3164 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
3165 (clobber (reg:CC CC_REGNUM))] | |
3166 "!TARGET_64BIT" | |
3167 "@ | |
3168 icm\t%0,%2,%S1 | |
3169 icmy\t%0,%2,%S1" | |
3170 [(set_attr "op_type" "RS,RSY") | |
3171 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3172 | |
3173 | |
3174 (define_insn_and_split "*extzv<mode>" | |
3175 [(set (match_operand:GPR 0 "register_operand" "=d") | |
3176 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3177 (match_operand 2 "const_int_operand" "n") | |
3178 (const_int 0))) | |
3179 (clobber (reg:CC CC_REGNUM))] | |
3180 "INTVAL (operands[2]) > 0 | |
3181 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
3182 "#" | |
3183 "&& reload_completed" | |
3184 [(parallel | |
3185 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) | |
3186 (clobber (reg:CC CC_REGNUM))]) | |
3187 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] | |
3188 { | |
3189 int bitsize = INTVAL (operands[2]); | |
3190 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3191 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3192 | |
3193 operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3194 set_mem_size (operands[1], GEN_INT (size)); | |
3195 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
3196 operands[3] = GEN_INT (mask); | |
3197 }) | |
3198 | |
3199 (define_insn_and_split "*extv<mode>" | |
3200 [(set (match_operand:GPR 0 "register_operand" "=d") | |
3201 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3202 (match_operand 2 "const_int_operand" "n") | |
3203 (const_int 0))) | |
3204 (clobber (reg:CC CC_REGNUM))] | |
3205 "INTVAL (operands[2]) > 0 | |
3206 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
3207 "#" | |
3208 "&& reload_completed" | |
3209 [(parallel | |
3210 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) | |
3211 (clobber (reg:CC CC_REGNUM))]) | |
3212 (parallel | |
3213 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3214 (clobber (reg:CC CC_REGNUM))])] | |
3215 { | |
3216 int bitsize = INTVAL (operands[2]); | |
3217 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3218 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3219 | |
3220 operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3221 set_mem_size (operands[1], GEN_INT (size)); | |
3222 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
3223 operands[3] = GEN_INT (mask); | |
3224 }) | |
3225 | |
3226 ; | |
3227 ; insv instruction patterns | |
3228 ; | |
3229 | |
3230 (define_expand "insv" | |
3231 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3232 (match_operand 1 "const_int_operand" "") | |
3233 (match_operand 2 "const_int_operand" "")) | |
3234 (match_operand 3 "general_operand" ""))] | |
3235 "" | |
3236 { | |
3237 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) | |
3238 DONE; | |
3239 FAIL; | |
3240 }) | |
3241 | |
3242 (define_insn "*insv<mode>_z10" | |
3243 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
3244 (match_operand 1 "const_int_operand" "I") | |
3245 (match_operand 2 "const_int_operand" "I")) | |
3246 (match_operand:GPR 3 "nonimmediate_operand" "d")) | |
3247 (clobber (reg:CC CC_REGNUM))] | |
3248 "TARGET_Z10 | |
3249 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= | |
3250 GET_MODE_BITSIZE (<MODE>mode)" | |
3251 { | |
3252 int start = INTVAL (operands[2]); | |
3253 int size = INTVAL (operands[1]); | |
3254 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode); | |
3255 | |
3256 operands[2] = GEN_INT (offset + start); /* start bit position */ | |
3257 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */ | |
3258 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - | |
3259 start - size); /* left shift count */ | |
3260 | |
3261 return "risbg\t%0,%3,%b2,%b1,%b4"; | |
3262 } | |
3263 [(set_attr "op_type" "RIE") | |
3264 (set_attr "z10prop" "z10_super_E1")]) | |
3265 | |
3266 ; and op1 with a mask being 1 for the selected bits and 0 for the rest | |
3267 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3268 (define_insn "*insv<mode>_z10_noshift" | |
3269 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3270 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3271 (match_operand 2 "const_int_operand" "n")) | |
3272 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") | |
3273 (match_operand 4 "const_int_operand" "n")))) | |
3274 (clobber (reg:CC CC_REGNUM))] | |
3275 "TARGET_Z10 | |
3276 && s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3277 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL) | |
3278 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))" | |
3279 | |
3280 { | |
3281 int start; | |
3282 int size; | |
3283 | |
3284 s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3285 GET_MODE_BITSIZE (<MODE>mode), &start, &size); | |
3286 | |
3287 operands[5] = GEN_INT (64 - start - size); /* start bit position */ | |
3288 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */ | |
3289 operands[7] = const0_rtx; /* left shift count */ | |
3290 | |
3291 return "risbg\t%0,%1,%b5,%b6,%b7"; | |
3292 } | |
3293 [(set_attr "op_type" "RIE") | |
3294 (set_attr "z10prop" "z10_super_E1")]) | |
3295 | |
3296 ; and op1 with a mask being 1 for the selected bits and 0 for the rest | |
3297 (define_insn "*insv<mode>_or_z10_noshift" | |
3298 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3299 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3300 (match_operand 2 "const_int_operand" "n")) | |
3301 (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
3302 (clobber (reg:CC CC_REGNUM))] | |
3303 "TARGET_Z10 | |
3304 && s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3305 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)" | |
3306 { | |
3307 int start; | |
3308 int size; | |
3309 | |
3310 s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3311 GET_MODE_BITSIZE (<MODE>mode), &start, &size); | |
3312 | |
3313 operands[4] = GEN_INT (64 - start - size); /* start bit position */ | |
3314 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */ | |
3315 operands[6] = const0_rtx; /* left shift count */ | |
3316 | |
3317 return "rosbg\t%0,%1,%b4,%b5,%b6"; | |
3318 } | |
3319 [(set_attr "op_type" "RIE")]) | |
3320 | |
3321 (define_insn "*insv<mode>_mem_reg" | |
3322 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S") | |
3323 (match_operand 1 "const_int_operand" "n,n") | |
3324 (const_int 0)) | |
3325 (match_operand:P 2 "register_operand" "d,d"))] | |
3326 "INTVAL (operands[1]) > 0 | |
3327 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3328 && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3329 { | |
3330 int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3331 | |
3332 operands[1] = GEN_INT ((1ul << size) - 1); | |
3333 return (which_alternative == 0) ? "stcm\t%2,%1,%S0" | |
3334 : "stcmy\t%2,%1,%S0"; | |
3335 } | |
3336 [(set_attr "op_type" "RS,RSY") | |
3337 (set_attr "z10prop" "z10_super,z10_super")]) | |
3338 | |
3339 (define_insn "*insvdi_mem_reghigh" | |
3340 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
3341 (match_operand 1 "const_int_operand" "n") | |
3342 (const_int 0)) | |
3343 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
3344 (const_int 32)))] | |
3345 "TARGET_64BIT | |
3346 && INTVAL (operands[1]) > 0 | |
3347 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3348 && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3349 { | |
3350 int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3351 | |
3352 operands[1] = GEN_INT ((1ul << size) - 1); | |
3353 return "stcmh\t%2,%1,%S0"; | |
3354 } | |
3355 [(set_attr "op_type" "RSY") | |
3356 (set_attr "z10prop" "z10_super")]) | |
3357 | |
3358 (define_insn "*insv<mode>_reg_imm" | |
3359 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") | |
3360 (const_int 16) | |
3361 (match_operand 1 "const_int_operand" "n")) | |
3362 (match_operand:P 2 "const_int_operand" "n"))] | |
3363 "TARGET_ZARCH | |
3364 && INTVAL (operands[1]) >= 0 | |
3365 && INTVAL (operands[1]) < BITS_PER_WORD | |
3366 && INTVAL (operands[1]) % 16 == 0" | |
3367 { | |
3368 switch (BITS_PER_WORD - INTVAL (operands[1])) | |
3369 { | |
3370 case 64: return "iihh\t%0,%x2"; break; | |
3371 case 48: return "iihl\t%0,%x2"; break; | |
3372 case 32: return "iilh\t%0,%x2"; break; | |
3373 case 16: return "iill\t%0,%x2"; break; | |
3374 default: gcc_unreachable(); | |
3375 } | |
3376 } | |
3377 [(set_attr "op_type" "RI") | |
3378 (set_attr "z10prop" "z10_super_E1")]) | |
3379 | |
3380 ; Update the left-most 32 bit of a DI. | |
3381 (define_insn "*insv_h_di_reg_extimm" | |
3382 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3383 (const_int 32) | |
3384 (const_int 0)) | |
3385 (match_operand:DI 1 "const_int_operand" "n"))] | |
3386 "TARGET_EXTIMM" | |
3387 "iihf\t%0,%o1" | |
3388 [(set_attr "op_type" "RIL") | |
3389 (set_attr "z10prop" "z10_fwd_E1")]) | |
3390 | |
3391 ; Update the right-most 32 bit of a DI, or the whole of a SI. | |
3392 (define_insn "*insv_l<mode>_reg_extimm" | |
3393 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") | |
3394 (const_int 32) | |
3395 (match_operand 1 "const_int_operand" "n")) | |
3396 (match_operand:P 2 "const_int_operand" "n"))] | |
3397 "TARGET_EXTIMM | |
3398 && BITS_PER_WORD - INTVAL (operands[1]) == 32" | |
3399 "iilf\t%0,%o2" | |
3400 [(set_attr "op_type" "RIL") | |
3401 (set_attr "z10prop" "z10_fwd_A1")]) | |
3402 | |
3403 ; | |
3404 ; extendsidi2 instruction pattern(s). | |
3405 ; | |
3406 | |
3407 (define_expand "extendsidi2" | |
3408 [(set (match_operand:DI 0 "register_operand" "") | |
3409 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3410 "" | |
3411 { | |
3412 if (!TARGET_64BIT) | |
3413 { | |
3414 emit_clobber (operands[0]); | |
3415 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
3416 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
3417 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
3418 DONE; | |
3419 } | |
3420 }) | |
3421 | |
3422 (define_insn "*extendsidi2" | |
3423 [(set (match_operand:DI 0 "register_operand" "=d,d,d") | |
3424 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
3425 "TARGET_64BIT" | |
3426 "@ | |
3427 lgfr\t%0,%1 | |
3428 lgf\t%0,%1 | |
3429 lgfrl\t%0,%1" | |
3430 [(set_attr "op_type" "RRE,RXY,RIL") | |
3431 (set_attr "type" "*,*,larl") | |
3432 (set_attr "cpu_facility" "*,*,z10") | |
3433 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
3434 | |
3435 ; | |
3436 ; extend(hi|qi)(si|di)2 instruction pattern(s). | |
3437 ; | |
3438 | |
3439 (define_expand "extend<HQI:mode><DSI:mode>2" | |
3440 [(set (match_operand:DSI 0 "register_operand" "") | |
3441 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
3442 "" | |
3443 { | |
3444 if (<DSI:MODE>mode == DImode && !TARGET_64BIT) | |
3445 { | |
3446 rtx tmp = gen_reg_rtx (SImode); | |
3447 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); | |
3448 emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
3449 DONE; | |
3450 } | |
3451 else if (!TARGET_EXTIMM) | |
3452 { | |
3453 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) - | |
3454 GET_MODE_BITSIZE (<HQI:MODE>mode)); | |
3455 | |
3456 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
3457 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
3458 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
3459 DONE; | |
3460 } | |
3461 }) | |
3462 | |
3463 ; | |
3464 ; extendhidi2 instruction pattern(s). | |
3465 ; | |
3466 | |
3467 (define_insn "*extendhidi2_extimm" | |
3468 [(set (match_operand:DI 0 "register_operand" "=d,d,d") | |
3469 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
3470 "TARGET_64BIT && TARGET_EXTIMM" | |
3471 "@ | |
3472 lghr\t%0,%1 | |
3473 lgh\t%0,%1 | |
3474 lghrl\t%0,%1" | |
3475 [(set_attr "op_type" "RRE,RXY,RIL") | |
3476 (set_attr "type" "*,*,larl") | |
3477 (set_attr "cpu_facility" "extimm,extimm,z10") | |
3478 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
3479 | |
3480 (define_insn "*extendhidi2" | |
3481 [(set (match_operand:DI 0 "register_operand" "=d") | |
3482 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] | |
3483 "TARGET_64BIT" | |
3484 "lgh\t%0,%1" | |
3485 [(set_attr "op_type" "RXY") | |
3486 (set_attr "z10prop" "z10_super_E1")]) | |
3487 | |
3488 ; | |
3489 ; extendhisi2 instruction pattern(s). | |
3490 ; | |
3491 | |
3492 (define_insn "*extendhisi2_extimm" | |
3493 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") | |
3494 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
3495 "TARGET_EXTIMM" | |
3496 "@ | |
3497 lhr\t%0,%1 | |
3498 lh\t%0,%1 | |
3499 lhy\t%0,%1 | |
3500 lhrl\t%0,%1" | |
3501 [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
3502 (set_attr "type" "*,*,*,larl") | |
3503 (set_attr "cpu_facility" "extimm,extimm,extimm,z10") | |
3504 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
3505 | |
3506 (define_insn "*extendhisi2" | |
3507 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3508 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
3509 "!TARGET_EXTIMM" | |
3510 "@ | |
3511 lh\t%0,%1 | |
3512 lhy\t%0,%1" | |
3513 [(set_attr "op_type" "RX,RXY") | |
3514 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3515 | |
3516 ; | |
3517 ; extendqi(si|di)2 instruction pattern(s). | |
3518 ; | |
3519 | |
3520 ; lbr, lgbr, lb, lgb | |
3521 (define_insn "*extendqi<mode>2_extimm" | |
3522 [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3523 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] | |
3524 "TARGET_EXTIMM" | |
3525 "@ | |
3526 l<g>br\t%0,%1 | |
3527 l<g>b\t%0,%1" | |
3528 [(set_attr "op_type" "RRE,RXY") | |
3529 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3530 | |
3531 ; lb, lgb | |
3532 (define_insn "*extendqi<mode>2" | |
3533 [(set (match_operand:GPR 0 "register_operand" "=d") | |
3534 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] | |
3535 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" | |
3536 "l<g>b\t%0,%1" | |
3537 [(set_attr "op_type" "RXY") | |
3538 (set_attr "z10prop" "z10_super_E1")]) | |
3539 | |
3540 (define_insn_and_split "*extendqi<mode>2_short_displ" | |
3541 [(set (match_operand:GPR 0 "register_operand" "=d") | |
3542 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
3543 (clobber (reg:CC CC_REGNUM))] | |
3544 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" | |
3545 "#" | |
3546 "&& reload_completed" | |
3547 [(parallel | |
3548 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) | |
3549 (clobber (reg:CC CC_REGNUM))]) | |
3550 (parallel | |
3551 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3552 (clobber (reg:CC CC_REGNUM))])] | |
3553 { | |
3554 operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3555 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode))); | |
3556 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) | |
3557 - GET_MODE_BITSIZE (QImode)); | |
3558 }) | |
3559 | |
3560 ; | |
3561 ; zero_extendsidi2 instruction pattern(s). | |
3562 ; | |
3563 | |
3564 (define_expand "zero_extendsidi2" | |
3565 [(set (match_operand:DI 0 "register_operand" "") | |
3566 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3567 "" | |
3568 { | |
3569 if (!TARGET_64BIT) | |
3570 { | |
3571 emit_clobber (operands[0]); | |
3572 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
3573 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
3574 DONE; | |
3575 } | |
3576 }) | |
3577 | |
3578 (define_insn "*zero_extendsidi2" | |
3579 [(set (match_operand:DI 0 "register_operand" "=d,d,d") | |
3580 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
3581 "TARGET_64BIT" | |
3582 "@ | |
3583 llgfr\t%0,%1 | |
3584 llgf\t%0,%1 | |
3585 llgfrl\t%0,%1" | |
3586 [(set_attr "op_type" "RRE,RXY,RIL") | |
3587 (set_attr "type" "*,*,larl") | |
3588 (set_attr "cpu_facility" "*,*,z10") | |
3589 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
3590 | |
3591 ; | |
3592 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
3593 ; | |
3594 | |
3595 (define_insn "*llgt_sidi" | |
3596 [(set (match_operand:DI 0 "register_operand" "=d") | |
3597 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) | |
3598 (const_int 2147483647)))] | |
3599 "TARGET_64BIT" | |
3600 "llgt\t%0,%1" | |
3601 [(set_attr "op_type" "RXE") | |
3602 (set_attr "z10prop" "z10_super_E1")]) | |
3603 | |
3604 (define_insn_and_split "*llgt_sidi_split" | |
3605 [(set (match_operand:DI 0 "register_operand" "=d") | |
3606 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) | |
3607 (const_int 2147483647))) | |
3608 (clobber (reg:CC CC_REGNUM))] | |
3609 "TARGET_64BIT" | |
3610 "#" | |
3611 "&& reload_completed" | |
3612 [(set (match_dup 0) | |
3613 (and:DI (subreg:DI (match_dup 1) 0) | |
3614 (const_int 2147483647)))] | |
3615 "") | |
3616 | |
3617 (define_insn "*llgt_sisi" | |
3618 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3619 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") | |
3620 (const_int 2147483647)))] | |
3621 "TARGET_ZARCH" | |
3622 "@ | |
3623 llgtr\t%0,%1 | |
3624 llgt\t%0,%1" | |
3625 [(set_attr "op_type" "RRE,RXE") | |
3626 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3627 | |
3628 (define_insn "*llgt_didi" | |
3629 [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3630 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
3631 (const_int 2147483647)))] | |
3632 "TARGET_64BIT" | |
3633 "@ | |
3634 llgtr\t%0,%1 | |
3635 llgt\t%0,%N1" | |
3636 [(set_attr "op_type" "RRE,RXE") | |
3637 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3638 | |
3639 (define_split | |
3640 [(set (match_operand:GPR 0 "register_operand" "") | |
3641 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
3642 (const_int 2147483647))) | |
3643 (clobber (reg:CC CC_REGNUM))] | |
3644 "TARGET_ZARCH && reload_completed" | |
3645 [(set (match_dup 0) | |
3646 (and:GPR (match_dup 1) | |
3647 (const_int 2147483647)))] | |
3648 "") | |
3649 | |
3650 ; | |
3651 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). | |
3652 ; | |
3653 | |
3654 (define_expand "zero_extend<mode>di2" | |
3655 [(set (match_operand:DI 0 "register_operand" "") | |
3656 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
3657 "" | |
3658 { | |
3659 if (!TARGET_64BIT) | |
3660 { | |
3661 rtx tmp = gen_reg_rtx (SImode); | |
3662 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
3663 emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
3664 DONE; | |
3665 } | |
3666 else if (!TARGET_EXTIMM) | |
3667 { | |
3668 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - | |
3669 GET_MODE_BITSIZE(<MODE>mode)); | |
3670 operands[1] = gen_lowpart (DImode, operands[1]); | |
3671 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
3672 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
3673 DONE; | |
3674 } | |
3675 }) | |
3676 | |
3677 (define_expand "zero_extend<mode>si2" | |
3678 [(set (match_operand:SI 0 "register_operand" "") | |
3679 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
3680 "" | |
3681 { | |
3682 if (!TARGET_EXTIMM) | |
3683 { | |
3684 operands[1] = gen_lowpart (SImode, operands[1]); | |
3685 emit_insn (gen_andsi3 (operands[0], operands[1], | |
3686 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); | |
3687 DONE; | |
3688 } | |
3689 }) | |
3690 | |
3691 ; llhrl, llghrl | |
3692 (define_insn "*zero_extendhi<mode>2_z10" | |
3693 [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3694 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
3695 "TARGET_Z10" | |
3696 "@ | |
3697 ll<g>hr\t%0,%1 | |
3698 ll<g>h\t%0,%1 | |
3699 ll<g>hrl\t%0,%1" | |
3700 [(set_attr "op_type" "RXY,RRE,RIL") | |
3701 (set_attr "type" "*,*,larl") | |
3702 (set_attr "cpu_facility" "*,*,z10") | |
3703 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) | |
3704 | |
3705 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc | |
3706 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" | |
3707 [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3708 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] | |
3709 "TARGET_EXTIMM" | |
3710 "@ | |
3711 ll<g><hc>r\t%0,%1 | |
3712 ll<g><hc>\t%0,%1" | |
3713 [(set_attr "op_type" "RRE,RXY") | |
3714 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
3715 | |
3716 ; llgh, llgc | |
3717 (define_insn "*zero_extend<HQI:mode><GPR:mode>2" | |
3718 [(set (match_operand:GPR 0 "register_operand" "=d") | |
3719 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] | |
3720 "TARGET_ZARCH && !TARGET_EXTIMM" | |
3721 "llg<hc>\t%0,%1" | |
3722 [(set_attr "op_type" "RXY") | |
3723 (set_attr "z10prop" "z10_fwd_A3")]) | |
3724 | |
3725 (define_insn_and_split "*zero_extendhisi2_31" | |
3726 [(set (match_operand:SI 0 "register_operand" "=&d") | |
3727 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) | |
3728 (clobber (reg:CC CC_REGNUM))] | |
3729 "!TARGET_ZARCH" | |
3730 "#" | |
3731 "&& reload_completed" | |
3732 [(set (match_dup 0) (const_int 0)) | |
3733 (parallel | |
3734 [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
3735 (clobber (reg:CC CC_REGNUM))])] | |
3736 "operands[2] = gen_lowpart (HImode, operands[0]);") | |
3737 | |
3738 (define_insn_and_split "*zero_extendqisi2_31" | |
3739 [(set (match_operand:SI 0 "register_operand" "=&d") | |
3740 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] | |
3741 "!TARGET_ZARCH" | |
3742 "#" | |
3743 "&& reload_completed" | |
3744 [(set (match_dup 0) (const_int 0)) | |
3745 (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
3746 "operands[2] = gen_lowpart (QImode, operands[0]);") | |
3747 | |
3748 ; | |
3749 ; zero_extendqihi2 instruction pattern(s). | |
3750 ; | |
3751 | |
3752 (define_expand "zero_extendqihi2" | |
3753 [(set (match_operand:HI 0 "register_operand" "") | |
3754 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] | |
3755 "TARGET_ZARCH && !TARGET_EXTIMM" | |
3756 { | |
3757 operands[1] = gen_lowpart (HImode, operands[1]); | |
3758 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
3759 DONE; | |
3760 }) | |
3761 | |
3762 (define_insn "*zero_extendqihi2_64" | |
3763 [(set (match_operand:HI 0 "register_operand" "=d") | |
3764 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] | |
3765 "TARGET_ZARCH && !TARGET_EXTIMM" | |
3766 "llgc\t%0,%1" | |
3767 [(set_attr "op_type" "RXY") | |
3768 (set_attr "z10prop" "z10_fwd_A3")]) | |
3769 | |
3770 (define_insn_and_split "*zero_extendqihi2_31" | |
3771 [(set (match_operand:HI 0 "register_operand" "=&d") | |
3772 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] | |
3773 "!TARGET_ZARCH" | |
3774 "#" | |
3775 "&& reload_completed" | |
3776 [(set (match_dup 0) (const_int 0)) | |
3777 (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
3778 "operands[2] = gen_lowpart (QImode, operands[0]);") | |
3779 | |
3780 ; | |
3781 ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
3782 ; | |
3783 | |
3784 (define_expand "fixuns_truncdddi2" | |
3785 [(parallel | |
3786 [(set (match_operand:DI 0 "register_operand" "") | |
3787 (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
3788 (clobber (match_scratch:TD 2 "=f"))])] | |
3789 | |
3790 "TARGET_HARD_DFP" | |
3791 { | |
3792 rtx label1 = gen_label_rtx (); | |
3793 rtx label2 = gen_label_rtx (); | |
3794 rtx temp = gen_reg_rtx (TDmode); | |
3795 REAL_VALUE_TYPE cmp, sub; | |
3796 | |
3797 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3798 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
3799 | |
3800 /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
3801 solution is doing the check and the subtraction in TD mode and using a | |
3802 TD -> DI convert afterwards. */ | |
3803 emit_insn (gen_extendddtd2 (temp, operands[1])); | |
3804 temp = force_reg (TDmode, temp); | |
3805 emit_insn (gen_cmptd (temp, | |
3806 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode))); | |
3807 emit_jump_insn (gen_blt (label1)); | |
3808 emit_insn (gen_subtd3 (temp, temp, | |
3809 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
3810 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
3811 emit_jump (label2); | |
3812 | |
3813 emit_label (label1); | |
3814 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
3815 emit_label (label2); | |
3816 DONE; | |
3817 }) | |
3818 | |
3819 (define_expand "fixuns_trunctddi2" | |
3820 [(set (match_operand:DI 0 "register_operand" "") | |
3821 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))] | |
3822 "TARGET_HARD_DFP" | |
3823 { | |
3824 rtx label1 = gen_label_rtx (); | |
3825 rtx label2 = gen_label_rtx (); | |
3826 rtx temp = gen_reg_rtx (TDmode); | |
3827 REAL_VALUE_TYPE cmp, sub; | |
3828 | |
3829 operands[1] = force_reg (TDmode, operands[1]); | |
3830 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3831 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
3832 | |
3833 emit_insn (gen_cmptd (operands[1], | |
3834 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode))); | |
3835 emit_jump_insn (gen_blt (label1)); | |
3836 emit_insn (gen_subtd3 (temp, operands[1], | |
3837 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
3838 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
3839 emit_jump (label2); | |
3840 | |
3841 emit_label (label1); | |
3842 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
3843 emit_label (label2); | |
3844 DONE; | |
3845 }) | |
3846 | |
3847 ; | |
3848 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 | |
3849 ; instruction pattern(s). | |
3850 ; | |
3851 | |
3852 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" | |
3853 [(set (match_operand:GPR 0 "register_operand" "") | |
3854 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))] | |
3855 "TARGET_HARD_FLOAT" | |
3856 { | |
3857 rtx label1 = gen_label_rtx (); | |
3858 rtx label2 = gen_label_rtx (); | |
3859 rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
3860 REAL_VALUE_TYPE cmp, sub; | |
3861 | |
3862 operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
3863 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); | |
3864 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); | |
3865 | |
3866 emit_insn (gen_cmp<BFP:mode> (operands[1], | |
3867 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode))); | |
3868 emit_jump_insn (gen_blt (label1)); | |
3869 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
3870 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); | |
3871 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
3872 GEN_INT (7))); | |
3873 emit_jump (label2); | |
3874 | |
3875 emit_label (label1); | |
3876 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
3877 operands[1], GEN_INT (5))); | |
3878 emit_label (label2); | |
3879 DONE; | |
3880 }) | |
3881 | |
3882 (define_expand "fix_trunc<DSF:mode><GPR:mode>2" | |
3883 [(set (match_operand:GPR 0 "register_operand" "") | |
3884 (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
3885 "TARGET_HARD_FLOAT" | |
3886 { | |
3887 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], | |
3888 GEN_INT (5))); | |
3889 DONE; | |
3890 }) | |
3891 | |
3892 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr | |
3893 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp" | |
3894 [(set (match_operand:GPR 0 "register_operand" "=d") | |
3895 (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
3896 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
3897 (clobber (reg:CC CC_REGNUM))] | |
3898 "TARGET_HARD_FLOAT" | |
3899 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" | |
3900 [(set_attr "op_type" "RRE") | |
3901 (set_attr "type" "ftoi")]) | |
3902 | |
3903 | |
3904 ; | |
3905 ; fix_trunc(td|dd)di2 instruction pattern(s). | |
3906 ; | |
3907 | |
3908 (define_expand "fix_trunc<mode>di2" | |
3909 [(set (match_operand:DI 0 "register_operand" "") | |
3910 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
3911 "TARGET_64BIT && TARGET_HARD_DFP" | |
3912 { | |
3913 operands[1] = force_reg (<MODE>mode, operands[1]); | |
3914 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
3915 GEN_INT (9))); | |
3916 DONE; | |
3917 }) | |
3918 | |
3919 ; cgxtr, cgdtr | |
3920 (define_insn "fix_trunc<DFP:mode>di2_dfp" | |
3921 [(set (match_operand:DI 0 "register_operand" "=d") | |
3922 (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
3923 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
3924 (clobber (reg:CC CC_REGNUM))] | |
3925 "TARGET_64BIT && TARGET_HARD_DFP" | |
3926 "cg<DFP:xde>tr\t%0,%h2,%1" | |
3927 [(set_attr "op_type" "RRF") | |
3928 (set_attr "type" "ftoidfp")]) | |
3929 | |
3930 | |
3931 ; | |
3932 ; fix_trunctf(si|di)2 instruction pattern(s). | |
3933 ; | |
3934 | |
3935 (define_expand "fix_trunctf<mode>2" | |
3936 [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
3937 (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
3938 (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
3939 (clobber (reg:CC CC_REGNUM))])] | |
3940 "TARGET_HARD_FLOAT" | |
3941 "") | |
3942 | |
3943 | |
3944 ; | |
3945 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
3946 ; | |
3947 | |
3948 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr | |
3949 (define_insn "floatdi<mode>2" | |
3950 [(set (match_operand:FP 0 "register_operand" "=f") | |
3951 (float:FP (match_operand:DI 1 "register_operand" "d")))] | |
3952 "TARGET_64BIT && TARGET_HARD_FLOAT" | |
3953 "c<xde>g<bt>r\t%0,%1" | |
3954 [(set_attr "op_type" "RRE") | |
3955 (set_attr "type" "itof<mode>" )]) | |
3956 | |
3957 ; cxfbr, cdfbr, cefbr | |
3958 (define_insn "floatsi<mode>2" | |
3959 [(set (match_operand:BFP 0 "register_operand" "=f") | |
3960 (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
3961 "TARGET_HARD_FLOAT" | |
3962 "c<xde>fbr\t%0,%1" | |
3963 [(set_attr "op_type" "RRE") | |
3964 (set_attr "type" "itof<mode>" )]) | |
3965 | |
3966 | |
3967 ; | |
3968 ; truncdfsf2 instruction pattern(s). | |
3969 ; | |
3970 | |
3971 (define_insn "truncdfsf2" | |
3972 [(set (match_operand:SF 0 "register_operand" "=f") | |
3973 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] | |
3974 "TARGET_HARD_FLOAT" | |
3975 "ledbr\t%0,%1" | |
3976 [(set_attr "op_type" "RRE") | |
3977 (set_attr "type" "ftruncdf")]) | |
3978 | |
3979 ; | |
3980 ; trunctf(df|sf)2 instruction pattern(s). | |
3981 ; | |
3982 | |
3983 ; ldxbr, lexbr | |
3984 (define_insn "trunctf<mode>2" | |
3985 [(set (match_operand:DSF 0 "register_operand" "=f") | |
3986 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
3987 (clobber (match_scratch:TF 2 "=f"))] | |
3988 "TARGET_HARD_FLOAT" | |
3989 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
3990 [(set_attr "length" "6") | |
3991 (set_attr "type" "ftrunctf")]) | |
3992 | |
3993 ; | |
3994 ; trunctddd2 and truncddsd2 instruction pattern(s). | |
3995 ; | |
3996 | |
3997 (define_insn "trunctddd2" | |
3998 [(set (match_operand:DD 0 "register_operand" "=f") | |
3999 (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) | |
4000 (clobber (match_scratch:TD 2 "=f"))] | |
4001 "TARGET_HARD_DFP" | |
4002 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" | |
4003 [(set_attr "length" "6") | |
4004 (set_attr "type" "ftruncdd")]) | |
4005 | |
4006 (define_insn "truncddsd2" | |
4007 [(set (match_operand:SD 0 "register_operand" "=f") | |
4008 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
4009 "TARGET_HARD_DFP" | |
4010 "ledtr\t%0,0,%1,0" | |
4011 [(set_attr "op_type" "RRF") | |
4012 (set_attr "type" "ftruncsd")]) | |
4013 | |
4014 ; | |
4015 ; extend(sf|df)(df|tf)2 instruction pattern(s). | |
4016 ; | |
4017 | |
4018 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb | |
4019 (define_insn "extend<DSF:mode><BFP:mode>2" | |
4020 [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
4021 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] | |
4022 "TARGET_HARD_FLOAT | |
4023 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)" | |
4024 "@ | |
4025 l<BFP:xde><DSF:xde>br\t%0,%1 | |
4026 l<BFP:xde><DSF:xde>b\t%0,%1" | |
4027 [(set_attr "op_type" "RRE,RXE") | |
4028 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
4029 | |
4030 ; | |
4031 ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4032 ; | |
4033 | |
4034 (define_insn "extendddtd2" | |
4035 [(set (match_operand:TD 0 "register_operand" "=f") | |
4036 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
4037 "TARGET_HARD_DFP" | |
4038 "lxdtr\t%0,%1,0" | |
4039 [(set_attr "op_type" "RRF") | |
4040 (set_attr "type" "fsimptf")]) | |
4041 | |
4042 (define_insn "extendsddd2" | |
4043 [(set (match_operand:DD 0 "register_operand" "=f") | |
4044 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
4045 "TARGET_HARD_DFP" | |
4046 "ldetr\t%0,%1,0" | |
4047 [(set_attr "op_type" "RRF") | |
4048 (set_attr "type" "fsimptf")]) | |
4049 | |
4050 ; Binary <-> Decimal floating point trunc patterns | |
4051 ; | |
4052 | |
4053 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
4054 [(set (reg:DFP_ALL FPR0_REGNUM) | |
4055 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4056 (use (reg:SI GPR0_REGNUM)) | |
4057 (clobber (reg:CC CC_REGNUM))] | |
4058 "TARGET_HARD_DFP" | |
4059 "pfpo") | |
4060 | |
4061 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
4062 [(set (reg:BFP FPR0_REGNUM) | |
4063 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4064 (use (reg:SI GPR0_REGNUM)) | |
4065 (clobber (reg:CC CC_REGNUM))] | |
4066 "TARGET_HARD_DFP" | |
4067 "pfpo") | |
4068 | |
4069 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
4070 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4071 (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4072 (parallel | |
4073 [(set (reg:DFP_ALL FPR0_REGNUM) | |
4074 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4075 (use (reg:SI GPR0_REGNUM)) | |
4076 (clobber (reg:CC CC_REGNUM))]) | |
4077 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4078 (reg:DFP_ALL FPR0_REGNUM))] | |
4079 "TARGET_HARD_DFP | |
4080 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" | |
4081 { | |
4082 HOST_WIDE_INT flags; | |
4083 | |
4084 flags = (PFPO_CONVERT | | |
4085 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4086 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4087 | |
4088 operands[2] = GEN_INT (flags); | |
4089 }) | |
4090 | |
4091 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
4092 [(set (reg:DFP_ALL FPR2_REGNUM) | |
4093 (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4094 (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4095 (parallel | |
4096 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4097 (use (reg:SI GPR0_REGNUM)) | |
4098 (clobber (reg:CC CC_REGNUM))]) | |
4099 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
4100 "TARGET_HARD_DFP | |
4101 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" | |
4102 { | |
4103 HOST_WIDE_INT flags; | |
4104 | |
4105 flags = (PFPO_CONVERT | | |
4106 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4107 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4108 | |
4109 operands[2] = GEN_INT (flags); | |
4110 }) | |
4111 | |
4112 ; | |
4113 ; Binary <-> Decimal floating point extend patterns | |
4114 ; | |
4115 | |
4116 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
4117 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4118 (use (reg:SI GPR0_REGNUM)) | |
4119 (clobber (reg:CC CC_REGNUM))] | |
4120 "TARGET_HARD_DFP" | |
4121 "pfpo") | |
4122 | |
4123 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
4124 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4125 (use (reg:SI GPR0_REGNUM)) | |
4126 (clobber (reg:CC CC_REGNUM))] | |
4127 "TARGET_HARD_DFP" | |
4128 "pfpo") | |
4129 | |
4130 (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
4131 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4132 (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4133 (parallel | |
4134 [(set (reg:DFP_ALL FPR0_REGNUM) | |
4135 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4136 (use (reg:SI GPR0_REGNUM)) | |
4137 (clobber (reg:CC CC_REGNUM))]) | |
4138 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4139 (reg:DFP_ALL FPR0_REGNUM))] | |
4140 "TARGET_HARD_DFP | |
4141 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" | |
4142 { | |
4143 HOST_WIDE_INT flags; | |
4144 | |
4145 flags = (PFPO_CONVERT | | |
4146 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4147 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4148 | |
4149 operands[2] = GEN_INT (flags); | |
4150 }) | |
4151 | |
4152 (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
4153 [(set (reg:DFP_ALL FPR2_REGNUM) | |
4154 (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4155 (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4156 (parallel | |
4157 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4158 (use (reg:SI GPR0_REGNUM)) | |
4159 (clobber (reg:CC CC_REGNUM))]) | |
4160 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
4161 "TARGET_HARD_DFP | |
4162 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" | |
4163 { | |
4164 HOST_WIDE_INT flags; | |
4165 | |
4166 flags = (PFPO_CONVERT | | |
4167 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4168 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4169 | |
4170 operands[2] = GEN_INT (flags); | |
4171 }) | |
4172 | |
4173 | |
4174 ;; | |
4175 ;; ARITHMETIC OPERATIONS | |
4176 ;; | |
4177 ; arithmetic operations set the ConditionCode, | |
4178 ; because of unpredictable Bits in Register for Halfword and Byte | |
4179 ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
4180 | |
4181 ;; | |
4182 ;;- Add instructions. | |
4183 ;; | |
4184 | |
4185 ; | |
4186 ; addti3 instruction pattern(s). | |
4187 ; | |
4188 | |
4189 (define_insn_and_split "addti3" | |
4190 [(set (match_operand:TI 0 "register_operand" "=&d") | |
4191 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
4192 (match_operand:TI 2 "general_operand" "do") ) ) | |
4193 (clobber (reg:CC CC_REGNUM))] | |
4194 "TARGET_64BIT" | |
4195 "#" | |
4196 "&& reload_completed" | |
4197 [(parallel | |
4198 [(set (reg:CCL1 CC_REGNUM) | |
4199 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) | |
4200 (match_dup 7))) | |
4201 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
4202 (parallel | |
4203 [(set (match_dup 3) (plus:DI | |
4204 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4205 (match_dup 4)) (match_dup 5))) | |
4206 (clobber (reg:CC CC_REGNUM))])] | |
4207 "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
4208 operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4209 operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4210 operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4211 operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
4212 operands[8] = operand_subword (operands[2], 1, 0, TImode);") | |
4213 | |
4214 ; | |
4215 ; adddi3 instruction pattern(s). | |
4216 ; | |
4217 | |
4218 (define_expand "adddi3" | |
4219 [(parallel | |
4220 [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
4221 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
4222 (match_operand:DI 2 "general_operand" ""))) | |
4223 (clobber (reg:CC CC_REGNUM))])] | |
4224 "" | |
4225 "") | |
4226 | |
4227 (define_insn "*adddi3_sign" | |
4228 [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4229 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) | |
4230 (match_operand:DI 1 "register_operand" "0,0"))) | |
4231 (clobber (reg:CC CC_REGNUM))] | |
4232 "TARGET_64BIT" | |
4233 "@ | |
4234 agfr\t%0,%2 | |
4235 agf\t%0,%2" | |
4236 [(set_attr "op_type" "RRE,RXY")]) | |
4237 | |
4238 (define_insn "*adddi3_zero_cc" | |
4239 [(set (reg CC_REGNUM) | |
4240 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) | |
4241 (match_operand:DI 1 "register_operand" "0,0")) | |
4242 (const_int 0))) | |
4243 (set (match_operand:DI 0 "register_operand" "=d,d") | |
4244 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
4245 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4246 "@ | |
4247 algfr\t%0,%2 | |
4248 algf\t%0,%2" | |
4249 [(set_attr "op_type" "RRE,RXY") | |
4250 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4251 | |
4252 (define_insn "*adddi3_zero_cconly" | |
4253 [(set (reg CC_REGNUM) | |
4254 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) | |
4255 (match_operand:DI 1 "register_operand" "0,0")) | |
4256 (const_int 0))) | |
4257 (clobber (match_scratch:DI 0 "=d,d"))] | |
4258 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4259 "@ | |
4260 algfr\t%0,%2 | |
4261 algf\t%0,%2" | |
4262 [(set_attr "op_type" "RRE,RXY") | |
4263 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4264 | |
4265 (define_insn "*adddi3_zero" | |
4266 [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4267 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) | |
4268 (match_operand:DI 1 "register_operand" "0,0"))) | |
4269 (clobber (reg:CC CC_REGNUM))] | |
4270 "TARGET_64BIT" | |
4271 "@ | |
4272 algfr\t%0,%2 | |
4273 algf\t%0,%2" | |
4274 [(set_attr "op_type" "RRE,RXY") | |
4275 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4276 | |
4277 (define_insn_and_split "*adddi3_31z" | |
4278 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") | |
4279 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
4280 (match_operand:DI 2 "general_operand" "do") ) ) | |
4281 (clobber (reg:CC CC_REGNUM))] | |
4282 "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4283 "#" | |
4284 "&& reload_completed" | |
4285 [(parallel | |
4286 [(set (reg:CCL1 CC_REGNUM) | |
4287 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
4288 (match_dup 7))) | |
4289 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4290 (parallel | |
4291 [(set (match_dup 3) (plus:SI | |
4292 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4293 (match_dup 4)) (match_dup 5))) | |
4294 (clobber (reg:CC CC_REGNUM))])] | |
4295 "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
4296 operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4297 operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4298 operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4299 operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4300 operands[8] = operand_subword (operands[2], 1, 0, DImode);") | |
4301 | |
4302 (define_insn_and_split "*adddi3_31" | |
4303 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") | |
4304 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
4305 (match_operand:DI 2 "general_operand" "do") ) ) | |
4306 (clobber (reg:CC CC_REGNUM))] | |
4307 "!TARGET_CPU_ZARCH" | |
4308 "#" | |
4309 "&& reload_completed" | |
4310 [(parallel | |
4311 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
4312 (clobber (reg:CC CC_REGNUM))]) | |
4313 (parallel | |
4314 [(set (reg:CCL1 CC_REGNUM) | |
4315 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
4316 (match_dup 7))) | |
4317 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4318 (set (pc) | |
4319 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4320 (pc) | |
4321 (label_ref (match_dup 9)))) | |
4322 (parallel | |
4323 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
4324 (clobber (reg:CC CC_REGNUM))]) | |
4325 (match_dup 9)] | |
4326 "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
4327 operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4328 operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4329 operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4330 operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4331 operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
4332 operands[9] = gen_label_rtx ();") | |
4333 | |
4334 ; | |
4335 ; addsi3 instruction pattern(s). | |
4336 ; | |
4337 | |
4338 (define_expand "addsi3" | |
4339 [(parallel | |
4340 [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
4341 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4342 (match_operand:SI 2 "general_operand" ""))) | |
4343 (clobber (reg:CC CC_REGNUM))])] | |
4344 "" | |
4345 "") | |
4346 | |
4347 (define_insn "*addsi3_sign" | |
4348 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4349 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
4350 (match_operand:SI 1 "register_operand" "0,0"))) | |
4351 (clobber (reg:CC CC_REGNUM))] | |
4352 "" | |
4353 "@ | |
4354 ah\t%0,%2 | |
4355 ahy\t%0,%2" | |
4356 [(set_attr "op_type" "RX,RXY")]) | |
4357 | |
4358 ; | |
4359 ; add(di|si)3 instruction pattern(s). | |
4360 ; | |
4361 | |
4362 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi | |
4363 (define_insn "*add<mode>3" | |
4364 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS") | |
4365 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") | |
4366 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) ) | |
4367 (clobber (reg:CC CC_REGNUM))] | |
4368 "" | |
4369 "@ | |
4370 a<g>r\t%0,%2 | |
4371 a<g>hi\t%0,%h2 | |
4372 al<g>fi\t%0,%2 | |
4373 sl<g>fi\t%0,%n2 | |
4374 a<g>\t%0,%2 | |
4375 a<y>\t%0,%2 | |
4376 a<g>si\t%0,%c2" | |
4377 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY") | |
4378 (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10") | |
4379 (set_attr "z10prop" "z10_super_E1, | |
4380 z10_super_E1, | |
4381 z10_super_E1, | |
4382 z10_super_E1, | |
4383 z10_super_E1, | |
4384 z10_super_E1, | |
4385 z10_super_E1")]) | |
4386 | |
4387 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi | |
4388 (define_insn "*add<mode>3_carry1_cc" | |
4389 [(set (reg CC_REGNUM) | |
4390 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
4391 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) | |
4392 (match_dup 1))) | |
4393 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d") | |
4394 (plus:GPR (match_dup 1) (match_dup 2)))] | |
4395 "s390_match_ccmode (insn, CCL1mode)" | |
4396 "@ | |
4397 al<g>r\t%0,%2 | |
4398 al<g>fi\t%0,%2 | |
4399 sl<g>fi\t%0,%n2 | |
4400 al<g>\t%0,%2 | |
4401 al<y>\t%0,%2 | |
4402 al<g>si\t%0,%c2" | |
4403 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") | |
4404 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") | |
4405 (set_attr "z10prop" "z10_super_E1, | |
4406 z10_super_E1, | |
4407 z10_super_E1, | |
4408 z10_super_E1, | |
4409 z10_super_E1, | |
4410 z10_super_E1")]) | |
4411 | |
4412 ; alr, al, aly, algr, alg | |
4413 (define_insn "*add<mode>3_carry1_cconly" | |
4414 [(set (reg CC_REGNUM) | |
4415 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") | |
4416 (match_operand:GPR 2 "general_operand" "d,R,T")) | |
4417 (match_dup 1))) | |
4418 (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
4419 "s390_match_ccmode (insn, CCL1mode)" | |
4420 "@ | |
4421 al<g>r\t%0,%2 | |
4422 al<g>\t%0,%2 | |
4423 al<y>\t%0,%2" | |
4424 [(set_attr "op_type" "RR<E>,RX<Y>,RXY") | |
4425 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4426 | |
4427 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi | |
4428 (define_insn "*add<mode>3_carry2_cc" | |
4429 [(set (reg CC_REGNUM) | |
4430 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
4431 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) | |
4432 (match_dup 2))) | |
4433 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") | |
4434 (plus:GPR (match_dup 1) (match_dup 2)))] | |
4435 "s390_match_ccmode (insn, CCL1mode)" | |
4436 "@ | |
4437 al<g>r\t%0,%2 | |
4438 al<g>fi\t%0,%2 | |
4439 sl<g>fi\t%0,%n2 | |
4440 al<g>\t%0,%2 | |
4441 al<y>\t%0,%2 | |
4442 al<g>si\t%0,%c2" | |
4443 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") | |
4444 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") | |
4445 (set_attr "z10prop" "z10_super_E1, | |
4446 z10_super_E1, | |
4447 z10_super_E1, | |
4448 z10_super_E1, | |
4449 z10_super_E1, | |
4450 z10_super_E1")]) | |
4451 | |
4452 ; alr, al, aly, algr, alg | |
4453 (define_insn "*add<mode>3_carry2_cconly" | |
4454 [(set (reg CC_REGNUM) | |
4455 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") | |
4456 (match_operand:GPR 2 "general_operand" "d,R,T")) | |
4457 (match_dup 2))) | |
4458 (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
4459 "s390_match_ccmode (insn, CCL1mode)" | |
4460 "@ | |
4461 al<g>r\t%0,%2 | |
4462 al<g>\t%0,%2 | |
4463 al<y>\t%0,%2" | |
4464 [(set_attr "op_type" "RR<E>,RX<Y>,RXY") | |
4465 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4466 | |
4467 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi | |
4468 (define_insn "*add<mode>3_cc" | |
4469 [(set (reg CC_REGNUM) | |
4470 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
4471 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) | |
4472 (const_int 0))) | |
4473 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") | |
4474 (plus:GPR (match_dup 1) (match_dup 2)))] | |
4475 "s390_match_ccmode (insn, CCLmode)" | |
4476 "@ | |
4477 al<g>r\t%0,%2 | |
4478 al<g>fi\t%0,%2 | |
4479 sl<g>fi\t%0,%n2 | |
4480 al<g>\t%0,%2 | |
4481 al<y>\t%0,%2 | |
4482 al<g>si\t%0,%c2" | |
4483 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") | |
4484 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") | |
4485 (set_attr "z10prop" "z10_super_E1, | |
4486 z10_super_E1, | |
4487 z10_super_E1, | |
4488 z10_super_E1, | |
4489 z10_super_E1, | |
4490 z10_super_E1")]) | |
4491 | |
4492 ; alr, al, aly, algr, alg | |
4493 (define_insn "*add<mode>3_cconly" | |
4494 [(set (reg CC_REGNUM) | |
4495 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") | |
4496 (match_operand:GPR 2 "general_operand" "d,R,T")) | |
4497 (const_int 0))) | |
4498 (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
4499 "s390_match_ccmode (insn, CCLmode)" | |
4500 "@ | |
4501 al<g>r\t%0,%2 | |
4502 al<g>\t%0,%2 | |
4503 al<y>\t%0,%2" | |
4504 [(set_attr "op_type" "RR<E>,RX<Y>,RXY") | |
4505 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4506 | |
4507 ; alr, al, aly, algr, alg | |
4508 (define_insn "*add<mode>3_cconly2" | |
4509 [(set (reg CC_REGNUM) | |
4510 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") | |
4511 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T")))) | |
4512 (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
4513 "s390_match_ccmode(insn, CCLmode)" | |
4514 "@ | |
4515 al<g>r\t%0,%2 | |
4516 al<g>\t%0,%2 | |
4517 al<y>\t%0,%2" | |
4518 [(set_attr "op_type" "RR<E>,RX<Y>,RXY") | |
4519 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4520 | |
4521 ; ahi, afi, aghi, agfi, asi, agsi | |
4522 (define_insn "*add<mode>3_imm_cc" | |
4523 [(set (reg CC_REGNUM) | |
4524 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0") | |
4525 (match_operand:GPR 2 "const_int_operand" "K,Os,C")) | |
4526 (const_int 0))) | |
4527 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS") | |
4528 (plus:GPR (match_dup 1) (match_dup 2)))] | |
4529 "s390_match_ccmode (insn, CCAmode) | |
4530 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
4531 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") | |
4532 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\")) | |
4533 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))" | |
4534 "@ | |
4535 a<g>hi\t%0,%h2 | |
4536 a<g>fi\t%0,%2 | |
4537 a<g>si\t%0,%c2" | |
4538 [(set_attr "op_type" "RI,RIL,SIY") | |
4539 (set_attr "cpu_facility" "*,extimm,z10") | |
4540 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4541 | |
4542 ; | |
4543 ; add(tf|df|sf|td|dd)3 instruction pattern(s). | |
4544 ; | |
4545 | |
4546 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr | |
4547 (define_insn "add<mode>3" | |
4548 [(set (match_operand:FP 0 "register_operand" "=f, f") | |
4549 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
4550 (match_operand:FP 2 "general_operand" " f,<Rf>"))) | |
4551 (clobber (reg:CC CC_REGNUM))] | |
4552 "TARGET_HARD_FLOAT" | |
4553 "@ | |
4554 a<xde><bt>r\t%0,<op1>%2 | |
4555 a<xde>b\t%0,%2" | |
4556 [(set_attr "op_type" "<RRer>,RXE") | |
4557 (set_attr "type" "fsimp<mode>")]) | |
4558 | |
4559 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr | |
4560 (define_insn "*add<mode>3_cc" | |
4561 [(set (reg CC_REGNUM) | |
4562 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
4563 (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4564 (match_operand:FP 3 "const0_operand" ""))) | |
4565 (set (match_operand:FP 0 "register_operand" "=f,f") | |
4566 (plus:FP (match_dup 1) (match_dup 2)))] | |
4567 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" | |
4568 "@ | |
4569 a<xde><bt>r\t%0,<op1>%2 | |
4570 a<xde>b\t%0,%2" | |
4571 [(set_attr "op_type" "<RRer>,RXE") | |
4572 (set_attr "type" "fsimp<mode>")]) | |
4573 | |
4574 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr | |
4575 (define_insn "*add<mode>3_cconly" | |
4576 [(set (reg CC_REGNUM) | |
4577 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
4578 (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4579 (match_operand:FP 3 "const0_operand" ""))) | |
4580 (clobber (match_scratch:FP 0 "=f,f"))] | |
4581 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" | |
4582 "@ | |
4583 a<xde><bt>r\t%0,<op1>%2 | |
4584 a<xde>b\t%0,%2" | |
4585 [(set_attr "op_type" "<RRer>,RXE") | |
4586 (set_attr "type" "fsimp<mode>")]) | |
4587 | |
4588 | |
4589 ;; | |
4590 ;;- Subtract instructions. | |
4591 ;; | |
4592 | |
4593 ; | |
4594 ; subti3 instruction pattern(s). | |
4595 ; | |
4596 | |
4597 (define_insn_and_split "subti3" | |
4598 [(set (match_operand:TI 0 "register_operand" "=&d") | |
4599 (minus:TI (match_operand:TI 1 "register_operand" "0") | |
4600 (match_operand:TI 2 "general_operand" "do") ) ) | |
4601 (clobber (reg:CC CC_REGNUM))] | |
4602 "TARGET_64BIT" | |
4603 "#" | |
4604 "&& reload_completed" | |
4605 [(parallel | |
4606 [(set (reg:CCL2 CC_REGNUM) | |
4607 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) | |
4608 (match_dup 7))) | |
4609 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
4610 (parallel | |
4611 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
4612 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) | |
4613 (clobber (reg:CC CC_REGNUM))])] | |
4614 "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
4615 operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4616 operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4617 operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4618 operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
4619 operands[8] = operand_subword (operands[2], 1, 0, TImode);") | |
4620 | |
4621 ; | |
4622 ; subdi3 instruction pattern(s). | |
4623 ; | |
4624 | |
4625 (define_expand "subdi3" | |
4626 [(parallel | |
4627 [(set (match_operand:DI 0 "register_operand" "") | |
4628 (minus:DI (match_operand:DI 1 "register_operand" "") | |
4629 (match_operand:DI 2 "general_operand" ""))) | |
4630 (clobber (reg:CC CC_REGNUM))])] | |
4631 "" | |
4632 "") | |
4633 | |
4634 (define_insn "*subdi3_sign" | |
4635 [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4636 (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
4637 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) | |
4638 (clobber (reg:CC CC_REGNUM))] | |
4639 "TARGET_64BIT" | |
4640 "@ | |
4641 sgfr\t%0,%2 | |
4642 sgf\t%0,%2" | |
4643 [(set_attr "op_type" "RRE,RXY") | |
4644 (set_attr "z10prop" "z10_c,*")]) | |
4645 | |
4646 (define_insn "*subdi3_zero_cc" | |
4647 [(set (reg CC_REGNUM) | |
4648 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
4649 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) | |
4650 (const_int 0))) | |
4651 (set (match_operand:DI 0 "register_operand" "=d,d") | |
4652 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
4653 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4654 "@ | |
4655 slgfr\t%0,%2 | |
4656 slgf\t%0,%2" | |
4657 [(set_attr "op_type" "RRE,RXY") | |
4658 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
4659 | |
4660 (define_insn "*subdi3_zero_cconly" | |
4661 [(set (reg CC_REGNUM) | |
4662 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
4663 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) | |
4664 (const_int 0))) | |
4665 (clobber (match_scratch:DI 0 "=d,d"))] | |
4666 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4667 "@ | |
4668 slgfr\t%0,%2 | |
4669 slgf\t%0,%2" | |
4670 [(set_attr "op_type" "RRE,RXY") | |
4671 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
4672 | |
4673 (define_insn "*subdi3_zero" | |
4674 [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4675 (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
4676 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) | |
4677 (clobber (reg:CC CC_REGNUM))] | |
4678 "TARGET_64BIT" | |
4679 "@ | |
4680 slgfr\t%0,%2 | |
4681 slgf\t%0,%2" | |
4682 [(set_attr "op_type" "RRE,RXY") | |
4683 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
4684 | |
4685 (define_insn_and_split "*subdi3_31z" | |
4686 [(set (match_operand:DI 0 "register_operand" "=&d") | |
4687 (minus:DI (match_operand:DI 1 "register_operand" "0") | |
4688 (match_operand:DI 2 "general_operand" "do") ) ) | |
4689 (clobber (reg:CC CC_REGNUM))] | |
4690 "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4691 "#" | |
4692 "&& reload_completed" | |
4693 [(parallel | |
4694 [(set (reg:CCL2 CC_REGNUM) | |
4695 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
4696 (match_dup 7))) | |
4697 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4698 (parallel | |
4699 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
4700 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) | |
4701 (clobber (reg:CC CC_REGNUM))])] | |
4702 "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
4703 operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4704 operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4705 operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4706 operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4707 operands[8] = operand_subword (operands[2], 1, 0, DImode);") | |
4708 | |
4709 (define_insn_and_split "*subdi3_31" | |
4710 [(set (match_operand:DI 0 "register_operand" "=&d") | |
4711 (minus:DI (match_operand:DI 1 "register_operand" "0") | |
4712 (match_operand:DI 2 "general_operand" "do") ) ) | |
4713 (clobber (reg:CC CC_REGNUM))] | |
4714 "!TARGET_CPU_ZARCH" | |
4715 "#" | |
4716 "&& reload_completed" | |
4717 [(parallel | |
4718 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
4719 (clobber (reg:CC CC_REGNUM))]) | |
4720 (parallel | |
4721 [(set (reg:CCL2 CC_REGNUM) | |
4722 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
4723 (match_dup 7))) | |
4724 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4725 (set (pc) | |
4726 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) | |
4727 (pc) | |
4728 (label_ref (match_dup 9)))) | |
4729 (parallel | |
4730 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
4731 (clobber (reg:CC CC_REGNUM))]) | |
4732 (match_dup 9)] | |
4733 "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
4734 operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4735 operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4736 operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4737 operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4738 operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
4739 operands[9] = gen_label_rtx ();") | |
4740 | |
4741 ; | |
4742 ; subsi3 instruction pattern(s). | |
4743 ; | |
4744 | |
4745 (define_expand "subsi3" | |
4746 [(parallel | |
4747 [(set (match_operand:SI 0 "register_operand" "") | |
4748 (minus:SI (match_operand:SI 1 "register_operand" "") | |
4749 (match_operand:SI 2 "general_operand" ""))) | |
4750 (clobber (reg:CC CC_REGNUM))])] | |
4751 "" | |
4752 "") | |
4753 | |
4754 (define_insn "*subsi3_sign" | |
4755 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4756 (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4757 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
4758 (clobber (reg:CC CC_REGNUM))] | |
4759 "" | |
4760 "@ | |
4761 sh\t%0,%2 | |
4762 shy\t%0,%2" | |
4763 [(set_attr "op_type" "RX,RXY")]) | |
4764 | |
4765 ; | |
4766 ; sub(di|si)3 instruction pattern(s). | |
4767 ; | |
4768 | |
4769 ; sr, s, sy, sgr, sg | |
4770 (define_insn "*sub<mode>3" | |
4771 [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4772 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") | |
4773 (match_operand:GPR 2 "general_operand" "d,R,T") ) ) | |
4774 (clobber (reg:CC CC_REGNUM))] | |
4775 "" | |
4776 "@ | |
4777 s<g>r\t%0,%2 | |
4778 s<g>\t%0,%2 | |
4779 s<y>\t%0,%2" | |
4780 [(set_attr "op_type" "RR<E>,RX<Y>,RXY") | |
4781 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
4782 | |
4783 ; slr, sl, sly, slgr, slg | |
4784 (define_insn "*sub<mode>3_borrow_cc" | |
4785 [(set (reg CC_REGNUM) | |
4786 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") | |
4787 (match_operand:GPR 2 "general_operand" "d,R,T")) | |
4788 (match_dup 1))) | |
4789 (set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4790 (minus:GPR (match_dup 1) (match_dup 2)))] | |
4791 "s390_match_ccmode (insn, CCL2mode)" | |
4792 "@ | |
4793 sl<g>r\t%0,%2 | |
4794 sl<g>\t%0,%2 | |
4795 sl<y>\t%0,%2" | |
4796 [(set_attr "op_type" "RR<E>,RX<Y>,RXY") | |
4797 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
4798 | |
4799 ; slr, sl, sly, slgr, slg | |
4800 (define_insn "*sub<mode>3_borrow_cconly" | |
4801 [(set (reg CC_REGNUM) | |
4802 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") | |
4803 (match_operand:GPR 2 "general_operand" "d,R,T")) | |
4804 (match_dup 1))) | |
4805 (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
4806 "s390_match_ccmode (insn, CCL2mode)" | |
4807 "@ | |
4808 sl<g>r\t%0,%2 | |
4809 sl<g>\t%0,%2 | |
4810 sl<y>\t%0,%2" | |
4811 [(set_attr "op_type" "RR<E>,RX<Y>,RXY") | |
4812 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
4813 | |
4814 ; slr, sl, sly, slgr, slg | |
4815 (define_insn "*sub<mode>3_cc" | |
4816 [(set (reg CC_REGNUM) | |
4817 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") | |
4818 (match_operand:GPR 2 "general_operand" "d,R,T")) | |
4819 (const_int 0))) | |
4820 (set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4821 (minus:GPR (match_dup 1) (match_dup 2)))] | |
4822 "s390_match_ccmode (insn, CCLmode)" | |
4823 "@ | |
4824 sl<g>r\t%0,%2 | |
4825 sl<g>\t%0,%2 | |
4826 sl<y>\t%0,%2" | |
4827 [(set_attr "op_type" "RR<E>,RX<Y>,RXY") | |
4828 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
4829 | |
4830 ; slr, sl, sly, slgr, slg | |
4831 (define_insn "*sub<mode>3_cc2" | |
4832 [(set (reg CC_REGNUM) | |
4833 (compare (match_operand:GPR 1 "register_operand" "0,0,0") | |
4834 (match_operand:GPR 2 "general_operand" "d,R,T"))) | |
4835 (set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4836 (minus:GPR (match_dup 1) (match_dup 2)))] | |
4837 "s390_match_ccmode (insn, CCL3mode)" | |
4838 "@ | |
4839 sl<g>r\t%0,%2 | |
4840 sl<g>\t%0,%2 | |
4841 sl<y>\t%0,%2" | |
4842 [(set_attr "op_type" "RR<E>,RX<Y>,RXY") | |
4843 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
4844 | |
4845 ; slr, sl, sly, slgr, slg | |
4846 (define_insn "*sub<mode>3_cconly" | |
4847 [(set (reg CC_REGNUM) | |
4848 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") | |
4849 (match_operand:GPR 2 "general_operand" "d,R,T")) | |
4850 (const_int 0))) | |
4851 (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
4852 "s390_match_ccmode (insn, CCLmode)" | |
4853 "@ | |
4854 sl<g>r\t%0,%2 | |
4855 sl<g>\t%0,%2 | |
4856 sl<y>\t%0,%2" | |
4857 [(set_attr "op_type" "RR<E>,RX<Y>,RXY") | |
4858 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
4859 | |
4860 | |
4861 ; slr, sl, sly, slgr, slg | |
4862 (define_insn "*sub<mode>3_cconly2" | |
4863 [(set (reg CC_REGNUM) | |
4864 (compare (match_operand:GPR 1 "register_operand" "0,0,0") | |
4865 (match_operand:GPR 2 "general_operand" "d,R,T"))) | |
4866 (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
4867 "s390_match_ccmode (insn, CCL3mode)" | |
4868 "@ | |
4869 sl<g>r\t%0,%2 | |
4870 sl<g>\t%0,%2 | |
4871 sl<y>\t%0,%2" | |
4872 [(set_attr "op_type" "RR<E>,RX<Y>,RXY") | |
4873 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
4874 | |
4875 | |
4876 ; | |
4877 ; sub(tf|df|sf|td|dd)3 instruction pattern(s). | |
4878 ; | |
4879 | |
4880 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr | |
4881 (define_insn "sub<mode>3" | |
4882 [(set (match_operand:FP 0 "register_operand" "=f, f") | |
4883 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
4884 (match_operand:FP 2 "general_operand" "f,<Rf>"))) | |
4885 (clobber (reg:CC CC_REGNUM))] | |
4886 "TARGET_HARD_FLOAT" | |
4887 "@ | |
4888 s<xde><bt>r\t%0,<op1>%2 | |
4889 s<xde>b\t%0,%2" | |
4890 [(set_attr "op_type" "<RRer>,RXE") | |
4891 (set_attr "type" "fsimp<mode>")]) | |
4892 | |
4893 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr | |
4894 (define_insn "*sub<mode>3_cc" | |
4895 [(set (reg CC_REGNUM) | |
4896 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") | |
4897 (match_operand:FP 2 "general_operand" "f,<Rf>")) | |
4898 (match_operand:FP 3 "const0_operand" ""))) | |
4899 (set (match_operand:FP 0 "register_operand" "=f,f") | |
4900 (minus:FP (match_dup 1) (match_dup 2)))] | |
4901 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" | |
4902 "@ | |
4903 s<xde><bt>r\t%0,<op1>%2 | |
4904 s<xde>b\t%0,%2" | |
4905 [(set_attr "op_type" "<RRer>,RXE") | |
4906 (set_attr "type" "fsimp<mode>")]) | |
4907 | |
4908 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr | |
4909 (define_insn "*sub<mode>3_cconly" | |
4910 [(set (reg CC_REGNUM) | |
4911 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") | |
4912 (match_operand:FP 2 "general_operand" "f,<Rf>")) | |
4913 (match_operand:FP 3 "const0_operand" ""))) | |
4914 (clobber (match_scratch:FP 0 "=f,f"))] | |
4915 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" | |
4916 "@ | |
4917 s<xde><bt>r\t%0,<op1>%2 | |
4918 s<xde>b\t%0,%2" | |
4919 [(set_attr "op_type" "<RRer>,RXE") | |
4920 (set_attr "type" "fsimp<mode>")]) | |
4921 | |
4922 | |
4923 ;; | |
4924 ;;- Conditional add/subtract instructions. | |
4925 ;; | |
4926 | |
4927 ; | |
4928 ; add(di|si)cc instruction pattern(s). | |
4929 ; | |
4930 | |
4931 ; the following 4 patterns are used when the result of an add with | |
4932 ; carry is checked for an overflow condition | |
4933 | |
4934 ; op1 + op2 + c < op1 | |
4935 | |
4936 ; alcr, alc, alcgr, alcg | |
4937 (define_insn "*add<mode>3_alc_carry1_cc" | |
4938 [(set (reg CC_REGNUM) | |
4939 (compare | |
4940 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4941 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
4942 (match_operand:GPR 2 "general_operand" "d,RT")) | |
4943 (match_dup 1))) | |
4944 (set (match_operand:GPR 0 "register_operand" "=d,d") | |
4945 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
4946 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4947 "@ | |
4948 alc<g>r\t%0,%2 | |
4949 alc<g>\t%0,%2" | |
4950 [(set_attr "op_type" "RRE,RXY")]) | |
4951 | |
4952 ; alcr, alc, alcgr, alcg | |
4953 (define_insn "*add<mode>3_alc_carry1_cconly" | |
4954 [(set (reg CC_REGNUM) | |
4955 (compare | |
4956 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4957 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
4958 (match_operand:GPR 2 "general_operand" "d,RT")) | |
4959 (match_dup 1))) | |
4960 (clobber (match_scratch:GPR 0 "=d,d"))] | |
4961 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4962 "@ | |
4963 alc<g>r\t%0,%2 | |
4964 alc<g>\t%0,%2" | |
4965 [(set_attr "op_type" "RRE,RXY")]) | |
4966 | |
4967 ; op1 + op2 + c < op2 | |
4968 | |
4969 ; alcr, alc, alcgr, alcg | |
4970 (define_insn "*add<mode>3_alc_carry2_cc" | |
4971 [(set (reg CC_REGNUM) | |
4972 (compare | |
4973 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4974 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
4975 (match_operand:GPR 2 "general_operand" "d,RT")) | |
4976 (match_dup 2))) | |
4977 (set (match_operand:GPR 0 "register_operand" "=d,d") | |
4978 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
4979 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4980 "@ | |
4981 alc<g>r\t%0,%2 | |
4982 alc<g>\t%0,%2" | |
4983 [(set_attr "op_type" "RRE,RXY")]) | |
4984 | |
4985 ; alcr, alc, alcgr, alcg | |
4986 (define_insn "*add<mode>3_alc_carry2_cconly" | |
4987 [(set (reg CC_REGNUM) | |
4988 (compare | |
4989 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4990 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
4991 (match_operand:GPR 2 "general_operand" "d,RT")) | |
4992 (match_dup 2))) | |
4993 (clobber (match_scratch:GPR 0 "=d,d"))] | |
4994 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4995 "@ | |
4996 alc<g>r\t%0,%2 | |
4997 alc<g>\t%0,%2" | |
4998 [(set_attr "op_type" "RRE,RXY")]) | |
4999 | |
5000 ; alcr, alc, alcgr, alcg | |
5001 (define_insn "*add<mode>3_alc_cc" | |
5002 [(set (reg CC_REGNUM) | |
5003 (compare | |
5004 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5005 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
5006 (match_operand:GPR 2 "general_operand" "d,RT")) | |
5007 (const_int 0))) | |
5008 (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5009 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5010 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" | |
5011 "@ | |
5012 alc<g>r\t%0,%2 | |
5013 alc<g>\t%0,%2" | |
5014 [(set_attr "op_type" "RRE,RXY")]) | |
5015 | |
5016 ; alcr, alc, alcgr, alcg | |
5017 (define_insn "*add<mode>3_alc" | |
5018 [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
5019 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5020 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
5021 (match_operand:GPR 2 "general_operand" "d,RT"))) | |
5022 (clobber (reg:CC CC_REGNUM))] | |
5023 "TARGET_CPU_ZARCH" | |
5024 "@ | |
5025 alc<g>r\t%0,%2 | |
5026 alc<g>\t%0,%2" | |
5027 [(set_attr "op_type" "RRE,RXY")]) | |
5028 | |
5029 ; slbr, slb, slbgr, slbg | |
5030 (define_insn "*sub<mode>3_slb_cc" | |
5031 [(set (reg CC_REGNUM) | |
5032 (compare | |
5033 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
5034 (match_operand:GPR 2 "general_operand" "d,RT")) | |
5035 (match_operand:GPR 3 "s390_slb_comparison" "")) | |
5036 (const_int 0))) | |
5037 (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5038 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
5039 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" | |
5040 "@ | |
5041 slb<g>r\t%0,%2 | |
5042 slb<g>\t%0,%2" | |
5043 [(set_attr "op_type" "RRE,RXY") | |
5044 (set_attr "z10prop" "z10_c,*")]) | |
5045 | |
5046 ; slbr, slb, slbgr, slbg | |
5047 (define_insn "*sub<mode>3_slb" | |
5048 [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
5049 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
5050 (match_operand:GPR 2 "general_operand" "d,RT")) | |
5051 (match_operand:GPR 3 "s390_slb_comparison" ""))) | |
5052 (clobber (reg:CC CC_REGNUM))] | |
5053 "TARGET_CPU_ZARCH" | |
5054 "@ | |
5055 slb<g>r\t%0,%2 | |
5056 slb<g>\t%0,%2" | |
5057 [(set_attr "op_type" "RRE,RXY") | |
5058 (set_attr "z10prop" "z10_c,*")]) | |
5059 | |
5060 (define_expand "add<mode>cc" | |
5061 [(match_operand:GPR 0 "register_operand" "") | |
5062 (match_operand 1 "comparison_operator" "") | |
5063 (match_operand:GPR 2 "register_operand" "") | |
5064 (match_operand:GPR 3 "const_int_operand" "")] | |
5065 "TARGET_CPU_ZARCH" | |
5066 "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
5067 s390_compare_op0, s390_compare_op1, | |
5068 operands[0], operands[2], | |
5069 operands[3])) FAIL; DONE;") | |
5070 | |
5071 ; | |
5072 ; scond instruction pattern(s). | |
5073 ; | |
5074 | |
5075 (define_insn_and_split "*scond<mode>" | |
5076 [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5077 (match_operand:GPR 1 "s390_alc_comparison" "")) | |
5078 (clobber (reg:CC CC_REGNUM))] | |
5079 "TARGET_CPU_ZARCH" | |
5080 "#" | |
5081 "&& reload_completed" | |
5082 [(set (match_dup 0) (const_int 0)) | |
5083 (parallel | |
5084 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) | |
5085 (match_dup 0))) | |
5086 (clobber (reg:CC CC_REGNUM))])] | |
5087 "") | |
5088 | |
5089 (define_insn_and_split "*scond<mode>_neg" | |
5090 [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5091 (match_operand:GPR 1 "s390_slb_comparison" "")) | |
5092 (clobber (reg:CC CC_REGNUM))] | |
5093 "TARGET_CPU_ZARCH" | |
5094 "#" | |
5095 "&& reload_completed" | |
5096 [(set (match_dup 0) (const_int 0)) | |
5097 (parallel | |
5098 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) | |
5099 (match_dup 1))) | |
5100 (clobber (reg:CC CC_REGNUM))]) | |
5101 (parallel | |
5102 [(set (match_dup 0) (neg:GPR (match_dup 0))) | |
5103 (clobber (reg:CC CC_REGNUM))])] | |
5104 "") | |
5105 | |
5106 | |
5107 (define_expand "s<code>" | |
5108 [(set (match_operand:SI 0 "register_operand" "") | |
5109 (SCOND (match_dup 0) | |
5110 (match_dup 0)))] | |
5111 "TARGET_CPU_ZARCH" | |
5112 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1, | |
5113 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
5114 | |
5115 (define_expand "seq" | |
5116 [(parallel | |
5117 [(set (match_operand:SI 0 "register_operand" "=d") | |
5118 (match_dup 1)) | |
5119 (clobber (reg:CC CC_REGNUM))]) | |
5120 (parallel | |
5121 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1))) | |
5122 (clobber (reg:CC CC_REGNUM))])] | |
5123 "" | |
5124 { | |
5125 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode) | |
5126 FAIL; | |
5127 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1); | |
5128 PUT_MODE (operands[1], SImode); | |
5129 }) | |
5130 | |
5131 (define_insn_and_split "*sne" | |
5132 [(set (match_operand:SI 0 "register_operand" "=d") | |
5133 (ne:SI (match_operand:CCZ1 1 "register_operand" "0") | |
5134 (const_int 0))) | |
5135 (clobber (reg:CC CC_REGNUM))] | |
5136 "" | |
5137 "#" | |
5138 "reload_completed" | |
5139 [(parallel | |
5140 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
5141 (clobber (reg:CC CC_REGNUM))])]) | |
5142 | |
5143 | |
5144 ;; | |
5145 ;;- Multiply instructions. | |
5146 ;; | |
5147 | |
5148 ; | |
5149 ; muldi3 instruction pattern(s). | |
5150 ; | |
5151 | |
5152 (define_insn "*muldi3_sign" | |
5153 [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5154 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) | |
5155 (match_operand:DI 1 "register_operand" "0,0")))] | |
5156 "TARGET_64BIT" | |
5157 "@ | |
5158 msgfr\t%0,%2 | |
5159 msgf\t%0,%2" | |
5160 [(set_attr "op_type" "RRE,RXY") | |
5161 (set_attr "type" "imuldi")]) | |
5162 | |
5163 (define_insn "muldi3" | |
5164 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") | |
5165 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5166 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
5167 "TARGET_64BIT" | |
5168 "@ | |
5169 msgr\t%0,%2 | |
5170 mghi\t%0,%h2 | |
5171 msg\t%0,%2 | |
5172 msgfi\t%0,%2" | |
5173 [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
5174 (set_attr "type" "imuldi") | |
5175 (set_attr "cpu_facility" "*,*,*,z10")]) | |
5176 | |
5177 ; | |
5178 ; mulsi3 instruction pattern(s). | |
5179 ; | |
5180 | |
5181 (define_insn "*mulsi3_sign" | |
5182 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5183 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5184 (match_operand:SI 1 "register_operand" "0,0")))] | |
5185 "" | |
5186 "@ | |
5187 mh\t%0,%2 | |
5188 mhy\t%0,%2" | |
5189 [(set_attr "op_type" "RX,RXY") | |
5190 (set_attr "type" "imulhi") | |
5191 (set_attr "cpu_facility" "*,z10")]) | |
5192 | |
5193 (define_insn "mulsi3" | |
5194 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") | |
5195 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5196 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
5197 "" | |
5198 "@ | |
5199 msr\t%0,%2 | |
5200 mhi\t%0,%h2 | |
5201 ms\t%0,%2 | |
5202 msy\t%0,%2 | |
5203 msfi\t%0,%2" | |
5204 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
5205 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
5206 (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
5207 | |
5208 ; | |
5209 ; mulsidi3 instruction pattern(s). | |
5210 ; | |
5211 | |
5212 (define_insn "mulsidi3" | |
5213 [(set (match_operand:DI 0 "register_operand" "=d,d,d") | |
5214 (mult:DI (sign_extend:DI | |
5215 (match_operand:SI 1 "register_operand" "%0,0,0")) | |
5216 (sign_extend:DI | |
5217 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] | |
5218 "!TARGET_64BIT" | |
5219 "@ | |
5220 mr\t%0,%2 | |
5221 m\t%0,%2 | |
5222 mfy\t%0,%2" | |
5223 [(set_attr "op_type" "RR,RX,RXY") | |
5224 (set_attr "type" "imulsi") | |
5225 (set_attr "cpu_facility" "*,*,z10")]) | |
5226 | |
5227 ; | |
5228 ; umulsidi3 instruction pattern(s). | |
5229 ; | |
5230 | |
5231 (define_insn "umulsidi3" | |
5232 [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5233 (mult:DI (zero_extend:DI | |
5234 (match_operand:SI 1 "register_operand" "%0,0")) | |
5235 (zero_extend:DI | |
5236 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))] | |
5237 "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
5238 "@ | |
5239 mlr\t%0,%2 | |
5240 ml\t%0,%2" | |
5241 [(set_attr "op_type" "RRE,RXY") | |
5242 (set_attr "type" "imulsi")]) | |
5243 | |
5244 ; | |
5245 ; mul(tf|df|sf|td|dd)3 instruction pattern(s). | |
5246 ; | |
5247 | |
5248 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr | |
5249 (define_insn "mul<mode>3" | |
5250 [(set (match_operand:FP 0 "register_operand" "=f,f") | |
5251 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
5252 (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
5253 "TARGET_HARD_FLOAT" | |
5254 "@ | |
5255 m<xdee><bt>r\t%0,<op1>%2 | |
5256 m<xdee>b\t%0,%2" | |
5257 [(set_attr "op_type" "<RRer>,RXE") | |
5258 (set_attr "type" "fmul<mode>")]) | |
5259 | |
5260 ; madbr, maebr, maxb, madb, maeb | |
5261 (define_insn "*fmadd<mode>" | |
5262 [(set (match_operand:DSF 0 "register_operand" "=f,f") | |
5263 (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f") | |
5264 (match_operand:DSF 2 "nonimmediate_operand" "f,R")) | |
5265 (match_operand:DSF 3 "register_operand" "0,0")))] | |
5266 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" | |
5267 "@ | |
5268 ma<xde>br\t%0,%1,%2 | |
5269 ma<xde>b\t%0,%1,%2" | |
5270 [(set_attr "op_type" "RRE,RXE") | |
5271 (set_attr "type" "fmul<mode>")]) | |
5272 | |
5273 ; msxbr, msdbr, msebr, msxb, msdb, mseb | |
5274 (define_insn "*fmsub<mode>" | |
5275 [(set (match_operand:DSF 0 "register_operand" "=f,f") | |
5276 (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f") | |
5277 (match_operand:DSF 2 "nonimmediate_operand" "f,R")) | |
5278 (match_operand:DSF 3 "register_operand" "0,0")))] | |
5279 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" | |
5280 "@ | |
5281 ms<xde>br\t%0,%1,%2 | |
5282 ms<xde>b\t%0,%1,%2" | |
5283 [(set_attr "op_type" "RRE,RXE") | |
5284 (set_attr "type" "fmul<mode>")]) | |
5285 | |
5286 ;; | |
5287 ;;- Divide and modulo instructions. | |
5288 ;; | |
5289 | |
5290 ; | |
5291 ; divmoddi4 instruction pattern(s). | |
5292 ; | |
5293 | |
5294 (define_expand "divmoddi4" | |
5295 [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
5296 (div:DI (match_operand:DI 1 "register_operand" "") | |
5297 (match_operand:DI 2 "general_operand" ""))) | |
5298 (set (match_operand:DI 3 "general_operand" "") | |
5299 (mod:DI (match_dup 1) (match_dup 2)))]) | |
5300 (clobber (match_dup 4))] | |
5301 "TARGET_64BIT" | |
5302 { | |
5303 rtx insn, div_equal, mod_equal; | |
5304 | |
5305 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
5306 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
5307 | |
5308 operands[4] = gen_reg_rtx(TImode); | |
5309 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); | |
5310 | |
5311 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
5312 set_unique_reg_note (insn, REG_EQUAL, div_equal); | |
5313 | |
5314 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
5315 set_unique_reg_note (insn, REG_EQUAL, mod_equal); | |
5316 | |
5317 DONE; | |
5318 }) | |
5319 | |
5320 (define_insn "divmodtidi3" | |
5321 [(set (match_operand:TI 0 "register_operand" "=d,d") | |
5322 (ior:TI | |
5323 (ashift:TI | |
5324 (zero_extend:TI | |
5325 (mod:DI (match_operand:DI 1 "register_operand" "0,0") | |
5326 (match_operand:DI 2 "general_operand" "d,RT"))) | |
5327 (const_int 64)) | |
5328 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
5329 "TARGET_64BIT" | |
5330 "@ | |
5331 dsgr\t%0,%2 | |
5332 dsg\t%0,%2" | |
5333 [(set_attr "op_type" "RRE,RXY") | |
5334 (set_attr "type" "idiv")]) | |
5335 | |
5336 (define_insn "divmodtisi3" | |
5337 [(set (match_operand:TI 0 "register_operand" "=d,d") | |
5338 (ior:TI | |
5339 (ashift:TI | |
5340 (zero_extend:TI | |
5341 (mod:DI (match_operand:DI 1 "register_operand" "0,0") | |
5342 (sign_extend:DI | |
5343 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) | |
5344 (const_int 64)) | |
5345 (zero_extend:TI | |
5346 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
5347 "TARGET_64BIT" | |
5348 "@ | |
5349 dsgfr\t%0,%2 | |
5350 dsgf\t%0,%2" | |
5351 [(set_attr "op_type" "RRE,RXY") | |
5352 (set_attr "type" "idiv")]) | |
5353 | |
5354 ; | |
5355 ; udivmoddi4 instruction pattern(s). | |
5356 ; | |
5357 | |
5358 (define_expand "udivmoddi4" | |
5359 [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
5360 (udiv:DI (match_operand:DI 1 "general_operand" "") | |
5361 (match_operand:DI 2 "nonimmediate_operand" ""))) | |
5362 (set (match_operand:DI 3 "general_operand" "") | |
5363 (umod:DI (match_dup 1) (match_dup 2)))]) | |
5364 (clobber (match_dup 4))] | |
5365 "TARGET_64BIT" | |
5366 { | |
5367 rtx insn, div_equal, mod_equal, equal; | |
5368 | |
5369 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
5370 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
5371 equal = gen_rtx_IOR (TImode, | |
5372 gen_rtx_ASHIFT (TImode, | |
5373 gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5374 GEN_INT (64)), | |
5375 gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
5376 | |
5377 operands[4] = gen_reg_rtx(TImode); | |
5378 emit_clobber (operands[4]); | |
5379 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
5380 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
5381 | |
5382 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
5383 set_unique_reg_note (insn, REG_EQUAL, equal); | |
5384 | |
5385 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
5386 set_unique_reg_note (insn, REG_EQUAL, div_equal); | |
5387 | |
5388 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
5389 set_unique_reg_note (insn, REG_EQUAL, mod_equal); | |
5390 | |
5391 DONE; | |
5392 }) | |
5393 | |
5394 (define_insn "udivmodtidi3" | |
5395 [(set (match_operand:TI 0 "register_operand" "=d,d") | |
5396 (ior:TI | |
5397 (ashift:TI | |
5398 (zero_extend:TI | |
5399 (truncate:DI | |
5400 (umod:TI (match_operand:TI 1 "register_operand" "0,0") | |
5401 (zero_extend:TI | |
5402 (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) | |
5403 (const_int 64)) | |
5404 (zero_extend:TI | |
5405 (truncate:DI | |
5406 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
5407 "TARGET_64BIT" | |
5408 "@ | |
5409 dlgr\t%0,%2 | |
5410 dlg\t%0,%2" | |
5411 [(set_attr "op_type" "RRE,RXY") | |
5412 (set_attr "type" "idiv")]) | |
5413 | |
5414 ; | |
5415 ; divmodsi4 instruction pattern(s). | |
5416 ; | |
5417 | |
5418 (define_expand "divmodsi4" | |
5419 [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5420 (div:SI (match_operand:SI 1 "general_operand" "") | |
5421 (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5422 (set (match_operand:SI 3 "general_operand" "") | |
5423 (mod:SI (match_dup 1) (match_dup 2)))]) | |
5424 (clobber (match_dup 4))] | |
5425 "!TARGET_64BIT" | |
5426 { | |
5427 rtx insn, div_equal, mod_equal, equal; | |
5428 | |
5429 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
5430 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
5431 equal = gen_rtx_IOR (DImode, | |
5432 gen_rtx_ASHIFT (DImode, | |
5433 gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5434 GEN_INT (32)), | |
5435 gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
5436 | |
5437 operands[4] = gen_reg_rtx(DImode); | |
5438 emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
5439 | |
5440 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
5441 set_unique_reg_note (insn, REG_EQUAL, equal); | |
5442 | |
5443 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
5444 set_unique_reg_note (insn, REG_EQUAL, div_equal); | |
5445 | |
5446 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
5447 set_unique_reg_note (insn, REG_EQUAL, mod_equal); | |
5448 | |
5449 DONE; | |
5450 }) | |
5451 | |
5452 (define_insn "divmoddisi3" | |
5453 [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5454 (ior:DI | |
5455 (ashift:DI | |
5456 (zero_extend:DI | |
5457 (truncate:SI | |
5458 (mod:DI (match_operand:DI 1 "register_operand" "0,0") | |
5459 (sign_extend:DI | |
5460 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) | |
5461 (const_int 32)) | |
5462 (zero_extend:DI | |
5463 (truncate:SI | |
5464 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
5465 "!TARGET_64BIT" | |
5466 "@ | |
5467 dr\t%0,%2 | |
5468 d\t%0,%2" | |
5469 [(set_attr "op_type" "RR,RX") | |
5470 (set_attr "type" "idiv")]) | |
5471 | |
5472 ; | |
5473 ; udivsi3 and umodsi3 instruction pattern(s). | |
5474 ; | |
5475 | |
5476 (define_expand "udivmodsi4" | |
5477 [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5478 (udiv:SI (match_operand:SI 1 "general_operand" "") | |
5479 (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5480 (set (match_operand:SI 3 "general_operand" "") | |
5481 (umod:SI (match_dup 1) (match_dup 2)))]) | |
5482 (clobber (match_dup 4))] | |
5483 "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
5484 { | |
5485 rtx insn, div_equal, mod_equal, equal; | |
5486 | |
5487 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5488 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5489 equal = gen_rtx_IOR (DImode, | |
5490 gen_rtx_ASHIFT (DImode, | |
5491 gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5492 GEN_INT (32)), | |
5493 gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
5494 | |
5495 operands[4] = gen_reg_rtx(DImode); | |
5496 emit_clobber (operands[4]); | |
5497 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
5498 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
5499 | |
5500 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
5501 set_unique_reg_note (insn, REG_EQUAL, equal); | |
5502 | |
5503 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
5504 set_unique_reg_note (insn, REG_EQUAL, div_equal); | |
5505 | |
5506 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
5507 set_unique_reg_note (insn, REG_EQUAL, mod_equal); | |
5508 | |
5509 DONE; | |
5510 }) | |
5511 | |
5512 (define_insn "udivmoddisi3" | |
5513 [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5514 (ior:DI | |
5515 (ashift:DI | |
5516 (zero_extend:DI | |
5517 (truncate:SI | |
5518 (umod:DI (match_operand:DI 1 "register_operand" "0,0") | |
5519 (zero_extend:DI | |
5520 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) | |
5521 (const_int 32)) | |
5522 (zero_extend:DI | |
5523 (truncate:SI | |
5524 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
5525 "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
5526 "@ | |
5527 dlr\t%0,%2 | |
5528 dl\t%0,%2" | |
5529 [(set_attr "op_type" "RRE,RXY") | |
5530 (set_attr "type" "idiv")]) | |
5531 | |
5532 (define_expand "udivsi3" | |
5533 [(set (match_operand:SI 0 "register_operand" "=d") | |
5534 (udiv:SI (match_operand:SI 1 "general_operand" "") | |
5535 (match_operand:SI 2 "general_operand" ""))) | |
5536 (clobber (match_dup 3))] | |
5537 "!TARGET_64BIT && !TARGET_CPU_ZARCH" | |
5538 { | |
5539 rtx insn, udiv_equal, umod_equal, equal; | |
5540 | |
5541 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5542 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5543 equal = gen_rtx_IOR (DImode, | |
5544 gen_rtx_ASHIFT (DImode, | |
5545 gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5546 GEN_INT (32)), | |
5547 gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
5548 | |
5549 operands[3] = gen_reg_rtx (DImode); | |
5550 | |
5551 if (CONSTANT_P (operands[2])) | |
5552 { | |
5553 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
5554 { | |
5555 rtx label1 = gen_label_rtx (); | |
5556 | |
5557 operands[1] = make_safe_from (operands[1], operands[0]); | |
5558 emit_move_insn (operands[0], const0_rtx); | |
5559 emit_insn (gen_cmpsi (operands[1], operands[2])); | |
5560 emit_jump_insn (gen_bltu (label1)); | |
5561 emit_move_insn (operands[0], const1_rtx); | |
5562 emit_label (label1); | |
5563 } | |
5564 else | |
5565 { | |
5566 operands[2] = force_reg (SImode, operands[2]); | |
5567 operands[2] = make_safe_from (operands[2], operands[0]); | |
5568 | |
5569 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5570 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5571 operands[2])); | |
5572 set_unique_reg_note (insn, REG_EQUAL, equal); | |
5573 | |
5574 insn = emit_move_insn (operands[0], | |
5575 gen_lowpart (SImode, operands[3])); | |
5576 set_unique_reg_note (insn, REG_EQUAL, udiv_equal); | |
5577 } | |
5578 } | |
5579 else | |
5580 { | |
5581 rtx label1 = gen_label_rtx (); | |
5582 rtx label2 = gen_label_rtx (); | |
5583 rtx label3 = gen_label_rtx (); | |
5584 | |
5585 operands[1] = force_reg (SImode, operands[1]); | |
5586 operands[1] = make_safe_from (operands[1], operands[0]); | |
5587 operands[2] = force_reg (SImode, operands[2]); | |
5588 operands[2] = make_safe_from (operands[2], operands[0]); | |
5589 | |
5590 emit_move_insn (operands[0], const0_rtx); | |
5591 emit_insn (gen_cmpsi (operands[2], operands[1])); | |
5592 emit_jump_insn (gen_bgtu (label3)); | |
5593 emit_insn (gen_cmpsi (operands[2], const0_rtx)); | |
5594 emit_jump_insn (gen_blt (label2)); | |
5595 emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
5596 emit_jump_insn (gen_beq (label1)); | |
5597 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5598 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5599 operands[2])); | |
5600 set_unique_reg_note (insn, REG_EQUAL, equal); | |
5601 | |
5602 insn = emit_move_insn (operands[0], | |
5603 gen_lowpart (SImode, operands[3])); | |
5604 set_unique_reg_note (insn, REG_EQUAL, udiv_equal); | |
5605 | |
5606 emit_jump (label3); | |
5607 emit_label (label1); | |
5608 emit_move_insn (operands[0], operands[1]); | |
5609 emit_jump (label3); | |
5610 emit_label (label2); | |
5611 emit_move_insn (operands[0], const1_rtx); | |
5612 emit_label (label3); | |
5613 } | |
5614 emit_move_insn (operands[0], operands[0]); | |
5615 DONE; | |
5616 }) | |
5617 | |
5618 (define_expand "umodsi3" | |
5619 [(set (match_operand:SI 0 "register_operand" "=d") | |
5620 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5621 (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5622 (clobber (match_dup 3))] | |
5623 "!TARGET_64BIT && !TARGET_CPU_ZARCH" | |
5624 { | |
5625 rtx insn, udiv_equal, umod_equal, equal; | |
5626 | |
5627 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5628 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5629 equal = gen_rtx_IOR (DImode, | |
5630 gen_rtx_ASHIFT (DImode, | |
5631 gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5632 GEN_INT (32)), | |
5633 gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
5634 | |
5635 operands[3] = gen_reg_rtx (DImode); | |
5636 | |
5637 if (CONSTANT_P (operands[2])) | |
5638 { | |
5639 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
5640 { | |
5641 rtx label1 = gen_label_rtx (); | |
5642 | |
5643 operands[1] = make_safe_from (operands[1], operands[0]); | |
5644 emit_move_insn (operands[0], operands[1]); | |
5645 emit_insn (gen_cmpsi (operands[0], operands[2])); | |
5646 emit_jump_insn (gen_bltu (label1)); | |
5647 emit_insn (gen_abssi2 (operands[0], operands[2])); | |
5648 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
5649 emit_label (label1); | |
5650 } | |
5651 else | |
5652 { | |
5653 operands[2] = force_reg (SImode, operands[2]); | |
5654 operands[2] = make_safe_from (operands[2], operands[0]); | |
5655 | |
5656 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5657 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5658 operands[2])); | |
5659 set_unique_reg_note (insn, REG_EQUAL, equal); | |
5660 | |
5661 insn = emit_move_insn (operands[0], | |
5662 gen_highpart (SImode, operands[3])); | |
5663 set_unique_reg_note (insn, REG_EQUAL, umod_equal); | |
5664 } | |
5665 } | |
5666 else | |
5667 { | |
5668 rtx label1 = gen_label_rtx (); | |
5669 rtx label2 = gen_label_rtx (); | |
5670 rtx label3 = gen_label_rtx (); | |
5671 | |
5672 operands[1] = force_reg (SImode, operands[1]); | |
5673 operands[1] = make_safe_from (operands[1], operands[0]); | |
5674 operands[2] = force_reg (SImode, operands[2]); | |
5675 operands[2] = make_safe_from (operands[2], operands[0]); | |
5676 | |
5677 emit_move_insn(operands[0], operands[1]); | |
5678 emit_insn (gen_cmpsi (operands[2], operands[1])); | |
5679 emit_jump_insn (gen_bgtu (label3)); | |
5680 emit_insn (gen_cmpsi (operands[2], const0_rtx)); | |
5681 emit_jump_insn (gen_blt (label2)); | |
5682 emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
5683 emit_jump_insn (gen_beq (label1)); | |
5684 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5685 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5686 operands[2])); | |
5687 set_unique_reg_note (insn, REG_EQUAL, equal); | |
5688 | |
5689 insn = emit_move_insn (operands[0], | |
5690 gen_highpart (SImode, operands[3])); | |
5691 set_unique_reg_note (insn, REG_EQUAL, umod_equal); | |
5692 | |
5693 emit_jump (label3); | |
5694 emit_label (label1); | |
5695 emit_move_insn (operands[0], const0_rtx); | |
5696 emit_jump (label3); | |
5697 emit_label (label2); | |
5698 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); | |
5699 emit_label (label3); | |
5700 } | |
5701 DONE; | |
5702 }) | |
5703 | |
5704 ; | |
5705 ; div(df|sf)3 instruction pattern(s). | |
5706 ; | |
5707 | |
5708 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr | |
5709 (define_insn "div<mode>3" | |
5710 [(set (match_operand:FP 0 "register_operand" "=f,f") | |
5711 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
5712 (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
5713 "TARGET_HARD_FLOAT" | |
5714 "@ | |
5715 d<xde><bt>r\t%0,<op1>%2 | |
5716 d<xde>b\t%0,%2" | |
5717 [(set_attr "op_type" "<RRer>,RXE") | |
5718 (set_attr "type" "fdiv<mode>")]) | |
5719 | |
5720 | |
5721 ;; | |
5722 ;;- And instructions. | |
5723 ;; | |
5724 | |
5725 (define_expand "and<mode>3" | |
5726 [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5727 (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5728 (match_operand:INT 2 "general_operand" ""))) | |
5729 (clobber (reg:CC CC_REGNUM))] | |
5730 "" | |
5731 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
5732 | |
5733 ; | |
5734 ; anddi3 instruction pattern(s). | |
5735 ; | |
5736 | |
5737 (define_insn "*anddi3_cc" | |
5738 [(set (reg CC_REGNUM) | |
5739 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
5740 (match_operand:DI 2 "general_operand" "d,RT")) | |
5741 (const_int 0))) | |
5742 (set (match_operand:DI 0 "register_operand" "=d,d") | |
5743 (and:DI (match_dup 1) (match_dup 2)))] | |
5744 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5745 "@ | |
5746 ngr\t%0,%2 | |
5747 ng\t%0,%2" | |
5748 [(set_attr "op_type" "RRE,RXY") | |
5749 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
5750 | |
5751 (define_insn "*anddi3_cconly" | |
5752 [(set (reg CC_REGNUM) | |
5753 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
5754 (match_operand:DI 2 "general_operand" "d,RT")) | |
5755 (const_int 0))) | |
5756 (clobber (match_scratch:DI 0 "=d,d"))] | |
5757 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT | |
5758 /* Do not steal TM patterns. */ | |
5759 && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
5760 "@ | |
5761 ngr\t%0,%2 | |
5762 ng\t%0,%2" | |
5763 [(set_attr "op_type" "RRE,RXY") | |
5764 (set_attr "z10prop" "z10_super_E1, z10_super_E1")]) | |
5765 | |
5766 (define_insn "*anddi3" | |
5767 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q") | |
5768 (and:DI (match_operand:DI 1 "nonimmediate_operand" | |
5769 "%d,o,0,0,0,0,0,0,0,0,0,0") | |
5770 (match_operand:DI 2 "general_operand" | |
5771 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q"))) | |
5772 (clobber (reg:CC CC_REGNUM))] | |
5773 "TARGET_64BIT && s390_logical_operator_ok_p (operands)" | |
5774 "@ | |
5775 # | |
5776 # | |
5777 nihh\t%0,%j2 | |
5778 nihl\t%0,%j2 | |
5779 nilh\t%0,%j2 | |
5780 nill\t%0,%j2 | |
5781 nihf\t%0,%m2 | |
5782 nilf\t%0,%m2 | |
5783 ngr\t%0,%2 | |
5784 ng\t%0,%2 | |
5785 # | |
5786 #" | |
5787 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") | |
5788 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*") | |
5789 (set_attr "z10prop" "*, | |
5790 *, | |
5791 z10_super_E1, | |
5792 z10_super_E1, | |
5793 z10_super_E1, | |
5794 z10_super_E1, | |
5795 z10_super_E1, | |
5796 z10_super_E1, | |
5797 z10_super_E1, | |
5798 z10_super_E1, | |
5799 *, | |
5800 *")]) | |
5801 | |
5802 (define_split | |
5803 [(set (match_operand:DI 0 "s_operand" "") | |
5804 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
5805 (clobber (reg:CC CC_REGNUM))] | |
5806 "reload_completed" | |
5807 [(parallel | |
5808 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
5809 (clobber (reg:CC CC_REGNUM))])] | |
5810 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
5811 | |
5812 | |
5813 ; | |
5814 ; andsi3 instruction pattern(s). | |
5815 ; | |
5816 | |
5817 (define_insn "*andsi3_cc" | |
5818 [(set (reg CC_REGNUM) | |
5819 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
5820 (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
5821 (const_int 0))) | |
5822 (set (match_operand:SI 0 "register_operand" "=d,d,d,d") | |
5823 (and:SI (match_dup 1) (match_dup 2)))] | |
5824 "s390_match_ccmode(insn, CCTmode)" | |
5825 "@ | |
5826 nilf\t%0,%o2 | |
5827 nr\t%0,%2 | |
5828 n\t%0,%2 | |
5829 ny\t%0,%2" | |
5830 [(set_attr "op_type" "RIL,RR,RX,RXY") | |
5831 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
5832 | |
5833 (define_insn "*andsi3_cconly" | |
5834 [(set (reg CC_REGNUM) | |
5835 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
5836 (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
5837 (const_int 0))) | |
5838 (clobber (match_scratch:SI 0 "=d,d,d,d"))] | |
5839 "s390_match_ccmode(insn, CCTmode) | |
5840 /* Do not steal TM patterns. */ | |
5841 && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
5842 "@ | |
5843 nilf\t%0,%o2 | |
5844 nr\t%0,%2 | |
5845 n\t%0,%2 | |
5846 ny\t%0,%2" | |
5847 [(set_attr "op_type" "RIL,RR,RX,RXY") | |
5848 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
5849 | |
5850 (define_insn "*andsi3_zarch" | |
5851 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") | |
5852 (and:SI (match_operand:SI 1 "nonimmediate_operand" | |
5853 "%d,o,0,0,0,0,0,0,0,0") | |
5854 (match_operand:SI 2 "general_operand" | |
5855 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q"))) | |
5856 (clobber (reg:CC CC_REGNUM))] | |
5857 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
5858 "@ | |
5859 # | |
5860 # | |
5861 nilh\t%0,%j2 | |
5862 nill\t%0,%j2 | |
5863 nilf\t%0,%o2 | |
5864 nr\t%0,%2 | |
5865 n\t%0,%2 | |
5866 ny\t%0,%2 | |
5867 # | |
5868 #" | |
5869 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS") | |
5870 (set_attr "z10prop" "*, | |
5871 *, | |
5872 z10_super_E1, | |
5873 z10_super_E1, | |
5874 z10_super_E1, | |
5875 z10_super_E1, | |
5876 z10_super_E1, | |
5877 z10_super_E1, | |
5878 *, | |
5879 *")]) | |
5880 | |
5881 (define_insn "*andsi3_esa" | |
5882 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") | |
5883 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
5884 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) | |
5885 (clobber (reg:CC CC_REGNUM))] | |
5886 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
5887 "@ | |
5888 nr\t%0,%2 | |
5889 n\t%0,%2 | |
5890 # | |
5891 #" | |
5892 [(set_attr "op_type" "RR,RX,SI,SS") | |
5893 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
5894 | |
5895 | |
5896 (define_split | |
5897 [(set (match_operand:SI 0 "s_operand" "") | |
5898 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
5899 (clobber (reg:CC CC_REGNUM))] | |
5900 "reload_completed" | |
5901 [(parallel | |
5902 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
5903 (clobber (reg:CC CC_REGNUM))])] | |
5904 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
5905 | |
5906 ; | |
5907 ; andhi3 instruction pattern(s). | |
5908 ; | |
5909 | |
5910 (define_insn "*andhi3_zarch" | |
5911 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") | |
5912 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5913 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) | |
5914 (clobber (reg:CC CC_REGNUM))] | |
5915 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
5916 "@ | |
5917 nr\t%0,%2 | |
5918 nill\t%0,%x2 | |
5919 # | |
5920 #" | |
5921 [(set_attr "op_type" "RR,RI,SI,SS") | |
5922 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*") | |
5923 ]) | |
5924 | |
5925 (define_insn "*andhi3_esa" | |
5926 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") | |
5927 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5928 (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
5929 (clobber (reg:CC CC_REGNUM))] | |
5930 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
5931 "@ | |
5932 nr\t%0,%2 | |
5933 # | |
5934 #" | |
5935 [(set_attr "op_type" "RR,SI,SS") | |
5936 (set_attr "z10prop" "z10_super_E1,*,*") | |
5937 ]) | |
5938 | |
5939 (define_split | |
5940 [(set (match_operand:HI 0 "s_operand" "") | |
5941 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
5942 (clobber (reg:CC CC_REGNUM))] | |
5943 "reload_completed" | |
5944 [(parallel | |
5945 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
5946 (clobber (reg:CC CC_REGNUM))])] | |
5947 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
5948 | |
5949 ; | |
5950 ; andqi3 instruction pattern(s). | |
5951 ; | |
5952 | |
5953 (define_insn "*andqi3_zarch" | |
5954 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5955 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5956 (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
5957 (clobber (reg:CC CC_REGNUM))] | |
5958 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
5959 "@ | |
5960 nr\t%0,%2 | |
5961 nill\t%0,%b2 | |
5962 ni\t%S0,%b2 | |
5963 niy\t%S0,%b2 | |
5964 #" | |
5965 [(set_attr "op_type" "RR,RI,SI,SIY,SS") | |
5966 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) | |
5967 | |
5968 (define_insn "*andqi3_esa" | |
5969 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5970 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5971 (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
5972 (clobber (reg:CC CC_REGNUM))] | |
5973 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
5974 "@ | |
5975 nr\t%0,%2 | |
5976 ni\t%S0,%b2 | |
5977 #" | |
5978 [(set_attr "op_type" "RR,SI,SS") | |
5979 (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
5980 | |
5981 ; | |
5982 ; Block and (NC) patterns. | |
5983 ; | |
5984 | |
5985 (define_insn "*nc" | |
5986 [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5987 (and:BLK (match_dup 0) | |
5988 (match_operand:BLK 1 "memory_operand" "Q"))) | |
5989 (use (match_operand 2 "const_int_operand" "n")) | |
5990 (clobber (reg:CC CC_REGNUM))] | |
5991 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
5992 "nc\t%O0(%2,%R0),%S1" | |
5993 [(set_attr "op_type" "SS")]) | |
5994 | |
5995 (define_split | |
5996 [(set (match_operand 0 "memory_operand" "") | |
5997 (and (match_dup 0) | |
5998 (match_operand 1 "memory_operand" ""))) | |
5999 (clobber (reg:CC CC_REGNUM))] | |
6000 "reload_completed | |
6001 && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6002 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6003 [(parallel | |
6004 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
6005 (use (match_dup 2)) | |
6006 (clobber (reg:CC CC_REGNUM))])] | |
6007 { | |
6008 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6009 operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6010 operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6011 }) | |
6012 | |
6013 (define_peephole2 | |
6014 [(parallel | |
6015 [(set (match_operand:BLK 0 "memory_operand" "") | |
6016 (and:BLK (match_dup 0) | |
6017 (match_operand:BLK 1 "memory_operand" ""))) | |
6018 (use (match_operand 2 "const_int_operand" "")) | |
6019 (clobber (reg:CC CC_REGNUM))]) | |
6020 (parallel | |
6021 [(set (match_operand:BLK 3 "memory_operand" "") | |
6022 (and:BLK (match_dup 3) | |
6023 (match_operand:BLK 4 "memory_operand" ""))) | |
6024 (use (match_operand 5 "const_int_operand" "")) | |
6025 (clobber (reg:CC CC_REGNUM))])] | |
6026 "s390_offset_p (operands[0], operands[3], operands[2]) | |
6027 && s390_offset_p (operands[1], operands[4], operands[2]) | |
6028 && !s390_overlap_p (operands[0], operands[1], | |
6029 INTVAL (operands[2]) + INTVAL (operands[5])) | |
6030 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
6031 [(parallel | |
6032 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
6033 (use (match_dup 8)) | |
6034 (clobber (reg:CC CC_REGNUM))])] | |
6035 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
6036 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6037 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6038 | |
6039 | |
6040 ;; | |
6041 ;;- Bit set (inclusive or) instructions. | |
6042 ;; | |
6043 | |
6044 (define_expand "ior<mode>3" | |
6045 [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6046 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6047 (match_operand:INT 2 "general_operand" ""))) | |
6048 (clobber (reg:CC CC_REGNUM))] | |
6049 "" | |
6050 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
6051 | |
6052 ; | |
6053 ; iordi3 instruction pattern(s). | |
6054 ; | |
6055 | |
6056 (define_insn "*iordi3_cc" | |
6057 [(set (reg CC_REGNUM) | |
6058 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
6059 (match_operand:DI 2 "general_operand" "d,RT")) | |
6060 (const_int 0))) | |
6061 (set (match_operand:DI 0 "register_operand" "=d,d") | |
6062 (ior:DI (match_dup 1) (match_dup 2)))] | |
6063 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6064 "@ | |
6065 ogr\t%0,%2 | |
6066 og\t%0,%2" | |
6067 [(set_attr "op_type" "RRE,RXY") | |
6068 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
6069 | |
6070 (define_insn "*iordi3_cconly" | |
6071 [(set (reg CC_REGNUM) | |
6072 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
6073 (match_operand:DI 2 "general_operand" "d,RT")) | |
6074 (const_int 0))) | |
6075 (clobber (match_scratch:DI 0 "=d,d"))] | |
6076 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6077 "@ | |
6078 ogr\t%0,%2 | |
6079 og\t%0,%2" | |
6080 [(set_attr "op_type" "RRE,RXY") | |
6081 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
6082 | |
6083 (define_insn "*iordi3" | |
6084 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") | |
6085 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0") | |
6086 (match_operand:DI 2 "general_operand" | |
6087 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q"))) | |
6088 (clobber (reg:CC CC_REGNUM))] | |
6089 "TARGET_64BIT && s390_logical_operator_ok_p (operands)" | |
6090 "@ | |
6091 oihh\t%0,%i2 | |
6092 oihl\t%0,%i2 | |
6093 oilh\t%0,%i2 | |
6094 oill\t%0,%i2 | |
6095 oihf\t%0,%k2 | |
6096 oilf\t%0,%k2 | |
6097 ogr\t%0,%2 | |
6098 og\t%0,%2 | |
6099 # | |
6100 #" | |
6101 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") | |
6102 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*") | |
6103 (set_attr "z10prop" "z10_super_E1, | |
6104 z10_super_E1, | |
6105 z10_super_E1, | |
6106 z10_super_E1, | |
6107 z10_super_E1, | |
6108 z10_super_E1, | |
6109 z10_super_E1, | |
6110 z10_super_E1, | |
6111 *, | |
6112 *")]) | |
6113 | |
6114 (define_split | |
6115 [(set (match_operand:DI 0 "s_operand" "") | |
6116 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
6117 (clobber (reg:CC CC_REGNUM))] | |
6118 "reload_completed" | |
6119 [(parallel | |
6120 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
6121 (clobber (reg:CC CC_REGNUM))])] | |
6122 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
6123 | |
6124 ; | |
6125 ; iorsi3 instruction pattern(s). | |
6126 ; | |
6127 | |
6128 (define_insn "*iorsi3_cc" | |
6129 [(set (reg CC_REGNUM) | |
6130 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
6131 (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
6132 (const_int 0))) | |
6133 (set (match_operand:SI 0 "register_operand" "=d,d,d,d") | |
6134 (ior:SI (match_dup 1) (match_dup 2)))] | |
6135 "s390_match_ccmode(insn, CCTmode)" | |
6136 "@ | |
6137 oilf\t%0,%o2 | |
6138 or\t%0,%2 | |
6139 o\t%0,%2 | |
6140 oy\t%0,%2" | |
6141 [(set_attr "op_type" "RIL,RR,RX,RXY") | |
6142 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
6143 | |
6144 (define_insn "*iorsi3_cconly" | |
6145 [(set (reg CC_REGNUM) | |
6146 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
6147 (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
6148 (const_int 0))) | |
6149 (clobber (match_scratch:SI 0 "=d,d,d,d"))] | |
6150 "s390_match_ccmode(insn, CCTmode)" | |
6151 "@ | |
6152 oilf\t%0,%o2 | |
6153 or\t%0,%2 | |
6154 o\t%0,%2 | |
6155 oy\t%0,%2" | |
6156 [(set_attr "op_type" "RIL,RR,RX,RXY") | |
6157 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
6158 | |
6159 (define_insn "*iorsi3_zarch" | |
6160 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") | |
6161 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") | |
6162 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q"))) | |
6163 (clobber (reg:CC CC_REGNUM))] | |
6164 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
6165 "@ | |
6166 oilh\t%0,%i2 | |
6167 oill\t%0,%i2 | |
6168 oilf\t%0,%o2 | |
6169 or\t%0,%2 | |
6170 o\t%0,%2 | |
6171 oy\t%0,%2 | |
6172 # | |
6173 #" | |
6174 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS") | |
6175 (set_attr "z10prop" "z10_super_E1, | |
6176 z10_super_E1, | |
6177 z10_super_E1, | |
6178 z10_super_E1, | |
6179 z10_super_E1, | |
6180 z10_super_E1, | |
6181 *, | |
6182 *")]) | |
6183 | |
6184 (define_insn "*iorsi3_esa" | |
6185 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") | |
6186 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
6187 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) | |
6188 (clobber (reg:CC CC_REGNUM))] | |
6189 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
6190 "@ | |
6191 or\t%0,%2 | |
6192 o\t%0,%2 | |
6193 # | |
6194 #" | |
6195 [(set_attr "op_type" "RR,RX,SI,SS") | |
6196 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
6197 | |
6198 (define_split | |
6199 [(set (match_operand:SI 0 "s_operand" "") | |
6200 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
6201 (clobber (reg:CC CC_REGNUM))] | |
6202 "reload_completed" | |
6203 [(parallel | |
6204 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
6205 (clobber (reg:CC CC_REGNUM))])] | |
6206 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
6207 | |
6208 ; | |
6209 ; iorhi3 instruction pattern(s). | |
6210 ; | |
6211 | |
6212 (define_insn "*iorhi3_zarch" | |
6213 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") | |
6214 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
6215 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) | |
6216 (clobber (reg:CC CC_REGNUM))] | |
6217 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
6218 "@ | |
6219 or\t%0,%2 | |
6220 oill\t%0,%x2 | |
6221 # | |
6222 #" | |
6223 [(set_attr "op_type" "RR,RI,SI,SS") | |
6224 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
6225 | |
6226 (define_insn "*iorhi3_esa" | |
6227 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") | |
6228 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6229 (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
6230 (clobber (reg:CC CC_REGNUM))] | |
6231 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
6232 "@ | |
6233 or\t%0,%2 | |
6234 # | |
6235 #" | |
6236 [(set_attr "op_type" "RR,SI,SS") | |
6237 (set_attr "z10prop" "z10_super_E1,*,*")]) | |
6238 | |
6239 (define_split | |
6240 [(set (match_operand:HI 0 "s_operand" "") | |
6241 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
6242 (clobber (reg:CC CC_REGNUM))] | |
6243 "reload_completed" | |
6244 [(parallel | |
6245 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
6246 (clobber (reg:CC CC_REGNUM))])] | |
6247 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
6248 | |
6249 ; | |
6250 ; iorqi3 instruction pattern(s). | |
6251 ; | |
6252 | |
6253 (define_insn "*iorqi3_zarch" | |
6254 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
6255 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6256 (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
6257 (clobber (reg:CC CC_REGNUM))] | |
6258 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
6259 "@ | |
6260 or\t%0,%2 | |
6261 oill\t%0,%b2 | |
6262 oi\t%S0,%b2 | |
6263 oiy\t%S0,%b2 | |
6264 #" | |
6265 [(set_attr "op_type" "RR,RI,SI,SIY,SS") | |
6266 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) | |
6267 | |
6268 (define_insn "*iorqi3_esa" | |
6269 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6270 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6271 (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
6272 (clobber (reg:CC CC_REGNUM))] | |
6273 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" | |
6274 "@ | |
6275 or\t%0,%2 | |
6276 oi\t%S0,%b2 | |
6277 #" | |
6278 [(set_attr "op_type" "RR,SI,SS") | |
6279 (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
6280 | |
6281 ; | |
6282 ; Block inclusive or (OC) patterns. | |
6283 ; | |
6284 | |
6285 (define_insn "*oc" | |
6286 [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6287 (ior:BLK (match_dup 0) | |
6288 (match_operand:BLK 1 "memory_operand" "Q"))) | |
6289 (use (match_operand 2 "const_int_operand" "n")) | |
6290 (clobber (reg:CC CC_REGNUM))] | |
6291 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
6292 "oc\t%O0(%2,%R0),%S1" | |
6293 [(set_attr "op_type" "SS")]) | |
6294 | |
6295 (define_split | |
6296 [(set (match_operand 0 "memory_operand" "") | |
6297 (ior (match_dup 0) | |
6298 (match_operand 1 "memory_operand" ""))) | |
6299 (clobber (reg:CC CC_REGNUM))] | |
6300 "reload_completed | |
6301 && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6302 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6303 [(parallel | |
6304 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
6305 (use (match_dup 2)) | |
6306 (clobber (reg:CC CC_REGNUM))])] | |
6307 { | |
6308 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6309 operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6310 operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6311 }) | |
6312 | |
6313 (define_peephole2 | |
6314 [(parallel | |
6315 [(set (match_operand:BLK 0 "memory_operand" "") | |
6316 (ior:BLK (match_dup 0) | |
6317 (match_operand:BLK 1 "memory_operand" ""))) | |
6318 (use (match_operand 2 "const_int_operand" "")) | |
6319 (clobber (reg:CC CC_REGNUM))]) | |
6320 (parallel | |
6321 [(set (match_operand:BLK 3 "memory_operand" "") | |
6322 (ior:BLK (match_dup 3) | |
6323 (match_operand:BLK 4 "memory_operand" ""))) | |
6324 (use (match_operand 5 "const_int_operand" "")) | |
6325 (clobber (reg:CC CC_REGNUM))])] | |
6326 "s390_offset_p (operands[0], operands[3], operands[2]) | |
6327 && s390_offset_p (operands[1], operands[4], operands[2]) | |
6328 && !s390_overlap_p (operands[0], operands[1], | |
6329 INTVAL (operands[2]) + INTVAL (operands[5])) | |
6330 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
6331 [(parallel | |
6332 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
6333 (use (match_dup 8)) | |
6334 (clobber (reg:CC CC_REGNUM))])] | |
6335 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
6336 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6337 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6338 | |
6339 | |
6340 ;; | |
6341 ;;- Xor instructions. | |
6342 ;; | |
6343 | |
6344 (define_expand "xor<mode>3" | |
6345 [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6346 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6347 (match_operand:INT 2 "general_operand" ""))) | |
6348 (clobber (reg:CC CC_REGNUM))] | |
6349 "" | |
6350 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
6351 | |
6352 ; | |
6353 ; xordi3 instruction pattern(s). | |
6354 ; | |
6355 | |
6356 (define_insn "*xordi3_cc" | |
6357 [(set (reg CC_REGNUM) | |
6358 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
6359 (match_operand:DI 2 "general_operand" "d,RT")) | |
6360 (const_int 0))) | |
6361 (set (match_operand:DI 0 "register_operand" "=d,d") | |
6362 (xor:DI (match_dup 1) (match_dup 2)))] | |
6363 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6364 "@ | |
6365 xgr\t%0,%2 | |
6366 xg\t%0,%2" | |
6367 [(set_attr "op_type" "RRE,RXY") | |
6368 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
6369 | |
6370 (define_insn "*xordi3_cconly" | |
6371 [(set (reg CC_REGNUM) | |
6372 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
6373 (match_operand:DI 2 "general_operand" "d,RT")) | |
6374 (const_int 0))) | |
6375 (clobber (match_scratch:DI 0 "=d,d"))] | |
6376 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6377 "@ | |
6378 xgr\t%0,%2 | |
6379 xg\t%0,%2" | |
6380 [(set_attr "op_type" "RRE,RXY") | |
6381 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
6382 | |
6383 (define_insn "*xordi3" | |
6384 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") | |
6385 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
6386 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q"))) | |
6387 (clobber (reg:CC CC_REGNUM))] | |
6388 "TARGET_64BIT && s390_logical_operator_ok_p (operands)" | |
6389 "@ | |
6390 xihf\t%0,%k2 | |
6391 xilf\t%0,%k2 | |
6392 xgr\t%0,%2 | |
6393 xg\t%0,%2 | |
6394 # | |
6395 #" | |
6396 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS") | |
6397 (set_attr "cpu_facility" "extimm,extimm,*,*,*,*") | |
6398 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) | |
6399 | |
6400 (define_split | |
6401 [(set (match_operand:DI 0 "s_operand" "") | |
6402 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
6403 (clobber (reg:CC CC_REGNUM))] | |
6404 "reload_completed" | |
6405 [(parallel | |
6406 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
6407 (clobber (reg:CC CC_REGNUM))])] | |
6408 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
6409 | |
6410 ; | |
6411 ; xorsi3 instruction pattern(s). | |
6412 ; | |
6413 | |
6414 (define_insn "*xorsi3_cc" | |
6415 [(set (reg CC_REGNUM) | |
6416 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
6417 (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
6418 (const_int 0))) | |
6419 (set (match_operand:SI 0 "register_operand" "=d,d,d,d") | |
6420 (xor:SI (match_dup 1) (match_dup 2)))] | |
6421 "s390_match_ccmode(insn, CCTmode)" | |
6422 "@ | |
6423 xilf\t%0,%o2 | |
6424 xr\t%0,%2 | |
6425 x\t%0,%2 | |
6426 xy\t%0,%2" | |
6427 [(set_attr "op_type" "RIL,RR,RX,RXY") | |
6428 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
6429 | |
6430 (define_insn "*xorsi3_cconly" | |
6431 [(set (reg CC_REGNUM) | |
6432 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
6433 (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
6434 (const_int 0))) | |
6435 (clobber (match_scratch:SI 0 "=d,d,d,d"))] | |
6436 "s390_match_ccmode(insn, CCTmode)" | |
6437 "@ | |
6438 xilf\t%0,%o2 | |
6439 xr\t%0,%2 | |
6440 x\t%0,%2 | |
6441 xy\t%0,%2" | |
6442 [(set_attr "op_type" "RIL,RR,RX,RXY") | |
6443 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
6444 | |
6445 (define_insn "*xorsi3" | |
6446 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") | |
6447 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
6448 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q"))) | |
6449 (clobber (reg:CC CC_REGNUM))] | |
6450 "s390_logical_operator_ok_p (operands)" | |
6451 "@ | |
6452 xilf\t%0,%o2 | |
6453 xr\t%0,%2 | |
6454 x\t%0,%2 | |
6455 xy\t%0,%2 | |
6456 # | |
6457 #" | |
6458 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS") | |
6459 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) | |
6460 | |
6461 (define_split | |
6462 [(set (match_operand:SI 0 "s_operand" "") | |
6463 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
6464 (clobber (reg:CC CC_REGNUM))] | |
6465 "reload_completed" | |
6466 [(parallel | |
6467 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
6468 (clobber (reg:CC CC_REGNUM))])] | |
6469 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
6470 | |
6471 ; | |
6472 ; xorhi3 instruction pattern(s). | |
6473 ; | |
6474 | |
6475 (define_insn "*xorhi3" | |
6476 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") | |
6477 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
6478 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q"))) | |
6479 (clobber (reg:CC CC_REGNUM))] | |
6480 "s390_logical_operator_ok_p (operands)" | |
6481 "@ | |
6482 xilf\t%0,%x2 | |
6483 xr\t%0,%2 | |
6484 # | |
6485 #" | |
6486 [(set_attr "op_type" "RIL,RR,SI,SS") | |
6487 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
6488 | |
6489 (define_split | |
6490 [(set (match_operand:HI 0 "s_operand" "") | |
6491 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
6492 (clobber (reg:CC CC_REGNUM))] | |
6493 "reload_completed" | |
6494 [(parallel | |
6495 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
6496 (clobber (reg:CC CC_REGNUM))])] | |
6497 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
6498 | |
6499 ; | |
6500 ; xorqi3 instruction pattern(s). | |
6501 ; | |
6502 | |
6503 (define_insn "*xorqi3" | |
6504 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
6505 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6506 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q"))) | |
6507 (clobber (reg:CC CC_REGNUM))] | |
6508 "s390_logical_operator_ok_p (operands)" | |
6509 "@ | |
6510 xilf\t%0,%b2 | |
6511 xr\t%0,%2 | |
6512 xi\t%S0,%b2 | |
6513 xiy\t%S0,%b2 | |
6514 #" | |
6515 [(set_attr "op_type" "RIL,RR,SI,SIY,SS") | |
6516 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) | |
6517 | |
6518 | |
6519 ; | |
6520 ; Block exclusive or (XC) patterns. | |
6521 ; | |
6522 | |
6523 (define_insn "*xc" | |
6524 [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6525 (xor:BLK (match_dup 0) | |
6526 (match_operand:BLK 1 "memory_operand" "Q"))) | |
6527 (use (match_operand 2 "const_int_operand" "n")) | |
6528 (clobber (reg:CC CC_REGNUM))] | |
6529 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
6530 "xc\t%O0(%2,%R0),%S1" | |
6531 [(set_attr "op_type" "SS")]) | |
6532 | |
6533 (define_split | |
6534 [(set (match_operand 0 "memory_operand" "") | |
6535 (xor (match_dup 0) | |
6536 (match_operand 1 "memory_operand" ""))) | |
6537 (clobber (reg:CC CC_REGNUM))] | |
6538 "reload_completed | |
6539 && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6540 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6541 [(parallel | |
6542 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
6543 (use (match_dup 2)) | |
6544 (clobber (reg:CC CC_REGNUM))])] | |
6545 { | |
6546 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6547 operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6548 operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6549 }) | |
6550 | |
6551 (define_peephole2 | |
6552 [(parallel | |
6553 [(set (match_operand:BLK 0 "memory_operand" "") | |
6554 (xor:BLK (match_dup 0) | |
6555 (match_operand:BLK 1 "memory_operand" ""))) | |
6556 (use (match_operand 2 "const_int_operand" "")) | |
6557 (clobber (reg:CC CC_REGNUM))]) | |
6558 (parallel | |
6559 [(set (match_operand:BLK 3 "memory_operand" "") | |
6560 (xor:BLK (match_dup 3) | |
6561 (match_operand:BLK 4 "memory_operand" ""))) | |
6562 (use (match_operand 5 "const_int_operand" "")) | |
6563 (clobber (reg:CC CC_REGNUM))])] | |
6564 "s390_offset_p (operands[0], operands[3], operands[2]) | |
6565 && s390_offset_p (operands[1], operands[4], operands[2]) | |
6566 && !s390_overlap_p (operands[0], operands[1], | |
6567 INTVAL (operands[2]) + INTVAL (operands[5])) | |
6568 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
6569 [(parallel | |
6570 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
6571 (use (match_dup 8)) | |
6572 (clobber (reg:CC CC_REGNUM))])] | |
6573 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
6574 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6575 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6576 | |
6577 ; | |
6578 ; Block xor (XC) patterns with src == dest. | |
6579 ; | |
6580 | |
6581 (define_insn "*xc_zero" | |
6582 [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6583 (const_int 0)) | |
6584 (use (match_operand 1 "const_int_operand" "n")) | |
6585 (clobber (reg:CC CC_REGNUM))] | |
6586 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" | |
6587 "xc\t%O0(%1,%R0),%S0" | |
6588 [(set_attr "op_type" "SS")]) | |
6589 | |
6590 (define_peephole2 | |
6591 [(parallel | |
6592 [(set (match_operand:BLK 0 "memory_operand" "") | |
6593 (const_int 0)) | |
6594 (use (match_operand 1 "const_int_operand" "")) | |
6595 (clobber (reg:CC CC_REGNUM))]) | |
6596 (parallel | |
6597 [(set (match_operand:BLK 2 "memory_operand" "") | |
6598 (const_int 0)) | |
6599 (use (match_operand 3 "const_int_operand" "")) | |
6600 (clobber (reg:CC CC_REGNUM))])] | |
6601 "s390_offset_p (operands[0], operands[2], operands[1]) | |
6602 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
6603 [(parallel | |
6604 [(set (match_dup 4) (const_int 0)) | |
6605 (use (match_dup 5)) | |
6606 (clobber (reg:CC CC_REGNUM))])] | |
6607 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
6608 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
6609 | |
6610 | |
6611 ;; | |
6612 ;;- Negate instructions. | |
6613 ;; | |
6614 | |
6615 ; | |
6616 ; neg(di|si)2 instruction pattern(s). | |
6617 ; | |
6618 | |
6619 (define_expand "neg<mode>2" | |
6620 [(parallel | |
6621 [(set (match_operand:DSI 0 "register_operand" "=d") | |
6622 (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
6623 (clobber (reg:CC CC_REGNUM))])] | |
6624 "" | |
6625 "") | |
6626 | |
6627 (define_insn "*negdi2_sign_cc" | |
6628 [(set (reg CC_REGNUM) | |
6629 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
6630 (match_operand:SI 1 "register_operand" "d") 0) | |
6631 (const_int 32)) (const_int 32))) | |
6632 (const_int 0))) | |
6633 (set (match_operand:DI 0 "register_operand" "=d") | |
6634 (neg:DI (sign_extend:DI (match_dup 1))))] | |
6635 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6636 "lcgfr\t%0,%1" | |
6637 [(set_attr "op_type" "RRE") | |
6638 (set_attr "z10prop" "z10_c")]) | |
6639 | |
6640 (define_insn "*negdi2_sign" | |
6641 [(set (match_operand:DI 0 "register_operand" "=d") | |
6642 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
6643 (clobber (reg:CC CC_REGNUM))] | |
6644 "TARGET_64BIT" | |
6645 "lcgfr\t%0,%1" | |
6646 [(set_attr "op_type" "RRE") | |
6647 (set_attr "z10prop" "z10_c")]) | |
6648 | |
6649 ; lcr, lcgr | |
6650 (define_insn "*neg<mode>2_cc" | |
6651 [(set (reg CC_REGNUM) | |
6652 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) | |
6653 (const_int 0))) | |
6654 (set (match_operand:GPR 0 "register_operand" "=d") | |
6655 (neg:GPR (match_dup 1)))] | |
6656 "s390_match_ccmode (insn, CCAmode)" | |
6657 "lc<g>r\t%0,%1" | |
6658 [(set_attr "op_type" "RR<E>") | |
6659 (set_attr "z10prop" "z10_super_c_E1")]) | |
6660 | |
6661 ; lcr, lcgr | |
6662 (define_insn "*neg<mode>2_cconly" | |
6663 [(set (reg CC_REGNUM) | |
6664 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) | |
6665 (const_int 0))) | |
6666 (clobber (match_scratch:GPR 0 "=d"))] | |
6667 "s390_match_ccmode (insn, CCAmode)" | |
6668 "lc<g>r\t%0,%1" | |
6669 [(set_attr "op_type" "RR<E>") | |
6670 (set_attr "z10prop" "z10_super_c_E1")]) | |
6671 | |
6672 ; lcr, lcgr | |
6673 (define_insn "*neg<mode>2" | |
6674 [(set (match_operand:GPR 0 "register_operand" "=d") | |
6675 (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
6676 (clobber (reg:CC CC_REGNUM))] | |
6677 "" | |
6678 "lc<g>r\t%0,%1" | |
6679 [(set_attr "op_type" "RR<E>") | |
6680 (set_attr "z10prop" "z10_super_c_E1")]) | |
6681 | |
6682 (define_insn_and_split "*negdi2_31" | |
6683 [(set (match_operand:DI 0 "register_operand" "=d") | |
6684 (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
6685 (clobber (reg:CC CC_REGNUM))] | |
6686 "!TARGET_64BIT" | |
6687 "#" | |
6688 "&& reload_completed" | |
6689 [(parallel | |
6690 [(set (match_dup 2) (neg:SI (match_dup 3))) | |
6691 (clobber (reg:CC CC_REGNUM))]) | |
6692 (parallel | |
6693 [(set (reg:CCAP CC_REGNUM) | |
6694 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) | |
6695 (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
6696 (set (pc) | |
6697 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
6698 (pc) | |
6699 (label_ref (match_dup 6)))) | |
6700 (parallel | |
6701 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
6702 (clobber (reg:CC CC_REGNUM))]) | |
6703 (match_dup 6)] | |
6704 "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
6705 operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
6706 operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
6707 operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
6708 operands[6] = gen_label_rtx ();") | |
6709 | |
6710 ; | |
6711 ; neg(df|sf)2 instruction pattern(s). | |
6712 ; | |
6713 | |
6714 (define_expand "neg<mode>2" | |
6715 [(parallel | |
6716 [(set (match_operand:BFP 0 "register_operand" "=f") | |
6717 (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
6718 (clobber (reg:CC CC_REGNUM))])] | |
6719 "TARGET_HARD_FLOAT" | |
6720 "") | |
6721 | |
6722 ; lcxbr, lcdbr, lcebr | |
6723 (define_insn "*neg<mode>2_cc" | |
6724 [(set (reg CC_REGNUM) | |
6725 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) | |
6726 (match_operand:BFP 2 "const0_operand" ""))) | |
6727 (set (match_operand:BFP 0 "register_operand" "=f") | |
6728 (neg:BFP (match_dup 1)))] | |
6729 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" | |
6730 "lc<xde>br\t%0,%1" | |
6731 [(set_attr "op_type" "RRE") | |
6732 (set_attr "type" "fsimp<mode>")]) | |
6733 | |
6734 ; lcxbr, lcdbr, lcebr | |
6735 (define_insn "*neg<mode>2_cconly" | |
6736 [(set (reg CC_REGNUM) | |
6737 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) | |
6738 (match_operand:BFP 2 "const0_operand" ""))) | |
6739 (clobber (match_scratch:BFP 0 "=f"))] | |
6740 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" | |
6741 "lc<xde>br\t%0,%1" | |
6742 [(set_attr "op_type" "RRE") | |
6743 (set_attr "type" "fsimp<mode>")]) | |
6744 | |
6745 ; lcdfr | |
6746 (define_insn "*neg<mode>2_nocc" | |
6747 [(set (match_operand:FP 0 "register_operand" "=f") | |
6748 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
6749 "TARGET_DFP" | |
6750 "lcdfr\t%0,%1" | |
6751 [(set_attr "op_type" "RRE") | |
6752 (set_attr "type" "fsimp<mode>")]) | |
6753 | |
6754 ; lcxbr, lcdbr, lcebr | |
6755 (define_insn "*neg<mode>2" | |
6756 [(set (match_operand:BFP 0 "register_operand" "=f") | |
6757 (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
6758 (clobber (reg:CC CC_REGNUM))] | |
6759 "TARGET_HARD_FLOAT" | |
6760 "lc<xde>br\t%0,%1" | |
6761 [(set_attr "op_type" "RRE") | |
6762 (set_attr "type" "fsimp<mode>")]) | |
6763 | |
6764 | |
6765 ;; | |
6766 ;;- Absolute value instructions. | |
6767 ;; | |
6768 | |
6769 ; | |
6770 ; abs(di|si)2 instruction pattern(s). | |
6771 ; | |
6772 | |
6773 (define_insn "*absdi2_sign_cc" | |
6774 [(set (reg CC_REGNUM) | |
6775 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
6776 (match_operand:SI 1 "register_operand" "d") 0) | |
6777 (const_int 32)) (const_int 32))) | |
6778 (const_int 0))) | |
6779 (set (match_operand:DI 0 "register_operand" "=d") | |
6780 (abs:DI (sign_extend:DI (match_dup 1))))] | |
6781 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6782 "lpgfr\t%0,%1" | |
6783 [(set_attr "op_type" "RRE") | |
6784 (set_attr "z10prop" "z10_c")]) | |
6785 | |
6786 (define_insn "*absdi2_sign" | |
6787 [(set (match_operand:DI 0 "register_operand" "=d") | |
6788 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
6789 (clobber (reg:CC CC_REGNUM))] | |
6790 "TARGET_64BIT" | |
6791 "lpgfr\t%0,%1" | |
6792 [(set_attr "op_type" "RRE") | |
6793 (set_attr "z10prop" "z10_c")]) | |
6794 | |
6795 ; lpr, lpgr | |
6796 (define_insn "*abs<mode>2_cc" | |
6797 [(set (reg CC_REGNUM) | |
6798 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) | |
6799 (const_int 0))) | |
6800 (set (match_operand:GPR 0 "register_operand" "=d") | |
6801 (abs:GPR (match_dup 1)))] | |
6802 "s390_match_ccmode (insn, CCAmode)" | |
6803 "lp<g>r\t%0,%1" | |
6804 [(set_attr "op_type" "RR<E>") | |
6805 (set_attr "z10prop" "z10_c")]) | |
6806 | |
6807 ; lpr, lpgr | |
6808 (define_insn "*abs<mode>2_cconly" | |
6809 [(set (reg CC_REGNUM) | |
6810 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) | |
6811 (const_int 0))) | |
6812 (clobber (match_scratch:GPR 0 "=d"))] | |
6813 "s390_match_ccmode (insn, CCAmode)" | |
6814 "lp<g>r\t%0,%1" | |
6815 [(set_attr "op_type" "RR<E>") | |
6816 (set_attr "z10prop" "z10_c")]) | |
6817 | |
6818 ; lpr, lpgr | |
6819 (define_insn "abs<mode>2" | |
6820 [(set (match_operand:GPR 0 "register_operand" "=d") | |
6821 (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
6822 (clobber (reg:CC CC_REGNUM))] | |
6823 "" | |
6824 "lp<g>r\t%0,%1" | |
6825 [(set_attr "op_type" "RR<E>") | |
6826 (set_attr "z10prop" "z10_c")]) | |
6827 | |
6828 ; | |
6829 ; abs(df|sf)2 instruction pattern(s). | |
6830 ; | |
6831 | |
6832 (define_expand "abs<mode>2" | |
6833 [(parallel | |
6834 [(set (match_operand:BFP 0 "register_operand" "=f") | |
6835 (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
6836 (clobber (reg:CC CC_REGNUM))])] | |
6837 "TARGET_HARD_FLOAT" | |
6838 "") | |
6839 | |
6840 ; lpxbr, lpdbr, lpebr | |
6841 (define_insn "*abs<mode>2_cc" | |
6842 [(set (reg CC_REGNUM) | |
6843 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) | |
6844 (match_operand:BFP 2 "const0_operand" ""))) | |
6845 (set (match_operand:BFP 0 "register_operand" "=f") | |
6846 (abs:BFP (match_dup 1)))] | |
6847 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" | |
6848 "lp<xde>br\t%0,%1" | |
6849 [(set_attr "op_type" "RRE") | |
6850 (set_attr "type" "fsimp<mode>")]) | |
6851 | |
6852 ; lpxbr, lpdbr, lpebr | |
6853 (define_insn "*abs<mode>2_cconly" | |
6854 [(set (reg CC_REGNUM) | |
6855 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) | |
6856 (match_operand:BFP 2 "const0_operand" ""))) | |
6857 (clobber (match_scratch:BFP 0 "=f"))] | |
6858 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" | |
6859 "lp<xde>br\t%0,%1" | |
6860 [(set_attr "op_type" "RRE") | |
6861 (set_attr "type" "fsimp<mode>")]) | |
6862 | |
6863 ; lpdfr | |
6864 (define_insn "*abs<mode>2_nocc" | |
6865 [(set (match_operand:FP 0 "register_operand" "=f") | |
6866 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
6867 "TARGET_DFP" | |
6868 "lpdfr\t%0,%1" | |
6869 [(set_attr "op_type" "RRE") | |
6870 (set_attr "type" "fsimp<mode>")]) | |
6871 | |
6872 ; lpxbr, lpdbr, lpebr | |
6873 (define_insn "*abs<mode>2" | |
6874 [(set (match_operand:BFP 0 "register_operand" "=f") | |
6875 (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
6876 (clobber (reg:CC CC_REGNUM))] | |
6877 "TARGET_HARD_FLOAT" | |
6878 "lp<xde>br\t%0,%1" | |
6879 [(set_attr "op_type" "RRE") | |
6880 (set_attr "type" "fsimp<mode>")]) | |
6881 | |
6882 | |
6883 ;; | |
6884 ;;- Negated absolute value instructions | |
6885 ;; | |
6886 | |
6887 ; | |
6888 ; Integer | |
6889 ; | |
6890 | |
6891 (define_insn "*negabsdi2_sign_cc" | |
6892 [(set (reg CC_REGNUM) | |
6893 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
6894 (match_operand:SI 1 "register_operand" "d") 0) | |
6895 (const_int 32)) (const_int 32)))) | |
6896 (const_int 0))) | |
6897 (set (match_operand:DI 0 "register_operand" "=d") | |
6898 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
6899 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6900 "lngfr\t%0,%1" | |
6901 [(set_attr "op_type" "RRE") | |
6902 (set_attr "z10prop" "z10_c")]) | |
6903 | |
6904 (define_insn "*negabsdi2_sign" | |
6905 [(set (match_operand:DI 0 "register_operand" "=d") | |
6906 (neg:DI (abs:DI (sign_extend:DI | |
6907 (match_operand:SI 1 "register_operand" "d"))))) | |
6908 (clobber (reg:CC CC_REGNUM))] | |
6909 "TARGET_64BIT" | |
6910 "lngfr\t%0,%1" | |
6911 [(set_attr "op_type" "RRE") | |
6912 (set_attr "z10prop" "z10_c")]) | |
6913 | |
6914 ; lnr, lngr | |
6915 (define_insn "*negabs<mode>2_cc" | |
6916 [(set (reg CC_REGNUM) | |
6917 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
6918 (const_int 0))) | |
6919 (set (match_operand:GPR 0 "register_operand" "=d") | |
6920 (neg:GPR (abs:GPR (match_dup 1))))] | |
6921 "s390_match_ccmode (insn, CCAmode)" | |
6922 "ln<g>r\t%0,%1" | |
6923 [(set_attr "op_type" "RR<E>") | |
6924 (set_attr "z10prop" "z10_c")]) | |
6925 | |
6926 ; lnr, lngr | |
6927 (define_insn "*negabs<mode>2_cconly" | |
6928 [(set (reg CC_REGNUM) | |
6929 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
6930 (const_int 0))) | |
6931 (clobber (match_scratch:GPR 0 "=d"))] | |
6932 "s390_match_ccmode (insn, CCAmode)" | |
6933 "ln<g>r\t%0,%1" | |
6934 [(set_attr "op_type" "RR<E>") | |
6935 (set_attr "z10prop" "z10_c")]) | |
6936 | |
6937 ; lnr, lngr | |
6938 (define_insn "*negabs<mode>2" | |
6939 [(set (match_operand:GPR 0 "register_operand" "=d") | |
6940 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
6941 (clobber (reg:CC CC_REGNUM))] | |
6942 "" | |
6943 "ln<g>r\t%0,%1" | |
6944 [(set_attr "op_type" "RR<E>") | |
6945 (set_attr "z10prop" "z10_c")]) | |
6946 | |
6947 ; | |
6948 ; Floating point | |
6949 ; | |
6950 | |
6951 ; lnxbr, lndbr, lnebr | |
6952 (define_insn "*negabs<mode>2_cc" | |
6953 [(set (reg CC_REGNUM) | |
6954 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
6955 (match_operand:BFP 2 "const0_operand" ""))) | |
6956 (set (match_operand:BFP 0 "register_operand" "=f") | |
6957 (neg:BFP (abs:BFP (match_dup 1))))] | |
6958 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" | |
6959 "ln<xde>br\t%0,%1" | |
6960 [(set_attr "op_type" "RRE") | |
6961 (set_attr "type" "fsimp<mode>")]) | |
6962 | |
6963 ; lnxbr, lndbr, lnebr | |
6964 (define_insn "*negabs<mode>2_cconly" | |
6965 [(set (reg CC_REGNUM) | |
6966 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
6967 (match_operand:BFP 2 "const0_operand" ""))) | |
6968 (clobber (match_scratch:BFP 0 "=f"))] | |
6969 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" | |
6970 "ln<xde>br\t%0,%1" | |
6971 [(set_attr "op_type" "RRE") | |
6972 (set_attr "type" "fsimp<mode>")]) | |
6973 | |
6974 ; lndfr | |
6975 (define_insn "*negabs<mode>2_nocc" | |
6976 [(set (match_operand:FP 0 "register_operand" "=f") | |
6977 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
6978 "TARGET_DFP" | |
6979 "lndfr\t%0,%1" | |
6980 [(set_attr "op_type" "RRE") | |
6981 (set_attr "type" "fsimp<mode>")]) | |
6982 | |
6983 ; lnxbr, lndbr, lnebr | |
6984 (define_insn "*negabs<mode>2" | |
6985 [(set (match_operand:BFP 0 "register_operand" "=f") | |
6986 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))) | |
6987 (clobber (reg:CC CC_REGNUM))] | |
6988 "TARGET_HARD_FLOAT" | |
6989 "ln<xde>br\t%0,%1" | |
6990 [(set_attr "op_type" "RRE") | |
6991 (set_attr "type" "fsimp<mode>")]) | |
6992 | |
6993 ;; | |
6994 ;;- Copy sign instructions | |
6995 ;; | |
6996 | |
6997 ; cpsdr | |
6998 (define_insn "copysign<mode>3" | |
6999 [(set (match_operand:FP 0 "register_operand" "=f") | |
7000 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
7001 (match_operand:FP 2 "register_operand" "f")] | |
7002 UNSPEC_COPYSIGN))] | |
7003 "TARGET_DFP" | |
7004 "cpsdr\t%0,%2,%1" | |
7005 [(set_attr "op_type" "RRF") | |
7006 (set_attr "type" "fsimp<mode>")]) | |
7007 | |
7008 ;; | |
7009 ;;- Square root instructions. | |
7010 ;; | |
7011 | |
7012 ; | |
7013 ; sqrt(df|sf)2 instruction pattern(s). | |
7014 ; | |
7015 | |
7016 ; sqxbr, sqdbr, sqebr, sqdb, sqeb | |
7017 (define_insn "sqrt<mode>2" | |
7018 [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
7019 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))] | |
7020 "TARGET_HARD_FLOAT" | |
7021 "@ | |
7022 sq<xde>br\t%0,%1 | |
7023 sq<xde>b\t%0,%1" | |
7024 [(set_attr "op_type" "RRE,RXE") | |
7025 (set_attr "type" "fsqrt<mode>")]) | |
7026 | |
7027 | |
7028 ;; | |
7029 ;;- One complement instructions. | |
7030 ;; | |
7031 | |
7032 ; | |
7033 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). | |
7034 ; | |
7035 | |
7036 (define_expand "one_cmpl<mode>2" | |
7037 [(parallel | |
7038 [(set (match_operand:INT 0 "register_operand" "") | |
7039 (xor:INT (match_operand:INT 1 "register_operand" "") | |
7040 (const_int -1))) | |
7041 (clobber (reg:CC CC_REGNUM))])] | |
7042 "" | |
7043 "") | |
7044 | |
7045 | |
7046 ;; | |
7047 ;; Find leftmost bit instructions. | |
7048 ;; | |
7049 | |
7050 (define_expand "clzdi2" | |
7051 [(set (match_operand:DI 0 "register_operand" "=d") | |
7052 (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
7053 "TARGET_EXTIMM && TARGET_64BIT" | |
7054 { | |
7055 rtx insn, clz_equal; | |
7056 rtx wide_reg = gen_reg_rtx (TImode); | |
7057 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
7058 | |
7059 clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
7060 | |
7061 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
7062 | |
7063 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); | |
7064 set_unique_reg_note (insn, REG_EQUAL, clz_equal); | |
7065 | |
7066 DONE; | |
7067 }) | |
7068 | |
7069 (define_insn "clztidi2" | |
7070 [(set (match_operand:TI 0 "register_operand" "=d") | |
7071 (ior:TI | |
7072 (ashift:TI | |
7073 (zero_extend:TI | |
7074 (xor:DI (match_operand:DI 1 "register_operand" "d") | |
7075 (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
7076 (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
7077 | |
7078 (const_int 64)) | |
7079 (zero_extend:TI (clz:DI (match_dup 1))))) | |
7080 (clobber (reg:CC CC_REGNUM))] | |
7081 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) | |
7082 == (unsigned HOST_WIDE_INT) 1 << 63 | |
7083 && TARGET_EXTIMM && TARGET_64BIT" | |
7084 "flogr\t%0,%1" | |
7085 [(set_attr "op_type" "RRE")]) | |
7086 | |
7087 | |
7088 ;; | |
7089 ;;- Rotate instructions. | |
7090 ;; | |
7091 | |
7092 ; | |
7093 ; rotl(di|si)3 instruction pattern(s). | |
7094 ; | |
7095 | |
7096 ; rll, rllg | |
7097 (define_insn "rotl<mode>3" | |
7098 [(set (match_operand:GPR 0 "register_operand" "=d") | |
7099 (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
7100 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] | |
7101 "TARGET_CPU_ZARCH" | |
7102 "rll<g>\t%0,%1,%Y2" | |
7103 [(set_attr "op_type" "RSE") | |
7104 (set_attr "atype" "reg") | |
7105 (set_attr "z10prop" "z10_super_E1")]) | |
7106 | |
7107 ; rll, rllg | |
7108 (define_insn "*rotl<mode>3_and" | |
7109 [(set (match_operand:GPR 0 "register_operand" "=d") | |
7110 (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
7111 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7112 (match_operand:SI 3 "const_int_operand" "n"))))] | |
7113 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
7114 "rll<g>\t%0,%1,%Y2" | |
7115 [(set_attr "op_type" "RSE") | |
7116 (set_attr "atype" "reg") | |
7117 (set_attr "z10prop" "z10_super_E1")]) | |
7118 | |
7119 | |
7120 ;; | |
7121 ;;- Shift instructions. | |
7122 ;; | |
7123 | |
7124 ; | |
7125 ; (ashl|lshr)(di|si)3 instruction pattern(s). | |
7126 ; | |
7127 | |
7128 (define_expand "<shift><mode>3" | |
7129 [(set (match_operand:DSI 0 "register_operand" "") | |
7130 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
7131 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
7132 "" | |
7133 "") | |
7134 | |
7135 ; sldl, srdl | |
7136 (define_insn "*<shift>di3_31" | |
7137 [(set (match_operand:DI 0 "register_operand" "=d") | |
7138 (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
7139 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] | |
7140 "!TARGET_64BIT" | |
7141 "s<lr>dl\t%0,%Y2" | |
7142 [(set_attr "op_type" "RS") | |
7143 (set_attr "atype" "reg")]) | |
7144 | |
7145 ; sll, srl, sllg, srlg | |
7146 (define_insn "*<shift><mode>3" | |
7147 [(set (match_operand:GPR 0 "register_operand" "=d") | |
7148 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7149 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] | |
7150 "" | |
7151 "s<lr>l<g>\t%0,<1>%Y2" | |
7152 [(set_attr "op_type" "RS<E>") | |
7153 (set_attr "atype" "reg") | |
7154 (set_attr "z10prop" "z10_super_E1")]) | |
7155 | |
7156 ; sldl, srdl | |
7157 (define_insn "*<shift>di3_31_and" | |
7158 [(set (match_operand:DI 0 "register_operand" "=d") | |
7159 (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
7160 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7161 (match_operand:SI 3 "const_int_operand" "n"))))] | |
7162 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" | |
7163 "s<lr>dl\t%0,%Y2" | |
7164 [(set_attr "op_type" "RS") | |
7165 (set_attr "atype" "reg")]) | |
7166 | |
7167 ; sll, srl, sllg, srlg | |
7168 (define_insn "*<shift><mode>3_and" | |
7169 [(set (match_operand:GPR 0 "register_operand" "=d") | |
7170 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7171 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7172 (match_operand:SI 3 "const_int_operand" "n"))))] | |
7173 "(INTVAL (operands[3]) & 63) == 63" | |
7174 "s<lr>l<g>\t%0,<1>%Y2" | |
7175 [(set_attr "op_type" "RS<E>") | |
7176 (set_attr "atype" "reg") | |
7177 (set_attr "z10prop" "z10_super_E1")]) | |
7178 | |
7179 ; | |
7180 ; ashr(di|si)3 instruction pattern(s). | |
7181 ; | |
7182 | |
7183 (define_expand "ashr<mode>3" | |
7184 [(parallel | |
7185 [(set (match_operand:DSI 0 "register_operand" "") | |
7186 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
7187 (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
7188 (clobber (reg:CC CC_REGNUM))])] | |
7189 "" | |
7190 "") | |
7191 | |
7192 (define_insn "*ashrdi3_cc_31" | |
7193 [(set (reg CC_REGNUM) | |
7194 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7195 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
7196 (const_int 0))) | |
7197 (set (match_operand:DI 0 "register_operand" "=d") | |
7198 (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
7199 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
7200 "srda\t%0,%Y2" | |
7201 [(set_attr "op_type" "RS") | |
7202 (set_attr "atype" "reg")]) | |
7203 | |
7204 (define_insn "*ashrdi3_cconly_31" | |
7205 [(set (reg CC_REGNUM) | |
7206 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7207 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
7208 (const_int 0))) | |
7209 (clobber (match_scratch:DI 0 "=d"))] | |
7210 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
7211 "srda\t%0,%Y2" | |
7212 [(set_attr "op_type" "RS") | |
7213 (set_attr "atype" "reg")]) | |
7214 | |
7215 (define_insn "*ashrdi3_31" | |
7216 [(set (match_operand:DI 0 "register_operand" "=d") | |
7217 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7218 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) | |
7219 (clobber (reg:CC CC_REGNUM))] | |
7220 "!TARGET_64BIT" | |
7221 "srda\t%0,%Y2" | |
7222 [(set_attr "op_type" "RS") | |
7223 (set_attr "atype" "reg")]) | |
7224 | |
7225 ; sra, srag | |
7226 (define_insn "*ashr<mode>3_cc" | |
7227 [(set (reg CC_REGNUM) | |
7228 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7229 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
7230 (const_int 0))) | |
7231 (set (match_operand:GPR 0 "register_operand" "=d") | |
7232 (ashiftrt:GPR (match_dup 1) (match_dup 2)))] | |
7233 "s390_match_ccmode(insn, CCSmode)" | |
7234 "sra<g>\t%0,<1>%Y2" | |
7235 [(set_attr "op_type" "RS<E>") | |
7236 (set_attr "atype" "reg") | |
7237 (set_attr "z10prop" "z10_super_E1")]) | |
7238 | |
7239 ; sra, srag | |
7240 (define_insn "*ashr<mode>3_cconly" | |
7241 [(set (reg CC_REGNUM) | |
7242 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7243 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
7244 (const_int 0))) | |
7245 (clobber (match_scratch:GPR 0 "=d"))] | |
7246 "s390_match_ccmode(insn, CCSmode)" | |
7247 "sra<g>\t%0,<1>%Y2" | |
7248 [(set_attr "op_type" "RS<E>") | |
7249 (set_attr "atype" "reg") | |
7250 (set_attr "z10prop" "z10_super_E1")]) | |
7251 | |
7252 ; sra, srag | |
7253 (define_insn "*ashr<mode>3" | |
7254 [(set (match_operand:GPR 0 "register_operand" "=d") | |
7255 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7256 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) | |
7257 (clobber (reg:CC CC_REGNUM))] | |
7258 "" | |
7259 "sra<g>\t%0,<1>%Y2" | |
7260 [(set_attr "op_type" "RS<E>") | |
7261 (set_attr "atype" "reg") | |
7262 (set_attr "z10prop" "z10_super_E1")]) | |
7263 | |
7264 | |
7265 ; shift pattern with implicit ANDs | |
7266 | |
7267 (define_insn "*ashrdi3_cc_31_and" | |
7268 [(set (reg CC_REGNUM) | |
7269 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7270 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7271 (match_operand:SI 3 "const_int_operand" "n"))) | |
7272 (const_int 0))) | |
7273 (set (match_operand:DI 0 "register_operand" "=d") | |
7274 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
7275 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) | |
7276 && (INTVAL (operands[3]) & 63) == 63" | |
7277 "srda\t%0,%Y2" | |
7278 [(set_attr "op_type" "RS") | |
7279 (set_attr "atype" "reg")]) | |
7280 | |
7281 (define_insn "*ashrdi3_cconly_31_and" | |
7282 [(set (reg CC_REGNUM) | |
7283 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7284 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7285 (match_operand:SI 3 "const_int_operand" "n"))) | |
7286 (const_int 0))) | |
7287 (clobber (match_scratch:DI 0 "=d"))] | |
7288 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) | |
7289 && (INTVAL (operands[3]) & 63) == 63" | |
7290 "srda\t%0,%Y2" | |
7291 [(set_attr "op_type" "RS") | |
7292 (set_attr "atype" "reg")]) | |
7293 | |
7294 (define_insn "*ashrdi3_31_and" | |
7295 [(set (match_operand:DI 0 "register_operand" "=d") | |
7296 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7297 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7298 (match_operand:SI 3 "const_int_operand" "n")))) | |
7299 (clobber (reg:CC CC_REGNUM))] | |
7300 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" | |
7301 "srda\t%0,%Y2" | |
7302 [(set_attr "op_type" "RS") | |
7303 (set_attr "atype" "reg")]) | |
7304 | |
7305 ; sra, srag | |
7306 (define_insn "*ashr<mode>3_cc_and" | |
7307 [(set (reg CC_REGNUM) | |
7308 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7309 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7310 (match_operand:SI 3 "const_int_operand" "n"))) | |
7311 (const_int 0))) | |
7312 (set (match_operand:GPR 0 "register_operand" "=d") | |
7313 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
7314 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" | |
7315 "sra<g>\t%0,<1>%Y2" | |
7316 [(set_attr "op_type" "RS<E>") | |
7317 (set_attr "atype" "reg") | |
7318 (set_attr "z10prop" "z10_super_E1")]) | |
7319 | |
7320 ; sra, srag | |
7321 (define_insn "*ashr<mode>3_cconly_and" | |
7322 [(set (reg CC_REGNUM) | |
7323 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7324 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7325 (match_operand:SI 3 "const_int_operand" "n"))) | |
7326 (const_int 0))) | |
7327 (clobber (match_scratch:GPR 0 "=d"))] | |
7328 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" | |
7329 "sra<g>\t%0,<1>%Y2" | |
7330 [(set_attr "op_type" "RS<E>") | |
7331 (set_attr "atype" "reg") | |
7332 (set_attr "z10prop" "z10_super_E1")]) | |
7333 | |
7334 ; sra, srag | |
7335 (define_insn "*ashr<mode>3_and" | |
7336 [(set (match_operand:GPR 0 "register_operand" "=d") | |
7337 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7338 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7339 (match_operand:SI 3 "const_int_operand" "n")))) | |
7340 (clobber (reg:CC CC_REGNUM))] | |
7341 "(INTVAL (operands[3]) & 63) == 63" | |
7342 "sra<g>\t%0,<1>%Y2" | |
7343 [(set_attr "op_type" "RS<E>") | |
7344 (set_attr "atype" "reg") | |
7345 (set_attr "z10prop" "z10_super_E1")]) | |
7346 | |
7347 | |
7348 ;; | |
7349 ;; Branch instruction patterns. | |
7350 ;; | |
7351 | |
7352 (define_expand "b<code>" | |
7353 [(set (pc) | |
7354 (if_then_else (COMPARE (match_operand 0 "" "") | |
7355 (const_int 0)) | |
7356 (match_dup 0) | |
7357 (pc)))] | |
7358 "" | |
7359 "s390_emit_jump (operands[0], | |
7360 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;") | |
7361 | |
7362 | |
7363 ;; | |
7364 ;;- Conditional jump instructions. | |
7365 ;; | |
7366 | |
7367 (define_insn "*cjump_64" | |
7368 [(set (pc) | |
7369 (if_then_else | |
7370 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
7371 (label_ref (match_operand 0 "" "")) | |
7372 (pc)))] | |
7373 "TARGET_CPU_ZARCH" | |
7374 { | |
7375 if (get_attr_length (insn) == 4) | |
7376 return "j%C1\t%l0"; | |
7377 else | |
7378 return "jg%C1\t%l0"; | |
7379 } | |
7380 [(set_attr "op_type" "RI") | |
7381 (set_attr "type" "branch") | |
7382 (set (attr "length") | |
7383 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7384 (const_int 4) (const_int 6)))]) | |
7385 | |
7386 (define_insn "*cjump_31" | |
7387 [(set (pc) | |
7388 (if_then_else | |
7389 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
7390 (label_ref (match_operand 0 "" "")) | |
7391 (pc)))] | |
7392 "!TARGET_CPU_ZARCH" | |
7393 { | |
7394 gcc_assert (get_attr_length (insn) == 4); | |
7395 return "j%C1\t%l0"; | |
7396 } | |
7397 [(set_attr "op_type" "RI") | |
7398 (set_attr "type" "branch") | |
7399 (set (attr "length") | |
7400 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) | |
7401 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7402 (const_int 4) (const_int 6)) | |
7403 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7404 (const_int 4) (const_int 8))))]) | |
7405 | |
7406 (define_insn "*cjump_long" | |
7407 [(set (pc) | |
7408 (if_then_else | |
7409 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
7410 (match_operand 0 "address_operand" "U") | |
7411 (pc)))] | |
7412 "" | |
7413 { | |
7414 if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7415 return "b%C1r\t%0"; | |
7416 else | |
7417 return "b%C1\t%a0"; | |
7418 } | |
7419 [(set (attr "op_type") | |
7420 (if_then_else (match_operand 0 "register_operand" "") | |
7421 (const_string "RR") (const_string "RX"))) | |
7422 (set_attr "type" "branch") | |
7423 (set_attr "atype" "agen")]) | |
7424 | |
7425 | |
7426 ;; | |
7427 ;;- Negated conditional jump instructions. | |
7428 ;; | |
7429 | |
7430 (define_insn "*icjump_64" | |
7431 [(set (pc) | |
7432 (if_then_else | |
7433 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
7434 (pc) | |
7435 (label_ref (match_operand 0 "" ""))))] | |
7436 "TARGET_CPU_ZARCH" | |
7437 { | |
7438 if (get_attr_length (insn) == 4) | |
7439 return "j%D1\t%l0"; | |
7440 else | |
7441 return "jg%D1\t%l0"; | |
7442 } | |
7443 [(set_attr "op_type" "RI") | |
7444 (set_attr "type" "branch") | |
7445 (set (attr "length") | |
7446 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7447 (const_int 4) (const_int 6)))]) | |
7448 | |
7449 (define_insn "*icjump_31" | |
7450 [(set (pc) | |
7451 (if_then_else | |
7452 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
7453 (pc) | |
7454 (label_ref (match_operand 0 "" ""))))] | |
7455 "!TARGET_CPU_ZARCH" | |
7456 { | |
7457 gcc_assert (get_attr_length (insn) == 4); | |
7458 return "j%D1\t%l0"; | |
7459 } | |
7460 [(set_attr "op_type" "RI") | |
7461 (set_attr "type" "branch") | |
7462 (set (attr "length") | |
7463 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) | |
7464 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7465 (const_int 4) (const_int 6)) | |
7466 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7467 (const_int 4) (const_int 8))))]) | |
7468 | |
7469 (define_insn "*icjump_long" | |
7470 [(set (pc) | |
7471 (if_then_else | |
7472 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
7473 (pc) | |
7474 (match_operand 0 "address_operand" "U")))] | |
7475 "" | |
7476 { | |
7477 if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7478 return "b%D1r\t%0"; | |
7479 else | |
7480 return "b%D1\t%a0"; | |
7481 } | |
7482 [(set (attr "op_type") | |
7483 (if_then_else (match_operand 0 "register_operand" "") | |
7484 (const_string "RR") (const_string "RX"))) | |
7485 (set_attr "type" "branch") | |
7486 (set_attr "atype" "agen")]) | |
7487 | |
7488 ;; | |
7489 ;;- Trap instructions. | |
7490 ;; | |
7491 | |
7492 (define_insn "trap" | |
7493 [(trap_if (const_int 1) (const_int 0))] | |
7494 "" | |
7495 "j\t.+2" | |
7496 [(set_attr "op_type" "RI") | |
7497 (set_attr "type" "branch")]) | |
7498 | |
7499 (define_expand "conditional_trap" | |
7500 [(trap_if (match_operand 0 "comparison_operator" "") | |
7501 (match_operand 1 "general_operand" ""))] | |
7502 "" | |
7503 { | |
7504 if (operands[1] != const0_rtx) FAIL; | |
7505 operands[0] = s390_emit_compare (GET_CODE (operands[0]), | |
7506 s390_compare_op0, s390_compare_op1); | |
7507 }) | |
7508 | |
7509 (define_insn "*trap" | |
7510 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
7511 (const_int 0))] | |
7512 "" | |
7513 "j%C0\t.+2"; | |
7514 [(set_attr "op_type" "RI") | |
7515 (set_attr "type" "branch")]) | |
7516 | |
7517 ; crt, cgrt, cit, cgit | |
7518 (define_insn "*cmp_and_trap_signed_int<mode>" | |
7519 [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
7520 [(match_operand:GPR 1 "register_operand" "d,d") | |
7521 (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
7522 (const_int 0))] | |
7523 "TARGET_Z10" | |
7524 "@ | |
7525 c<g>rt%C0\t%1,%2 | |
7526 c<g>it%C0\t%1,%h2" | |
7527 [(set_attr "op_type" "RRF,RIE") | |
7528 (set_attr "type" "branch") | |
7529 (set_attr "z10prop" "z10_super_c,z10_super")]) | |
7530 | |
7531 ; clrt, clgrt, clfit, clgit | |
7532 (define_insn "*cmp_and_trap_unsigned_int<mode>" | |
7533 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
7534 [(match_operand:GPR 1 "register_operand" "d,d") | |
7535 (match_operand:GPR 2 "nonmemory_operand" "d,D")]) | |
7536 (const_int 0))] | |
7537 "TARGET_Z10" | |
7538 "@ | |
7539 cl<g>rt%C0\t%1,%2 | |
7540 cl<gf>it%C0\t%1,%x2" | |
7541 [(set_attr "op_type" "RRF,RIE") | |
7542 (set_attr "type" "branch") | |
7543 (set_attr "z10prop" "z10_super_c,z10_super")]) | |
7544 | |
7545 ;; | |
7546 ;;- Loop instructions. | |
7547 ;; | |
7548 ;; This is all complicated by the fact that since this is a jump insn | |
7549 ;; we must handle our own output reloads. | |
7550 | |
7551 (define_expand "doloop_end" | |
7552 [(use (match_operand 0 "" "")) ; loop pseudo | |
7553 (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
7554 (use (match_operand 2 "" "")) ; max iterations | |
7555 (use (match_operand 3 "" "")) ; loop level | |
7556 (use (match_operand 4 "" ""))] ; label | |
7557 "" | |
7558 { | |
7559 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) | |
7560 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
7561 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
7562 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
7563 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) | |
7564 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
7565 else | |
7566 FAIL; | |
7567 | |
7568 DONE; | |
7569 }) | |
7570 | |
7571 (define_insn_and_split "doloop_si64" | |
7572 [(set (pc) | |
7573 (if_then_else | |
7574 (ne (match_operand:SI 1 "register_operand" "d,d,d") | |
7575 (const_int 1)) | |
7576 (label_ref (match_operand 0 "" "")) | |
7577 (pc))) | |
7578 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") | |
7579 (plus:SI (match_dup 1) (const_int -1))) | |
7580 (clobber (match_scratch:SI 3 "=X,&1,&?d")) | |
7581 (clobber (reg:CC CC_REGNUM))] | |
7582 "TARGET_CPU_ZARCH" | |
7583 { | |
7584 if (which_alternative != 0) | |
7585 return "#"; | |
7586 else if (get_attr_length (insn) == 4) | |
7587 return "brct\t%1,%l0"; | |
7588 else | |
7589 return "ahi\t%1,-1\;jgne\t%l0"; | |
7590 } | |
7591 "&& reload_completed | |
7592 && (! REG_P (operands[2]) | |
7593 || ! rtx_equal_p (operands[1], operands[2]))" | |
7594 [(set (match_dup 3) (match_dup 1)) | |
7595 (parallel [(set (reg:CCAN CC_REGNUM) | |
7596 (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) | |
7597 (const_int 0))) | |
7598 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
7599 (set (match_dup 2) (match_dup 3)) | |
7600 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) | |
7601 (label_ref (match_dup 0)) | |
7602 (pc)))] | |
7603 "" | |
7604 [(set_attr "op_type" "RI") | |
7605 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not | |
7606 ; hurt us in the (rare) case of ahi. | |
7607 (set_attr "z10prop" "z10_super_E1") | |
7608 (set_attr "type" "branch") | |
7609 (set (attr "length") | |
7610 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7611 (const_int 4) (const_int 10)))]) | |
7612 | |
7613 (define_insn_and_split "doloop_si31" | |
7614 [(set (pc) | |
7615 (if_then_else | |
7616 (ne (match_operand:SI 1 "register_operand" "d,d,d") | |
7617 (const_int 1)) | |
7618 (label_ref (match_operand 0 "" "")) | |
7619 (pc))) | |
7620 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") | |
7621 (plus:SI (match_dup 1) (const_int -1))) | |
7622 (clobber (match_scratch:SI 3 "=X,&1,&?d")) | |
7623 (clobber (reg:CC CC_REGNUM))] | |
7624 "!TARGET_CPU_ZARCH" | |
7625 { | |
7626 if (which_alternative != 0) | |
7627 return "#"; | |
7628 else if (get_attr_length (insn) == 4) | |
7629 return "brct\t%1,%l0"; | |
7630 else | |
7631 gcc_unreachable (); | |
7632 } | |
7633 "&& reload_completed | |
7634 && (! REG_P (operands[2]) | |
7635 || ! rtx_equal_p (operands[1], operands[2]))" | |
7636 [(set (match_dup 3) (match_dup 1)) | |
7637 (parallel [(set (reg:CCAN CC_REGNUM) | |
7638 (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) | |
7639 (const_int 0))) | |
7640 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
7641 (set (match_dup 2) (match_dup 3)) | |
7642 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) | |
7643 (label_ref (match_dup 0)) | |
7644 (pc)))] | |
7645 "" | |
7646 [(set_attr "op_type" "RI") | |
7647 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not | |
7648 ; hurt us in the (rare) case of ahi. | |
7649 (set_attr "z10prop" "z10_super_E1") | |
7650 (set_attr "type" "branch") | |
7651 (set (attr "length") | |
7652 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) | |
7653 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7654 (const_int 4) (const_int 6)) | |
7655 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7656 (const_int 4) (const_int 8))))]) | |
7657 | |
7658 (define_insn "*doloop_si_long" | |
7659 [(set (pc) | |
7660 (if_then_else | |
7661 (ne (match_operand:SI 1 "register_operand" "d") | |
7662 (const_int 1)) | |
7663 (match_operand 0 "address_operand" "U") | |
7664 (pc))) | |
7665 (set (match_operand:SI 2 "register_operand" "=1") | |
7666 (plus:SI (match_dup 1) (const_int -1))) | |
7667 (clobber (match_scratch:SI 3 "=X")) | |
7668 (clobber (reg:CC CC_REGNUM))] | |
7669 "!TARGET_CPU_ZARCH" | |
7670 { | |
7671 if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7672 return "bctr\t%1,%0"; | |
7673 else | |
7674 return "bct\t%1,%a0"; | |
7675 } | |
7676 [(set (attr "op_type") | |
7677 (if_then_else (match_operand 0 "register_operand" "") | |
7678 (const_string "RR") (const_string "RX"))) | |
7679 (set_attr "type" "branch") | |
7680 (set_attr "atype" "agen") | |
7681 (set_attr "z10prop" "z10_c")]) | |
7682 | |
7683 (define_insn_and_split "doloop_di" | |
7684 [(set (pc) | |
7685 (if_then_else | |
7686 (ne (match_operand:DI 1 "register_operand" "d,d,d") | |
7687 (const_int 1)) | |
7688 (label_ref (match_operand 0 "" "")) | |
7689 (pc))) | |
7690 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") | |
7691 (plus:DI (match_dup 1) (const_int -1))) | |
7692 (clobber (match_scratch:DI 3 "=X,&1,&?d")) | |
7693 (clobber (reg:CC CC_REGNUM))] | |
7694 "TARGET_64BIT" | |
7695 { | |
7696 if (which_alternative != 0) | |
7697 return "#"; | |
7698 else if (get_attr_length (insn) == 4) | |
7699 return "brctg\t%1,%l0"; | |
7700 else | |
7701 return "aghi\t%1,-1\;jgne\t%l0"; | |
7702 } | |
7703 "&& reload_completed | |
7704 && (! REG_P (operands[2]) | |
7705 || ! rtx_equal_p (operands[1], operands[2]))" | |
7706 [(set (match_dup 3) (match_dup 1)) | |
7707 (parallel [(set (reg:CCAN CC_REGNUM) | |
7708 (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) | |
7709 (const_int 0))) | |
7710 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
7711 (set (match_dup 2) (match_dup 3)) | |
7712 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) | |
7713 (label_ref (match_dup 0)) | |
7714 (pc)))] | |
7715 "" | |
7716 [(set_attr "op_type" "RI") | |
7717 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not | |
7718 ; hurt us in the (rare) case of ahi. | |
7719 (set_attr "z10prop" "z10_super_E1") | |
7720 (set_attr "type" "branch") | |
7721 (set (attr "length") | |
7722 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7723 (const_int 4) (const_int 10)))]) | |
7724 | |
7725 ;; | |
7726 ;;- Unconditional jump instructions. | |
7727 ;; | |
7728 | |
7729 ; | |
7730 ; jump instruction pattern(s). | |
7731 ; | |
7732 | |
7733 (define_expand "jump" | |
7734 [(match_operand 0 "" "")] | |
7735 "" | |
7736 "s390_emit_jump (operands[0], NULL_RTX); DONE;") | |
7737 | |
7738 (define_insn "*jump64" | |
7739 [(set (pc) (label_ref (match_operand 0 "" "")))] | |
7740 "TARGET_CPU_ZARCH" | |
7741 { | |
7742 if (get_attr_length (insn) == 4) | |
7743 return "j\t%l0"; | |
7744 else | |
7745 return "jg\t%l0"; | |
7746 } | |
7747 [(set_attr "op_type" "RI") | |
7748 (set_attr "type" "branch") | |
7749 (set (attr "length") | |
7750 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7751 (const_int 4) (const_int 6)))]) | |
7752 | |
7753 (define_insn "*jump31" | |
7754 [(set (pc) (label_ref (match_operand 0 "" "")))] | |
7755 "!TARGET_CPU_ZARCH" | |
7756 { | |
7757 gcc_assert (get_attr_length (insn) == 4); | |
7758 return "j\t%l0"; | |
7759 } | |
7760 [(set_attr "op_type" "RI") | |
7761 (set_attr "type" "branch") | |
7762 (set (attr "length") | |
7763 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) | |
7764 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7765 (const_int 4) (const_int 6)) | |
7766 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7767 (const_int 4) (const_int 8))))]) | |
7768 | |
7769 ; | |
7770 ; indirect-jump instruction pattern(s). | |
7771 ; | |
7772 | |
7773 (define_insn "indirect_jump" | |
7774 [(set (pc) (match_operand 0 "address_operand" "U"))] | |
7775 "" | |
7776 { | |
7777 if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7778 return "br\t%0"; | |
7779 else | |
7780 return "b\t%a0"; | |
7781 } | |
7782 [(set (attr "op_type") | |
7783 (if_then_else (match_operand 0 "register_operand" "") | |
7784 (const_string "RR") (const_string "RX"))) | |
7785 (set_attr "type" "branch") | |
7786 (set_attr "atype" "agen")]) | |
7787 | |
7788 ; | |
7789 ; casesi instruction pattern(s). | |
7790 ; | |
7791 | |
7792 (define_insn "casesi_jump" | |
7793 [(set (pc) (match_operand 0 "address_operand" "U")) | |
7794 (use (label_ref (match_operand 1 "" "")))] | |
7795 "" | |
7796 { | |
7797 if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7798 return "br\t%0"; | |
7799 else | |
7800 return "b\t%a0"; | |
7801 } | |
7802 [(set (attr "op_type") | |
7803 (if_then_else (match_operand 0 "register_operand" "") | |
7804 (const_string "RR") (const_string "RX"))) | |
7805 (set_attr "type" "branch") | |
7806 (set_attr "atype" "agen")]) | |
7807 | |
7808 (define_expand "casesi" | |
7809 [(match_operand:SI 0 "general_operand" "") | |
7810 (match_operand:SI 1 "general_operand" "") | |
7811 (match_operand:SI 2 "general_operand" "") | |
7812 (label_ref (match_operand 3 "" "")) | |
7813 (label_ref (match_operand 4 "" ""))] | |
7814 "" | |
7815 { | |
7816 rtx index = gen_reg_rtx (SImode); | |
7817 rtx base = gen_reg_rtx (Pmode); | |
7818 rtx target = gen_reg_rtx (Pmode); | |
7819 | |
7820 emit_move_insn (index, operands[0]); | |
7821 emit_insn (gen_subsi3 (index, index, operands[1])); | |
7822 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
7823 operands[4]); | |
7824 | |
7825 if (Pmode != SImode) | |
7826 index = convert_to_mode (Pmode, index, 1); | |
7827 if (GET_CODE (index) != REG) | |
7828 index = copy_to_mode_reg (Pmode, index); | |
7829 | |
7830 if (TARGET_64BIT) | |
7831 emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
7832 else | |
7833 emit_insn (gen_ashlsi3 (index, index, const2_rtx)); | |
7834 | |
7835 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); | |
7836 | |
7837 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); | |
7838 emit_move_insn (target, index); | |
7839 | |
7840 if (flag_pic) | |
7841 target = gen_rtx_PLUS (Pmode, base, target); | |
7842 emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
7843 | |
7844 DONE; | |
7845 }) | |
7846 | |
7847 | |
7848 ;; | |
7849 ;;- Jump to subroutine. | |
7850 ;; | |
7851 ;; | |
7852 | |
7853 ; | |
7854 ; untyped call instruction pattern(s). | |
7855 ; | |
7856 | |
7857 ;; Call subroutine returning any type. | |
7858 (define_expand "untyped_call" | |
7859 [(parallel [(call (match_operand 0 "" "") | |
7860 (const_int 0)) | |
7861 (match_operand 1 "" "") | |
7862 (match_operand 2 "" "")])] | |
7863 "" | |
7864 { | |
7865 int i; | |
7866 | |
7867 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
7868 | |
7869 for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
7870 { | |
7871 rtx set = XVECEXP (operands[2], 0, i); | |
7872 emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
7873 } | |
7874 | |
7875 /* The optimizer does not know that the call sets the function value | |
7876 registers we stored in the result block. We avoid problems by | |
7877 claiming that all hard registers are used and clobbered at this | |
7878 point. */ | |
7879 emit_insn (gen_blockage ()); | |
7880 | |
7881 DONE; | |
7882 }) | |
7883 | |
7884 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
7885 ;; all of memory. This blocks insns from being moved across this point. | |
7886 | |
7887 (define_insn "blockage" | |
7888 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] | |
7889 "" | |
7890 "" | |
7891 [(set_attr "type" "none") | |
7892 (set_attr "length" "0")]) | |
7893 | |
7894 ; | |
7895 ; sibcall patterns | |
7896 ; | |
7897 | |
7898 (define_expand "sibcall" | |
7899 [(call (match_operand 0 "" "") | |
7900 (match_operand 1 "" ""))] | |
7901 "" | |
7902 { | |
7903 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); | |
7904 DONE; | |
7905 }) | |
7906 | |
7907 (define_insn "*sibcall_br" | |
7908 [(call (mem:QI (reg SIBCALL_REGNUM)) | |
7909 (match_operand 0 "const_int_operand" "n"))] | |
7910 "SIBLING_CALL_P (insn) | |
7911 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" | |
7912 "br\t%%r1" | |
7913 [(set_attr "op_type" "RR") | |
7914 (set_attr "type" "branch") | |
7915 (set_attr "atype" "agen")]) | |
7916 | |
7917 (define_insn "*sibcall_brc" | |
7918 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7919 (match_operand 1 "const_int_operand" "n"))] | |
7920 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7921 "j\t%0" | |
7922 [(set_attr "op_type" "RI") | |
7923 (set_attr "type" "branch")]) | |
7924 | |
7925 (define_insn "*sibcall_brcl" | |
7926 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7927 (match_operand 1 "const_int_operand" "n"))] | |
7928 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7929 "jg\t%0" | |
7930 [(set_attr "op_type" "RIL") | |
7931 (set_attr "type" "branch")]) | |
7932 | |
7933 ; | |
7934 ; sibcall_value patterns | |
7935 ; | |
7936 | |
7937 (define_expand "sibcall_value" | |
7938 [(set (match_operand 0 "" "") | |
7939 (call (match_operand 1 "" "") | |
7940 (match_operand 2 "" "")))] | |
7941 "" | |
7942 { | |
7943 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
7944 DONE; | |
7945 }) | |
7946 | |
7947 (define_insn "*sibcall_value_br" | |
7948 [(set (match_operand 0 "" "") | |
7949 (call (mem:QI (reg SIBCALL_REGNUM)) | |
7950 (match_operand 1 "const_int_operand" "n")))] | |
7951 "SIBLING_CALL_P (insn) | |
7952 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" | |
7953 "br\t%%r1" | |
7954 [(set_attr "op_type" "RR") | |
7955 (set_attr "type" "branch") | |
7956 (set_attr "atype" "agen")]) | |
7957 | |
7958 (define_insn "*sibcall_value_brc" | |
7959 [(set (match_operand 0 "" "") | |
7960 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7961 (match_operand 2 "const_int_operand" "n")))] | |
7962 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7963 "j\t%1" | |
7964 [(set_attr "op_type" "RI") | |
7965 (set_attr "type" "branch")]) | |
7966 | |
7967 (define_insn "*sibcall_value_brcl" | |
7968 [(set (match_operand 0 "" "") | |
7969 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7970 (match_operand 2 "const_int_operand" "n")))] | |
7971 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7972 "jg\t%1" | |
7973 [(set_attr "op_type" "RIL") | |
7974 (set_attr "type" "branch")]) | |
7975 | |
7976 | |
7977 ; | |
7978 ; call instruction pattern(s). | |
7979 ; | |
7980 | |
7981 (define_expand "call" | |
7982 [(call (match_operand 0 "" "") | |
7983 (match_operand 1 "" "")) | |
7984 (use (match_operand 2 "" ""))] | |
7985 "" | |
7986 { | |
7987 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, | |
7988 gen_rtx_REG (Pmode, RETURN_REGNUM)); | |
7989 DONE; | |
7990 }) | |
7991 | |
7992 (define_insn "*bras" | |
7993 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7994 (match_operand 1 "const_int_operand" "n")) | |
7995 (clobber (match_operand 2 "register_operand" "=r"))] | |
7996 "!SIBLING_CALL_P (insn) | |
7997 && TARGET_SMALL_EXEC | |
7998 && GET_MODE (operands[2]) == Pmode" | |
7999 "bras\t%2,%0" | |
8000 [(set_attr "op_type" "RI") | |
8001 (set_attr "type" "jsr")]) | |
8002 | |
8003 (define_insn "*brasl" | |
8004 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8005 (match_operand 1 "const_int_operand" "n")) | |
8006 (clobber (match_operand 2 "register_operand" "=r"))] | |
8007 "!SIBLING_CALL_P (insn) | |
8008 && TARGET_CPU_ZARCH | |
8009 && GET_MODE (operands[2]) == Pmode" | |
8010 "brasl\t%2,%0" | |
8011 [(set_attr "op_type" "RIL") | |
8012 (set_attr "type" "jsr")]) | |
8013 | |
8014 (define_insn "*basr" | |
8015 [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
8016 (match_operand 1 "const_int_operand" "n")) | |
8017 (clobber (match_operand 2 "register_operand" "=r"))] | |
8018 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" | |
8019 { | |
8020 if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8021 return "basr\t%2,%0"; | |
8022 else | |
8023 return "bas\t%2,%a0"; | |
8024 } | |
8025 [(set (attr "op_type") | |
8026 (if_then_else (match_operand 0 "register_operand" "") | |
8027 (const_string "RR") (const_string "RX"))) | |
8028 (set_attr "type" "jsr") | |
8029 (set_attr "atype" "agen")]) | |
8030 | |
8031 ; | |
8032 ; call_value instruction pattern(s). | |
8033 ; | |
8034 | |
8035 (define_expand "call_value" | |
8036 [(set (match_operand 0 "" "") | |
8037 (call (match_operand 1 "" "") | |
8038 (match_operand 2 "" ""))) | |
8039 (use (match_operand 3 "" ""))] | |
8040 "" | |
8041 { | |
8042 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], | |
8043 gen_rtx_REG (Pmode, RETURN_REGNUM)); | |
8044 DONE; | |
8045 }) | |
8046 | |
8047 (define_insn "*bras_r" | |
8048 [(set (match_operand 0 "" "") | |
8049 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8050 (match_operand:SI 2 "const_int_operand" "n"))) | |
8051 (clobber (match_operand 3 "register_operand" "=r"))] | |
8052 "!SIBLING_CALL_P (insn) | |
8053 && TARGET_SMALL_EXEC | |
8054 && GET_MODE (operands[3]) == Pmode" | |
8055 "bras\t%3,%1" | |
8056 [(set_attr "op_type" "RI") | |
8057 (set_attr "type" "jsr")]) | |
8058 | |
8059 (define_insn "*brasl_r" | |
8060 [(set (match_operand 0 "" "") | |
8061 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8062 (match_operand 2 "const_int_operand" "n"))) | |
8063 (clobber (match_operand 3 "register_operand" "=r"))] | |
8064 "!SIBLING_CALL_P (insn) | |
8065 && TARGET_CPU_ZARCH | |
8066 && GET_MODE (operands[3]) == Pmode" | |
8067 "brasl\t%3,%1" | |
8068 [(set_attr "op_type" "RIL") | |
8069 (set_attr "type" "jsr")]) | |
8070 | |
8071 (define_insn "*basr_r" | |
8072 [(set (match_operand 0 "" "") | |
8073 (call (mem:QI (match_operand 1 "address_operand" "U")) | |
8074 (match_operand 2 "const_int_operand" "n"))) | |
8075 (clobber (match_operand 3 "register_operand" "=r"))] | |
8076 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" | |
8077 { | |
8078 if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8079 return "basr\t%3,%1"; | |
8080 else | |
8081 return "bas\t%3,%a1"; | |
8082 } | |
8083 [(set (attr "op_type") | |
8084 (if_then_else (match_operand 1 "register_operand" "") | |
8085 (const_string "RR") (const_string "RX"))) | |
8086 (set_attr "type" "jsr") | |
8087 (set_attr "atype" "agen")]) | |
8088 | |
8089 ;; | |
8090 ;;- Thread-local storage support. | |
8091 ;; | |
8092 | |
8093 (define_expand "get_tp_64" | |
8094 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))] | |
8095 "TARGET_64BIT" | |
8096 "") | |
8097 | |
8098 (define_expand "get_tp_31" | |
8099 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))] | |
8100 "!TARGET_64BIT" | |
8101 "") | |
8102 | |
8103 (define_expand "set_tp_64" | |
8104 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) | |
8105 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] | |
8106 "TARGET_64BIT" | |
8107 "") | |
8108 | |
8109 (define_expand "set_tp_31" | |
8110 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" "")) | |
8111 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))] | |
8112 "!TARGET_64BIT" | |
8113 "") | |
8114 | |
8115 (define_insn "*set_tp" | |
8116 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] | |
8117 "" | |
8118 "" | |
8119 [(set_attr "type" "none") | |
8120 (set_attr "length" "0")]) | |
8121 | |
8122 (define_insn "*tls_load_64" | |
8123 [(set (match_operand:DI 0 "register_operand" "=d") | |
8124 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") | |
8125 (match_operand:DI 2 "" "")] | |
8126 UNSPEC_TLS_LOAD))] | |
8127 "TARGET_64BIT" | |
8128 "lg\t%0,%1%J2" | |
8129 [(set_attr "op_type" "RXE") | |
8130 (set_attr "z10prop" "z10_fwd_A3")]) | |
8131 | |
8132 (define_insn "*tls_load_31" | |
8133 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
8134 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
8135 (match_operand:SI 2 "" "")] | |
8136 UNSPEC_TLS_LOAD))] | |
8137 "!TARGET_64BIT" | |
8138 "@ | |
8139 l\t%0,%1%J2 | |
8140 ly\t%0,%1%J2" | |
8141 [(set_attr "op_type" "RX,RXY") | |
8142 (set_attr "type" "load") | |
8143 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) | |
8144 | |
8145 (define_insn "*bras_tls" | |
8146 [(set (match_operand 0 "" "") | |
8147 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8148 (match_operand 2 "const_int_operand" "n"))) | |
8149 (clobber (match_operand 3 "register_operand" "=r")) | |
8150 (use (match_operand 4 "" ""))] | |
8151 "!SIBLING_CALL_P (insn) | |
8152 && TARGET_SMALL_EXEC | |
8153 && GET_MODE (operands[3]) == Pmode" | |
8154 "bras\t%3,%1%J4" | |
8155 [(set_attr "op_type" "RI") | |
8156 (set_attr "type" "jsr")]) | |
8157 | |
8158 (define_insn "*brasl_tls" | |
8159 [(set (match_operand 0 "" "") | |
8160 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8161 (match_operand 2 "const_int_operand" "n"))) | |
8162 (clobber (match_operand 3 "register_operand" "=r")) | |
8163 (use (match_operand 4 "" ""))] | |
8164 "!SIBLING_CALL_P (insn) | |
8165 && TARGET_CPU_ZARCH | |
8166 && GET_MODE (operands[3]) == Pmode" | |
8167 "brasl\t%3,%1%J4" | |
8168 [(set_attr "op_type" "RIL") | |
8169 (set_attr "type" "jsr")]) | |
8170 | |
8171 (define_insn "*basr_tls" | |
8172 [(set (match_operand 0 "" "") | |
8173 (call (mem:QI (match_operand 1 "address_operand" "U")) | |
8174 (match_operand 2 "const_int_operand" "n"))) | |
8175 (clobber (match_operand 3 "register_operand" "=r")) | |
8176 (use (match_operand 4 "" ""))] | |
8177 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" | |
8178 { | |
8179 if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8180 return "basr\t%3,%1%J4"; | |
8181 else | |
8182 return "bas\t%3,%a1%J4"; | |
8183 } | |
8184 [(set (attr "op_type") | |
8185 (if_then_else (match_operand 1 "register_operand" "") | |
8186 (const_string "RR") (const_string "RX"))) | |
8187 (set_attr "type" "jsr") | |
8188 (set_attr "atype" "agen")]) | |
8189 | |
8190 ;; | |
8191 ;;- Atomic operations | |
8192 ;; | |
8193 | |
8194 ; | |
8195 ; memory barrier pattern. | |
8196 ; | |
8197 | |
8198 (define_expand "memory_barrier" | |
8199 [(set (match_dup 0) | |
8200 (unspec:BLK [(match_dup 0)] UNSPEC_MB))] | |
8201 "" | |
8202 { | |
8203 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
8204 MEM_VOLATILE_P (operands[0]) = 1; | |
8205 }) | |
8206 | |
8207 (define_insn "*memory_barrier" | |
8208 [(set (match_operand:BLK 0 "" "") | |
8209 (unspec:BLK [(match_dup 0)] UNSPEC_MB))] | |
8210 "" | |
8211 "bcr\t15,0" | |
8212 [(set_attr "op_type" "RR")]) | |
8213 | |
8214 ; Although bcr is superscalar on Z10, this variant will never become part of | |
8215 ; an execution group. | |
8216 | |
8217 ; | |
8218 ; compare and swap patterns. | |
8219 ; | |
8220 | |
8221 (define_expand "sync_compare_and_swap<mode>" | |
8222 [(parallel | |
8223 [(set (match_operand:TDSI 0 "register_operand" "") | |
8224 (match_operand:TDSI 1 "memory_operand" "")) | |
8225 (set (match_dup 1) | |
8226 (unspec_volatile:TDSI | |
8227 [(match_dup 1) | |
8228 (match_operand:TDSI 2 "register_operand" "") | |
8229 (match_operand:TDSI 3 "register_operand" "")] | |
8230 UNSPECV_CAS)) | |
8231 (set (reg:CCZ1 CC_REGNUM) | |
8232 (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
8233 "") | |
8234 | |
8235 (define_expand "sync_compare_and_swap<mode>" | |
8236 [(parallel | |
8237 [(set (match_operand:HQI 0 "register_operand" "") | |
8238 (match_operand:HQI 1 "memory_operand" "")) | |
8239 (set (match_dup 1) | |
8240 (unspec_volatile:HQI | |
8241 [(match_dup 1) | |
8242 (match_operand:HQI 2 "general_operand" "") | |
8243 (match_operand:HQI 3 "general_operand" "")] | |
8244 UNSPECV_CAS)) | |
8245 (set (reg:CCZ1 CC_REGNUM) | |
8246 (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
8247 "" | |
8248 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], | |
8249 operands[2], operands[3]); DONE;") | |
8250 | |
8251 (define_expand "sync_compare_and_swap_cc<mode>" | |
8252 [(parallel | |
8253 [(set (match_operand:TDSI 0 "register_operand" "") | |
8254 (match_operand:TDSI 1 "memory_operand" "")) | |
8255 (set (match_dup 1) | |
8256 (unspec_volatile:TDSI | |
8257 [(match_dup 1) | |
8258 (match_operand:TDSI 2 "register_operand" "") | |
8259 (match_operand:TDSI 3 "register_operand" "")] | |
8260 UNSPECV_CAS)) | |
8261 (set (match_dup 4) | |
8262 (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
8263 "" | |
8264 { | |
8265 /* Emulate compare. */ | |
8266 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM); | |
8267 s390_compare_op0 = operands[1]; | |
8268 s390_compare_op1 = operands[2]; | |
8269 s390_compare_emitted = operands[4]; | |
8270 }) | |
8271 | |
8272 ; cds, cdsg | |
8273 (define_insn "*sync_compare_and_swap<mode>" | |
8274 [(set (match_operand:DP 0 "register_operand" "=r") | |
8275 (match_operand:DP 1 "memory_operand" "+Q")) | |
8276 (set (match_dup 1) | |
8277 (unspec_volatile:DP | |
8278 [(match_dup 1) | |
8279 (match_operand:DP 2 "register_operand" "0") | |
8280 (match_operand:DP 3 "register_operand" "r")] | |
8281 UNSPECV_CAS)) | |
8282 (set (reg:CCZ1 CC_REGNUM) | |
8283 (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
8284 "" | |
8285 "cds<tg>\t%0,%3,%S1" | |
8286 [(set_attr "op_type" "RS<TE>") | |
8287 (set_attr "type" "sem")]) | |
8288 | |
8289 ; cs, csg | |
8290 (define_insn "*sync_compare_and_swap<mode>" | |
8291 [(set (match_operand:GPR 0 "register_operand" "=r") | |
8292 (match_operand:GPR 1 "memory_operand" "+Q")) | |
8293 (set (match_dup 1) | |
8294 (unspec_volatile:GPR | |
8295 [(match_dup 1) | |
8296 (match_operand:GPR 2 "register_operand" "0") | |
8297 (match_operand:GPR 3 "register_operand" "r")] | |
8298 UNSPECV_CAS)) | |
8299 (set (reg:CCZ1 CC_REGNUM) | |
8300 (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
8301 "" | |
8302 "cs<g>\t%0,%3,%S1" | |
8303 [(set_attr "op_type" "RS<E>") | |
8304 (set_attr "type" "sem")]) | |
8305 | |
8306 | |
8307 ; | |
8308 ; Other atomic instruction patterns. | |
8309 ; | |
8310 | |
8311 (define_expand "sync_lock_test_and_set<mode>" | |
8312 [(match_operand:HQI 0 "register_operand") | |
8313 (match_operand:HQI 1 "memory_operand") | |
8314 (match_operand:HQI 2 "general_operand")] | |
8315 "" | |
8316 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
8317 operands[2], false); DONE;") | |
8318 | |
8319 (define_expand "sync_<atomic><mode>" | |
8320 [(set (match_operand:HQI 0 "memory_operand") | |
8321 (ATOMIC:HQI (match_dup 0) | |
8322 (match_operand:HQI 1 "general_operand")))] | |
8323 "" | |
8324 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
8325 operands[1], false); DONE;") | |
8326 | |
8327 (define_expand "sync_old_<atomic><mode>" | |
8328 [(set (match_operand:HQI 0 "register_operand") | |
8329 (match_operand:HQI 1 "memory_operand")) | |
8330 (set (match_dup 1) | |
8331 (ATOMIC:HQI (match_dup 1) | |
8332 (match_operand:HQI 2 "general_operand")))] | |
8333 "" | |
8334 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
8335 operands[2], false); DONE;") | |
8336 | |
8337 (define_expand "sync_new_<atomic><mode>" | |
8338 [(set (match_operand:HQI 0 "register_operand") | |
8339 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand") | |
8340 (match_operand:HQI 2 "general_operand"))) | |
8341 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))] | |
8342 "" | |
8343 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
8344 operands[2], true); DONE;") | |
8345 | |
8346 ;; | |
8347 ;;- Miscellaneous instructions. | |
8348 ;; | |
8349 | |
8350 ; | |
8351 ; allocate stack instruction pattern(s). | |
8352 ; | |
8353 | |
8354 (define_expand "allocate_stack" | |
8355 [(match_operand 0 "general_operand" "") | |
8356 (match_operand 1 "general_operand" "")] | |
8357 "TARGET_BACKCHAIN" | |
8358 { | |
8359 rtx temp = gen_reg_rtx (Pmode); | |
8360 | |
8361 emit_move_insn (temp, s390_back_chain_rtx ()); | |
8362 anti_adjust_stack (operands[1]); | |
8363 emit_move_insn (s390_back_chain_rtx (), temp); | |
8364 | |
8365 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
8366 DONE; | |
8367 }) | |
8368 | |
8369 | |
8370 ; | |
8371 ; setjmp instruction pattern. | |
8372 ; | |
8373 | |
8374 (define_expand "builtin_setjmp_receiver" | |
8375 [(match_operand 0 "" "")] | |
8376 "flag_pic" | |
8377 { | |
8378 emit_insn (s390_load_got ()); | |
8379 emit_use (pic_offset_table_rtx); | |
8380 DONE; | |
8381 }) | |
8382 | |
8383 ;; These patterns say how to save and restore the stack pointer. We need not | |
8384 ;; save the stack pointer at function level since we are careful to | |
8385 ;; preserve the backchain. At block level, we have to restore the backchain | |
8386 ;; when we restore the stack pointer. | |
8387 ;; | |
8388 ;; For nonlocal gotos, we must save both the stack pointer and its | |
8389 ;; backchain and restore both. Note that in the nonlocal case, the | |
8390 ;; save area is a memory location. | |
8391 | |
8392 (define_expand "save_stack_function" | |
8393 [(match_operand 0 "general_operand" "") | |
8394 (match_operand 1 "general_operand" "")] | |
8395 "" | |
8396 "DONE;") | |
8397 | |
8398 (define_expand "restore_stack_function" | |
8399 [(match_operand 0 "general_operand" "") | |
8400 (match_operand 1 "general_operand" "")] | |
8401 "" | |
8402 "DONE;") | |
8403 | |
8404 (define_expand "restore_stack_block" | |
8405 [(match_operand 0 "register_operand" "") | |
8406 (match_operand 1 "register_operand" "")] | |
8407 "TARGET_BACKCHAIN" | |
8408 { | |
8409 rtx temp = gen_reg_rtx (Pmode); | |
8410 | |
8411 emit_move_insn (temp, s390_back_chain_rtx ()); | |
8412 emit_move_insn (operands[0], operands[1]); | |
8413 emit_move_insn (s390_back_chain_rtx (), temp); | |
8414 | |
8415 DONE; | |
8416 }) | |
8417 | |
8418 (define_expand "save_stack_nonlocal" | |
8419 [(match_operand 0 "memory_operand" "") | |
8420 (match_operand 1 "register_operand" "")] | |
8421 "" | |
8422 { | |
8423 enum machine_mode mode = TARGET_64BIT ? OImode : TImode; | |
8424 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
8425 | |
8426 /* Copy the backchain to the first word, sp to the second and the | |
8427 literal pool base to the third. */ | |
8428 | |
8429 if (TARGET_BACKCHAIN) | |
8430 { | |
8431 rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); | |
8432 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); | |
8433 } | |
8434 | |
8435 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); | |
8436 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); | |
8437 | |
8438 DONE; | |
8439 }) | |
8440 | |
8441 (define_expand "restore_stack_nonlocal" | |
8442 [(match_operand 0 "register_operand" "") | |
8443 (match_operand 1 "memory_operand" "")] | |
8444 "" | |
8445 { | |
8446 enum machine_mode mode = TARGET_64BIT ? OImode : TImode; | |
8447 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
8448 rtx temp = NULL_RTX; | |
8449 | |
8450 /* Restore the backchain from the first word, sp from the second and the | |
8451 literal pool base from the third. */ | |
8452 | |
8453 if (TARGET_BACKCHAIN) | |
8454 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); | |
8455 | |
8456 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); | |
8457 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); | |
8458 | |
8459 if (temp) | |
8460 emit_move_insn (s390_back_chain_rtx (), temp); | |
8461 | |
8462 emit_use (base); | |
8463 DONE; | |
8464 }) | |
8465 | |
8466 (define_expand "exception_receiver" | |
8467 [(const_int 0)] | |
8468 "" | |
8469 { | |
8470 s390_set_has_landing_pad_p (true); | |
8471 DONE; | |
8472 }) | |
8473 | |
8474 ; | |
8475 ; nop instruction pattern(s). | |
8476 ; | |
8477 | |
8478 (define_insn "nop" | |
8479 [(const_int 0)] | |
8480 "" | |
8481 "lr\t0,0" | |
8482 [(set_attr "op_type" "RR") | |
8483 (set_attr "z10prop" "z10_fr_E1")]) | |
8484 | |
8485 (define_insn "nop1" | |
8486 [(const_int 1)] | |
8487 "" | |
8488 "lr\t1,1" | |
8489 [(set_attr "op_type" "RR")]) | |
8490 | |
8491 | |
8492 ; | |
8493 ; Special literal pool access instruction pattern(s). | |
8494 ; | |
8495 | |
8496 (define_insn "*pool_entry" | |
8497 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
8498 UNSPECV_POOL_ENTRY)] | |
8499 "" | |
8500 { | |
8501 enum machine_mode mode = GET_MODE (PATTERN (insn)); | |
8502 unsigned int align = GET_MODE_BITSIZE (mode); | |
8503 s390_output_pool_entry (operands[0], mode, align); | |
8504 return ""; | |
8505 } | |
8506 [(set (attr "length") | |
8507 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) | |
8508 | |
8509 (define_insn "pool_align" | |
8510 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
8511 UNSPECV_POOL_ALIGN)] | |
8512 "" | |
8513 ".align\t%0" | |
8514 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) | |
8515 | |
8516 (define_insn "pool_section_start" | |
8517 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
8518 "" | |
8519 ".section\t.rodata" | |
8520 [(set_attr "length" "0")]) | |
8521 | |
8522 (define_insn "pool_section_end" | |
8523 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
8524 "" | |
8525 ".previous" | |
8526 [(set_attr "length" "0")]) | |
8527 | |
8528 (define_insn "main_base_31_small" | |
8529 [(set (match_operand 0 "register_operand" "=a") | |
8530 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8531 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
8532 "basr\t%0,0" | |
8533 [(set_attr "op_type" "RR") | |
8534 (set_attr "type" "la")]) | |
8535 | |
8536 (define_insn "main_base_31_large" | |
8537 [(set (match_operand 0 "register_operand" "=a") | |
8538 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
8539 (set (pc) (label_ref (match_operand 2 "" "")))] | |
8540 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
8541 "bras\t%0,%2" | |
8542 [(set_attr "op_type" "RI")]) | |
8543 | |
8544 (define_insn "main_base_64" | |
8545 [(set (match_operand 0 "register_operand" "=a") | |
8546 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8547 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
8548 "larl\t%0,%1" | |
8549 [(set_attr "op_type" "RIL") | |
8550 (set_attr "type" "larl") | |
8551 (set_attr "z10prop" "z10_fwd_A1")]) | |
8552 | |
8553 (define_insn "main_pool" | |
8554 [(set (match_operand 0 "register_operand" "=a") | |
8555 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
8556 "GET_MODE (operands[0]) == Pmode" | |
8557 { | |
8558 gcc_unreachable (); | |
8559 } | |
8560 [(set (attr "type") | |
8561 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) | |
8562 (const_string "larl") (const_string "la")))]) | |
8563 | |
8564 (define_insn "reload_base_31" | |
8565 [(set (match_operand 0 "register_operand" "=a") | |
8566 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8567 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
8568 "basr\t%0,0\;la\t%0,%1-.(%0)" | |
8569 [(set_attr "length" "6") | |
8570 (set_attr "type" "la")]) | |
8571 | |
8572 (define_insn "reload_base_64" | |
8573 [(set (match_operand 0 "register_operand" "=a") | |
8574 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8575 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
8576 "larl\t%0,%1" | |
8577 [(set_attr "op_type" "RIL") | |
8578 (set_attr "type" "larl") | |
8579 (set_attr "z10prop" "z10_fwd_A1")]) | |
8580 | |
8581 (define_insn "pool" | |
8582 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] | |
8583 "" | |
8584 { | |
8585 gcc_unreachable (); | |
8586 } | |
8587 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) | |
8588 | |
8589 ;; | |
8590 ;; Insns related to generating the function prologue and epilogue. | |
8591 ;; | |
8592 | |
8593 | |
8594 (define_expand "prologue" | |
8595 [(use (const_int 0))] | |
8596 "" | |
8597 "s390_emit_prologue (); DONE;") | |
8598 | |
8599 (define_expand "epilogue" | |
8600 [(use (const_int 1))] | |
8601 "" | |
8602 "s390_emit_epilogue (false); DONE;") | |
8603 | |
8604 (define_expand "sibcall_epilogue" | |
8605 [(use (const_int 0))] | |
8606 "" | |
8607 "s390_emit_epilogue (true); DONE;") | |
8608 | |
8609 (define_insn "*return" | |
8610 [(return) | |
8611 (use (match_operand 0 "register_operand" "a"))] | |
8612 "GET_MODE (operands[0]) == Pmode" | |
8613 "br\t%0" | |
8614 [(set_attr "op_type" "RR") | |
8615 (set_attr "type" "jsr") | |
8616 (set_attr "atype" "agen")]) | |
8617 | |
8618 | |
8619 ;; Instruction definition to extend a 31-bit pointer into a 64-bit | |
8620 ;; pointer. This is used for compatibility. | |
8621 | |
8622 (define_expand "ptr_extend" | |
8623 [(set (match_operand:DI 0 "register_operand" "=r") | |
8624 (match_operand:SI 1 "register_operand" "r"))] | |
8625 "TARGET_64BIT" | |
8626 { | |
8627 emit_insn (gen_anddi3 (operands[0], | |
8628 gen_lowpart (DImode, operands[1]), | |
8629 GEN_INT (0x7fffffff))); | |
8630 DONE; | |
8631 }) | |
8632 | |
8633 ;; Instruction definition to expand eh_return macro to support | |
8634 ;; swapping in special linkage return addresses. | |
8635 | |
8636 (define_expand "eh_return" | |
8637 [(use (match_operand 0 "register_operand" ""))] | |
8638 "TARGET_TPF" | |
8639 { | |
8640 s390_emit_tpf_eh_return (operands[0]); | |
8641 DONE; | |
8642 }) | |
8643 | |
8644 ; | |
8645 ; Stack Protector Patterns | |
8646 ; | |
8647 | |
8648 (define_expand "stack_protect_set" | |
8649 [(set (match_operand 0 "memory_operand" "") | |
8650 (match_operand 1 "memory_operand" ""))] | |
8651 "" | |
8652 { | |
8653 #ifdef TARGET_THREAD_SSP_OFFSET | |
8654 operands[1] | |
8655 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
8656 GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
8657 #endif | |
8658 if (TARGET_64BIT) | |
8659 emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
8660 else | |
8661 emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
8662 | |
8663 DONE; | |
8664 }) | |
8665 | |
8666 (define_insn "stack_protect_set<mode>" | |
8667 [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
8668 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
8669 "" | |
8670 "mvc\t%O0(%G0,%R0),%S1" | |
8671 [(set_attr "op_type" "SS")]) | |
8672 | |
8673 (define_expand "stack_protect_test" | |
8674 [(set (reg:CC CC_REGNUM) | |
8675 (compare (match_operand 0 "memory_operand" "") | |
8676 (match_operand 1 "memory_operand" ""))) | |
8677 (match_operand 2 "" "")] | |
8678 "" | |
8679 { | |
8680 #ifdef TARGET_THREAD_SSP_OFFSET | |
8681 operands[1] | |
8682 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
8683 GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
8684 #endif | |
8685 s390_compare_op0 = operands[0]; | |
8686 s390_compare_op1 = operands[1]; | |
8687 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM); | |
8688 | |
8689 if (TARGET_64BIT) | |
8690 emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
8691 else | |
8692 emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
8693 | |
8694 emit_jump_insn (gen_beq (operands[2])); | |
8695 | |
8696 DONE; | |
8697 }) | |
8698 | |
8699 (define_insn "stack_protect_test<mode>" | |
8700 [(set (reg:CCZ CC_REGNUM) | |
8701 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
8702 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
8703 "" | |
8704 "clc\t%O0(%G0,%R0),%S1" | |
8705 [(set_attr "op_type" "SS")]) | |
8706 | |
8707 ; This is used in s390_emit_prologue in order to prevent insns | |
8708 ; adjusting the stack pointer to be moved over insns writing stack | |
8709 ; slots using a copy of the stack pointer in a different register. | |
8710 (define_insn "stack_tie" | |
8711 [(set (match_operand:BLK 0 "memory_operand" "+m") | |
8712 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
8713 "" | |
8714 "" | |
8715 [(set_attr "length" "0")]) | |
8716 | |
8717 | |
8718 ; | |
8719 ; Data prefetch patterns | |
8720 ; | |
8721 | |
8722 (define_insn "prefetch" | |
8723 [(prefetch (match_operand 0 "address_operand" "UW,X") | |
8724 (match_operand:SI 1 "const_int_operand" "n,n") | |
8725 (match_operand:SI 2 "const_int_operand" "n,n"))] | |
8726 "TARGET_Z10" | |
8727 { | |
8728 if (larl_operand (operands[0], Pmode)) | |
8729 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
8730 | |
8731 if (s390_mem_constraint ("W", operands[0]) | |
8732 || s390_mem_constraint ("U", operands[0])) | |
8733 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; | |
8734 | |
8735 /* This point might be reached if op0 is a larl operand with an | |
8736 uneven addend. In this case we simply omit issuing a prefetch | |
8737 instruction. */ | |
8738 | |
8739 return ""; | |
8740 } | |
8741 [(set_attr "type" "load,larl") | |
8742 (set_attr "op_type" "RXY,RIL") | |
8743 (set_attr "z10prop" "z10_super")]) | |
8744 | |
8745 | |
8746 ; | |
8747 ; Byte swap instructions | |
8748 ; | |
8749 | |
8750 (define_insn "bswap<mode>2" | |
8751 [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8752 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))] | |
8753 "" | |
8754 "@ | |
8755 lrv<g>r\t%0,%1 | |
8756 lrv<g>\t%0,%1" | |
8757 [(set_attr "type" "*,load") | |
8758 (set_attr "op_type" "RRE,RXY") | |
8759 (set_attr "z10prop" "z10_super")]) |