comparison gcc/config/sh/sh.opt @ 0:a06113de4d67

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author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Fri, 17 Jul 2009 14:47:48 +0900
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1 ; Options for the SH port of the compiler.
2
3 ; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 ;
5 ; This file is part of GCC.
6 ;
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
9 ; Software Foundation; either version 3, or (at your option) any later
10 ; version.
11 ;
12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 ; for more details.
16 ;
17 ; You should have received a copy of the GNU General Public License
18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>.
20
21 ;; Used for various architecture options.
22 Mask(SH_E)
23
24 ;; Set if the default precision of th FPU is single.
25 Mask(FPU_SINGLE)
26
27 ;; Set if we should generate code using type 2A insns.
28 Mask(HARD_SH2A)
29
30 ;; Set if we should generate code using type 2A DF insns.
31 Mask(HARD_SH2A_DOUBLE)
32
33 ;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
34 Mask(HARD_SH4)
35
36 ;; Set if we should generate code for a SH5 CPU (either ISA).
37 Mask(SH5)
38
39 ;; Set if we should save all target registers.
40 Mask(SAVE_ALL_TARGET_REGS)
41
42 m1
43 Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
44 Generate SH1 code
45
46 m2
47 Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2)
48 Generate SH2 code
49
50 m2a
51 Target RejectNegative Condition(SUPPORT_SH2A)
52 Generate SH2a code
53
54 m2a-nofpu
55 Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
56 Generate SH2a FPU-less code
57
58 m2a-single
59 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
60 Generate default single-precision SH2a code
61
62 m2a-single-only
63 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
64 Generate only single-precision SH2a code
65
66 m2e
67 Target RejectNegative Condition(SUPPORT_SH2E)
68 Generate SH2e code
69
70 m3
71 Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
72 Generate SH3 code
73
74 m3e
75 Target RejectNegative Condition(SUPPORT_SH3E)
76 Generate SH3e code
77
78 m4
79 Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4)
80 Generate SH4 code
81
82 m4-100
83 Target RejectNegative Condition(SUPPORT_SH4)
84 Generate SH4-100 code
85
86 m4-200
87 Target RejectNegative Condition(SUPPORT_SH4)
88 Generate SH4-200 code
89
90 ;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and
91 ;; pipeline - irrespective of ABI.
92 m4-300
93 Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300)
94 Generate SH4-300 code
95
96 m4-nofpu
97 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
98 Generate SH4 FPU-less code
99
100 m4-100-nofpu
101 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
102 Generate SH4-100 FPU-less code
103
104 m4-200-nofpu
105 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
106 Generate SH4-200 FPU-less code
107
108 m4-300-nofpu
109 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
110 Generate SH4-300 FPU-less code
111
112 m4-340
113 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
114 Generate code for SH4 340 series (MMU/FPU-less)
115 ;; passes -isa=sh4-nommu-nofpu to the assembler.
116
117 m4-400
118 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
119 Generate code for SH4 400 series (MMU/FPU-less)
120 ;; passes -isa=sh4-nommu-nofpu to the assembler.
121
122 m4-500
123 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
124 Generate code for SH4 500 series (FPU-less).
125 ;; passes -isa=sh4-nofpu to the assembler.
126
127 m4-single
128 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
129 Generate default single-precision SH4 code
130
131 m4-100-single
132 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
133 Generate default single-precision SH4-100 code
134
135 m4-200-single
136 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
137 Generate default single-precision SH4-200 code
138
139 m4-300-single
140 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) VarExists
141 Generate default single-precision SH4-300 code
142
143 m4-single-only
144 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
145 Generate only single-precision SH4 code
146
147 m4-100-single-only
148 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
149 Generate only single-precision SH4-100 code
150
151 m4-200-single-only
152 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
153 Generate only single-precision SH4-200 code
154
155 m4-300-single-only
156 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) VarExists
157 Generate only single-precision SH4-300 code
158
159 m4a
160 Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
161 Generate SH4a code
162
163 m4a-nofpu
164 Target RejectNegative Condition(SUPPORT_SH4A_NOFPU)
165 Generate SH4a FPU-less code
166
167 m4a-single
168 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE)
169 Generate default single-precision SH4a code
170
171 m4a-single-only
172 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY)
173 Generate only single-precision SH4a code
174
175 m4al
176 Target RejectNegative Condition(SUPPORT_SH4AL)
177 Generate SH4al-dsp code
178
179 m5-32media
180 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
181 Generate 32-bit SHmedia code
182
183 m5-32media-nofpu
184 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
185 Generate 32-bit FPU-less SHmedia code
186
187 m5-64media
188 Target RejectNegative Condition(SUPPORT_SH5_64MEDIA)
189 Generate 64-bit SHmedia code
190
191 m5-64media-nofpu
192 Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU)
193 Generate 64-bit FPU-less SHmedia code
194
195 m5-compact
196 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
197 Generate SHcompact code
198
199 m5-compact-nofpu
200 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
201 Generate FPU-less SHcompact code
202
203 madjust-unroll
204 Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5)
205 Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this
206
207 mb
208 Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
209 Generate code in big endian mode
210
211 mbigtable
212 Target Report RejectNegative Mask(BIGTABLE)
213 Generate 32-bit offsets in switch tables
214
215 mbitops
216 Target Report RejectNegative Mask(BITOPS)
217 Generate bit instructions
218
219 mbranch-cost=
220 Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
221 Cost to assume for a branch insn
222
223 mcbranchdi
224 Target Var(TARGET_CBRANCHDI4)
225 Enable cbranchdi4 pattern
226
227 mexpand-cbranchdi
228 Target Var(TARGET_EXPAND_CBRANCHDI4)
229 Expand cbranchdi4 pattern early into separate comparisons and branches.
230
231 mcmpeqdi
232 Target Var(TARGET_CMPEQDI_T)
233 Emit cmpeqdi_t pattern even when -mcbranchdi and -mexpand-cbranchdi are in effect.
234
235 mcut2-workaround
236 Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND)
237 Enable SH5 cut2 workaround
238
239 mdalign
240 Target Report RejectNegative Mask(ALIGN_DOUBLE)
241 Align doubles at 64-bit boundaries
242
243 mdiv=
244 Target RejectNegative Joined Var(sh_div_str) Init("")
245 Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table
246
247 mdivsi3_libfunc=
248 Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
249 Specify name for 32 bit signed division function
250
251 mfixed-range=
252 Target RejectNegative Joined Var(sh_fixed_range_str)
253 Specify range of registers to make fixed
254
255 mfmovd
256 Target RejectNegative Mask(FMOVD) Undocumented
257
258 mfused-madd
259 Target Var(TARGET_FMAC)
260 Enable the use of the fused floating point multiply-accumulate operation
261
262 mgettrcost=
263 Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1)
264 Cost to assume for gettr insn
265
266 mhitachi
267 Target Report RejectNegative Mask(HITACHI)
268 Follow Renesas (formerly Hitachi) / SuperH calling conventions
269
270 mieee
271 Target Report Mask(IEEE)
272 Increase the IEEE compliance for floating-point code
273
274 mindexed-addressing
275 Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA)
276 Enable the use of the indexed addressing mode for SHmedia32/SHcompact
277
278 minline-ic_invalidate
279 Target Report Var(TARGET_INLINE_IC_INVALIDATE)
280 inline code to invalidate instruction cache entries after setting up nested function trampolines
281
282 minvalid-symbols
283 Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5)
284 Assume symbols might be invalid
285
286 misize
287 Target Report RejectNegative Mask(DUMPISIZE)
288 Annotate assembler instructions with estimated addresses
289
290 ml
291 Target Report RejectNegative Mask(LITTLE_ENDIAN)
292 Generate code in little endian mode
293
294 mnomacsave
295 Target Report RejectNegative Mask(NOMACSAVE)
296 Mark MAC register as call-clobbered
297
298 ;; ??? This option is not useful, but is retained in case there are people
299 ;; who are still relying on it. It may be deleted in the future.
300 mpadstruct
301 Target Report RejectNegative Mask(PADSTRUCT)
302 Make structs a multiple of 4 bytes (warning: ABI altered)
303
304 mprefergot
305 Target Report RejectNegative Mask(PREFERGOT)
306 Emit function-calls using global offset table when generating PIC
307
308 mpt-fixed
309 Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5)
310 Assume pt* instructions won't trap
311
312 mrelax
313 Target Report RejectNegative Mask(RELAX)
314 Shorten address references during linking
315
316 mrenesas
317 Target Mask(HITACHI) MaskExists
318 Follow Renesas (formerly Hitachi) / SuperH calling conventions
319
320 mspace
321 Target Report RejectNegative Mask(SMALLCODE)
322 Deprecated. Use -Os instead
323
324 multcost=
325 Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)
326 Cost to assume for a multiply insn
327
328 musermode
329 Target Report RejectNegative Mask(USERMODE)
330 Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode.
331
332 ;; We might want to enable this by default for TARGET_HARD_SH4, because
333 ;; zero-offset branches have zero latency. Needs some benchmarking.
334 mpretend-cmove
335 Target Var(TARGET_PRETEND_CMOVE)
336 Pretend a branch-around-a-move is a conditional move.