Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/sparc/sparc.h @ 0:a06113de4d67
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author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
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date | Fri, 17 Jul 2009 14:47:48 +0900 |
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children | 3bfb6c00c1e0 |
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1 /* Definitions of target machine for GNU compiler, for Sun SPARC. | |
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999 | |
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 | |
4 Free Software Foundation, Inc. | |
5 Contributed by Michael Tiemann (tiemann@cygnus.com). | |
6 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, | |
7 at Cygnus Support. | |
8 | |
9 This file is part of GCC. | |
10 | |
11 GCC is free software; you can redistribute it and/or modify | |
12 it under the terms of the GNU General Public License as published by | |
13 the Free Software Foundation; either version 3, or (at your option) | |
14 any later version. | |
15 | |
16 GCC is distributed in the hope that it will be useful, | |
17 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 GNU General Public License for more details. | |
20 | |
21 You should have received a copy of the GNU General Public License | |
22 along with GCC; see the file COPYING3. If not see | |
23 <http://www.gnu.org/licenses/>. */ | |
24 | |
25 #include "config/vxworks-dummy.h" | |
26 | |
27 /* Note that some other tm.h files include this one and then override | |
28 whatever definitions are necessary. */ | |
29 | |
30 /* Define the specific costs for a given cpu */ | |
31 | |
32 struct processor_costs { | |
33 /* Integer load */ | |
34 const int int_load; | |
35 | |
36 /* Integer signed load */ | |
37 const int int_sload; | |
38 | |
39 /* Integer zeroed load */ | |
40 const int int_zload; | |
41 | |
42 /* Float load */ | |
43 const int float_load; | |
44 | |
45 /* fmov, fneg, fabs */ | |
46 const int float_move; | |
47 | |
48 /* fadd, fsub */ | |
49 const int float_plusminus; | |
50 | |
51 /* fcmp */ | |
52 const int float_cmp; | |
53 | |
54 /* fmov, fmovr */ | |
55 const int float_cmove; | |
56 | |
57 /* fmul */ | |
58 const int float_mul; | |
59 | |
60 /* fdivs */ | |
61 const int float_div_sf; | |
62 | |
63 /* fdivd */ | |
64 const int float_div_df; | |
65 | |
66 /* fsqrts */ | |
67 const int float_sqrt_sf; | |
68 | |
69 /* fsqrtd */ | |
70 const int float_sqrt_df; | |
71 | |
72 /* umul/smul */ | |
73 const int int_mul; | |
74 | |
75 /* mulX */ | |
76 const int int_mulX; | |
77 | |
78 /* integer multiply cost for each bit set past the most | |
79 significant 3, so the formula for multiply cost becomes: | |
80 | |
81 if (rs1 < 0) | |
82 highest_bit = highest_clear_bit(rs1); | |
83 else | |
84 highest_bit = highest_set_bit(rs1); | |
85 if (highest_bit < 3) | |
86 highest_bit = 3; | |
87 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor); | |
88 | |
89 A value of zero indicates that the multiply costs is fixed, | |
90 and not variable. */ | |
91 const int int_mul_bit_factor; | |
92 | |
93 /* udiv/sdiv */ | |
94 const int int_div; | |
95 | |
96 /* divX */ | |
97 const int int_divX; | |
98 | |
99 /* movcc, movr */ | |
100 const int int_cmove; | |
101 | |
102 /* penalty for shifts, due to scheduling rules etc. */ | |
103 const int shift_penalty; | |
104 }; | |
105 | |
106 extern const struct processor_costs *sparc_costs; | |
107 | |
108 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of | |
109 Solaris only; otherwise just define __sparc__. Sadly the headers | |
110 are such a mess there is no Solaris-specific header. */ | |
111 #define TARGET_CPU_CPP_BUILTINS() \ | |
112 do \ | |
113 { \ | |
114 builtin_define_std ("sparc"); \ | |
115 if (TARGET_64BIT) \ | |
116 { \ | |
117 builtin_assert ("cpu=sparc64"); \ | |
118 builtin_assert ("machine=sparc64"); \ | |
119 } \ | |
120 else \ | |
121 { \ | |
122 builtin_assert ("cpu=sparc"); \ | |
123 builtin_assert ("machine=sparc"); \ | |
124 } \ | |
125 } \ | |
126 while (0) | |
127 | |
128 /* Specify this in a cover file to provide bi-architecture (32/64) support. */ | |
129 /* #define SPARC_BI_ARCH */ | |
130 | |
131 /* Macro used later in this file to determine default architecture. */ | |
132 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) | |
133 | |
134 /* TARGET_ARCH{32,64} are the main macros to decide which of the two | |
135 architectures to compile for. We allow targets to choose compile time or | |
136 runtime selection. */ | |
137 #ifdef IN_LIBGCC2 | |
138 #if defined(__sparcv9) || defined(__arch64__) | |
139 #define TARGET_ARCH32 0 | |
140 #else | |
141 #define TARGET_ARCH32 1 | |
142 #endif /* sparc64 */ | |
143 #else | |
144 #ifdef SPARC_BI_ARCH | |
145 #define TARGET_ARCH32 (! TARGET_64BIT) | |
146 #else | |
147 #define TARGET_ARCH32 (DEFAULT_ARCH32_P) | |
148 #endif /* SPARC_BI_ARCH */ | |
149 #endif /* IN_LIBGCC2 */ | |
150 #define TARGET_ARCH64 (! TARGET_ARCH32) | |
151 | |
152 /* Code model selection in 64-bit environment. | |
153 | |
154 The machine mode used for addresses is 32-bit wide: | |
155 | |
156 TARGET_CM_32: 32-bit address space. | |
157 It is the code model used when generating 32-bit code. | |
158 | |
159 The machine mode used for addresses is 64-bit wide: | |
160 | |
161 TARGET_CM_MEDLOW: 32-bit address space. | |
162 The executable must be in the low 32 bits of memory. | |
163 This avoids generating %uhi and %ulo terms. Programs | |
164 can be statically or dynamically linked. | |
165 | |
166 TARGET_CM_MEDMID: 44-bit address space. | |
167 The executable must be in the low 44 bits of memory, | |
168 and the %[hml]44 terms are used. The text and data | |
169 segments have a maximum size of 2GB (31-bit span). | |
170 The maximum offset from any instruction to the label | |
171 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). | |
172 | |
173 TARGET_CM_MEDANY: 64-bit address space. | |
174 The text and data segments have a maximum size of 2GB | |
175 (31-bit span) and may be located anywhere in memory. | |
176 The maximum offset from any instruction to the label | |
177 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). | |
178 | |
179 TARGET_CM_EMBMEDANY: 64-bit address space. | |
180 The text and data segments have a maximum size of 2GB | |
181 (31-bit span) and may be located anywhere in memory. | |
182 The global register %g4 contains the start address of | |
183 the data segment. Programs are statically linked and | |
184 PIC is not supported. | |
185 | |
186 Different code models are not supported in 32-bit environment. */ | |
187 | |
188 enum cmodel { | |
189 CM_32, | |
190 CM_MEDLOW, | |
191 CM_MEDMID, | |
192 CM_MEDANY, | |
193 CM_EMBMEDANY | |
194 }; | |
195 | |
196 /* One of CM_FOO. */ | |
197 extern enum cmodel sparc_cmodel; | |
198 | |
199 /* V9 code model selection. */ | |
200 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) | |
201 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) | |
202 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) | |
203 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) | |
204 | |
205 #define SPARC_DEFAULT_CMODEL CM_32 | |
206 | |
207 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO) | |
208 which requires the following macro to be true if enabled. Prior to V9, | |
209 there are no instructions to even talk about memory synchronization. | |
210 Note that the UltraSPARC III processors don't implement RMO, unlike the | |
211 UltraSPARC II processors. Niagara and Niagara-2 do not implement RMO | |
212 either. | |
213 | |
214 Default to false; for example, Solaris never enables RMO, only ever uses | |
215 total memory ordering (TMO). */ | |
216 #define SPARC_RELAXED_ORDERING false | |
217 | |
218 /* Do not use the .note.GNU-stack convention by default. */ | |
219 #define NEED_INDICATE_EXEC_STACK 0 | |
220 | |
221 /* This is call-clobbered in the normal ABI, but is reserved in the | |
222 home grown (aka upward compatible) embedded ABI. */ | |
223 #define EMBMEDANY_BASE_REG "%g4" | |
224 | |
225 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, | |
226 and specified by the user via --with-cpu=foo. | |
227 This specifies the cpu implementation, not the architecture size. */ | |
228 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit | |
229 capable cpu's. */ | |
230 #define TARGET_CPU_sparc 0 | |
231 #define TARGET_CPU_v7 0 /* alias for previous */ | |
232 #define TARGET_CPU_sparclet 1 | |
233 #define TARGET_CPU_sparclite 2 | |
234 #define TARGET_CPU_v8 3 /* generic v8 implementation */ | |
235 #define TARGET_CPU_supersparc 4 | |
236 #define TARGET_CPU_hypersparc 5 | |
237 #define TARGET_CPU_sparc86x 6 | |
238 #define TARGET_CPU_sparclite86x 6 | |
239 #define TARGET_CPU_v9 7 /* generic v9 implementation */ | |
240 #define TARGET_CPU_sparcv9 7 /* alias */ | |
241 #define TARGET_CPU_sparc64 7 /* alias */ | |
242 #define TARGET_CPU_ultrasparc 8 | |
243 #define TARGET_CPU_ultrasparc3 9 | |
244 #define TARGET_CPU_niagara 10 | |
245 #define TARGET_CPU_niagara2 11 | |
246 | |
247 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ | |
248 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ | |
249 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ | |
250 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ | |
251 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 | |
252 | |
253 #define CPP_CPU32_DEFAULT_SPEC "" | |
254 #define ASM_CPU32_DEFAULT_SPEC "" | |
255 | |
256 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 | |
257 /* ??? What does Sun's CC pass? */ | |
258 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
259 /* ??? It's not clear how other assemblers will handle this, so by default | |
260 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case | |
261 is handled in sol2.h. */ | |
262 #define ASM_CPU64_DEFAULT_SPEC "-Av9" | |
263 #endif | |
264 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc | |
265 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
266 #define ASM_CPU64_DEFAULT_SPEC "-Av9a" | |
267 #endif | |
268 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 | |
269 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
270 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
271 #endif | |
272 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara | |
273 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
274 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
275 #endif | |
276 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 | |
277 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
278 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
279 #endif | |
280 | |
281 #else | |
282 | |
283 #define CPP_CPU64_DEFAULT_SPEC "" | |
284 #define ASM_CPU64_DEFAULT_SPEC "" | |
285 | |
286 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ | |
287 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 | |
288 #define CPP_CPU32_DEFAULT_SPEC "" | |
289 #define ASM_CPU32_DEFAULT_SPEC "" | |
290 #endif | |
291 | |
292 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet | |
293 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" | |
294 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" | |
295 #endif | |
296 | |
297 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite | |
298 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" | |
299 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" | |
300 #endif | |
301 | |
302 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc | |
303 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" | |
304 #define ASM_CPU32_DEFAULT_SPEC "" | |
305 #endif | |
306 | |
307 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc | |
308 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" | |
309 #define ASM_CPU32_DEFAULT_SPEC "" | |
310 #endif | |
311 | |
312 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x | |
313 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" | |
314 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" | |
315 #endif | |
316 | |
317 #endif | |
318 | |
319 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) | |
320 #error Unrecognized value in TARGET_CPU_DEFAULT. | |
321 #endif | |
322 | |
323 #ifdef SPARC_BI_ARCH | |
324 | |
325 #define CPP_CPU_DEFAULT_SPEC \ | |
326 (DEFAULT_ARCH32_P ? "\ | |
327 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ | |
328 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ | |
329 " : "\ | |
330 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ | |
331 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ | |
332 ") | |
333 #define ASM_CPU_DEFAULT_SPEC \ | |
334 (DEFAULT_ARCH32_P ? "\ | |
335 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ | |
336 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ | |
337 " : "\ | |
338 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ | |
339 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ | |
340 ") | |
341 | |
342 #else /* !SPARC_BI_ARCH */ | |
343 | |
344 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) | |
345 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) | |
346 | |
347 #endif /* !SPARC_BI_ARCH */ | |
348 | |
349 /* Define macros to distinguish architectures. */ | |
350 | |
351 /* Common CPP definitions used by CPP_SPEC amongst the various targets | |
352 for handling -mcpu=xxx switches. */ | |
353 #define CPP_CPU_SPEC "\ | |
354 %{msoft-float:-D_SOFT_FLOAT} \ | |
355 %{mcypress:} \ | |
356 %{msparclite:-D__sparclite__} \ | |
357 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ | |
358 %{mv8:-D__sparc_v8__} \ | |
359 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ | |
360 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ | |
361 %{mcpu=sparclite:-D__sparclite__} \ | |
362 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ | |
363 %{mcpu=v8:-D__sparc_v8__} \ | |
364 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ | |
365 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ | |
366 %{mcpu=sparclite86x:-D__sparclite86x__} \ | |
367 %{mcpu=v9:-D__sparc_v9__} \ | |
368 %{mcpu=ultrasparc:-D__sparc_v9__} \ | |
369 %{mcpu=ultrasparc3:-D__sparc_v9__} \ | |
370 %{mcpu=niagara:-D__sparc_v9__} \ | |
371 %{mcpu=niagara2:-D__sparc_v9__} \ | |
372 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ | |
373 " | |
374 #define CPP_ARCH32_SPEC "" | |
375 #define CPP_ARCH64_SPEC "-D__arch64__" | |
376 | |
377 #define CPP_ARCH_DEFAULT_SPEC \ | |
378 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) | |
379 | |
380 #define CPP_ARCH_SPEC "\ | |
381 %{m32:%(cpp_arch32)} \ | |
382 %{m64:%(cpp_arch64)} \ | |
383 %{!m32:%{!m64:%(cpp_arch_default)}} \ | |
384 " | |
385 | |
386 /* Macros to distinguish endianness. */ | |
387 #define CPP_ENDIAN_SPEC "\ | |
388 %{mlittle-endian:-D__LITTLE_ENDIAN__} \ | |
389 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}" | |
390 | |
391 /* Macros to distinguish the particular subtarget. */ | |
392 #define CPP_SUBTARGET_SPEC "" | |
393 | |
394 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)" | |
395 | |
396 /* Prevent error on `-sun4' and `-target sun4' options. */ | |
397 /* This used to translate -dalign to -malign, but that is no good | |
398 because it can't turn off the usual meaning of making debugging dumps. */ | |
399 /* Translate old style -m<cpu> into new style -mcpu=<cpu>. | |
400 ??? Delete support for -m<cpu> for 2.9. */ | |
401 | |
402 #define CC1_SPEC "\ | |
403 %{sun4:} %{target:} \ | |
404 %{mcypress:-mcpu=cypress} \ | |
405 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ | |
406 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ | |
407 " | |
408 | |
409 /* Override in target specific files. */ | |
410 #define ASM_CPU_SPEC "\ | |
411 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ | |
412 %{msparclite:-Asparclite} \ | |
413 %{mf930:-Asparclite} %{mf934:-Asparclite} \ | |
414 %{mcpu=sparclite:-Asparclite} \ | |
415 %{mcpu=sparclite86x:-Asparclite} \ | |
416 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ | |
417 %{mv8plus:-Av8plus} \ | |
418 %{mcpu=v9:-Av9} \ | |
419 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ | |
420 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ | |
421 %{mcpu=niagara:%{!mv8plus:-Av9b}} \ | |
422 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ | |
423 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ | |
424 " | |
425 | |
426 /* Word size selection, among other things. | |
427 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ | |
428 | |
429 #define ASM_ARCH32_SPEC "-32" | |
430 #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
431 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" | |
432 #else | |
433 #define ASM_ARCH64_SPEC "-64" | |
434 #endif | |
435 #define ASM_ARCH_DEFAULT_SPEC \ | |
436 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) | |
437 | |
438 #define ASM_ARCH_SPEC "\ | |
439 %{m32:%(asm_arch32)} \ | |
440 %{m64:%(asm_arch64)} \ | |
441 %{!m32:%{!m64:%(asm_arch_default)}} \ | |
442 " | |
443 | |
444 #ifdef HAVE_AS_RELAX_OPTION | |
445 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" | |
446 #else | |
447 #define ASM_RELAX_SPEC "" | |
448 #endif | |
449 | |
450 /* Special flags to the Sun-4 assembler when using pipe for input. */ | |
451 | |
452 #define ASM_SPEC "\ | |
453 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \ | |
454 %(asm_cpu) %(asm_relax)" | |
455 | |
456 #define AS_NEEDS_DASH_FOR_PIPED_INPUT | |
457 | |
458 /* This macro defines names of additional specifications to put in the specs | |
459 that can be used in various specifications like CC1_SPEC. Its definition | |
460 is an initializer with a subgrouping for each command option. | |
461 | |
462 Each subgrouping contains a string constant, that defines the | |
463 specification name, and a string constant that used by the GCC driver | |
464 program. | |
465 | |
466 Do not define this macro if it does not need to do anything. */ | |
467 | |
468 #define EXTRA_SPECS \ | |
469 { "cpp_cpu", CPP_CPU_SPEC }, \ | |
470 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ | |
471 { "cpp_arch32", CPP_ARCH32_SPEC }, \ | |
472 { "cpp_arch64", CPP_ARCH64_SPEC }, \ | |
473 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ | |
474 { "cpp_arch", CPP_ARCH_SPEC }, \ | |
475 { "cpp_endian", CPP_ENDIAN_SPEC }, \ | |
476 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ | |
477 { "asm_cpu", ASM_CPU_SPEC }, \ | |
478 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ | |
479 { "asm_arch32", ASM_ARCH32_SPEC }, \ | |
480 { "asm_arch64", ASM_ARCH64_SPEC }, \ | |
481 { "asm_relax", ASM_RELAX_SPEC }, \ | |
482 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ | |
483 { "asm_arch", ASM_ARCH_SPEC }, \ | |
484 SUBTARGET_EXTRA_SPECS | |
485 | |
486 #define SUBTARGET_EXTRA_SPECS | |
487 | |
488 /* Because libgcc can generate references back to libc (via .umul etc.) we have | |
489 to list libc again after the second libgcc. */ | |
490 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" | |
491 | |
492 | |
493 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") | |
494 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") | |
495 | |
496 /* ??? This should be 32 bits for v9 but what can we do? */ | |
497 #define WCHAR_TYPE "short unsigned int" | |
498 #define WCHAR_TYPE_SIZE 16 | |
499 | |
500 /* Show we can debug even without a frame pointer. */ | |
501 #define CAN_DEBUG_WITHOUT_FP | |
502 | |
503 /* Option handling. */ | |
504 | |
505 #define OVERRIDE_OPTIONS sparc_override_options () | |
506 | |
507 /* Mask of all CPU selection flags. */ | |
508 #define MASK_ISA \ | |
509 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) | |
510 | |
511 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. | |
512 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y | |
513 to get high 32 bits. False in V8+ or V9 because multiply stores | |
514 a 64-bit result in a register. */ | |
515 | |
516 #define TARGET_HARD_MUL32 \ | |
517 ((TARGET_V8 || TARGET_SPARCLITE \ | |
518 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \ | |
519 && ! TARGET_V8PLUS && TARGET_ARCH32) | |
520 | |
521 #define TARGET_HARD_MUL \ | |
522 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ | |
523 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) | |
524 | |
525 /* MASK_APP_REGS must always be the default because that's what | |
526 FIXED_REGISTERS is set to and -ffixed- is processed before | |
527 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */ | |
528 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) | |
529 | |
530 /* Processor type. | |
531 These must match the values for the cpu attribute in sparc.md. */ | |
532 enum processor_type { | |
533 PROCESSOR_V7, | |
534 PROCESSOR_CYPRESS, | |
535 PROCESSOR_V8, | |
536 PROCESSOR_SUPERSPARC, | |
537 PROCESSOR_SPARCLITE, | |
538 PROCESSOR_F930, | |
539 PROCESSOR_F934, | |
540 PROCESSOR_HYPERSPARC, | |
541 PROCESSOR_SPARCLITE86X, | |
542 PROCESSOR_SPARCLET, | |
543 PROCESSOR_TSC701, | |
544 PROCESSOR_V9, | |
545 PROCESSOR_ULTRASPARC, | |
546 PROCESSOR_ULTRASPARC3, | |
547 PROCESSOR_NIAGARA, | |
548 PROCESSOR_NIAGARA2 | |
549 }; | |
550 | |
551 /* This is set from -m{cpu,tune}=xxx. */ | |
552 extern enum processor_type sparc_cpu; | |
553 | |
554 /* Recast the cpu class to be the cpu attribute. | |
555 Every file includes us, but not every file includes insn-attr.h. */ | |
556 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) | |
557 | |
558 /* Support for a compile-time default CPU, et cetera. The rules are: | |
559 --with-cpu is ignored if -mcpu is specified. | |
560 --with-tune is ignored if -mtune is specified. | |
561 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu | |
562 are specified. */ | |
563 #define OPTION_DEFAULT_SPECS \ | |
564 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ | |
565 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ | |
566 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" } | |
567 | |
568 /* sparc_select[0] is reserved for the default cpu. */ | |
569 struct sparc_cpu_select | |
570 { | |
571 const char *string; | |
572 const char *const name; | |
573 const int set_tune_p; | |
574 const int set_arch_p; | |
575 }; | |
576 | |
577 extern struct sparc_cpu_select sparc_select[]; | |
578 | |
579 /* target machine storage layout */ | |
580 | |
581 /* Define this if most significant bit is lowest numbered | |
582 in instructions that operate on numbered bit-fields. */ | |
583 #define BITS_BIG_ENDIAN 1 | |
584 | |
585 /* Define this if most significant byte of a word is the lowest numbered. */ | |
586 #define BYTES_BIG_ENDIAN 1 | |
587 | |
588 /* Define this if most significant word of a multiword number is the lowest | |
589 numbered. */ | |
590 #define WORDS_BIG_ENDIAN 1 | |
591 | |
592 /* Define this to set the endianness to use in libgcc2.c, which can | |
593 not depend on target_flags. */ | |
594 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__) | |
595 #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
596 #else | |
597 #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
598 #endif | |
599 | |
600 #define MAX_BITS_PER_WORD 64 | |
601 | |
602 /* Width of a word, in units (bytes). */ | |
603 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) | |
604 #ifdef IN_LIBGCC2 | |
605 #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
606 #else | |
607 #define MIN_UNITS_PER_WORD 4 | |
608 #endif | |
609 | |
610 #define UNITS_PER_SIMD_WORD(MODE) (TARGET_VIS ? 8 : UNITS_PER_WORD) | |
611 | |
612 /* Now define the sizes of the C data types. */ | |
613 | |
614 #define SHORT_TYPE_SIZE 16 | |
615 #define INT_TYPE_SIZE 32 | |
616 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) | |
617 #define LONG_LONG_TYPE_SIZE 64 | |
618 #define FLOAT_TYPE_SIZE 32 | |
619 #define DOUBLE_TYPE_SIZE 64 | |
620 | |
621 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the | |
622 SPARC ABI says that it is 128-bit wide. */ | |
623 /* #define LONG_DOUBLE_TYPE_SIZE 128 */ | |
624 | |
625 /* The widest floating-point format really supported by the hardware. */ | |
626 #define WIDEST_HARDWARE_FP_SIZE 64 | |
627 | |
628 /* Width in bits of a pointer. | |
629 See also the macro `Pmode' defined below. */ | |
630 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) | |
631 | |
632 /* If we have to extend pointers (only when TARGET_ARCH64 and not | |
633 TARGET_PTR64), we want to do it unsigned. This macro does nothing | |
634 if ptr_mode and Pmode are the same. */ | |
635 #define POINTERS_EXTEND_UNSIGNED 1 | |
636 | |
637 /* For TARGET_ARCH64 we need this, as we don't have instructions | |
638 for arithmetic operations which do zero/sign extension at the same time, | |
639 so without this we end up with a srl/sra after every assignment to an | |
640 user variable, which means very very bad code. */ | |
641 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \ | |
642 if (TARGET_ARCH64 \ | |
643 && GET_MODE_CLASS (MODE) == MODE_INT \ | |
644 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
645 (MODE) = word_mode; | |
646 | |
647 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
648 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) | |
649 | |
650 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
651 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because | |
652 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ | |
653 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) | |
654 /* Temporary hack until the FIXME above is fixed. */ | |
655 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) | |
656 | |
657 /* ALIGN FRAMES on double word boundaries */ | |
658 | |
659 #define SPARC_STACK_ALIGN(LOC) \ | |
660 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) | |
661 | |
662 /* Allocation boundary (in *bits*) for the code of a function. */ | |
663 #define FUNCTION_BOUNDARY 32 | |
664 | |
665 /* Alignment of field after `int : 0' in a structure. */ | |
666 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) | |
667 | |
668 /* Every structure's size must be a multiple of this. */ | |
669 #define STRUCTURE_SIZE_BOUNDARY 8 | |
670 | |
671 /* A bit-field declared as `int' forces `int' alignment for the struct. */ | |
672 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
673 | |
674 /* No data type wants to be aligned rounder than this. */ | |
675 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) | |
676 | |
677 /* The best alignment to use in cases where we have a choice. */ | |
678 #define FASTEST_ALIGNMENT 64 | |
679 | |
680 /* Define this macro as an expression for the alignment of a structure | |
681 (given by STRUCT as a tree node) if the alignment computed in the | |
682 usual way is COMPUTED and the alignment explicitly specified was | |
683 SPECIFIED. | |
684 | |
685 The default is to use SPECIFIED if it is larger; otherwise, use | |
686 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ | |
687 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ | |
688 (TARGET_FASTER_STRUCTS ? \ | |
689 ((TREE_CODE (STRUCT) == RECORD_TYPE \ | |
690 || TREE_CODE (STRUCT) == UNION_TYPE \ | |
691 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ | |
692 && TYPE_FIELDS (STRUCT) != 0 \ | |
693 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ | |
694 : MAX ((COMPUTED), (SPECIFIED))) \ | |
695 : MAX ((COMPUTED), (SPECIFIED))) | |
696 | |
697 /* Make strings word-aligned so strcpy from constants will be faster. */ | |
698 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
699 ((TREE_CODE (EXP) == STRING_CST \ | |
700 && (ALIGN) < FASTEST_ALIGNMENT) \ | |
701 ? FASTEST_ALIGNMENT : (ALIGN)) | |
702 | |
703 /* Make arrays of chars word-aligned for the same reasons. */ | |
704 #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
705 (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
706 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
707 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
708 | |
709 /* Make local arrays of chars word-aligned for the same reasons. */ | |
710 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) | |
711 | |
712 /* Set this nonzero if move instructions will actually fail to work | |
713 when given unaligned data. */ | |
714 #define STRICT_ALIGNMENT 1 | |
715 | |
716 /* Things that must be doubleword aligned cannot go in the text section, | |
717 because the linker fails to align the text section enough! | |
718 Put them in the data section. This macro is only used in this file. */ | |
719 #define MAX_TEXT_ALIGN 32 | |
720 | |
721 /* Standard register usage. */ | |
722 | |
723 /* Number of actual hardware registers. | |
724 The hardware registers are assigned numbers for the compiler | |
725 from 0 to just below FIRST_PSEUDO_REGISTER. | |
726 All registers that the compiler knows about must be given numbers, | |
727 even those that are not normally considered general registers. | |
728 | |
729 SPARC has 32 integer registers and 32 floating point registers. | |
730 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not | |
731 accessible. We still account for them to simplify register computations | |
732 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so | |
733 32+32+32+4 == 100. | |
734 Register 100 is used as the integer condition code register. | |
735 Register 101 is used as the soft frame pointer register. */ | |
736 | |
737 #define FIRST_PSEUDO_REGISTER 102 | |
738 | |
739 #define SPARC_FIRST_FP_REG 32 | |
740 /* Additional V9 fp regs. */ | |
741 #define SPARC_FIRST_V9_FP_REG 64 | |
742 #define SPARC_LAST_V9_FP_REG 95 | |
743 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ | |
744 #define SPARC_FIRST_V9_FCC_REG 96 | |
745 #define SPARC_LAST_V9_FCC_REG 99 | |
746 /* V8 fcc reg. */ | |
747 #define SPARC_FCC_REG 96 | |
748 /* Integer CC reg. We don't distinguish %icc from %xcc. */ | |
749 #define SPARC_ICC_REG 100 | |
750 | |
751 /* Nonzero if REGNO is an fp reg. */ | |
752 #define SPARC_FP_REG_P(REGNO) \ | |
753 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) | |
754 | |
755 /* Argument passing regs. */ | |
756 #define SPARC_OUTGOING_INT_ARG_FIRST 8 | |
757 #define SPARC_INCOMING_INT_ARG_FIRST 24 | |
758 #define SPARC_FP_ARG_FIRST 32 | |
759 | |
760 /* 1 for registers that have pervasive standard uses | |
761 and are not available for the register allocator. | |
762 | |
763 On non-v9 systems: | |
764 g1 is free to use as temporary. | |
765 g2-g4 are reserved for applications. Gcc normally uses them as | |
766 temporaries, but this can be disabled via the -mno-app-regs option. | |
767 g5 through g7 are reserved for the operating system. | |
768 | |
769 On v9 systems: | |
770 g1,g5 are free to use as temporaries, and are free to use between calls | |
771 if the call is to an external function via the PLT. | |
772 g4 is free to use as a temporary in the non-embedded case. | |
773 g4 is reserved in the embedded case. | |
774 g2-g3 are reserved for applications. Gcc normally uses them as | |
775 temporaries, but this can be disabled via the -mno-app-regs option. | |
776 g6-g7 are reserved for the operating system (or application in | |
777 embedded case). | |
778 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must | |
779 currently be a fixed register until this pattern is rewritten. | |
780 Register 1 is also used when restoring call-preserved registers in large | |
781 stack frames. | |
782 | |
783 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in | |
784 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. | |
785 */ | |
786 | |
787 #define FIXED_REGISTERS \ | |
788 {1, 0, 2, 2, 2, 2, 1, 1, \ | |
789 0, 0, 0, 0, 0, 0, 1, 0, \ | |
790 0, 0, 0, 0, 0, 0, 0, 0, \ | |
791 0, 0, 0, 0, 0, 0, 1, 1, \ | |
792 \ | |
793 0, 0, 0, 0, 0, 0, 0, 0, \ | |
794 0, 0, 0, 0, 0, 0, 0, 0, \ | |
795 0, 0, 0, 0, 0, 0, 0, 0, \ | |
796 0, 0, 0, 0, 0, 0, 0, 0, \ | |
797 \ | |
798 0, 0, 0, 0, 0, 0, 0, 0, \ | |
799 0, 0, 0, 0, 0, 0, 0, 0, \ | |
800 0, 0, 0, 0, 0, 0, 0, 0, \ | |
801 0, 0, 0, 0, 0, 0, 0, 0, \ | |
802 \ | |
803 0, 0, 0, 0, 0, 1} | |
804 | |
805 /* 1 for registers not available across function calls. | |
806 These must include the FIXED_REGISTERS and also any | |
807 registers that can be used without being saved. | |
808 The latter must include the registers where values are returned | |
809 and the register where structure-value addresses are passed. | |
810 Aside from that, you can include as many other registers as you like. */ | |
811 | |
812 #define CALL_USED_REGISTERS \ | |
813 {1, 1, 1, 1, 1, 1, 1, 1, \ | |
814 1, 1, 1, 1, 1, 1, 1, 1, \ | |
815 0, 0, 0, 0, 0, 0, 0, 0, \ | |
816 0, 0, 0, 0, 0, 0, 1, 1, \ | |
817 \ | |
818 1, 1, 1, 1, 1, 1, 1, 1, \ | |
819 1, 1, 1, 1, 1, 1, 1, 1, \ | |
820 1, 1, 1, 1, 1, 1, 1, 1, \ | |
821 1, 1, 1, 1, 1, 1, 1, 1, \ | |
822 \ | |
823 1, 1, 1, 1, 1, 1, 1, 1, \ | |
824 1, 1, 1, 1, 1, 1, 1, 1, \ | |
825 1, 1, 1, 1, 1, 1, 1, 1, \ | |
826 1, 1, 1, 1, 1, 1, 1, 1, \ | |
827 \ | |
828 1, 1, 1, 1, 1, 1} | |
829 | |
830 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that | |
831 they won't be allocated. */ | |
832 | |
833 #define CONDITIONAL_REGISTER_USAGE \ | |
834 do \ | |
835 { \ | |
836 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ | |
837 { \ | |
838 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
839 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
840 } \ | |
841 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \ | |
842 /* then honor it. */ \ | |
843 if (TARGET_ARCH32 && fixed_regs[5]) \ | |
844 fixed_regs[5] = 1; \ | |
845 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \ | |
846 fixed_regs[5] = 0; \ | |
847 if (! TARGET_V9) \ | |
848 { \ | |
849 int regno; \ | |
850 for (regno = SPARC_FIRST_V9_FP_REG; \ | |
851 regno <= SPARC_LAST_V9_FP_REG; \ | |
852 regno++) \ | |
853 fixed_regs[regno] = 1; \ | |
854 /* %fcc0 is used by v8 and v9. */ \ | |
855 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \ | |
856 regno <= SPARC_LAST_V9_FCC_REG; \ | |
857 regno++) \ | |
858 fixed_regs[regno] = 1; \ | |
859 } \ | |
860 if (! TARGET_FPU) \ | |
861 { \ | |
862 int regno; \ | |
863 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \ | |
864 fixed_regs[regno] = 1; \ | |
865 } \ | |
866 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \ | |
867 /* then honor it. Likewise with g3 and g4. */ \ | |
868 if (fixed_regs[2] == 2) \ | |
869 fixed_regs[2] = ! TARGET_APP_REGS; \ | |
870 if (fixed_regs[3] == 2) \ | |
871 fixed_regs[3] = ! TARGET_APP_REGS; \ | |
872 if (TARGET_ARCH32 && fixed_regs[4] == 2) \ | |
873 fixed_regs[4] = ! TARGET_APP_REGS; \ | |
874 else if (TARGET_CM_EMBMEDANY) \ | |
875 fixed_regs[4] = 1; \ | |
876 else if (fixed_regs[4] == 2) \ | |
877 fixed_regs[4] = 0; \ | |
878 } \ | |
879 while (0) | |
880 | |
881 /* Return number of consecutive hard regs needed starting at reg REGNO | |
882 to hold something of mode MODE. | |
883 This is ordinarily the length in words of a value of mode MODE | |
884 but can be less for certain modes in special long registers. | |
885 | |
886 On SPARC, ordinary registers hold 32 bits worth; | |
887 this means both integer and floating point registers. | |
888 On v9, integer regs hold 64 bits worth; floating point regs hold | |
889 32 bits worth (this includes the new fp regs as even the odd ones are | |
890 included in the hard register count). */ | |
891 | |
892 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
893 (TARGET_ARCH64 \ | |
894 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \ | |
895 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ | |
896 : (GET_MODE_SIZE (MODE) + 3) / 4) \ | |
897 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
898 | |
899 /* Due to the ARCH64 discrepancy above we must override this next | |
900 macro too. */ | |
901 #define REGMODE_NATURAL_SIZE(MODE) \ | |
902 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD) | |
903 | |
904 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
905 See sparc.c for how we initialize this. */ | |
906 extern const int *hard_regno_mode_classes; | |
907 extern int sparc_mode_class[]; | |
908 | |
909 /* ??? Because of the funny way we pass parameters we should allow certain | |
910 ??? types of float/complex values to be in integer registers during | |
911 ??? RTL generation. This only matters on arch32. */ | |
912 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
913 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) | |
914 | |
915 /* Value is 1 if it is OK to rename a hard register FROM to another hard | |
916 register TO. We cannot rename %g1 as it may be used before the save | |
917 register window instruction in the prologue. */ | |
918 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) | |
919 | |
920 /* Value is 1 if it is a good idea to tie two pseudo registers | |
921 when one has mode MODE1 and one has mode MODE2. | |
922 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
923 for any hard reg, then this must be 0 for correct output. | |
924 | |
925 For V9: SFmode can't be combined with other float modes, because they can't | |
926 be allocated to the %d registers. Also, DFmode won't fit in odd %f | |
927 registers, but SFmode will. */ | |
928 #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
929 ((MODE1) == (MODE2) \ | |
930 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ | |
931 && (! TARGET_V9 \ | |
932 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ | |
933 || (MODE1 != SFmode && MODE2 != SFmode))))) | |
934 | |
935 /* Specify the registers used for certain standard purposes. | |
936 The values of these macros are register numbers. */ | |
937 | |
938 /* Register to use for pushing function arguments. */ | |
939 #define STACK_POINTER_REGNUM 14 | |
940 | |
941 /* The stack bias (amount by which the hardware register is offset by). */ | |
942 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) | |
943 | |
944 /* Actual top-of-stack address is 92/176 greater than the contents of the | |
945 stack pointer register for !v9/v9. That is: | |
946 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return | |
947 address, and 6*4 bytes for the 6 register parameters. | |
948 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer | |
949 parameter regs. */ | |
950 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) | |
951 | |
952 /* Base register for access to local variables of the function. */ | |
953 #define HARD_FRAME_POINTER_REGNUM 30 | |
954 | |
955 /* The soft frame pointer does not have the stack bias applied. */ | |
956 #define FRAME_POINTER_REGNUM 101 | |
957 | |
958 /* Given the stack bias, the stack pointer isn't actually aligned. */ | |
959 #define INIT_EXPANDERS \ | |
960 do { \ | |
961 if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \ | |
962 { \ | |
963 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \ | |
964 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \ | |
965 } \ | |
966 } while (0) | |
967 | |
968 /* Value should be nonzero if functions must have frame pointers. | |
969 Zero means the frame pointer need not be set up (and parms | |
970 may be accessed via the stack pointer) in functions that seem suitable. | |
971 Used in flow.c, global.c, ra.c and reload1.c. */ | |
972 #define FRAME_POINTER_REQUIRED \ | |
973 (! (leaf_function_p () && only_leaf_regs_used ())) | |
974 | |
975 /* Base register for access to arguments of the function. */ | |
976 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM | |
977 | |
978 /* Register in which static-chain is passed to a function. This must | |
979 not be a register used by the prologue. */ | |
980 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) | |
981 | |
982 /* Register which holds offset table for position-independent | |
983 data references. */ | |
984 | |
985 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM) | |
986 | |
987 /* Pick a default value we can notice from override_options: | |
988 !v9: Default is on. | |
989 v9: Default is off. | |
990 Originally it was -1, but later on the container of options changed to | |
991 unsigned byte, so we decided to pick 127 as default value, which does | |
992 reflect an undefined default value in case of 0/1. */ | |
993 | |
994 #define DEFAULT_PCC_STRUCT_RETURN 127 | |
995 | |
996 /* Functions which return large structures get the address | |
997 to place the wanted value at offset 64 from the frame. | |
998 Must reserve 64 bytes for the in and local registers. | |
999 v9: Functions which return large structures get the address to place the | |
1000 wanted value from an invisible first argument. */ | |
1001 #define STRUCT_VALUE_OFFSET 64 | |
1002 | |
1003 /* Define the classes of registers for register constraints in the | |
1004 machine description. Also define ranges of constants. | |
1005 | |
1006 One of the classes must always be named ALL_REGS and include all hard regs. | |
1007 If there is more than one class, another class must be named NO_REGS | |
1008 and contain no registers. | |
1009 | |
1010 The name GENERAL_REGS must be the name of a class (or an alias for | |
1011 another name such as ALL_REGS). This is the class of registers | |
1012 that is allowed by "g" or "r" in a register constraint. | |
1013 Also, registers outside this class are allocated only when | |
1014 instructions express preferences for them. | |
1015 | |
1016 The classes must be numbered in nondecreasing order; that is, | |
1017 a larger-numbered class must never be contained completely | |
1018 in a smaller-numbered class. | |
1019 | |
1020 For any two classes, it is very desirable that there be another | |
1021 class that represents their union. */ | |
1022 | |
1023 /* The SPARC has various kinds of registers: general, floating point, | |
1024 and condition codes [well, it has others as well, but none that we | |
1025 care directly about]. | |
1026 | |
1027 For v9 we must distinguish between the upper and lower floating point | |
1028 registers because the upper ones can't hold SFmode values. | |
1029 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) | |
1030 satisfying a group need for a class will also satisfy a single need for | |
1031 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp | |
1032 regs. | |
1033 | |
1034 It is important that one class contains all the general and all the standard | |
1035 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, | |
1036 because reg_class_record() will bias the selection in favor of fp regs, | |
1037 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, | |
1038 because FP_REGS > GENERAL_REGS. | |
1039 | |
1040 It is also important that one class contain all the general and all | |
1041 the fp regs. Otherwise when spilling a DFmode reg, it may be from | |
1042 EXTRA_FP_REGS but find_reloads() may use class | |
1043 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die | |
1044 because the compiler thinks it doesn't have a spill reg when in | |
1045 fact it does. | |
1046 | |
1047 v9 also has 4 floating point condition code registers. Since we don't | |
1048 have a class that is the union of FPCC_REGS with either of the others, | |
1049 it is important that it appear first. Otherwise the compiler will die | |
1050 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its | |
1051 constraints. | |
1052 | |
1053 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine | |
1054 may try to use it to hold an SImode value. See register_operand. | |
1055 ??? Should %fcc[0123] be handled similarly? | |
1056 */ | |
1057 | |
1058 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, | |
1059 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, | |
1060 ALL_REGS, LIM_REG_CLASSES }; | |
1061 | |
1062 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1063 | |
1064 /* Give names of register classes as strings for dump file. */ | |
1065 | |
1066 #define REG_CLASS_NAMES \ | |
1067 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ | |
1068 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ | |
1069 "ALL_REGS" } | |
1070 | |
1071 /* Define which registers fit in which classes. | |
1072 This is an initializer for a vector of HARD_REG_SET | |
1073 of length N_REG_CLASSES. */ | |
1074 | |
1075 #define REG_CLASS_CONTENTS \ | |
1076 {{0, 0, 0, 0}, /* NO_REGS */ \ | |
1077 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ | |
1078 {0xffff, 0, 0, 0}, /* I64_REGS */ \ | |
1079 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ | |
1080 {0, -1, 0, 0}, /* FP_REGS */ \ | |
1081 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ | |
1082 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ | |
1083 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ | |
1084 {-1, -1, -1, 0x3f}} /* ALL_REGS */ | |
1085 | |
1086 /* The following macro defines cover classes for Integrated Register | |
1087 Allocator. Cover classes is a set of non-intersected register | |
1088 classes covering all hard registers used for register allocation | |
1089 purpose. Any move between two registers of a cover class should be | |
1090 cheaper than load or store of the registers. The macro value is | |
1091 array of register classes with LIM_REG_CLASSES used as the end | |
1092 marker. */ | |
1093 | |
1094 #define IRA_COVER_CLASSES \ | |
1095 { \ | |
1096 GENERAL_REGS, EXTRA_FP_REGS, FPCC_REGS, LIM_REG_CLASSES \ | |
1097 } | |
1098 | |
1099 /* Defines invalid mode changes. Borrowed from pa64-regs.h. | |
1100 | |
1101 SImode loads to floating-point registers are not zero-extended. | |
1102 The definition for LOAD_EXTEND_OP specifies that integer loads | |
1103 narrower than BITS_PER_WORD will be zero-extended. As a result, | |
1104 we inhibit changes from SImode unless they are to a mode that is | |
1105 identical in size. */ | |
1106 | |
1107 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1108 (TARGET_ARCH64 \ | |
1109 && (FROM) == SImode \ | |
1110 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
1111 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) | |
1112 | |
1113 /* The same information, inverted: | |
1114 Return the class number of the smallest class containing | |
1115 reg number REGNO. This could be a conditional expression | |
1116 or could index an array. */ | |
1117 | |
1118 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
1119 | |
1120 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] | |
1121 | |
1122 /* This is the order in which to allocate registers normally. | |
1123 | |
1124 We put %f0-%f7 last among the float registers, so as to make it more | |
1125 likely that a pseudo-register which dies in the float return register | |
1126 area will get allocated to the float return register, thus saving a move | |
1127 instruction at the end of the function. | |
1128 | |
1129 Similarly for integer return value registers. | |
1130 | |
1131 We know in this case that we will not end up with a leaf function. | |
1132 | |
1133 The register allocator is given the global and out registers first | |
1134 because these registers are call clobbered and thus less useful to | |
1135 global register allocation. | |
1136 | |
1137 Next we list the local and in registers. They are not call clobbered | |
1138 and thus very useful for global register allocation. We list the input | |
1139 registers before the locals so that it is more likely the incoming | |
1140 arguments received in those registers can just stay there and not be | |
1141 reloaded. */ | |
1142 | |
1143 #define REG_ALLOC_ORDER \ | |
1144 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ | |
1145 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ | |
1146 15, /* %o7 */ \ | |
1147 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ | |
1148 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ | |
1149 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ | |
1150 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ | |
1151 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
1152 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
1153 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
1154 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ | |
1155 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
1156 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ | |
1157 96, 97, 98, 99, /* %fcc0-3 */ \ | |
1158 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */ | |
1159 | |
1160 /* This is the order in which to allocate registers for | |
1161 leaf functions. If all registers can fit in the global and | |
1162 output registers, then we have the possibility of having a leaf | |
1163 function. | |
1164 | |
1165 The macro actually mentioned the input registers first, | |
1166 because they get renumbered into the output registers once | |
1167 we know really do have a leaf function. | |
1168 | |
1169 To be more precise, this register allocation order is used | |
1170 when %o7 is found to not be clobbered right before register | |
1171 allocation. Normally, the reason %o7 would be clobbered is | |
1172 due to a call which could not be transformed into a sibling | |
1173 call. | |
1174 | |
1175 As a consequence, it is possible to use the leaf register | |
1176 allocation order and not end up with a leaf function. We will | |
1177 not get suboptimal register allocation in that case because by | |
1178 definition of being potentially leaf, there were no function | |
1179 calls. Therefore, allocation order within the local register | |
1180 window is not critical like it is when we do have function calls. */ | |
1181 | |
1182 #define REG_LEAF_ALLOC_ORDER \ | |
1183 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ | |
1184 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ | |
1185 15, /* %o7 */ \ | |
1186 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ | |
1187 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ | |
1188 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ | |
1189 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ | |
1190 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
1191 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
1192 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
1193 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ | |
1194 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
1195 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ | |
1196 96, 97, 98, 99, /* %fcc0-3 */ \ | |
1197 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ | |
1198 | |
1199 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | |
1200 | |
1201 extern char sparc_leaf_regs[]; | |
1202 #define LEAF_REGISTERS sparc_leaf_regs | |
1203 | |
1204 extern char leaf_reg_remap[]; | |
1205 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) | |
1206 | |
1207 /* The class value for index registers, and the one for base regs. */ | |
1208 #define INDEX_REG_CLASS GENERAL_REGS | |
1209 #define BASE_REG_CLASS GENERAL_REGS | |
1210 | |
1211 /* Local macro to handle the two v9 classes of FP regs. */ | |
1212 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) | |
1213 | |
1214 /* Predicates for 10-bit, 11-bit and 13-bit signed constants. */ | |
1215 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) | |
1216 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) | |
1217 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) | |
1218 | |
1219 /* 10- and 11-bit immediates are only used for a few specific insns. | |
1220 SMALL_INT is used throughout the port so we continue to use it. */ | |
1221 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) | |
1222 | |
1223 /* Predicate for constants that can be loaded with a sethi instruction. | |
1224 This is the general, 64-bit aware, bitwise version that ensures that | |
1225 only constants whose representation fits in the mask | |
1226 | |
1227 0x00000000fffffc00 | |
1228 | |
1229 are accepted. It will reject, for example, negative SImode constants | |
1230 on 64-bit hosts, so correct handling is to mask the value beforehand | |
1231 according to the mode of the instruction. */ | |
1232 #define SPARC_SETHI_P(X) \ | |
1233 (((unsigned HOST_WIDE_INT) (X) \ | |
1234 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) | |
1235 | |
1236 /* Version of the above predicate for SImode constants and below. */ | |
1237 #define SPARC_SETHI32_P(X) \ | |
1238 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) | |
1239 | |
1240 /* Given an rtx X being reloaded into a reg required to be | |
1241 in class CLASS, return the class of reg to actually use. | |
1242 In general this is just CLASS; but on some machines | |
1243 in some cases it is preferable to use a more restrictive class. */ | |
1244 /* - We can't load constants into FP registers. | |
1245 - We can't load FP constants into integer registers when soft-float, | |
1246 because there is no soft-float pattern with a r/F constraint. | |
1247 - We can't load FP constants into integer registers for TFmode unless | |
1248 it is 0.0L, because there is no movtf pattern with a r/F constraint. | |
1249 - Try and reload integer constants (symbolic or otherwise) back into | |
1250 registers directly, rather than having them dumped to memory. */ | |
1251 | |
1252 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
1253 (CONSTANT_P (X) \ | |
1254 ? ((FP_REG_CLASS_P (CLASS) \ | |
1255 || (CLASS) == GENERAL_OR_FP_REGS \ | |
1256 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \ | |
1257 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ | |
1258 && ! TARGET_FPU) \ | |
1259 || (GET_MODE (X) == TFmode \ | |
1260 && ! const_zero_operand (X, TFmode))) \ | |
1261 ? NO_REGS \ | |
1262 : (!FP_REG_CLASS_P (CLASS) \ | |
1263 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \ | |
1264 ? GENERAL_REGS \ | |
1265 : (CLASS)) \ | |
1266 : (CLASS)) | |
1267 | |
1268 /* Return the register class of a scratch register needed to load IN into | |
1269 a register of class CLASS in MODE. | |
1270 | |
1271 We need a temporary when loading/storing a HImode/QImode value | |
1272 between memory and the FPU registers. This can happen when combine puts | |
1273 a paradoxical subreg in a float/fix conversion insn. | |
1274 | |
1275 We need a temporary when loading/storing a DFmode value between | |
1276 unaligned memory and the upper FPU registers. */ | |
1277 | |
1278 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
1279 ((FP_REG_CLASS_P (CLASS) \ | |
1280 && ((MODE) == HImode || (MODE) == QImode) \ | |
1281 && (GET_CODE (IN) == MEM \ | |
1282 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ | |
1283 && true_regnum (IN) == -1))) \ | |
1284 ? GENERAL_REGS \ | |
1285 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ | |
1286 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ | |
1287 && ! mem_min_alignment ((IN), 8)) \ | |
1288 ? FP_REGS \ | |
1289 : (((TARGET_CM_MEDANY \ | |
1290 && symbolic_operand ((IN), (MODE))) \ | |
1291 || (TARGET_CM_EMBMEDANY \ | |
1292 && text_segment_operand ((IN), (MODE)))) \ | |
1293 && !flag_pic) \ | |
1294 ? GENERAL_REGS \ | |
1295 : NO_REGS) | |
1296 | |
1297 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
1298 ((FP_REG_CLASS_P (CLASS) \ | |
1299 && ((MODE) == HImode || (MODE) == QImode) \ | |
1300 && (GET_CODE (IN) == MEM \ | |
1301 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ | |
1302 && true_regnum (IN) == -1))) \ | |
1303 ? GENERAL_REGS \ | |
1304 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ | |
1305 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ | |
1306 && ! mem_min_alignment ((IN), 8)) \ | |
1307 ? FP_REGS \ | |
1308 : (((TARGET_CM_MEDANY \ | |
1309 && symbolic_operand ((IN), (MODE))) \ | |
1310 || (TARGET_CM_EMBMEDANY \ | |
1311 && text_segment_operand ((IN), (MODE)))) \ | |
1312 && !flag_pic) \ | |
1313 ? GENERAL_REGS \ | |
1314 : NO_REGS) | |
1315 | |
1316 /* On SPARC it is not possible to directly move data between | |
1317 GENERAL_REGS and FP_REGS. */ | |
1318 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
1319 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) | |
1320 | |
1321 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 | |
1322 because the movsi and movsf patterns don't handle r/f moves. | |
1323 For v8 we copy the default definition. */ | |
1324 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1325 (TARGET_ARCH64 \ | |
1326 ? (GET_MODE_BITSIZE (MODE) < 32 \ | |
1327 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
1328 : MODE) \ | |
1329 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ | |
1330 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ | |
1331 : MODE)) | |
1332 | |
1333 /* Return the maximum number of consecutive registers | |
1334 needed to represent mode MODE in a register of class CLASS. */ | |
1335 /* On SPARC, this is the size of MODE in words. */ | |
1336 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
1337 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ | |
1338 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
1339 | |
1340 /* Stack layout; function entry, exit and calling. */ | |
1341 | |
1342 /* Define this if pushing a word on the stack | |
1343 makes the stack pointer a smaller address. */ | |
1344 #define STACK_GROWS_DOWNWARD | |
1345 | |
1346 /* Define this to nonzero if the nominal address of the stack frame | |
1347 is at the high-address end of the local variables; | |
1348 that is, each additional local variable allocated | |
1349 goes at a more negative offset in the frame. */ | |
1350 #define FRAME_GROWS_DOWNWARD 1 | |
1351 | |
1352 /* Offset within stack frame to start allocating local variables at. | |
1353 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1354 first local allocated. Otherwise, it is the offset to the BEGINNING | |
1355 of the first local allocated. */ | |
1356 #define STARTING_FRAME_OFFSET 0 | |
1357 | |
1358 /* Offset of first parameter from the argument pointer register value. | |
1359 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg | |
1360 even if this function isn't going to use it. | |
1361 v9: This is 128 for the ins and locals. */ | |
1362 #define FIRST_PARM_OFFSET(FNDECL) \ | |
1363 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) | |
1364 | |
1365 /* Offset from the argument pointer register value to the CFA. | |
1366 This is different from FIRST_PARM_OFFSET because the register window | |
1367 comes between the CFA and the arguments. */ | |
1368 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1369 | |
1370 /* When a parameter is passed in a register, stack space is still | |
1371 allocated for it. | |
1372 !v9: All 6 possible integer registers have backing store allocated. | |
1373 v9: Only space for the arguments passed is allocated. */ | |
1374 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special | |
1375 meaning to the backend. Further, we need to be able to detect if a | |
1376 varargs/unprototyped function is called, as they may want to spill more | |
1377 registers than we've provided space. Ugly, ugly. So for now we retain | |
1378 all 6 slots even for v9. */ | |
1379 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) | |
1380 | |
1381 /* Definitions for register elimination. */ | |
1382 | |
1383 #define ELIMINABLE_REGS \ | |
1384 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1385 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } | |
1386 | |
1387 /* The way this is structured, we can't eliminate SFP in favor of SP | |
1388 if the frame pointer is required: we want to use the SFP->HFP elimination | |
1389 in that case. But the test in update_eliminables doesn't know we are | |
1390 assuming below that we only do the former elimination. */ | |
1391 #define CAN_ELIMINATE(FROM, TO) \ | |
1392 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED) | |
1393 | |
1394 /* We always pretend that this is a leaf function because if it's not, | |
1395 there's no point in trying to eliminate the frame pointer. If it | |
1396 is a leaf function, we guessed right! */ | |
1397 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1398 do { \ | |
1399 if ((TO) == STACK_POINTER_REGNUM) \ | |
1400 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \ | |
1401 else \ | |
1402 (OFFSET) = 0; \ | |
1403 (OFFSET) += SPARC_STACK_BIAS; \ | |
1404 } while (0) | |
1405 | |
1406 /* Keep the stack pointer constant throughout the function. | |
1407 This is both an optimization and a necessity: longjmp | |
1408 doesn't behave itself when the stack pointer moves within | |
1409 the function! */ | |
1410 #define ACCUMULATE_OUTGOING_ARGS 1 | |
1411 | |
1412 /* Value is the number of bytes of arguments automatically | |
1413 popped when returning from a subroutine call. | |
1414 FUNDECL is the declaration node of the function (as a tree), | |
1415 FUNTYPE is the data type of the function (as a tree), | |
1416 or for a library call it is an identifier node for the subroutine name. | |
1417 SIZE is the number of bytes of arguments passed on the stack. */ | |
1418 | |
1419 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 | |
1420 | |
1421 /* Define this macro if the target machine has "register windows". This | |
1422 C expression returns the register number as seen by the called function | |
1423 corresponding to register number OUT as seen by the calling function. | |
1424 Return OUT if register number OUT is not an outbound register. */ | |
1425 | |
1426 #define INCOMING_REGNO(OUT) \ | |
1427 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) | |
1428 | |
1429 /* Define this macro if the target machine has "register windows". This | |
1430 C expression returns the register number as seen by the calling function | |
1431 corresponding to register number IN as seen by the called function. | |
1432 Return IN if register number IN is not an inbound register. */ | |
1433 | |
1434 #define OUTGOING_REGNO(IN) \ | |
1435 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) | |
1436 | |
1437 /* Define this macro if the target machine has register windows. This | |
1438 C expression returns true if the register is call-saved but is in the | |
1439 register window. */ | |
1440 | |
1441 #define LOCAL_REGNO(REGNO) \ | |
1442 ((REGNO) >= 16 && (REGNO) <= 31) | |
1443 | |
1444 /* Define how to find the value returned by a function. | |
1445 VALTYPE is the data type of the value (as a tree). | |
1446 If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1447 otherwise, FUNC is 0. */ | |
1448 | |
1449 /* On SPARC the value is found in the first "output" register. */ | |
1450 | |
1451 #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
1452 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1) | |
1453 | |
1454 /* But the called function leaves it in the first "input" register. */ | |
1455 | |
1456 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ | |
1457 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0) | |
1458 | |
1459 /* Define how to find the value returned by a library function | |
1460 assuming the value has mode MODE. */ | |
1461 | |
1462 #define LIBCALL_VALUE(MODE) \ | |
1463 function_value (NULL_TREE, (MODE), 1) | |
1464 | |
1465 /* 1 if N is a possible register number for a function value | |
1466 as seen by the caller. | |
1467 On SPARC, the first "output" reg is used for integer values, | |
1468 and the first floating point register is used for floating point values. */ | |
1469 | |
1470 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) | |
1471 | |
1472 /* Define the size of space to allocate for the return value of an | |
1473 untyped_call. */ | |
1474 | |
1475 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) | |
1476 | |
1477 /* 1 if N is a possible register number for function argument passing. | |
1478 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ | |
1479 | |
1480 #define FUNCTION_ARG_REGNO_P(N) \ | |
1481 (TARGET_ARCH64 \ | |
1482 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ | |
1483 : ((N) >= 8 && (N) <= 13)) | |
1484 | |
1485 /* Define a data type for recording info about an argument list | |
1486 during the scan of that argument list. This data type should | |
1487 hold all necessary information about the function itself | |
1488 and about the args processed so far, enough to enable macros | |
1489 such as FUNCTION_ARG to determine where the next arg should go. | |
1490 | |
1491 On SPARC (!v9), this is a single integer, which is a number of words | |
1492 of arguments scanned so far (including the invisible argument, | |
1493 if any, which holds the structure-value-address). | |
1494 Thus 7 or more means all following args should go on the stack. | |
1495 | |
1496 For v9, we also need to know whether a prototype is present. */ | |
1497 | |
1498 struct sparc_args { | |
1499 int words; /* number of words passed so far */ | |
1500 int prototype_p; /* nonzero if a prototype is present */ | |
1501 int libcall_p; /* nonzero if a library call */ | |
1502 }; | |
1503 #define CUMULATIVE_ARGS struct sparc_args | |
1504 | |
1505 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1506 for a call to a function whose data type is FNTYPE. | |
1507 For a library call, FNTYPE is 0. */ | |
1508 | |
1509 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
1510 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); | |
1511 | |
1512 /* Update the data in CUM to advance over an argument | |
1513 of mode MODE and data type TYPE. | |
1514 TYPE is null for libcalls where that information may not be available. */ | |
1515 | |
1516 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1517 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED)) | |
1518 | |
1519 /* Determine where to put an argument to a function. | |
1520 Value is zero to push the argument on the stack, | |
1521 or a hard register in which to store the argument. | |
1522 | |
1523 MODE is the argument's machine mode. | |
1524 TYPE is the data type of the argument (as a tree). | |
1525 This is null for libcalls where that information may | |
1526 not be available. | |
1527 CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1528 the preceding args and about the function being called. | |
1529 NAMED is nonzero if this argument is a named parameter | |
1530 (otherwise it is an extra parameter matching an ellipsis). */ | |
1531 | |
1532 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
1533 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0) | |
1534 | |
1535 /* Define where a function finds its arguments. | |
1536 This is different from FUNCTION_ARG because of register windows. */ | |
1537 | |
1538 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
1539 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1) | |
1540 | |
1541 /* If defined, a C expression which determines whether, and in which direction, | |
1542 to pad out an argument with extra space. The value should be of type | |
1543 `enum direction': either `upward' to pad above the argument, | |
1544 `downward' to pad below, or `none' to inhibit padding. */ | |
1545 | |
1546 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ | |
1547 function_arg_padding ((MODE), (TYPE)) | |
1548 | |
1549 /* If defined, a C expression that gives the alignment boundary, in bits, | |
1550 of an argument with the specified mode and type. If it is not defined, | |
1551 PARM_BOUNDARY is used for all arguments. | |
1552 For sparc64, objects requiring 16 byte alignment are passed that way. */ | |
1553 | |
1554 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
1555 ((TARGET_ARCH64 \ | |
1556 && (GET_MODE_ALIGNMENT (MODE) == 128 \ | |
1557 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \ | |
1558 ? 128 : PARM_BOUNDARY) | |
1559 | |
1560 /* Define the information needed to generate branch and scc insns. This is | |
1561 stored from the compare operation. Note that we can't use "rtx" here | |
1562 since it hasn't been defined! */ | |
1563 | |
1564 extern GTY(()) rtx sparc_compare_op0; | |
1565 extern GTY(()) rtx sparc_compare_op1; | |
1566 extern GTY(()) rtx sparc_compare_emitted; | |
1567 | |
1568 | |
1569 /* Generate the special assembly code needed to tell the assembler whatever | |
1570 it might need to know about the return value of a function. | |
1571 | |
1572 For SPARC assemblers, we need to output a .proc pseudo-op which conveys | |
1573 information to the assembler relating to peephole optimization (done in | |
1574 the assembler). */ | |
1575 | |
1576 #define ASM_DECLARE_RESULT(FILE, RESULT) \ | |
1577 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) | |
1578 | |
1579 /* Output the special assembly code needed to tell the assembler some | |
1580 register is used as global register variable. | |
1581 | |
1582 SPARC 64bit psABI declares registers %g2 and %g3 as application | |
1583 registers and %g6 and %g7 as OS registers. Any object using them | |
1584 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them | |
1585 and how they are used (scratch or some global variable). | |
1586 Linker will then refuse to link together objects which use those | |
1587 registers incompatibly. | |
1588 | |
1589 Unless the registers are used for scratch, two different global | |
1590 registers cannot be declared to the same name, so in the unlikely | |
1591 case of a global register variable occupying more than one register | |
1592 we prefix the second and following registers with .gnu.part1. etc. */ | |
1593 | |
1594 extern GTY(()) char sparc_hard_reg_printed[8]; | |
1595 | |
1596 #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
1597 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ | |
1598 do { \ | |
1599 if (TARGET_ARCH64) \ | |
1600 { \ | |
1601 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ | |
1602 int reg; \ | |
1603 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ | |
1604 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ | |
1605 { \ | |
1606 if (reg == (REGNO)) \ | |
1607 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ | |
1608 else \ | |
1609 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ | |
1610 reg, reg - (REGNO), (NAME)); \ | |
1611 sparc_hard_reg_printed[reg] = 1; \ | |
1612 } \ | |
1613 } \ | |
1614 } while (0) | |
1615 #endif | |
1616 | |
1617 | |
1618 /* Emit rtl for profiling. */ | |
1619 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) | |
1620 | |
1621 /* All the work done in PROFILE_HOOK, but still required. */ | |
1622 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) | |
1623 | |
1624 /* Set the name of the mcount function for the system. */ | |
1625 #define MCOUNT_FUNCTION "*mcount" | |
1626 | |
1627 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1628 the stack pointer does not matter. The value is tested only in | |
1629 functions that have frame pointers. | |
1630 No definition is equivalent to always zero. */ | |
1631 | |
1632 #define EXIT_IGNORE_STACK \ | |
1633 (get_frame_size () != 0 \ | |
1634 || cfun->calls_alloca || crtl->outgoing_args_size) | |
1635 | |
1636 /* Define registers used by the epilogue and return instruction. */ | |
1637 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \ | |
1638 || (crtl->calls_eh_return && (REGNO) == 1)) | |
1639 | |
1640 /* Length in units of the trampoline for entering a nested function. */ | |
1641 | |
1642 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) | |
1643 | |
1644 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */ | |
1645 | |
1646 /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1647 FNADDR is an RTX for the address of the function's pure code. | |
1648 CXT is an RTX for the static chain value for the function. */ | |
1649 | |
1650 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1651 if (TARGET_ARCH64) \ | |
1652 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ | |
1653 else \ | |
1654 sparc_initialize_trampoline (TRAMP, FNADDR, CXT) | |
1655 | |
1656 /* Generate RTL to flush the register windows so as to make arbitrary frames | |
1657 available. */ | |
1658 #define SETUP_FRAME_ADDRESSES() \ | |
1659 emit_insn (gen_flush_register_windows ()) | |
1660 | |
1661 /* Given an rtx for the address of a frame, | |
1662 return an rtx for the address of the word in the frame | |
1663 that holds the dynamic chain--the previous frame's address. */ | |
1664 #define DYNAMIC_CHAIN_ADDRESS(frame) \ | |
1665 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) | |
1666 | |
1667 /* Given an rtx for the frame pointer, | |
1668 return an rtx for the address of the frame. */ | |
1669 #define FRAME_ADDR_RTX(frame) plus_constant (frame, SPARC_STACK_BIAS) | |
1670 | |
1671 /* The return address isn't on the stack, it is in a register, so we can't | |
1672 access it from the current frame pointer. We can access it from the | |
1673 previous frame pointer though by reading a value from the register window | |
1674 save area. */ | |
1675 #define RETURN_ADDR_IN_PREVIOUS_FRAME | |
1676 | |
1677 /* This is the offset of the return address to the true next instruction to be | |
1678 executed for the current function. */ | |
1679 #define RETURN_ADDR_OFFSET \ | |
1680 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct)) | |
1681 | |
1682 /* The current return address is in %i7. The return address of anything | |
1683 farther back is in the register window save area at [%fp+60]. */ | |
1684 /* ??? This ignores the fact that the actual return address is +8 for normal | |
1685 returns, and +12 for structure returns. */ | |
1686 #define RETURN_ADDR_RTX(count, frame) \ | |
1687 ((count == -1) \ | |
1688 ? gen_rtx_REG (Pmode, 31) \ | |
1689 : gen_rtx_MEM (Pmode, \ | |
1690 memory_address (Pmode, plus_constant (frame, \ | |
1691 15 * UNITS_PER_WORD \ | |
1692 + SPARC_STACK_BIAS)))) | |
1693 | |
1694 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's | |
1695 +12, but always using +8 is close enough for frame unwind purposes. | |
1696 Actually, just using %o7 is close enough for unwinding, but %o7+8 | |
1697 is something you can return to. */ | |
1698 #define INCOMING_RETURN_ADDR_RTX \ | |
1699 plus_constant (gen_rtx_REG (word_mode, 15), 8) | |
1700 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15) | |
1701 | |
1702 /* The offset from the incoming value of %sp to the top of the stack frame | |
1703 for the current function. On sparc64, we have to account for the stack | |
1704 bias if present. */ | |
1705 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS | |
1706 | |
1707 /* Describe how we implement __builtin_eh_return. */ | |
1708 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) | |
1709 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */ | |
1710 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */ | |
1711 | |
1712 /* Select a format to encode pointers in exception handling data. CODE | |
1713 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
1714 true if the symbol may be affected by dynamic relocations. | |
1715 | |
1716 If assembler and linker properly support .uaword %r_disp32(foo), | |
1717 then use PC relative 32-bit relocations instead of absolute relocs | |
1718 for shared libraries. On sparc64, use pc relative 32-bit relocs even | |
1719 for binaries, to save memory. | |
1720 | |
1721 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the | |
1722 symbol %r_disp32() is against was not local, but .hidden. In that | |
1723 case, we have to use DW_EH_PE_absptr for pic personality. */ | |
1724 #ifdef HAVE_AS_SPARC_UA_PCREL | |
1725 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN | |
1726 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
1727 (flag_pic \ | |
1728 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ | |
1729 : ((TARGET_ARCH64 && ! GLOBAL) \ | |
1730 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
1731 : DW_EH_PE_absptr)) | |
1732 #else | |
1733 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
1734 (flag_pic \ | |
1735 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ | |
1736 : ((TARGET_ARCH64 && ! GLOBAL) \ | |
1737 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
1738 : DW_EH_PE_absptr)) | |
1739 #endif | |
1740 | |
1741 /* Emit a PC-relative relocation. */ | |
1742 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ | |
1743 do { \ | |
1744 fputs (integer_asm_op (SIZE, FALSE), FILE); \ | |
1745 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ | |
1746 assemble_name (FILE, LABEL); \ | |
1747 fputc (')', FILE); \ | |
1748 } while (0) | |
1749 #endif | |
1750 | |
1751 /* Addressing modes, and classification of registers for them. */ | |
1752 | |
1753 /* Macros to check register numbers against specific register classes. */ | |
1754 | |
1755 /* These assume that REGNO is a hard or pseudo reg number. | |
1756 They give nonzero only if REGNO is a hard reg of the suitable class | |
1757 or a pseudo reg currently allocated to a suitable hard reg. | |
1758 Since they use reg_renumber, they are safe only once reg_renumber | |
1759 has been allocated, which happens in local-alloc.c. */ | |
1760 | |
1761 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1762 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \ | |
1763 || (REGNO) == FRAME_POINTER_REGNUM \ | |
1764 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) | |
1765 | |
1766 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) | |
1767 | |
1768 #define REGNO_OK_FOR_FP_P(REGNO) \ | |
1769 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ | |
1770 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) | |
1771 #define REGNO_OK_FOR_CCFP_P(REGNO) \ | |
1772 (TARGET_V9 \ | |
1773 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ | |
1774 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) | |
1775 | |
1776 /* Now macros that check whether X is a register and also, | |
1777 strictly, whether it is in a specified class. | |
1778 | |
1779 These macros are specific to the SPARC, and may be used only | |
1780 in code for printing assembler insns and in conditions for | |
1781 define_optimization. */ | |
1782 | |
1783 /* 1 if X is an fp register. */ | |
1784 | |
1785 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) | |
1786 | |
1787 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */ | |
1788 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31)) | |
1789 | |
1790 /* Maximum number of registers that can appear in a valid memory address. */ | |
1791 | |
1792 #define MAX_REGS_PER_ADDRESS 2 | |
1793 | |
1794 /* Recognize any constant value that is a valid address. | |
1795 When PIC, we do not accept an address that would require a scratch reg | |
1796 to load into a register. */ | |
1797 | |
1798 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) | |
1799 | |
1800 /* Define this, so that when PIC, reload won't try to reload invalid | |
1801 addresses which require two reload registers. */ | |
1802 | |
1803 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
1804 | |
1805 /* Nonzero if the constant value X is a legitimate general operand. | |
1806 Anything can be made to work except floating point constants. | |
1807 If TARGET_VIS, 0.0 can be made to work as well. */ | |
1808 | |
1809 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) | |
1810 | |
1811 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1812 and check its validity for a certain class. | |
1813 We have two alternate definitions for each of them. | |
1814 The usual definition accepts all pseudo regs; the other rejects | |
1815 them unless they have been allocated suitable hard regs. | |
1816 The symbol REG_OK_STRICT causes the latter definition to be used. | |
1817 | |
1818 Most source files want to accept pseudo regs in the hope that | |
1819 they will get allocated to the class that the insn wants them to be in. | |
1820 Source files for reload pass need to be strict. | |
1821 After reload, it makes no difference, since pseudo regs have | |
1822 been eliminated by then. */ | |
1823 | |
1824 #ifndef REG_OK_STRICT | |
1825 | |
1826 /* Nonzero if X is a hard reg that can be used as an index | |
1827 or if it is a pseudo reg. */ | |
1828 #define REG_OK_FOR_INDEX_P(X) \ | |
1829 (REGNO (X) < 32 \ | |
1830 || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1831 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
1832 | |
1833 /* Nonzero if X is a hard reg that can be used as a base reg | |
1834 or if it is a pseudo reg. */ | |
1835 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X) | |
1836 | |
1837 #else | |
1838 | |
1839 /* Nonzero if X is a hard reg that can be used as an index. */ | |
1840 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1841 /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1842 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1843 | |
1844 #endif | |
1845 | |
1846 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ | |
1847 | |
1848 #ifdef HAVE_AS_OFFSETABLE_LO10 | |
1849 #define USE_AS_OFFSETABLE_LO10 1 | |
1850 #else | |
1851 #define USE_AS_OFFSETABLE_LO10 0 | |
1852 #endif | |
1853 | |
1854 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1855 that is a valid memory address for an instruction. | |
1856 The MODE argument is the machine mode for the MEM expression | |
1857 that wants to use this address. | |
1858 | |
1859 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT | |
1860 ordinarily. This changes a bit when generating PIC. | |
1861 | |
1862 If you change this, execute "rm explow.o recog.o reload.o". */ | |
1863 | |
1864 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode) | |
1865 | |
1866 #define RTX_OK_FOR_BASE_P(X) \ | |
1867 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
1868 || (GET_CODE (X) == SUBREG \ | |
1869 && GET_CODE (SUBREG_REG (X)) == REG \ | |
1870 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
1871 | |
1872 #define RTX_OK_FOR_INDEX_P(X) \ | |
1873 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
1874 || (GET_CODE (X) == SUBREG \ | |
1875 && GET_CODE (SUBREG_REG (X)) == REG \ | |
1876 && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
1877 | |
1878 #define RTX_OK_FOR_OFFSET_P(X) \ | |
1879 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8) | |
1880 | |
1881 #define RTX_OK_FOR_OLO10_P(X) \ | |
1882 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8) | |
1883 | |
1884 #ifdef REG_OK_STRICT | |
1885 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1886 { \ | |
1887 if (legitimate_address_p (MODE, X, 1)) \ | |
1888 goto ADDR; \ | |
1889 } | |
1890 #else | |
1891 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1892 { \ | |
1893 if (legitimate_address_p (MODE, X, 0)) \ | |
1894 goto ADDR; \ | |
1895 } | |
1896 #endif | |
1897 | |
1898 /* Go to LABEL if ADDR (a legitimate address expression) | |
1899 has an effect that depends on the machine mode it is used for. | |
1900 | |
1901 In PIC mode, | |
1902 | |
1903 (mem:HI [%l7+a]) | |
1904 | |
1905 is not equivalent to | |
1906 | |
1907 (mem:QI [%l7+a]) (mem:QI [%l7+a+1]) | |
1908 | |
1909 because [%l7+a+1] is interpreted as the address of (a+1). */ | |
1910 | |
1911 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ | |
1912 { \ | |
1913 if (flag_pic == 1) \ | |
1914 { \ | |
1915 if (GET_CODE (ADDR) == PLUS) \ | |
1916 { \ | |
1917 rtx op0 = XEXP (ADDR, 0); \ | |
1918 rtx op1 = XEXP (ADDR, 1); \ | |
1919 if (op0 == pic_offset_table_rtx \ | |
1920 && SYMBOLIC_CONST (op1)) \ | |
1921 goto LABEL; \ | |
1922 } \ | |
1923 } \ | |
1924 } | |
1925 | |
1926 /* Try machine-dependent ways of modifying an illegitimate address | |
1927 to be legitimate. If we find one, return the new, valid address. | |
1928 This macro is used in only one place: `memory_address' in explow.c. | |
1929 | |
1930 OLDX is the address as it was before break_out_memory_refs was called. | |
1931 In some cases it is useful to look at this to decide what needs to be done. | |
1932 | |
1933 MODE and WIN are passed so that this macro can use | |
1934 GO_IF_LEGITIMATE_ADDRESS. | |
1935 | |
1936 It is always safe for this macro to do nothing. It exists to recognize | |
1937 opportunities to optimize the output. */ | |
1938 | |
1939 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ | |
1940 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1941 { \ | |
1942 (X) = legitimize_address (X, OLDX, MODE); \ | |
1943 if (memory_address_p (MODE, X)) \ | |
1944 goto WIN; \ | |
1945 } | |
1946 | |
1947 /* Try a machine-dependent way of reloading an illegitimate address | |
1948 operand. If we find one, push the reload and jump to WIN. This | |
1949 macro is used in only one place: `find_reloads_address' in reload.c. | |
1950 | |
1951 For SPARC 32, we wish to handle addresses by splitting them into | |
1952 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. | |
1953 This cuts the number of extra insns by one. | |
1954 | |
1955 Do nothing when generating PIC code and the address is a | |
1956 symbolic operand or requires a scratch register. */ | |
1957 | |
1958 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
1959 do { \ | |
1960 /* Decompose SImode constants into hi+lo_sum. We do have to \ | |
1961 rerecognize what we produce, so be careful. */ \ | |
1962 if (CONSTANT_P (X) \ | |
1963 && (MODE != TFmode || TARGET_ARCH64) \ | |
1964 && GET_MODE (X) == SImode \ | |
1965 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \ | |
1966 && ! (flag_pic \ | |
1967 && (symbolic_operand (X, Pmode) \ | |
1968 || pic_address_needs_scratch (X))) \ | |
1969 && sparc_cmodel <= CM_MEDLOW) \ | |
1970 { \ | |
1971 X = gen_rtx_LO_SUM (GET_MODE (X), \ | |
1972 gen_rtx_HIGH (GET_MODE (X), X), X); \ | |
1973 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ | |
1974 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ | |
1975 OPNUM, TYPE); \ | |
1976 goto WIN; \ | |
1977 } \ | |
1978 /* ??? 64-bit reloads. */ \ | |
1979 } while (0) | |
1980 | |
1981 /* Specify the machine mode that this machine uses | |
1982 for the index in the tablejump instruction. */ | |
1983 /* If we ever implement any of the full models (such as CM_FULLANY), | |
1984 this has to be DImode in that case */ | |
1985 #ifdef HAVE_GAS_SUBSECTION_ORDERING | |
1986 #define CASE_VECTOR_MODE \ | |
1987 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
1988 #else | |
1989 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise | |
1990 we have to sign extend which slows things down. */ | |
1991 #define CASE_VECTOR_MODE \ | |
1992 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
1993 #endif | |
1994 | |
1995 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1996 #define DEFAULT_SIGNED_CHAR 1 | |
1997 | |
1998 /* Max number of bytes we can move from memory to memory | |
1999 in one reasonably fast instruction. */ | |
2000 #define MOVE_MAX 8 | |
2001 | |
2002 /* If a memory-to-memory move would take MOVE_RATIO or more simple | |
2003 move-instruction pairs, we will do a movmem or libcall instead. */ | |
2004 | |
2005 #define MOVE_RATIO(speed) ((speed) ? 8 : 3) | |
2006 | |
2007 /* Define if operations between registers always perform the operation | |
2008 on the full register even if a narrower mode is specified. */ | |
2009 #define WORD_REGISTER_OPERATIONS | |
2010 | |
2011 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2012 will either zero-extend or sign-extend. The value of this macro should | |
2013 be the code that says which one of the two operations is implicitly | |
2014 done, UNKNOWN if none. */ | |
2015 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
2016 | |
2017 /* Nonzero if access to memory by bytes is slow and undesirable. | |
2018 For RISC chips, it means that access to memory by bytes is no | |
2019 better than access by words when possible, so grab a whole word | |
2020 and maybe make use of that. */ | |
2021 #define SLOW_BYTE_ACCESS 1 | |
2022 | |
2023 /* Define this to be nonzero if shift instructions ignore all but the low-order | |
2024 few bits. */ | |
2025 #define SHIFT_COUNT_TRUNCATED 1 | |
2026 | |
2027 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
2028 is done just by pretending it is already truncated. */ | |
2029 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2030 | |
2031 /* Specify the machine mode used for addresses. */ | |
2032 #define Pmode (TARGET_ARCH64 ? DImode : SImode) | |
2033 | |
2034 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
2035 return the mode to be used for the comparison. For floating-point, | |
2036 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand | |
2037 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special | |
2038 processing is needed. */ | |
2039 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) | |
2040 | |
2041 /* Return nonzero if MODE implies a floating point inequality can be | |
2042 reversed. For SPARC this is always true because we have a full | |
2043 compliment of ordered and unordered comparisons, but until generic | |
2044 code knows how to reverse it correctly we keep the old definition. */ | |
2045 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) | |
2046 | |
2047 /* A function address in a call instruction for indexing purposes. */ | |
2048 #define FUNCTION_MODE Pmode | |
2049 | |
2050 /* Define this if addresses of constant functions | |
2051 shouldn't be put through pseudo regs where they can be cse'd. | |
2052 Desirable on machines where ordinary constants are expensive | |
2053 but a CALL with constant address is cheap. */ | |
2054 #define NO_FUNCTION_CSE | |
2055 | |
2056 /* alloca should avoid clobbering the old register save area. */ | |
2057 #define SETJMP_VIA_SAVE_AREA | |
2058 | |
2059 /* The _Q_* comparison libcalls return booleans. */ | |
2060 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) | |
2061 | |
2062 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such | |
2063 that the inputs are fully consumed before the output memory is clobbered. */ | |
2064 | |
2065 #define TARGET_BUGGY_QP_LIB 0 | |
2066 | |
2067 /* Assume by default that we do not have the Solaris-specific conversion | |
2068 routines nor 64-bit integer multiply and divide routines. */ | |
2069 | |
2070 #define SUN_CONVERSION_LIBFUNCS 0 | |
2071 #define DITF_CONVERSION_LIBFUNCS 0 | |
2072 #define SUN_INTEGER_MULTIPLY_64 0 | |
2073 | |
2074 /* Compute extra cost of moving data between one register class | |
2075 and another. */ | |
2076 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS) | |
2077 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ | |
2078 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \ | |
2079 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \ | |
2080 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ | |
2081 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \ | |
2082 || sparc_cpu == PROCESSOR_ULTRASPARC3 \ | |
2083 || sparc_cpu == PROCESSOR_NIAGARA \ | |
2084 || sparc_cpu == PROCESSOR_NIAGARA2) ? 12 : 6) : 2) | |
2085 | |
2086 /* Provide the cost of a branch. For pre-v9 processors we use | |
2087 a value of 3 to take into account the potential annulling of | |
2088 the delay slot (which ends up being a bubble in the pipeline slot) | |
2089 plus a cycle to take into consideration the instruction cache | |
2090 effects. | |
2091 | |
2092 On v9 and later, which have branch prediction facilities, we set | |
2093 it to the depth of the pipeline as that is the cost of a | |
2094 mispredicted branch. | |
2095 | |
2096 On Niagara, normal branches insert 3 bubbles into the pipe | |
2097 and annulled branches insert 4 bubbles. | |
2098 | |
2099 On Niagara-2, a not-taken branch costs 1 cycle whereas a taken | |
2100 branch costs 6 cycles. */ | |
2101 | |
2102 #define BRANCH_COST(speed_p, predictable_p) \ | |
2103 ((sparc_cpu == PROCESSOR_V9 \ | |
2104 || sparc_cpu == PROCESSOR_ULTRASPARC) \ | |
2105 ? 7 \ | |
2106 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ | |
2107 ? 9 \ | |
2108 : (sparc_cpu == PROCESSOR_NIAGARA \ | |
2109 ? 4 \ | |
2110 : (sparc_cpu == PROCESSOR_NIAGARA2 \ | |
2111 ? 5 \ | |
2112 : 3)))) | |
2113 | |
2114 /* Control the assembler format that we output. */ | |
2115 | |
2116 /* A C string constant describing how to begin a comment in the target | |
2117 assembler language. The compiler assumes that the comment will end at | |
2118 the end of the line. */ | |
2119 | |
2120 #define ASM_COMMENT_START "!" | |
2121 | |
2122 /* Output to assembler file text saying following lines | |
2123 may contain character constants, extra white space, comments, etc. */ | |
2124 | |
2125 #define ASM_APP_ON "" | |
2126 | |
2127 /* Output to assembler file text saying following lines | |
2128 no longer contain unusual constructs. */ | |
2129 | |
2130 #define ASM_APP_OFF "" | |
2131 | |
2132 /* How to refer to registers in assembler output. | |
2133 This sequence is indexed by compiler's hard-register-number (see above). */ | |
2134 | |
2135 #define REGISTER_NAMES \ | |
2136 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ | |
2137 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ | |
2138 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ | |
2139 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ | |
2140 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ | |
2141 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ | |
2142 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ | |
2143 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ | |
2144 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ | |
2145 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ | |
2146 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ | |
2147 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ | |
2148 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" } | |
2149 | |
2150 /* Define additional names for use in asm clobbers and asm declarations. */ | |
2151 | |
2152 #define ADDITIONAL_REGISTER_NAMES \ | |
2153 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} | |
2154 | |
2155 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length | |
2156 can run past this up to a continuation point. Once we used 1500, but | |
2157 a single entry in C++ can run more than 500 bytes, due to the length of | |
2158 mangled symbol names. dbxout.c should really be fixed to do | |
2159 continuations when they are actually needed instead of trying to | |
2160 guess... */ | |
2161 #define DBX_CONTIN_LENGTH 1000 | |
2162 | |
2163 /* This is how to output a command to make the user-level label named NAME | |
2164 defined for reference from other files. */ | |
2165 | |
2166 /* Globalizing directive for a label. */ | |
2167 #define GLOBAL_ASM_OP "\t.global " | |
2168 | |
2169 /* The prefix to add to user-visible assembler symbols. */ | |
2170 | |
2171 #define USER_LABEL_PREFIX "_" | |
2172 | |
2173 /* This is how to store into the string LABEL | |
2174 the symbol_ref name of an internal numbered label where | |
2175 PREFIX is the class of label and NUM is the number within the class. | |
2176 This is suitable for output with `assemble_name'. */ | |
2177 | |
2178 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
2179 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) | |
2180 | |
2181 /* This is how we hook in and defer the case-vector until the end of | |
2182 the function. */ | |
2183 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ | |
2184 sparc_defer_case_vector ((LAB),(VEC), 0) | |
2185 | |
2186 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ | |
2187 sparc_defer_case_vector ((LAB),(VEC), 1) | |
2188 | |
2189 /* This is how to output an element of a case-vector that is absolute. */ | |
2190 | |
2191 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
2192 do { \ | |
2193 char label[30]; \ | |
2194 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
2195 if (CASE_VECTOR_MODE == SImode) \ | |
2196 fprintf (FILE, "\t.word\t"); \ | |
2197 else \ | |
2198 fprintf (FILE, "\t.xword\t"); \ | |
2199 assemble_name (FILE, label); \ | |
2200 fputc ('\n', FILE); \ | |
2201 } while (0) | |
2202 | |
2203 /* This is how to output an element of a case-vector that is relative. | |
2204 (SPARC uses such vectors only when generating PIC.) */ | |
2205 | |
2206 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
2207 do { \ | |
2208 char label[30]; \ | |
2209 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ | |
2210 if (CASE_VECTOR_MODE == SImode) \ | |
2211 fprintf (FILE, "\t.word\t"); \ | |
2212 else \ | |
2213 fprintf (FILE, "\t.xword\t"); \ | |
2214 assemble_name (FILE, label); \ | |
2215 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ | |
2216 fputc ('-', FILE); \ | |
2217 assemble_name (FILE, label); \ | |
2218 fputc ('\n', FILE); \ | |
2219 } while (0) | |
2220 | |
2221 /* This is what to output before and after case-vector (both | |
2222 relative and absolute). If .subsection -1 works, we put case-vectors | |
2223 at the beginning of the current section. */ | |
2224 | |
2225 #ifdef HAVE_GAS_SUBSECTION_ORDERING | |
2226 | |
2227 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ | |
2228 fprintf(FILE, "\t.subsection\t-1\n") | |
2229 | |
2230 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ | |
2231 fprintf(FILE, "\t.previous\n") | |
2232 | |
2233 #endif | |
2234 | |
2235 /* This is how to output an assembler line | |
2236 that says to advance the location counter | |
2237 to a multiple of 2**LOG bytes. */ | |
2238 | |
2239 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2240 if ((LOG) != 0) \ | |
2241 fprintf (FILE, "\t.align %d\n", (1<<(LOG))) | |
2242 | |
2243 /* This is how to output an assembler line that says to advance | |
2244 the location counter to a multiple of 2**LOG bytes using the | |
2245 "nop" instruction as padding. */ | |
2246 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \ | |
2247 if ((LOG) != 0) \ | |
2248 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG))) | |
2249 | |
2250 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
2251 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) | |
2252 | |
2253 /* This says how to output an assembler line | |
2254 to define a global common symbol. */ | |
2255 | |
2256 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
2257 ( fputs ("\t.common ", (FILE)), \ | |
2258 assemble_name ((FILE), (NAME)), \ | |
2259 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) | |
2260 | |
2261 /* This says how to output an assembler line to define a local common | |
2262 symbol. */ | |
2263 | |
2264 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ | |
2265 ( fputs ("\t.reserve ", (FILE)), \ | |
2266 assemble_name ((FILE), (NAME)), \ | |
2267 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ | |
2268 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) | |
2269 | |
2270 /* A C statement (sans semicolon) to output to the stdio stream | |
2271 FILE the assembler definition of uninitialized global DECL named | |
2272 NAME whose size is SIZE bytes and alignment is ALIGN bytes. | |
2273 Try to use asm_output_aligned_bss to implement this macro. */ | |
2274 | |
2275 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
2276 do { \ | |
2277 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ | |
2278 } while (0) | |
2279 | |
2280 #define IDENT_ASM_OP "\t.ident\t" | |
2281 | |
2282 /* Output #ident as a .ident. */ | |
2283 | |
2284 #define ASM_OUTPUT_IDENT(FILE, NAME) \ | |
2285 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME); | |
2286 | |
2287 /* Prettify the assembly. */ | |
2288 | |
2289 extern int sparc_indent_opcode; | |
2290 | |
2291 #define ASM_OUTPUT_OPCODE(FILE, PTR) \ | |
2292 do { \ | |
2293 if (sparc_indent_opcode) \ | |
2294 { \ | |
2295 putc (' ', FILE); \ | |
2296 sparc_indent_opcode = 0; \ | |
2297 } \ | |
2298 } while (0) | |
2299 | |
2300 #define SPARC_SYMBOL_REF_TLS_P(RTX) \ | |
2301 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
2302 | |
2303 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
2304 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \ | |
2305 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&') | |
2306 | |
2307 /* Print operand X (an rtx) in assembler syntax to file FILE. | |
2308 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2309 For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2310 | |
2311 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2312 | |
2313 /* Print a memory address as an operand to reference that memory location. */ | |
2314 | |
2315 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
2316 { register rtx base, index = 0; \ | |
2317 int offset = 0; \ | |
2318 register rtx addr = ADDR; \ | |
2319 if (GET_CODE (addr) == REG) \ | |
2320 fputs (reg_names[REGNO (addr)], FILE); \ | |
2321 else if (GET_CODE (addr) == PLUS) \ | |
2322 { \ | |
2323 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ | |
2324 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ | |
2325 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ | |
2326 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ | |
2327 else \ | |
2328 base = XEXP (addr, 0), index = XEXP (addr, 1); \ | |
2329 if (GET_CODE (base) == LO_SUM) \ | |
2330 { \ | |
2331 gcc_assert (USE_AS_OFFSETABLE_LO10 \ | |
2332 && TARGET_ARCH64 \ | |
2333 && ! TARGET_CM_MEDMID); \ | |
2334 output_operand (XEXP (base, 0), 0); \ | |
2335 fputs ("+%lo(", FILE); \ | |
2336 output_address (XEXP (base, 1)); \ | |
2337 fprintf (FILE, ")+%d", offset); \ | |
2338 } \ | |
2339 else \ | |
2340 { \ | |
2341 fputs (reg_names[REGNO (base)], FILE); \ | |
2342 if (index == 0) \ | |
2343 fprintf (FILE, "%+d", offset); \ | |
2344 else if (GET_CODE (index) == REG) \ | |
2345 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ | |
2346 else if (GET_CODE (index) == SYMBOL_REF \ | |
2347 || GET_CODE (index) == LABEL_REF \ | |
2348 || GET_CODE (index) == CONST) \ | |
2349 fputc ('+', FILE), output_addr_const (FILE, index); \ | |
2350 else gcc_unreachable (); \ | |
2351 } \ | |
2352 } \ | |
2353 else if (GET_CODE (addr) == MINUS \ | |
2354 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ | |
2355 { \ | |
2356 output_addr_const (FILE, XEXP (addr, 0)); \ | |
2357 fputs ("-(", FILE); \ | |
2358 output_addr_const (FILE, XEXP (addr, 1)); \ | |
2359 fputs ("-.)", FILE); \ | |
2360 } \ | |
2361 else if (GET_CODE (addr) == LO_SUM) \ | |
2362 { \ | |
2363 output_operand (XEXP (addr, 0), 0); \ | |
2364 if (TARGET_CM_MEDMID) \ | |
2365 fputs ("+%l44(", FILE); \ | |
2366 else \ | |
2367 fputs ("+%lo(", FILE); \ | |
2368 output_address (XEXP (addr, 1)); \ | |
2369 fputc (')', FILE); \ | |
2370 } \ | |
2371 else if (flag_pic && GET_CODE (addr) == CONST \ | |
2372 && GET_CODE (XEXP (addr, 0)) == MINUS \ | |
2373 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ | |
2374 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ | |
2375 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ | |
2376 { \ | |
2377 addr = XEXP (addr, 0); \ | |
2378 output_addr_const (FILE, XEXP (addr, 0)); \ | |
2379 /* Group the args of the second CONST in parenthesis. */ \ | |
2380 fputs ("-(", FILE); \ | |
2381 /* Skip past the second CONST--it does nothing for us. */\ | |
2382 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ | |
2383 /* Close the parenthesis. */ \ | |
2384 fputc (')', FILE); \ | |
2385 } \ | |
2386 else \ | |
2387 { \ | |
2388 output_addr_const (FILE, addr); \ | |
2389 } \ | |
2390 } | |
2391 | |
2392 /* TLS support defaulting to original Sun flavor. GNU extensions | |
2393 must be activated in separate configuration files. */ | |
2394 #ifdef HAVE_AS_TLS | |
2395 #define TARGET_TLS 1 | |
2396 #else | |
2397 #define TARGET_TLS 0 | |
2398 #endif | |
2399 | |
2400 #define TARGET_SUN_TLS TARGET_TLS | |
2401 #define TARGET_GNU_TLS 0 | |
2402 | |
2403 /* The number of Pmode words for the setjmp buffer. */ | |
2404 #define JMP_BUF_SIZE 12 | |
2405 | |
2406 /* We use gcc _mcount for profiling. */ | |
2407 #define NO_PROFILE_COUNTERS 0 |