Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/sparc/supersparc.md @ 0:a06113de4d67
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| author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 17 Jul 2009 14:47:48 +0900 |
| parents | |
| children | 04ced10e8804 |
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| -1:000000000000 | 0:a06113de4d67 |
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| 1 ;; Scheduling description for SuperSPARC. | |
| 2 ;; Copyright (C) 2002, 2007 Free Software Foundation, Inc. | |
| 3 ;; | |
| 4 ;; This file is part of GCC. | |
| 5 ;; | |
| 6 ;; GCC is free software; you can redistribute it and/or modify | |
| 7 ;; it under the terms of the GNU General Public License as published by | |
| 8 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 9 ;; any later version. | |
| 10 ;; | |
| 11 ;; GCC is distributed in the hope that it will be useful, | |
| 12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 ;; GNU General Public License for more details. | |
| 15 ;; | |
| 16 ;; You should have received a copy of the GNU General Public License | |
| 17 ;; along with GCC; see the file COPYING3. If not see | |
| 18 ;; <http://www.gnu.org/licenses/>. | |
| 19 | |
| 20 ;; The SuperSPARC is a tri-issue, which was considered quite parallel | |
| 21 ;; at the time it was released. Much like UltraSPARC-I and UltraSPARC-II | |
| 22 ;; there are two integer units but only one of them may take shifts. | |
| 23 ;; | |
| 24 ;; ??? If SuperSPARC has the same slotting rules as ultrasparc for these | |
| 25 ;; ??? shifts, we should model that. | |
| 26 | |
| 27 (define_automaton "supersparc_0,supersparc_1") | |
| 28 | |
| 29 (define_cpu_unit "ss_memory, ss_shift, ss_iwport0, ss_iwport1" "supersparc_0") | |
| 30 (define_cpu_unit "ss_fpalu" "supersparc_0") | |
| 31 (define_cpu_unit "ss_fpmds" "supersparc_1") | |
| 32 | |
| 33 (define_reservation "ss_iwport" "(ss_iwport0 | ss_iwport1)") | |
| 34 | |
| 35 (define_insn_reservation "ss_iuload" 1 | |
| 36 (and (eq_attr "cpu" "supersparc") | |
| 37 (eq_attr "type" "load,sload")) | |
| 38 "ss_memory") | |
| 39 | |
| 40 ;; Ok, fpu loads deliver the result in zero cycles. But we | |
| 41 ;; have to show the ss_memory reservation somehow, thus... | |
| 42 (define_insn_reservation "ss_fpload" 0 | |
| 43 (and (eq_attr "cpu" "supersparc") | |
| 44 (eq_attr "type" "fpload")) | |
| 45 "ss_memory") | |
| 46 | |
| 47 (define_bypass 0 "ss_fpload" "ss_fp_alu,ss_fp_mult,ss_fp_divs,ss_fp_divd,ss_fp_sqrt") | |
| 48 | |
| 49 (define_insn_reservation "ss_store" 1 | |
| 50 (and (eq_attr "cpu" "supersparc") | |
| 51 (eq_attr "type" "store,fpstore")) | |
| 52 "ss_memory") | |
| 53 | |
| 54 (define_insn_reservation "ss_ialu_shift" 1 | |
| 55 (and (eq_attr "cpu" "supersparc") | |
| 56 (eq_attr "type" "shift")) | |
| 57 "ss_shift + ss_iwport") | |
| 58 | |
| 59 (define_insn_reservation "ss_ialu_any" 1 | |
| 60 (and (eq_attr "cpu" "supersparc") | |
| 61 (eq_attr "type" "load,sload,store,shift,ialu")) | |
| 62 "ss_iwport") | |
| 63 | |
| 64 (define_insn_reservation "ss_fp_alu" 3 | |
| 65 (and (eq_attr "cpu" "supersparc") | |
| 66 (eq_attr "type" "fp,fpmove,fpcmp")) | |
| 67 "ss_fpalu, nothing*2") | |
| 68 | |
| 69 (define_insn_reservation "ss_fp_mult" 3 | |
| 70 (and (eq_attr "cpu" "supersparc") | |
| 71 (eq_attr "type" "fpmul")) | |
| 72 "ss_fpmds, nothing*2") | |
| 73 | |
| 74 (define_insn_reservation "ss_fp_divs" 6 | |
| 75 (and (eq_attr "cpu" "supersparc") | |
| 76 (eq_attr "type" "fpdivs")) | |
| 77 "ss_fpmds*4, nothing*2") | |
| 78 | |
| 79 (define_insn_reservation "ss_fp_divd" 9 | |
| 80 (and (eq_attr "cpu" "supersparc") | |
| 81 (eq_attr "type" "fpdivd")) | |
| 82 "ss_fpmds*7, nothing*2") | |
| 83 | |
| 84 (define_insn_reservation "ss_fp_sqrt" 12 | |
| 85 (and (eq_attr "cpu" "supersparc") | |
| 86 (eq_attr "type" "fpsqrts,fpsqrtd")) | |
| 87 "ss_fpmds*10, nothing*2") | |
| 88 | |
| 89 (define_insn_reservation "ss_imul" 4 | |
| 90 (and (eq_attr "cpu" "supersparc") | |
| 91 (eq_attr "type" "imul")) | |
| 92 "ss_fpmds*4") |