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comparison gcc/config/arm/arm.md @ 63:b7f97abdc517 gcc-4.6-20100522

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update gcc from gcc-4.5.0 to gcc-4.6
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Mon, 24 May 2010 12:47:05 +0900
parents 77e2b8dfacca
children f6334be47118
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56:3c8a44c06a95 63:b7f97abdc517
1 ;;- Machine description for ARM for GNU compiler 1 ;;- Machine description for ARM for GNU compiler
2 ;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000, 2 ;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 3 ;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 ;; Free Software Foundation, Inc. 4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 5 ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 ;; and Martin Simmons (@harleqn.co.uk). 6 ;; and Martin Simmons (@harleqn.co.uk).
7 ;; More major hacks by Richard Earnshaw (rearnsha@arm.com). 7 ;; More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 8
99 ; correctly for PIC usage. 99 ; correctly for PIC usage.
100 (UNSPEC_GOTSYM_OFF 24) ; The offset of the start of the the GOT from a 100 (UNSPEC_GOTSYM_OFF 24) ; The offset of the start of the the GOT from a
101 ; a given symbolic address. 101 ; a given symbolic address.
102 (UNSPEC_THUMB1_CASESI 25) ; A Thumb1 compressed dispatch-table call. 102 (UNSPEC_THUMB1_CASESI 25) ; A Thumb1 compressed dispatch-table call.
103 (UNSPEC_RBIT 26) ; rbit operation. 103 (UNSPEC_RBIT 26) ; rbit operation.
104 (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from
105 ; another symbolic address.
104 ] 106 ]
105 ) 107 )
106 108
107 ;; UNSPEC_VOLATILE Usage: 109 ;; UNSPEC_VOLATILE Usage:
108 110
143 145
144 ; IS_THUMB is set to 'yes' when we are generating Thumb code, and 'no' when 146 ; IS_THUMB is set to 'yes' when we are generating Thumb code, and 'no' when
145 ; generating ARM code. This is used to control the length of some insn 147 ; generating ARM code. This is used to control the length of some insn
146 ; patterns that share the same RTL in both ARM and Thumb code. 148 ; patterns that share the same RTL in both ARM and Thumb code.
147 (define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code"))) 149 (define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code")))
148
149 ; IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects
150 ; scheduling decisions for the load unit and the multiplier.
151 (define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_tune_strongarm")))
152
153 ; IS_XSCALE is set to 'yes' when compiling for XScale.
154 (define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale")))
155 150
156 ;; Operand number of an input operand that is shifted. Zero if the 151 ;; Operand number of an input operand that is shifted. Zero if the
157 ;; given instruction does not shift one of its input operands. 152 ;; given instruction does not shift one of its input operands.
158 (define_attr "shift" "" (const_int 0)) 153 (define_attr "shift" "" (const_int 0))
159 154
1263 [(set (match_operand:SI 0 "register_operand" "=l,l,l") 1258 [(set (match_operand:SI 0 "register_operand" "=l,l,l")
1264 (mult:SI (match_operand:SI 1 "register_operand" "0,l,0") 1259 (mult:SI (match_operand:SI 1 "register_operand" "0,l,0")
1265 (match_operand:SI 2 "register_operand" "l,0,0")))] 1260 (match_operand:SI 2 "register_operand" "l,0,0")))]
1266 "TARGET_THUMB1 && arm_arch6" 1261 "TARGET_THUMB1 && arm_arch6"
1267 "@ 1262 "@
1268 mul\\t%0, %2 1263 mul\\t%0, %2
1269 mul\\t%0, %1 1264 mul\\t%0, %1
1270 mul\\t%0, %1" 1265 mul\\t%0, %1"
1271 [(set_attr "length" "2") 1266 [(set_attr "length" "2")
1272 (set_attr "insn" "mul")] 1267 (set_attr "insn" "mul")]
1273 ) 1268 )
1274 1269
3536 3531
3537 ;; Unary arithmetic insns 3532 ;; Unary arithmetic insns
3538 3533
3539 (define_expand "negdi2" 3534 (define_expand "negdi2"
3540 [(parallel 3535 [(parallel
3541 [(set (match_operand:DI 0 "s_register_operand" "") 3536 [(set (match_operand:DI 0 "s_register_operand" "")
3542 (neg:DI (match_operand:DI 1 "s_register_operand" ""))) 3537 (neg:DI (match_operand:DI 1 "s_register_operand" "")))
3543 (clobber (reg:CC CC_REGNUM))])] 3538 (clobber (reg:CC CC_REGNUM))])]
3544 "TARGET_EITHER" 3539 "TARGET_EITHER"
3545 " 3540 ""
3546 if (TARGET_THUMB1)
3547 {
3548 if (GET_CODE (operands[1]) != REG)
3549 operands[1] = force_reg (DImode, operands[1]);
3550 }
3551 "
3552 ) 3541 )
3553 3542
3554 ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). 3543 ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
3555 ;; The first alternative allows the common case of a *full* overlap. 3544 ;; The first alternative allows the common case of a *full* overlap.
3556 (define_insn "*arm_negdi2" 3545 (define_insn "*arm_negdi2"
3562 [(set_attr "conds" "clob") 3551 [(set_attr "conds" "clob")
3563 (set_attr "length" "8")] 3552 (set_attr "length" "8")]
3564 ) 3553 )
3565 3554
3566 (define_insn "*thumb1_negdi2" 3555 (define_insn "*thumb1_negdi2"
3567 [(set (match_operand:DI 0 "register_operand" "=&l") 3556 [(set (match_operand:DI 0 "register_operand" "=&l")
3568 (neg:DI (match_operand:DI 1 "register_operand" "l"))) 3557 (neg:DI (match_operand:DI 1 "register_operand" "l")))
3569 (clobber (reg:CC CC_REGNUM))] 3558 (clobber (reg:CC CC_REGNUM))]
3570 "TARGET_THUMB1" 3559 "TARGET_THUMB1"
3571 "mov\\t%R0, #0\;neg\\t%Q0, %Q1\;sbc\\t%R0, %R1" 3560 "mov\\t%R0, #0\;neg\\t%Q0, %Q1\;sbc\\t%R0, %R1"
3572 [(set_attr "length" "6")] 3561 [(set_attr "length" "6")]
3573 ) 3562 )
5240 5229
5241 ;; The rather odd constraints on the following are to force reload to leave 5230 ;; The rather odd constraints on the following are to force reload to leave
5242 ;; the insn alone, and to force the minipool generation pass to then move 5231 ;; the insn alone, and to force the minipool generation pass to then move
5243 ;; the GOT symbol to memory. 5232 ;; the GOT symbol to memory.
5244 5233
5245 (define_insn "pic_load_addr_arm" 5234 (define_insn "pic_load_addr_32bit"
5246 [(set (match_operand:SI 0 "s_register_operand" "=r") 5235 [(set (match_operand:SI 0 "s_register_operand" "=r")
5247 (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))] 5236 (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
5248 "TARGET_ARM && flag_pic" 5237 "TARGET_32BIT && flag_pic"
5249 "ldr%?\\t%0, %1" 5238 "ldr%?\\t%0, %1"
5250 [(set_attr "type" "load1") 5239 [(set_attr "type" "load1")
5251 (set (attr "pool_range") (const_int 4096)) 5240 (set_attr "pool_range" "4096")
5252 (set (attr "neg_pool_range") (const_int 4084))] 5241 (set (attr "neg_pool_range")
5242 (if_then_else (eq_attr "is_thumb" "no")
5243 (const_int 4084)
5244 (const_int 0)))]
5253 ) 5245 )
5254 5246
5255 (define_insn "pic_load_addr_thumb1" 5247 (define_insn "pic_load_addr_thumb1"
5256 [(set (match_operand:SI 0 "s_register_operand" "=l") 5248 [(set (match_operand:SI 0 "s_register_operand" "=l")
5257 (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))] 5249 (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
5265 [(set (match_operand:SI 0 "register_operand" "=r") 5257 [(set (match_operand:SI 0 "register_operand" "=r")
5266 (unspec:SI [(match_operand:SI 1 "register_operand" "0") 5258 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
5267 (const_int 4) 5259 (const_int 4)
5268 (match_operand 2 "" "")] 5260 (match_operand 2 "" "")]
5269 UNSPEC_PIC_BASE))] 5261 UNSPEC_PIC_BASE))]
5270 "TARGET_THUMB1" 5262 "TARGET_THUMB"
5271 "* 5263 "*
5272 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\", 5264 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
5273 INTVAL (operands[2])); 5265 INTVAL (operands[2]));
5274 return \"add\\t%0, %|pc\"; 5266 return \"add\\t%0, %|pc\";
5275 " 5267 "
6661 } 6653 }
6662 if (!thumb1_cmp_operand (operands[2], SImode)) 6654 if (!thumb1_cmp_operand (operands[2], SImode))
6663 operands[2] = force_reg (SImode, operands[2]); 6655 operands[2] = force_reg (SImode, operands[2]);
6664 ") 6656 ")
6665 6657
6658 ;; A pattern to recognize a special situation and optimize for it.
6659 ;; On the thumb, zero-extension from memory is preferrable to sign-extension
6660 ;; due to the available addressing modes. Hence, convert a signed comparison
6661 ;; with zero into an unsigned comparison with 127 if possible.
6662 (define_expand "cbranchqi4"
6663 [(set (pc) (if_then_else
6664 (match_operator 0 "lt_ge_comparison_operator"
6665 [(match_operand:QI 1 "memory_operand" "")
6666 (match_operand:QI 2 "const0_operand" "")])
6667 (label_ref (match_operand 3 "" ""))
6668 (pc)))]
6669 "TARGET_THUMB1"
6670 {
6671 rtx xops[3];
6672 xops[1] = gen_reg_rtx (SImode);
6673 emit_insn (gen_zero_extendqisi2 (xops[1], operands[1]));
6674 xops[2] = GEN_INT (127);
6675 xops[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]) == GE ? LEU : GTU,
6676 VOIDmode, xops[1], xops[2]);
6677 xops[3] = operands[3];
6678 emit_insn (gen_cbranchsi4 (xops[0], xops[1], xops[2], xops[3]));
6679 DONE;
6680 })
6681
6666 (define_expand "cbranchsf4" 6682 (define_expand "cbranchsf4"
6667 [(set (pc) (if_then_else 6683 [(set (pc) (if_then_else
6668 (match_operator 0 "arm_comparison_operator" 6684 (match_operator 0 "arm_comparison_operator"
6669 [(match_operand:SF 1 "s_register_operand" "") 6685 [(match_operand:SF 1 "s_register_operand" "")
6670 (match_operand:SF 2 "arm_float_compare_operand" "")]) 6686 (match_operand:SF 2 "arm_float_compare_operand" "")])
6698 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" 6714 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
6699 "emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2], 6715 "emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
6700 operands[3])); DONE;" 6716 operands[3])); DONE;"
6701 ) 6717 )
6702 6718
6703 (define_insn "*cbranchsi4_insn" 6719 (define_insn "cbranchsi4_insn"
6704 [(set (pc) (if_then_else 6720 [(set (pc) (if_then_else
6705 (match_operator 0 "arm_comparison_operator" 6721 (match_operator 0 "arm_comparison_operator"
6706 [(match_operand:SI 1 "s_register_operand" "l,*h") 6722 [(match_operand:SI 1 "s_register_operand" "l,*h")
6707 (match_operand:SI 2 "thumb1_cmp_operand" "lI*h,*r")]) 6723 (match_operand:SI 2 "thumb1_cmp_operand" "lI*h,*r")])
6708 (label_ref (match_operand 3 "" "")) 6724 (label_ref (match_operand 3 "" ""))
6709 (pc)))] 6725 (pc)))]
6710 "TARGET_THUMB1" 6726 "TARGET_THUMB1"
6711 "* 6727 "*
6712 output_asm_insn (\"cmp\\t%1, %2\", operands); 6728 rtx t = prev_nonnote_insn (insn);
6729 if (t != NULL_RTX
6730 && INSN_P (t)
6731 && INSN_CODE (t) == CODE_FOR_cbranchsi4_insn)
6732 {
6733 t = XEXP (SET_SRC (PATTERN (t)), 0);
6734 if (!rtx_equal_p (XEXP (t, 0), operands[1])
6735 || !rtx_equal_p (XEXP (t, 1), operands[2]))
6736 t = NULL_RTX;
6737 }
6738 else
6739 t = NULL_RTX;
6740 if (t == NULL_RTX)
6741 output_asm_insn (\"cmp\\t%1, %2\", operands);
6713 6742
6714 switch (get_attr_length (insn)) 6743 switch (get_attr_length (insn))
6715 { 6744 {
6716 case 4: return \"b%d0\\t%l3\"; 6745 case 4: return \"b%d0\\t%l3\";
6717 case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; 6746 case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\";
7523 (define_insn "*addsi3_cbranch" 7552 (define_insn "*addsi3_cbranch"
7524 [(set (pc) 7553 [(set (pc)
7525 (if_then_else 7554 (if_then_else
7526 (match_operator 4 "arm_comparison_operator" 7555 (match_operator 4 "arm_comparison_operator"
7527 [(plus:SI 7556 [(plus:SI
7528 (match_operand:SI 2 "s_register_operand" "%l,0,*0,1,1,1") 7557 (match_operand:SI 2 "s_register_operand" "%l,0,*l,1,1,1")
7529 (match_operand:SI 3 "reg_or_int_operand" "lL,IJ,*r,lIJ,lIJ,lIJ")) 7558 (match_operand:SI 3 "reg_or_int_operand" "lL,IJ,*l,lIJ,lIJ,lIJ"))
7530 (const_int 0)]) 7559 (const_int 0)])
7531 (label_ref (match_operand 5 "" "")) 7560 (label_ref (match_operand 5 "" ""))
7532 (pc))) 7561 (pc)))
7533 (set 7562 (set
7534 (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,*?h,*?m,*?m") 7563 (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,*?h,*?m,*?m")
7535 (plus:SI (match_dup 2) (match_dup 3))) 7564 (plus:SI (match_dup 2) (match_dup 3)))
7536 (clobber (match_scratch:SI 1 "=X,X,X,l,&l,&l"))] 7565 (clobber (match_scratch:SI 1 "=X,X,l,l,&l,&l"))]
7537 "TARGET_THUMB1 7566 "TARGET_THUMB1
7538 && (GET_CODE (operands[4]) == EQ 7567 && (GET_CODE (operands[4]) == EQ
7539 || GET_CODE (operands[4]) == NE 7568 || GET_CODE (operands[4]) == NE
7540 || GET_CODE (operands[4]) == GE 7569 || GET_CODE (operands[4]) == GE
7541 || GET_CODE (operands[4]) == LT)" 7570 || GET_CODE (operands[4]) == LT)"
7542 "* 7571 "*
7543 { 7572 {
7544 rtx cond[3]; 7573 rtx cond[3];
7545 7574
7546 7575 cond[0] = (which_alternative < 2) ? operands[0] : operands[1];
7547 cond[0] = (which_alternative < 3) ? operands[0] : operands[1];
7548 cond[1] = operands[2]; 7576 cond[1] = operands[2];
7549 cond[2] = operands[3]; 7577 cond[2] = operands[3];
7550 7578
7551 if (GET_CODE (cond[2]) == CONST_INT && INTVAL (cond[2]) < 0) 7579 if (GET_CODE (cond[2]) == CONST_INT && INTVAL (cond[2]) < 0)
7552 output_asm_insn (\"sub\\t%0, %1, #%n2\", cond); 7580 output_asm_insn (\"sub\\t%0, %1, #%n2\", cond);
7553 else 7581 else
7554 output_asm_insn (\"add\\t%0, %1, %2\", cond); 7582 output_asm_insn (\"add\\t%0, %1, %2\", cond);
7555 7583
7556 if (which_alternative >= 3 7584 if (which_alternative >= 2
7557 && which_alternative < 4) 7585 && which_alternative < 4)
7558 output_asm_insn (\"mov\\t%0, %1\", operands); 7586 output_asm_insn (\"mov\\t%0, %1\", operands);
7559 else if (which_alternative >= 4) 7587 else if (which_alternative >= 4)
7560 output_asm_insn (\"str\\t%1, %0\", operands); 7588 output_asm_insn (\"str\\t%1, %0\", operands);
7561 7589
8620 (define_insn "*call_symbol" 8648 (define_insn "*call_symbol"
8621 [(call (mem:SI (match_operand:SI 0 "" "")) 8649 [(call (mem:SI (match_operand:SI 0 "" ""))
8622 (match_operand 1 "" "")) 8650 (match_operand 1 "" ""))
8623 (use (match_operand 2 "" "")) 8651 (use (match_operand 2 "" ""))
8624 (clobber (reg:SI LR_REGNUM))] 8652 (clobber (reg:SI LR_REGNUM))]
8625 "TARGET_ARM 8653 "TARGET_32BIT
8626 && (GET_CODE (operands[0]) == SYMBOL_REF) 8654 && (GET_CODE (operands[0]) == SYMBOL_REF)
8627 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" 8655 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
8628 "* 8656 "*
8629 { 8657 {
8630 return NEED_PLT_RELOC ? \"bl%?\\t%a0(PLT)\" : \"bl%?\\t%a0\"; 8658 return NEED_PLT_RELOC ? \"bl%?\\t%a0(PLT)\" : \"bl%?\\t%a0\";
8636 [(set (match_operand 0 "" "") 8664 [(set (match_operand 0 "" "")
8637 (call (mem:SI (match_operand:SI 1 "" "")) 8665 (call (mem:SI (match_operand:SI 1 "" ""))
8638 (match_operand:SI 2 "" ""))) 8666 (match_operand:SI 2 "" "")))
8639 (use (match_operand 3 "" "")) 8667 (use (match_operand 3 "" ""))
8640 (clobber (reg:SI LR_REGNUM))] 8668 (clobber (reg:SI LR_REGNUM))]
8641 "TARGET_ARM 8669 "TARGET_32BIT
8642 && (GET_CODE (operands[1]) == SYMBOL_REF) 8670 && (GET_CODE (operands[1]) == SYMBOL_REF)
8643 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" 8671 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
8644 "* 8672 "*
8645 { 8673 {
8646 return NEED_PLT_RELOC ? \"bl%?\\t%a1(PLT)\" : \"bl%?\\t%a1\"; 8674 return NEED_PLT_RELOC ? \"bl%?\\t%a1(PLT)\" : \"bl%?\\t%a1\";
8651 (define_insn "*call_insn" 8679 (define_insn "*call_insn"
8652 [(call (mem:SI (match_operand:SI 0 "" "")) 8680 [(call (mem:SI (match_operand:SI 0 "" ""))
8653 (match_operand:SI 1 "" "")) 8681 (match_operand:SI 1 "" ""))
8654 (use (match_operand 2 "" "")) 8682 (use (match_operand 2 "" ""))
8655 (clobber (reg:SI LR_REGNUM))] 8683 (clobber (reg:SI LR_REGNUM))]
8656 "TARGET_THUMB 8684 "TARGET_THUMB1
8657 && GET_CODE (operands[0]) == SYMBOL_REF 8685 && GET_CODE (operands[0]) == SYMBOL_REF
8658 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" 8686 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
8659 "bl\\t%a0" 8687 "bl\\t%a0"
8660 [(set_attr "length" "4") 8688 [(set_attr "length" "4")
8661 (set_attr "type" "call")] 8689 (set_attr "type" "call")]
8665 [(set (match_operand 0 "" "") 8693 [(set (match_operand 0 "" "")
8666 (call (mem:SI (match_operand 1 "" "")) 8694 (call (mem:SI (match_operand 1 "" ""))
8667 (match_operand 2 "" ""))) 8695 (match_operand 2 "" "")))
8668 (use (match_operand 3 "" "")) 8696 (use (match_operand 3 "" ""))
8669 (clobber (reg:SI LR_REGNUM))] 8697 (clobber (reg:SI LR_REGNUM))]
8670 "TARGET_THUMB 8698 "TARGET_THUMB1
8671 && GET_CODE (operands[1]) == SYMBOL_REF 8699 && GET_CODE (operands[1]) == SYMBOL_REF
8672 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" 8700 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
8673 "bl\\t%a1" 8701 "bl\\t%a1"
8674 [(set_attr "length" "4") 8702 [(set_attr "length" "4")
8675 (set_attr "type" "call")] 8703 (set_attr "type" "call")]
8679 (define_expand "sibcall" 8707 (define_expand "sibcall"
8680 [(parallel [(call (match_operand 0 "memory_operand" "") 8708 [(parallel [(call (match_operand 0 "memory_operand" "")
8681 (match_operand 1 "general_operand" "")) 8709 (match_operand 1 "general_operand" ""))
8682 (return) 8710 (return)
8683 (use (match_operand 2 "" ""))])] 8711 (use (match_operand 2 "" ""))])]
8684 "TARGET_ARM" 8712 "TARGET_32BIT"
8685 " 8713 "
8686 { 8714 {
8687 if (operands[2] == NULL_RTX) 8715 if (operands[2] == NULL_RTX)
8688 operands[2] = const0_rtx; 8716 operands[2] = const0_rtx;
8689 }" 8717 }"
8693 [(parallel [(set (match_operand 0 "" "") 8721 [(parallel [(set (match_operand 0 "" "")
8694 (call (match_operand 1 "memory_operand" "") 8722 (call (match_operand 1 "memory_operand" "")
8695 (match_operand 2 "general_operand" ""))) 8723 (match_operand 2 "general_operand" "")))
8696 (return) 8724 (return)
8697 (use (match_operand 3 "" ""))])] 8725 (use (match_operand 3 "" ""))])]
8698 "TARGET_ARM" 8726 "TARGET_32BIT"
8699 " 8727 "
8700 { 8728 {
8701 if (operands[3] == NULL_RTX) 8729 if (operands[3] == NULL_RTX)
8702 operands[3] = const0_rtx; 8730 operands[3] = const0_rtx;
8703 }" 8731 }"
8706 (define_insn "*sibcall_insn" 8734 (define_insn "*sibcall_insn"
8707 [(call (mem:SI (match_operand:SI 0 "" "X")) 8735 [(call (mem:SI (match_operand:SI 0 "" "X"))
8708 (match_operand 1 "" "")) 8736 (match_operand 1 "" ""))
8709 (return) 8737 (return)
8710 (use (match_operand 2 "" ""))] 8738 (use (match_operand 2 "" ""))]
8711 "TARGET_ARM && GET_CODE (operands[0]) == SYMBOL_REF" 8739 "TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF"
8712 "* 8740 "*
8713 return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; 8741 return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\";
8714 " 8742 "
8715 [(set_attr "type" "call")] 8743 [(set_attr "type" "call")]
8716 ) 8744 )
8719 [(set (match_operand 0 "" "") 8747 [(set (match_operand 0 "" "")
8720 (call (mem:SI (match_operand:SI 1 "" "X")) 8748 (call (mem:SI (match_operand:SI 1 "" "X"))
8721 (match_operand 2 "" ""))) 8749 (match_operand 2 "" "")))
8722 (return) 8750 (return)
8723 (use (match_operand 3 "" ""))] 8751 (use (match_operand 3 "" ""))]
8724 "TARGET_ARM && GET_CODE (operands[1]) == SYMBOL_REF" 8752 "TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF"
8725 "* 8753 "*
8726 return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; 8754 return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\";
8727 " 8755 "
8728 [(set_attr "type" "call")] 8756 [(set_attr "type" "call")]
8729 ) 8757 )
8730 8758
8759 (define_expand "return"
8760 [(return)]
8761 "TARGET_32BIT && USE_RETURN_INSN (FALSE)"
8762 "")
8763
8731 ;; Often the return insn will be the same as loading from memory, so set attr 8764 ;; Often the return insn will be the same as loading from memory, so set attr
8732 (define_insn "return" 8765 (define_insn "*arm_return"
8733 [(return)] 8766 [(return)]
8734 "TARGET_ARM && USE_RETURN_INSN (FALSE)" 8767 "TARGET_ARM && USE_RETURN_INSN (FALSE)"
8735 "* 8768 "*
8736 { 8769 {
8737 if (arm_ccfsm_state == 2) 8770 if (arm_ccfsm_state == 2)
11192 "movt%?\t%0, %c1" 11225 "movt%?\t%0, %c1"
11193 [(set_attr "predicable" "yes") 11226 [(set_attr "predicable" "yes")
11194 (set_attr "length" "4")] 11227 (set_attr "length" "4")]
11195 ) 11228 )
11196 11229
11230 (define_insn "arm_rev"
11231 [(set (match_operand:SI 0 "s_register_operand" "=r")
11232 (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
11233 "TARGET_EITHER && arm_arch6"
11234 "rev\t%0, %1"
11235 [(set (attr "length")
11236 (if_then_else (eq_attr "is_thumb" "yes")
11237 (const_int 2)
11238 (const_int 4)))]
11239 )
11240
11241 (define_expand "arm_legacy_rev"
11242 [(set (match_operand:SI 2 "s_register_operand" "")
11243 (xor:SI (rotatert:SI (match_operand:SI 1 "s_register_operand" "")
11244 (const_int 16))
11245 (match_dup 1)))
11246 (set (match_dup 2)
11247 (lshiftrt:SI (match_dup 2)
11248 (const_int 8)))
11249 (set (match_operand:SI 3 "s_register_operand" "")
11250 (rotatert:SI (match_dup 1)
11251 (const_int 8)))
11252 (set (match_dup 2)
11253 (and:SI (match_dup 2)
11254 (const_int -65281)))
11255 (set (match_operand:SI 0 "s_register_operand" "")
11256 (xor:SI (match_dup 3)
11257 (match_dup 2)))]
11258 "TARGET_32BIT"
11259 ""
11260 )
11261
11262 ;; Reuse temporaries to keep register pressure down.
11263 (define_expand "thumb_legacy_rev"
11264 [(set (match_operand:SI 2 "s_register_operand" "")
11265 (ashift:SI (match_operand:SI 1 "s_register_operand" "")
11266 (const_int 24)))
11267 (set (match_operand:SI 3 "s_register_operand" "")
11268 (lshiftrt:SI (match_dup 1)
11269 (const_int 24)))
11270 (set (match_dup 3)
11271 (ior:SI (match_dup 3)
11272 (match_dup 2)))
11273 (set (match_operand:SI 4 "s_register_operand" "")
11274 (const_int 16))
11275 (set (match_operand:SI 5 "s_register_operand" "")
11276 (rotatert:SI (match_dup 1)
11277 (match_dup 4)))
11278 (set (match_dup 2)
11279 (ashift:SI (match_dup 5)
11280 (const_int 24)))
11281 (set (match_dup 5)
11282 (lshiftrt:SI (match_dup 5)
11283 (const_int 24)))
11284 (set (match_dup 5)
11285 (ior:SI (match_dup 5)
11286 (match_dup 2)))
11287 (set (match_dup 5)
11288 (rotatert:SI (match_dup 5)
11289 (match_dup 4)))
11290 (set (match_operand:SI 0 "s_register_operand" "")
11291 (ior:SI (match_dup 5)
11292 (match_dup 3)))]
11293 "TARGET_THUMB"
11294 ""
11295 )
11296
11297 (define_expand "bswapsi2"
11298 [(set (match_operand:SI 0 "s_register_operand" "=r")
11299 (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
11300 "TARGET_EITHER"
11301 "
11302 if (!arm_arch6)
11303 {
11304 if (!optimize_size)
11305 {
11306 rtx op2 = gen_reg_rtx (SImode);
11307 rtx op3 = gen_reg_rtx (SImode);
11308
11309 if (TARGET_THUMB)
11310 {
11311 rtx op4 = gen_reg_rtx (SImode);
11312 rtx op5 = gen_reg_rtx (SImode);
11313
11314 emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
11315 op2, op3, op4, op5));
11316 }
11317 else
11318 {
11319 emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
11320 op2, op3));
11321 }
11322
11323 DONE;
11324 }
11325 else
11326 FAIL;
11327 }
11328 "
11329 )
11330
11197 ;; Load the FPA co-processor patterns 11331 ;; Load the FPA co-processor patterns
11198 (include "fpa.md") 11332 (include "fpa.md")
11199 ;; Load the Maverick co-processor patterns 11333 ;; Load the Maverick co-processor patterns
11200 (include "cirrus.md") 11334 (include "cirrus.md")
11201 ;; Vector bits common to IWMMXT and Neon 11335 ;; Vector bits common to IWMMXT and Neon