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comparison gcc/config/h8300/h8300.md @ 63:b7f97abdc517 gcc-4.6-20100522

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update gcc from gcc-4.5.0 to gcc-4.6
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Mon, 24 May 2010 12:47:05 +0900
parents 77e2b8dfacca
children f6334be47118
comparison
equal deleted inserted replaced
56:3c8a44c06a95 63:b7f97abdc517
1 ;; GCC machine description for Renesas H8/300 1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 3 ;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
4 ;; Free Software Foundation, Inc. 4 ;; Free Software Foundation, Inc.
5 5
6 ;; Contributed by Steve Chamberlain (sac@cygnus.com), 6 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
7 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). 7 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 8
151 ;; definitely doesn't have the effect of causing the called function 151 ;; definitely doesn't have the effect of causing the called function
152 ;; to return to the target of the delayed branch. 152 ;; to return to the target of the delayed branch.
153 (define_attr "can_delay" "no,yes" 153 (define_attr "can_delay" "no,yes"
154 (cond [(eq_attr "type" "branch,bitbranch,call") 154 (cond [(eq_attr "type" "branch,bitbranch,call")
155 (const_string "no") 155 (const_string "no")
156 (ne (symbol_ref "get_attr_length (insn)") (const_int 2)) 156 (geu (symbol_ref "get_attr_length (insn)") (const_int 2))
157 (const_string "no")] 157 (const_string "no")]
158 (const_string "yes"))) 158 (const_string "yes")))
159 159
160 ;; Only allow jumps to have a delay slot if we think they might 160 ;; Only allow jumps to have a delay slot if we think they might
161 ;; be short enough. This is just an optimization: we don't know 161 ;; be short enough. This is just an optimization: we don't know
220 (define_insn "*movqi_h8sx" 220 (define_insn "*movqi_h8sx"
221 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ") 221 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
222 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))] 222 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
223 "TARGET_H8300SX" 223 "TARGET_H8300SX"
224 "@ 224 "@
225 mov.b %X1,%X0 225 mov.b %X1:4,%X0
226 mov.b %X1,%X0" 226 mov.b %X1,%X0"
227 [(set_attr "length_table" "mov_imm4,movb") 227 [(set_attr "length_table" "mov_imm4,movb")
228 (set_attr "cc" "set_znv")]) 228 (set_attr "cc" "set_znv")])
229 229
230 (define_expand "movqi" 230 (define_expand "movqi"
298 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ") 298 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
299 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))] 299 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
300 "TARGET_H8300SX" 300 "TARGET_H8300SX"
301 "@ 301 "@
302 sub.w %T0,%T0 302 sub.w %T0,%T0
303 mov.w %T1,%T0 303 mov.w %T1:3,%T0
304 mov.w %T1,%T0 304 mov.w %T1:4,%T0
305 mov.w %T1,%T0 305 mov.w %T1,%T0
306 mov.w %T1,%T0" 306 mov.w %T1,%T0"
307 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw") 307 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
308 (set_attr "length" "2,2,*,*,*") 308 (set_attr "length" "2,2,*,*,*")
309 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")]) 309 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
509 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r") 509 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
510 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))] 510 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
511 "TARGET_H8300SX" 511 "TARGET_H8300SX"
512 "@ 512 "@
513 sub.l %S0,%S0 513 sub.l %S0,%S0
514 mov.l %S1,%S0 514 mov.l %S1:3,%S0
515 mov.l %S1,%S0 515 mov.l %S1,%S0
516 mov.l %S1,%S0 516 mov.l %S1,%S0
517 clrmac 517 clrmac
518 clrmac\;ldmac %1,macl 518 clrmac\;ldmac %1,macl
519 stmac macl,%0" 519 stmac macl,%0"
1141 (define_insn "*cmphi_h8300hs_znvc" 1141 (define_insn "*cmphi_h8300hs_znvc"
1142 [(set (cc0) 1142 [(set (cc0)
1143 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ") 1143 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
1144 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))] 1144 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
1145 "TARGET_H8300H || TARGET_H8300S" 1145 "TARGET_H8300H || TARGET_H8300S"
1146 "cmp.w %T1,%T0" 1146 "*
1147 {
1148 switch (which_alternative)
1149 {
1150 case 0:
1151 if (!TARGET_H8300SX)
1152 return \"cmp.w %T1,%T0\";
1153 else
1154 return \"cmp.w %T1:3,%T0\";
1155 case 1:
1156 return \"cmp.w %T1,%T0\";
1157 default:
1158 gcc_unreachable ();
1159 }
1160 }"
1147 [(set_attr "length_table" "short_immediate,addw") 1161 [(set_attr "length_table" "short_immediate,addw")
1148 (set_attr "cc" "compare,compare")]) 1162 (set_attr "cc" "compare,compare")])
1149 1163
1150 (define_insn "cmpsi" 1164 (define_insn "cmpsi"
1151 [(set (cc0) 1165 [(set (cc0)
1152 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ") 1166 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
1153 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))] 1167 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
1154 "TARGET_H8300H || TARGET_H8300S" 1168 "TARGET_H8300H || TARGET_H8300S"
1155 "cmp.l %S1,%S0" 1169 "*
1170 {
1171 switch (which_alternative)
1172 {
1173 case 0:
1174 if (!TARGET_H8300SX)
1175 return \"cmp.l %S1,%S0\";
1176 else
1177 return \"cmp.l %S1:3,%S0\";
1178 case 1:
1179 return \"cmp.l %S1,%S0\";
1180 default:
1181 gcc_unreachable ();
1182 }
1183 }"
1156 [(set_attr "length" "2,*") 1184 [(set_attr "length" "2,*")
1157 (set_attr "length_table" "*,addl") 1185 (set_attr "length_table" "*,addl")
1158 (set_attr "cc" "compare,compare")]) 1186 (set_attr "cc" "compare,compare")])
1159 1187
1160 ;; ---------------------------------------------------------------------- 1188 ;; ----------------------------------------------------------------------
1257 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ") 1285 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1258 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0") 1286 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1259 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))] 1287 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1260 "TARGET_H8300SX && h8300_operands_match_p (operands)" 1288 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1261 "@ 1289 "@
1262 add.w %T2,%T0 1290 add.w %T2:3,%T0
1263 sub.w %G2,%T0 1291 sub.w %G2:3,%T0
1264 add.b %t2,%t0 1292 add.b %t2,%t0
1265 add.w %T2,%T0" 1293 add.w %T2,%T0"
1266 [(set_attr "length_table" "short_immediate,short_immediate,*,addw") 1294 [(set_attr "length_table" "short_immediate,short_immediate,*,addw")
1267 (set_attr "length" "*,*,2,*") 1295 (set_attr "length" "*,*,2,*")
1268 (set_attr "cc" "set_zn")]) 1296 (set_attr "cc" "set_zn")])
1732 [(set_attr "length" "6")]) 1760 [(set_attr "length" "6")])
1733 1761
1734 ;; ---------------------------------------------------------------------- 1762 ;; ----------------------------------------------------------------------
1735 ;; AND INSTRUCTIONS 1763 ;; AND INSTRUCTIONS
1736 ;; ---------------------------------------------------------------------- 1764 ;; ----------------------------------------------------------------------
1737 1765 (define_insn "bclrqi_msx"
1766 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1767 (and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1768 (match_operand:QI 2 "single_zero_operand" "Y0")))]
1769 "TARGET_H8300SX"
1770 "bclr\\t%W2,%0"
1771 [(set_attr "length" "8")])
1772
1773 (define_split
1774 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1775 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1776 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1777 "TARGET_H8300SX"
1778 [(set (match_dup 0)
1779 (and:QI (match_dup 1)
1780 (match_dup 2)))]
1781 {
1782 operands[0] = adjust_address (operands[0], QImode, 1);
1783 operands[1] = adjust_address (operands[1], QImode, 1);
1784 })
1785
1786 (define_insn "bclrhi_msx"
1787 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1788 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1789 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1790 "TARGET_H8300SX"
1791 "bclr\\t%W2,%0"
1792 [(set_attr "length" "8")])
1738 (define_insn "*andqi3_2" 1793 (define_insn "*andqi3_2"
1739 [(set (match_operand:QI 0 "bit_operand" "=rQ,r") 1794 [(set (match_operand:QI 0 "bit_operand" "=rQ,r")
1740 (and:QI (match_operand:QI 1 "bit_operand" "%0,WU") 1795 (and:QI (match_operand:QI 1 "bit_operand" "%0,WU")
1741 (match_operand:QI 2 "h8300_src_operand" "rQi,IP1>X")))] 1796 (match_operand:QI 2 "h8300_src_operand" "rQi,IP1>X")))]
1742 "TARGET_H8300SX" 1797 "TARGET_H8300SX"
1836 "") 1891 "")
1837 1892
1838 ;; ---------------------------------------------------------------------- 1893 ;; ----------------------------------------------------------------------
1839 ;; OR INSTRUCTIONS 1894 ;; OR INSTRUCTIONS
1840 ;; ---------------------------------------------------------------------- 1895 ;; ----------------------------------------------------------------------
1896 (define_insn "bsetqi_msx"
1897 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1898 (ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1899 (match_operand:QI 2 "single_one_operand" "Y2")))]
1900 "TARGET_H8300SX"
1901 "bset\\t%V2,%0"
1902 [(set_attr "length" "8")])
1903
1904 (define_split
1905 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1906 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1907 (match_operand:HI 2 "single_one_operand" "Y2")))]
1908 "TARGET_H8300SX"
1909 [(set (match_dup 0)
1910 (ior:QI (match_dup 1)
1911 (match_dup 2)))]
1912 {
1913 operands[0] = adjust_address (operands[0], QImode, 1);
1914 operands[1] = adjust_address (operands[1], QImode, 1);
1915 })
1916
1917 (define_insn "bsethi_msx"
1918 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1919 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1920 (match_operand:HI 2 "single_one_operand" "Y2")))]
1921 "TARGET_H8300SX"
1922 "bset\\t%V2,%0"
1923 [(set_attr "length" "8")])
1841 1924
1842 (define_insn "iorqi3_1" 1925 (define_insn "iorqi3_1"
1843 [(set (match_operand:QI 0 "bit_operand" "=rQ,U") 1926 [(set (match_operand:QI 0 "bit_operand" "=rQ,U")
1844 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0") 1927 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1845 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))] 1928 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
1874 "") 1957 "")
1875 1958
1876 ;; ---------------------------------------------------------------------- 1959 ;; ----------------------------------------------------------------------
1877 ;; XOR INSTRUCTIONS 1960 ;; XOR INSTRUCTIONS
1878 ;; ---------------------------------------------------------------------- 1961 ;; ----------------------------------------------------------------------
1962 (define_insn "bnotqi_msx"
1963 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1964 (xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1965 (match_operand:QI 2 "single_one_operand" "Y2")))]
1966 "TARGET_H8300SX"
1967 "bnot\\t%V2,%0"
1968 [(set_attr "length" "8")])
1969
1970 (define_split
1971 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1972 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1973 (match_operand:HI 2 "single_one_operand" "Y2")))]
1974 "TARGET_H8300SX"
1975 [(set (match_dup 0)
1976 (xor:QI (match_dup 1)
1977 (match_dup 2)))]
1978 {
1979 operands[0] = adjust_address (operands[0], QImode, 1);
1980 operands[1] = adjust_address (operands[1], QImode, 1);
1981 })
1982
1983 (define_insn "bnothi_msx"
1984 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1985 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1986 (match_operand:HI 2 "single_one_operand" "Y2")))]
1987 "TARGET_H8300SX"
1988 "bnot\\t%V2,%0"
1989 [(set_attr "length" "8")])
1879 1990
1880 (define_insn "xorqi3_1" 1991 (define_insn "xorqi3_1"
1881 [(set (match_operand:QI 0 "bit_operand" "=r,U") 1992 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1882 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0") 1993 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1883 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))] 1994 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
3143 [(set (match_operand:HI 0 "register_operand" "=&r") 3254 [(set (match_operand:HI 0 "register_operand" "=&r")
3144 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r") 3255 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
3145 (match_operand:HI 3 "const_int_operand" "n")) 3256 (match_operand:HI 3 "const_int_operand" "n"))
3146 (const_int 1) 3257 (const_int 1)
3147 (match_operand:HI 2 "const_int_operand" "n")))] 3258 (match_operand:HI 2 "const_int_operand" "n")))]
3148 "TARGET_H8300 3259 "(TARGET_H8300 || TARGET_H8300SX)
3149 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" 3260 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3150 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0" 3261 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
3151 [(set_attr "length" "8")]) 3262 [(set_attr "length" "8")])
3152 3263
3153 ;; 3264 ;;