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comparison gcc/config/i386/driver-i386.c @ 63:b7f97abdc517 gcc-4.6-20100522

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update gcc from gcc-4.5.0 to gcc-4.6
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Mon, 24 May 2010 12:47:05 +0900
parents 77e2b8dfacca
children f6334be47118
comparison
equal deleted inserted replaced
56:3c8a44c06a95 63:b7f97abdc517
262 CACHE_INST = 2, 262 CACHE_INST = 2,
263 CACHE_UNIFIED = 3 263 CACHE_UNIFIED = 3
264 }; 264 };
265 265
266 static void 266 static void
267 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2) 267 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
268 struct cache_desc *level3)
268 { 269 {
269 struct cache_desc *cache; 270 struct cache_desc *cache;
270 271
271 unsigned eax, ebx, ecx, edx; 272 unsigned eax, ebx, ecx, edx;
272 int count; 273 int count;
287 cache = level1; 288 cache = level1;
288 break; 289 break;
289 case 2: 290 case 2:
290 cache = level2; 291 cache = level2;
291 break; 292 break;
293 case 3:
294 cache = level3;
295 break;
292 default: 296 default:
293 cache = NULL; 297 cache = NULL;
294 } 298 }
295 299
296 if (cache) 300 if (cache)
301 cache->assoc = ((ebx >> 22) & 0x03ff) + 1; 305 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
302 cache->line = (ebx & 0x0fff) + 1; 306 cache->line = (ebx & 0x0fff) + 1;
303 307
304 cache->sizekb = (cache->assoc * part 308 cache->sizekb = (cache->assoc * part
305 * cache->line * sets) / 1024; 309 * cache->line * sets) / 1024;
306 } 310 }
307 } 311 }
308 default: 312 default:
309 break; 313 break;
310 } 314 }
311 } 315 }
312 } 316 }
313 317
314 /* Returns the description of caches for an Intel processor. */ 318 /* Returns the description of caches for an Intel processor. */
315 319
316 static const char * 320 static const char *
317 detect_caches_intel (bool xeon_mp, unsigned max_level, unsigned max_ext_level) 321 detect_caches_intel (bool xeon_mp, unsigned max_level,
318 { 322 unsigned max_ext_level, unsigned *l2sizekb)
319 struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}; 323 {
324 struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
320 325
321 if (max_level >= 4) 326 if (max_level >= 4)
322 detect_caches_cpuid4 (&level1, &level2); 327 detect_caches_cpuid4 (&level1, &level2, &level3);
323 else if (max_level >= 2) 328 else if (max_level >= 2)
324 detect_caches_cpuid2 (xeon_mp, &level1, &level2); 329 detect_caches_cpuid2 (xeon_mp, &level1, &level2);
325 else 330 else
326 return ""; 331 return "";
327 332
328 if (level1.sizekb == 0) 333 if (level1.sizekb == 0)
329 return ""; 334 return "";
330 335
336 /* Let the L3 replace the L2. This assumes inclusive caches
337 and single threaded program for now. */
338 if (level3.sizekb)
339 level2 = level3;
340
331 /* Intel CPUs are equipped with AMD style L2 cache info. Try this 341 /* Intel CPUs are equipped with AMD style L2 cache info. Try this
332 method if other methods fail to provide L2 cache parameters. */ 342 method if other methods fail to provide L2 cache parameters. */
333 if (level2.sizekb == 0 && max_ext_level >= 0x80000006) 343 if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
334 detect_l2_cache (&level2); 344 detect_l2_cache (&level2);
345
346 *l2sizekb = level2.sizekb;
335 347
336 return describe_cache (level1, level2); 348 return describe_cache (level1, level2);
337 } 349 }
338 350
339 enum vendor_signatures 351 enum vendor_signatures
382 unsigned int has_lahf_lm = 0, has_sse4a = 0; 394 unsigned int has_lahf_lm = 0, has_sse4a = 0;
383 unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0; 395 unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
384 unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0; 396 unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
385 unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0; 397 unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0;
386 unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0; 398 unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
399 unsigned int has_fma4 = 0, has_xop = 0;
387 400
388 bool arch; 401 bool arch;
402
403 unsigned int l2sizekb = 0;
389 404
390 if (argc < 1) 405 if (argc < 1)
391 return NULL; 406 return NULL;
392 407
393 arch = !strcmp (argv[0], "arch"); 408 arch = !strcmp (argv[0], "arch");
444 459
445 has_lahf_lm = ecx & bit_LAHF_LM; 460 has_lahf_lm = ecx & bit_LAHF_LM;
446 has_sse4a = ecx & bit_SSE4a; 461 has_sse4a = ecx & bit_SSE4a;
447 has_abm = ecx & bit_ABM; 462 has_abm = ecx & bit_ABM;
448 has_lwp = ecx & bit_LWP; 463 has_lwp = ecx & bit_LWP;
464 has_fma4 = ecx & bit_FMA4;
465 has_xop = ecx & bit_XOP;
449 466
450 has_longmode = edx & bit_LM; 467 has_longmode = edx & bit_LM;
451 has_3dnowp = edx & bit_3DNOWP; 468 has_3dnowp = edx & bit_3DNOWP;
452 has_3dnow = edx & bit_3DNOW; 469 has_3dnow = edx & bit_3DNOW;
453 } 470 }
457 if (vendor == SIG_AMD) 474 if (vendor == SIG_AMD)
458 cache = detect_caches_amd (ext_level); 475 cache = detect_caches_amd (ext_level);
459 else if (vendor == SIG_INTEL) 476 else if (vendor == SIG_INTEL)
460 { 477 {
461 bool xeon_mp = (family == 15 && model == 6); 478 bool xeon_mp = (family == 15 && model == 6);
462 cache = detect_caches_intel (xeon_mp, max_level, ext_level); 479 cache = detect_caches_intel (xeon_mp, max_level,
480 ext_level, &l2sizekb);
463 } 481 }
464 } 482 }
465 483
466 if (vendor == SIG_AMD) 484 if (vendor == SIG_AMD)
467 { 485 {
473 else 491 else
474 name = 0; 492 name = 0;
475 493
476 if (name == SIG_GEODE) 494 if (name == SIG_GEODE)
477 processor = PROCESSOR_GEODE; 495 processor = PROCESSOR_GEODE;
496 else if (has_xop)
497 processor = PROCESSOR_BDVER1;
478 else if (has_sse4a) 498 else if (has_sse4a)
479 processor = PROCESSOR_AMDFAM10; 499 processor = PROCESSOR_AMDFAM10;
480 else if (has_sse2 || has_longmode) 500 else if (has_sse2 || has_longmode)
481 processor = PROCESSOR_K8; 501 processor = PROCESSOR_K8;
482 else if (has_3dnowp) 502 else if (has_3dnowp)
521 cpu = "pentium-mmx"; 541 cpu = "pentium-mmx";
522 else 542 else
523 cpu = "pentium"; 543 cpu = "pentium";
524 break; 544 break;
525 case PROCESSOR_PENTIUMPRO: 545 case PROCESSOR_PENTIUMPRO:
526 if (has_longmode) 546 switch (model)
527 /* It is Core 2 or Atom. */
528 cpu = (model == 28) ? "atom" : "core2";
529 else if (arch)
530 { 547 {
531 if (has_sse3) 548 case 0x1c:
532 /* It is Core Duo. */ 549 case 0x26:
533 cpu = "prescott"; 550 /* Atom. */
534 else if (has_sse2) 551 cpu = "atom";
535 /* It is Pentium M. */ 552 break;
536 cpu = "pentium-m"; 553 case 0x1a:
537 else if (has_sse) 554 case 0x1e:
538 /* It is Pentium III. */ 555 case 0x1f:
539 cpu = "pentium3"; 556 case 0x2e:
540 else if (has_mmx) 557 /* FIXME: Optimize for Nehalem. */
541 /* It is Pentium II. */ 558 cpu = "core2";
542 cpu = "pentium2"; 559 break;
560 case 0x25:
561 case 0x2f:
562 /* FIXME: Optimize for Westmere. */
563 cpu = "core2";
564 break;
565 case 0x17:
566 case 0x1d:
567 /* Penryn. FIXME: -mtune=core2 is slower than -mtune=generic */
568 cpu = "core2";
569 break;
570 case 0x0f:
571 /* Merom. FIXME: -mtune=core2 is slower than -mtune=generic */
572 cpu = "core2";
573 break;
574 default:
575 if (arch)
576 {
577 if (has_ssse3)
578 /* If it is an unknown CPU with SSSE3, assume Core 2. */
579 cpu = "core2";
580 else if (has_sse3)
581 /* It is Core Duo. */
582 cpu = "pentium-m";
583 else if (has_sse2)
584 /* It is Pentium M. */
585 cpu = "pentium-m";
586 else if (has_sse)
587 /* It is Pentium III. */
588 cpu = "pentium3";
589 else if (has_mmx)
590 /* It is Pentium II. */
591 cpu = "pentium2";
592 else
593 /* Default to Pentium Pro. */
594 cpu = "pentiumpro";
595 }
543 else 596 else
544 /* Default to Pentium Pro. */ 597 /* For -mtune, we default to -mtune=generic. */
545 cpu = "pentiumpro"; 598 cpu = "generic";
599 break;
546 } 600 }
547 else
548 /* For -mtune, we default to -mtune=generic. */
549 cpu = "generic";
550 break; 601 break;
551 case PROCESSOR_PENTIUM4: 602 case PROCESSOR_PENTIUM4:
552 if (has_sse3) 603 if (has_sse3)
553 { 604 {
554 if (has_longmode) 605 if (has_longmode)
580 else 631 else
581 cpu = "k8"; 632 cpu = "k8";
582 break; 633 break;
583 case PROCESSOR_AMDFAM10: 634 case PROCESSOR_AMDFAM10:
584 cpu = "amdfam10"; 635 cpu = "amdfam10";
636 break;
637 case PROCESSOR_BDVER1:
638 cpu = "bdver1";
585 break; 639 break;
586 640
587 default: 641 default:
588 /* Use something reasonable. */ 642 /* Use something reasonable. */
589 if (arch) 643 if (arch)
626 options = concat (options, " -mpopcnt", NULL); 680 options = concat (options, " -mpopcnt", NULL);
627 if (has_abm) 681 if (has_abm)
628 options = concat (options, " -mabm", NULL); 682 options = concat (options, " -mabm", NULL);
629 if (has_lwp) 683 if (has_lwp)
630 options = concat (options, " -mlwp", NULL); 684 options = concat (options, " -mlwp", NULL);
685 if (has_fma4)
686 options = concat (options, " -mfma4", NULL);
687 if (has_xop)
688 options = concat (options, " -mxop", NULL);
631 689
632 if (has_avx) 690 if (has_avx)
633 options = concat (options, " -mavx", NULL); 691 options = concat (options, " -mavx", NULL);
634 else if (has_sse4_2) 692 else if (has_sse4_2)
635 options = concat (options, " -msse4.2", NULL); 693 options = concat (options, " -msse4.2", NULL);