CbC/CbC_gcc: gcc/config/mips/mips.c comparison

comparison gcc/config/mips/mips.c @ 63:b7f97abdc517 gcc-4.6-20100522

update gcc from gcc-4.5.0 to gcc-4.6

author	ryoma <e075725@ie.u-ryukyu.ac.jp>
date	Mon, 24 May 2010 12:47:05 +0900
parents	77e2b8dfacca
children	f6334be47118

comparison

equal deleted inserted replaced

-:3c8a44c06a95
+:b7f97abdc517
 /* Subroutines used for MIPS code generation.
 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
-1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
 Free Software Foundation, Inc.
 Contributed by A. Lichnewsky, lich@inria.inria.fr.
 Changes by Michael Meissner, meissner@osf.org.
 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
 Brendan Eich, brendan@microunity.com.
 #include "tm.h"
 #include <signal.h>
 #include "rtl.h"
 #include "regs.h"
 #include "hard-reg-set.h"
-#include "real.h"
 #include "insn-config.h"
 #include "conditions.h"
 #include "insn-attr.h"
 #include "recog.h"
 #include "toplev.h"
 TREE_CHAIN (f_foff) = f_res;
 layout_type (record);
 return record;
 }
-else if (TARGET_IRIX && TARGET_IRIX6)
+else if (TARGET_IRIX6)
 /* On IRIX 6, this type is 'char *'.  */
 return build_pointer_type (char_type_node);
 else
 /* Otherwise, we use 'void *'.  */
 return ptr_type_node;
 	  fputs ("\t.extern\t", file);
 	  assemble_name (file, name);
 	  fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
 		   int_size_in_bytes (TREE_TYPE (decl)));
 	}
-else if (TARGET_IRIX
-	       && mips_abi == ABI_32
-	       && TREE_CODE (decl) == FUNCTION_DECL)
-	{
-	  /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
-	     `.global name .text' directive for every used but
-	     undefined function.  If we don't, the linker may perform
-	     an optimization (skipping over the insns that set $gp)
-	     when it is unsafe.  */
-	  fputs ("\t.globl ", file);
-	  assemble_name (file, name);
-	  fputs (" .text\n", file);
-	}
 }
 }
 /* Implement ASM_OUTPUT_SOURCE_FILENAME.  */
 default_file_start ();
 /* Generate a special section to describe the ABI switches used to
 produce the resultant binary.  This is unnecessary on IRIX and
 causes unwanted warnings from the native linker.  */
-if (!TARGET_IRIX)
+if (!TARGET_IRIX6)
 {
 /* Record the ABI itself.  Modern versions of binutils encode
 	 this information in the ELF header flags, but GDB needs the
 	 information in order to correctly debug binaries produced by
 	 older binutils.  See the function mips_gdbarch_init in
 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
 	fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
 		 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
 #ifdef HAVE_AS_GNU_ATTRIBUTE
-fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
+{
-	       (TARGET_HARD_FLOAT_ABI
+	int attr;
-		? (TARGET_DOUBLE_FLOAT
-		   ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
+	/* No floating-point operations, -mno-float.  */
+	if (TARGET_NO_FLOAT)
+	  attr = 0;
+	/* Soft-float code, -msoft-float.  */
+	else if (!TARGET_HARD_FLOAT_ABI)
+	  attr = 3;
+	/* Single-float code, -msingle-float.  */
+	else if (!TARGET_DOUBLE_FLOAT)
+	  attr = 2;
+	/* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64.  */
+	else if (!TARGET_64BIT && TARGET_FLOAT64)
+	  attr = 4;
+	/* Regular FP code, FP regs same size as GP regs, -mdouble-float.  */
+	else
+	  attr = 1;
+	fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
+}
 #endif
 }
 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code.  */
 if (TARGET_ABICALLS)
 assemble_start_function.  This is needed so that the name used here
 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
 mips_start_function_definition (fnname, TARGET_MIPS16);
-/* Stop mips_file_end from treating this function as external.  */
-if (TARGET_IRIX && mips_abi == ABI_32)
-TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
 /* Output MIPS-specific frame information.  */
 if (!flag_inhibit_size_directive)
 {
 const struct mips_frame_info *frame;
 We therefore disallow all mode changes involving FPRs.  */
 return reg_classes_intersect_p (FP_REGS, rclass);
 }
+/* Implement target hook small_register_classes_for_mode_p.  */
+static bool
+mips_small_register_classes_for_mode_p (enum machine_mode mode
+					ATTRIBUTE_UNUSED)
+{
+return TARGET_MIPS16;
+}
 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction.  */
 static bool
 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
 {
 	{
 	  output_asm_insn (s, operands);
 	  s = "bnez\t%2,1f\n\tbreak\t7\n1:";
 	}
 else if (GENERATE_DIVIDE_TRAPS)
-{
+	{
-	  output_asm_insn (s, operands);
+	  /* Avoid long replay penalty on load miss by putting the trap before
-	  s = "teq\t%2,%.,7";
+	     the divide.  */
-}
+	  if (TUNE_74K)
+	    output_asm_insn ("teq\t%2,%.,7", operands);
+	  else
+	    {
+	      output_asm_insn (s, operands);
+	      s = "teq\t%2,%.,7";
+	    }
+	}
 else
 	{
 	  output_asm_insn ("%(bne\t%2,%.,1f", operands);
 	  output_asm_insn (s, operands);
 	  s = "break\t7%)\n1:";
 free_dominance_info (CDI_DOMINATORS);
 }
 /* If INSN is a call, return the underlying CALL expr.  Return NULL_RTX
-otherwise.  */
+otherwise.  If INSN has two call rtx, then store the second one in
+SECOND_CALL.  */
 static rtx
-mips_call_expr_from_insn (rtx insn)
+mips_call_expr_from_insn (rtx insn, rtx *second_call)
 {
 rtx x;
+rtx x2;
 if (!CALL_P (insn))
 return NULL_RTX;
 x = PATTERN (insn);
 if (GET_CODE (x) == PARALLEL)
-x = XVECEXP (x, 0, 0);
+{
+/* Calls returning complex values have two CALL rtx.  Look for the second
+	 one here, and return it via the SECOND_CALL arg.  */
+x2 = XVECEXP (x, 0, 1);
+if (GET_CODE (x2) == SET)
+	x2 = XEXP (x2, 1);
+if (GET_CODE (x2) == CALL)
+	*second_call = x2;
+x = XVECEXP (x, 0, 0);
+}
 if (GET_CODE (x) == SET)
 x = XEXP (x, 1);
 gcc_assert (GET_CODE (x) == CALL);
 return x;
 }
 /* REG is set in DEF.  See if the definition is one of the ways we load a
 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.  If
 rtx insn;
 FOR_EACH_BB (bb)
 FOR_BB_INSNS (bb, insn)
 {
-rtx call, reg, symbol;
+rtx call, reg, symbol, second_call;
-call = mips_call_expr_from_insn (insn);
+second_call = 0;
+call = mips_call_expr_from_insn (insn, &second_call);
 if (!call)
 	continue;
 gcc_assert (MEM_P (XEXP (call, 0)));
 reg = XEXP (XEXP (call, 0), 0);
 if (!REG_P (reg))
 	continue;
 symbol = mips_find_pic_call_symbol (insn, reg);
 if (symbol)
-	mips_annotate_pic_call_expr (call, symbol);
+	{
+	  mips_annotate_pic_call_expr (call, symbol);
+	  if (second_call)
+	    mips_annotate_pic_call_expr (second_call, symbol);
+	}
 }
 }
 /* A temporary variable used by for_each_rtx callbacks, etc.  */
 static rtx mips_sim_insn;
 #ifdef SUBTARGET_OVERRIDE_OPTIONS
 SUBTARGET_OVERRIDE_OPTIONS;
 #endif
+/* -mno-float overrides -mhard-float and -msoft-float.  */
+if (TARGET_NO_FLOAT)
+{
+target_flags |= MASK_SOFT_FLOAT_ABI;
+target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
+}
 /* Set the small data limit.  */
 mips_small_data_threshold = (g_switch_set
 			       ? g_switch_value
 			       : MIPS_DEFAULT_GVALUE);
 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
 mips_multipass_dfa_lookahead
+#undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
+#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
+mips_small_register_classes_for_mode_p
 #undef TARGET_DEFAULT_TARGET_FLAGS
 #define TARGET_DEFAULT_TARGET_FLAGS		\
 (TARGET_DEFAULT				\
 | TARGET_CPU_DEFAULT				\

Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/mips/mips.c @ 63:b7f97abdc517 gcc-4.6-20100522