Mercurial > hg > CbC > CbC_gcc
comparison gcc/ira.c @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
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date | Mon, 24 May 2010 12:47:05 +0900 |
parents | 77e2b8dfacca |
children | f6334be47118 |
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56:3c8a44c06a95 | 63:b7f97abdc517 |
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1 /* Integrated Register Allocator (IRA) entry point. | 1 /* Integrated Register Allocator (IRA) entry point. |
2 Copyright (C) 2006, 2007, 2008, 2009 | 2 Copyright (C) 2006, 2007, 2008, 2009, 2010 |
3 Free Software Foundation, Inc. | 3 Free Software Foundation, Inc. |
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>. | 4 Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
5 | 5 |
6 This file is part of GCC. | 6 This file is part of GCC. |
7 | 7 |
308 #include "flags.h" | 308 #include "flags.h" |
309 #include "obstack.h" | 309 #include "obstack.h" |
310 #include "bitmap.h" | 310 #include "bitmap.h" |
311 #include "hard-reg-set.h" | 311 #include "hard-reg-set.h" |
312 #include "basic-block.h" | 312 #include "basic-block.h" |
313 #include "df.h" | |
313 #include "expr.h" | 314 #include "expr.h" |
314 #include "recog.h" | 315 #include "recog.h" |
315 #include "params.h" | 316 #include "params.h" |
316 #include "timevar.h" | 317 #include "timevar.h" |
317 #include "tree-pass.h" | 318 #include "tree-pass.h" |
318 #include "output.h" | 319 #include "output.h" |
319 #include "except.h" | 320 #include "except.h" |
320 #include "reload.h" | 321 #include "reload.h" |
321 #include "errors.h" | 322 #include "toplev.h" |
322 #include "integrate.h" | 323 #include "integrate.h" |
323 #include "df.h" | |
324 #include "ggc.h" | 324 #include "ggc.h" |
325 #include "ira-int.h" | 325 #include "ira-int.h" |
326 | 326 |
327 | 327 |
328 /* A modified value of flag `-fira-verbose' used internally. */ | 328 /* A modified value of flag `-fira-verbose' used internally. */ |
411 /* Array of the number of hard registers of given class which are | 411 /* Array of the number of hard registers of given class which are |
412 available for allocation. The order is defined by the | 412 available for allocation. The order is defined by the |
413 allocation order. */ | 413 allocation order. */ |
414 short ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | 414 short ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; |
415 | 415 |
416 /* Array of the number of hard registers of given class which are | |
417 available for allocation. The order is defined by the | |
418 the hard register numbers. */ | |
419 short ira_non_ordered_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
420 | |
416 /* The number of elements of the above array for given register | 421 /* The number of elements of the above array for given register |
417 class. */ | 422 class. */ |
418 int ira_class_hard_regs_num[N_REG_CLASSES]; | 423 int ira_class_hard_regs_num[N_REG_CLASSES]; |
419 | 424 |
420 /* Index (in ira_class_hard_regs) for given register class and hard | 425 /* Index (in ira_class_hard_regs) for given register class and hard |
429 { | 434 { |
430 int cl, i, hard_regno, n; | 435 int cl, i, hard_regno, n; |
431 HARD_REG_SET processed_hard_reg_set; | 436 HARD_REG_SET processed_hard_reg_set; |
432 | 437 |
433 ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); | 438 ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); |
434 /* We could call ORDER_REGS_FOR_LOCAL_ALLOC here (it is usually | |
435 putting hard callee-used hard registers first). But our | |
436 heuristics work better. */ | |
437 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | 439 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
438 { | 440 { |
439 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | 441 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
440 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | 442 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); |
441 CLEAR_HARD_REG_SET (processed_hard_reg_set); | 443 CLEAR_HARD_REG_SET (processed_hard_reg_set); |
442 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | 444 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
443 ira_class_hard_reg_index[cl][0] = -1; | 445 { |
446 ira_non_ordered_class_hard_regs[cl][0] = -1; | |
447 ira_class_hard_reg_index[cl][0] = -1; | |
448 } | |
444 for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) | 449 for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
445 { | 450 { |
446 #ifdef REG_ALLOC_ORDER | 451 #ifdef REG_ALLOC_ORDER |
447 hard_regno = reg_alloc_order[i]; | 452 hard_regno = reg_alloc_order[i]; |
448 #else | 453 #else |
458 ira_class_hard_reg_index[cl][hard_regno] = n; | 463 ira_class_hard_reg_index[cl][hard_regno] = n; |
459 ira_class_hard_regs[cl][n++] = hard_regno; | 464 ira_class_hard_regs[cl][n++] = hard_regno; |
460 } | 465 } |
461 } | 466 } |
462 ira_class_hard_regs_num[cl] = n; | 467 ira_class_hard_regs_num[cl] = n; |
468 for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
469 if (TEST_HARD_REG_BIT (temp_hard_regset, i)) | |
470 ira_non_ordered_class_hard_regs[cl][n++] = i; | |
471 ira_assert (ira_class_hard_regs_num[cl] == n); | |
463 } | 472 } |
464 } | 473 } |
465 | 474 |
466 /* Number of given class hard registers available for the register | 475 /* Number of given class hard registers available for the register |
467 allocation for given classes. */ | 476 allocation for given classes. */ |
488 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means | 497 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means |
489 that we can use the hard frame pointer for the allocation. */ | 498 that we can use the hard frame pointer for the allocation. */ |
490 static void | 499 static void |
491 setup_alloc_regs (bool use_hard_frame_p) | 500 setup_alloc_regs (bool use_hard_frame_p) |
492 { | 501 { |
502 #ifdef ADJUST_REG_ALLOC_ORDER | |
503 ADJUST_REG_ALLOC_ORDER; | |
504 #endif | |
493 COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); | 505 COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); |
494 if (! use_hard_frame_p) | 506 if (! use_hard_frame_p) |
495 SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); | 507 SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); |
496 setup_class_hard_regs (); | 508 setup_class_hard_regs (); |
497 setup_available_class_regs (); | 509 setup_available_class_regs (); |
1885 basic_block bb; | 1897 basic_block bb; |
1886 | 1898 |
1887 FOR_EACH_BB (bb) | 1899 FOR_EACH_BB (bb) |
1888 { | 1900 { |
1889 /* We don't use LIVE info in IRA. */ | 1901 /* We don't use LIVE info in IRA. */ |
1890 regset r = DF_LR_IN (bb); | 1902 bitmap r = DF_LR_IN (bb); |
1891 | 1903 |
1892 if (REGNO_REG_SET_P (r, from)) | 1904 if (REGNO_REG_SET_P (r, from)) |
1893 { | 1905 { |
1894 CLEAR_REGNO_REG_SET (r, from); | 1906 CLEAR_REGNO_REG_SET (r, from); |
1895 SET_REGNO_REG_SET (r, to); | 1907 SET_REGNO_REG_SET (r, to); |
2278 for (; list; list = XEXP (list, 1)) | 2290 for (; list; list = XEXP (list, 1)) |
2279 { | 2291 { |
2280 rtx insn = XEXP (list, 0); | 2292 rtx insn = XEXP (list, 0); |
2281 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); | 2293 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); |
2282 } | 2294 } |
2295 } | |
2296 | |
2297 /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the | |
2298 equivalent replacement. */ | |
2299 | |
2300 static rtx | |
2301 adjust_cleared_regs (rtx loc, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data) | |
2302 { | |
2303 if (REG_P (loc)) | |
2304 { | |
2305 bitmap cleared_regs = (bitmap) data; | |
2306 if (bitmap_bit_p (cleared_regs, REGNO (loc))) | |
2307 return simplify_replace_fn_rtx (*reg_equiv[REGNO (loc)].src_p, | |
2308 NULL_RTX, adjust_cleared_regs, data); | |
2309 } | |
2310 return NULL_RTX; | |
2283 } | 2311 } |
2284 | 2312 |
2285 /* Nonzero if we recorded an equivalence for a LABEL_REF. */ | 2313 /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
2286 static int recorded_label_ref; | 2314 static int recorded_label_ref; |
2287 | 2315 |
2715 } | 2743 } |
2716 } | 2744 } |
2717 } | 2745 } |
2718 | 2746 |
2719 if (!bitmap_empty_p (cleared_regs)) | 2747 if (!bitmap_empty_p (cleared_regs)) |
2720 FOR_EACH_BB (bb) | 2748 { |
2721 { | 2749 FOR_EACH_BB (bb) |
2722 bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); | 2750 { |
2723 bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); | 2751 bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); |
2724 bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); | 2752 bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); |
2725 bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); | 2753 bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); |
2726 } | 2754 bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); |
2755 } | |
2756 | |
2757 /* Last pass - adjust debug insns referencing cleared regs. */ | |
2758 if (MAY_HAVE_DEBUG_INSNS) | |
2759 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
2760 if (DEBUG_INSN_P (insn)) | |
2761 { | |
2762 rtx old_loc = INSN_VAR_LOCATION_LOC (insn); | |
2763 INSN_VAR_LOCATION_LOC (insn) | |
2764 = simplify_replace_fn_rtx (old_loc, NULL_RTX, | |
2765 adjust_cleared_regs, | |
2766 (void *) cleared_regs); | |
2767 if (old_loc != INSN_VAR_LOCATION_LOC (insn)) | |
2768 df_insn_rescan (insn); | |
2769 } | |
2770 } | |
2727 | 2771 |
2728 BITMAP_FREE (cleared_regs); | 2772 BITMAP_FREE (cleared_regs); |
2729 | 2773 |
2730 out: | 2774 out: |
2731 /* Clean up. */ | 2775 /* Clean up. */ |
3093 int saved_flag_ira_share_spill_slots; | 3137 int saved_flag_ira_share_spill_slots; |
3094 basic_block bb; | 3138 basic_block bb; |
3095 | 3139 |
3096 timevar_push (TV_IRA); | 3140 timevar_push (TV_IRA); |
3097 | 3141 |
3142 if (flag_caller_saves) | |
3143 init_caller_save (); | |
3144 | |
3098 if (flag_ira_verbose < 10) | 3145 if (flag_ira_verbose < 10) |
3099 { | 3146 { |
3100 internal_flag_ira_verbose = flag_ira_verbose; | 3147 internal_flag_ira_verbose = flag_ira_verbose; |
3101 ira_dump_file = f; | 3148 ira_dump_file = f; |
3102 } | 3149 } |