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comparison gcc/config/i386/i386.md @ 132:d34655255c78

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update gcc-8.2
author mir3636
date Thu, 25 Oct 2018 10:21:07 +0900
parents ab0bcb71f44d 84e7813d76e9
children 351920fa3827
comparison
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130:e108057fa461 132:d34655255c78
1 ;; GCC machine description for IA-32 and x86-64. 1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988-2017 Free Software Foundation, Inc. 2 ;; Copyright (C) 1988-2018 Free Software Foundation, Inc.
3 ;; Mostly by William Schelter. 3 ;; Mostly by William Schelter.
4 ;; x86_64 support added by Jan Hubicka 4 ;; x86_64 support added by Jan Hubicka
5 ;; 5 ;;
6 ;; This file is part of GCC. 6 ;; This file is part of GCC.
7 ;; 7 ;;
60 ;; Y -- print condition for XOP pcom* instruction. 60 ;; Y -- print condition for XOP pcom* instruction.
61 ;; + -- print a branch hint as 'cs' or 'ds' prefix 61 ;; + -- print a branch hint as 'cs' or 'ds' prefix
62 ;; ; -- print a semicolon (after prefixes due to bug in older gas). 62 ;; ; -- print a semicolon (after prefixes due to bug in older gas).
63 ;; ~ -- print "i" if TARGET_AVX2, "f" otherwise. 63 ;; ~ -- print "i" if TARGET_AVX2, "f" otherwise.
64 ;; ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode 64 ;; ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
65 ;; ! -- print MPX or NOTRACK prefix for jxx/call/ret instructions if required. 65 ;; ! -- print NOTRACK prefix for jxx/call/ret instructions if required.
66 66
67 (define_c_enum "unspec" [ 67 (define_c_enum "unspec" [
68 ;; Relocation specifiers 68 ;; Relocation specifiers
69 UNSPEC_GOT 69 UNSPEC_GOT
70 UNSPEC_GOTOFF 70 UNSPEC_GOTOFF
97 97
98 ;; Other random patterns 98 ;; Other random patterns
99 UNSPEC_SCAS 99 UNSPEC_SCAS
100 UNSPEC_FNSTSW 100 UNSPEC_FNSTSW
101 UNSPEC_SAHF 101 UNSPEC_SAHF
102 UNSPEC_NOTRAP
102 UNSPEC_PARITY 103 UNSPEC_PARITY
103 UNSPEC_FSTCW 104 UNSPEC_FSTCW
104 UNSPEC_FLDCW
105 UNSPEC_REP 105 UNSPEC_REP
106 UNSPEC_LD_MPIC ; load_macho_picbase 106 UNSPEC_LD_MPIC ; load_macho_picbase
107 UNSPEC_TRUNC_NOOP 107 UNSPEC_TRUNC_NOOP
108 UNSPEC_DIV_ALREADY_SPLIT 108 UNSPEC_DIV_ALREADY_SPLIT
109 UNSPEC_PAUSE 109 UNSPEC_PAUSE
141 141
142 ;; x87 Rounding 142 ;; x87 Rounding
143 UNSPEC_FRNDINT_FLOOR 143 UNSPEC_FRNDINT_FLOOR
144 UNSPEC_FRNDINT_CEIL 144 UNSPEC_FRNDINT_CEIL
145 UNSPEC_FRNDINT_TRUNC 145 UNSPEC_FRNDINT_TRUNC
146 UNSPEC_FRNDINT_MASK_PM
147 UNSPEC_FIST_FLOOR 146 UNSPEC_FIST_FLOOR
148 UNSPEC_FIST_CEIL 147 UNSPEC_FIST_CEIL
149 148
150 ;; x87 Double output FP 149 ;; x87 Double output FP
151 UNSPEC_SINCOS_COS 150 UNSPEC_SINCOS_COS
180 UNSPEC_BEXTR 179 UNSPEC_BEXTR
181 180
182 ;; For BMI2 support 181 ;; For BMI2 support
183 UNSPEC_PDEP 182 UNSPEC_PDEP
184 UNSPEC_PEXT 183 UNSPEC_PEXT
185
186 UNSPEC_BNDMK
187 UNSPEC_BNDMK_ADDR
188 UNSPEC_BNDSTX
189 UNSPEC_BNDLDX
190 UNSPEC_BNDLDX_ADDR
191 UNSPEC_BNDCL
192 UNSPEC_BNDCU
193 UNSPEC_BNDCN
194 UNSPEC_MPX_FENCE
195 184
196 ;; IRET support 185 ;; IRET support
197 UNSPEC_INTERRUPT_RETURN 186 UNSPEC_INTERRUPT_RETURN
198 ]) 187 ])
199 188
234 UNSPECV_XRSTORS64 223 UNSPECV_XRSTORS64
235 UNSPECV_XSAVEC 224 UNSPECV_XSAVEC
236 UNSPECV_XSAVEC64 225 UNSPECV_XSAVEC64
237 UNSPECV_XGETBV 226 UNSPECV_XGETBV
238 UNSPECV_XSETBV 227 UNSPECV_XSETBV
228 UNSPECV_WBINVD
229 UNSPECV_WBNOINVD
239 230
240 ;; For atomic compound assignments. 231 ;; For atomic compound assignments.
241 UNSPECV_FNSTENV 232 UNSPECV_FNSTENV
242 UNSPECV_FLDENV 233 UNSPECV_FLDENV
243 UNSPECV_FNSTSW 234 UNSPECV_FNSTSW
284 UNSPECV_RSTORSSP 275 UNSPECV_RSTORSSP
285 UNSPECV_WRSS 276 UNSPECV_WRSS
286 UNSPECV_WRUSS 277 UNSPECV_WRUSS
287 UNSPECV_SETSSBSY 278 UNSPECV_SETSSBSY
288 UNSPECV_CLRSSBSY 279 UNSPECV_CLRSSBSY
280
281 ;; For MOVDIRI and MOVDIR64B support
282 UNSPECV_MOVDIRI
283 UNSPECV_MOVDIR64B
284
285 ;; For WAITPKG support
286 UNSPECV_UMWAIT
287 UNSPECV_UMONITOR
288 UNSPECV_TPAUSE
289
290 ;; For CLDEMOTE support
291 UNSPECV_CLDEMOTE
292
293 ;; For Speculation Barrier support
294 UNSPECV_SPECULATION_BARRIER
289 ]) 295 ])
290 296
291 ;; Constants to represent rounding modes in the ROUND instruction 297 ;; Constants to represent rounding modes in the ROUND instruction
292 (define_constants 298 (define_constants
293 [(ROUND_FLOOR 0x1) 299 [(ROUND_FLOOR 0x1)
350 (ST6_REG 14) 356 (ST6_REG 14)
351 (ST7_REG 15) 357 (ST7_REG 15)
352 (ARGP_REG 16) 358 (ARGP_REG 16)
353 (FLAGS_REG 17) 359 (FLAGS_REG 17)
354 (FPSR_REG 18) 360 (FPSR_REG 18)
355 (FPCR_REG 19) 361 (FRAME_REG 19)
356 (FRAME_REG 20) 362 (XMM0_REG 20)
357 (XMM0_REG 21) 363 (XMM1_REG 21)
358 (XMM1_REG 22) 364 (XMM2_REG 22)
359 (XMM2_REG 23) 365 (XMM3_REG 23)
360 (XMM3_REG 24) 366 (XMM4_REG 24)
361 (XMM4_REG 25) 367 (XMM5_REG 25)
362 (XMM5_REG 26) 368 (XMM6_REG 26)
363 (XMM6_REG 27) 369 (XMM7_REG 27)
364 (XMM7_REG 28) 370 (MM0_REG 28)
365 (MM0_REG 29) 371 (MM1_REG 29)
366 (MM1_REG 30) 372 (MM2_REG 30)
367 (MM2_REG 31) 373 (MM3_REG 31)
368 (MM3_REG 32) 374 (MM4_REG 32)
369 (MM4_REG 33) 375 (MM5_REG 33)
370 (MM5_REG 34) 376 (MM6_REG 34)
371 (MM6_REG 35) 377 (MM7_REG 35)
372 (MM7_REG 36) 378 (R8_REG 36)
373 (R8_REG 37) 379 (R9_REG 37)
374 (R9_REG 38) 380 (R10_REG 38)
375 (R10_REG 39) 381 (R11_REG 39)
376 (R11_REG 40) 382 (R12_REG 40)
377 (R12_REG 41) 383 (R13_REG 41)
378 (R13_REG 42) 384 (R14_REG 42)
379 (R14_REG 43) 385 (R15_REG 43)
380 (R15_REG 44) 386 (XMM8_REG 44)
381 (XMM8_REG 45) 387 (XMM9_REG 45)
382 (XMM9_REG 46) 388 (XMM10_REG 46)
383 (XMM10_REG 47) 389 (XMM11_REG 47)
384 (XMM11_REG 48) 390 (XMM12_REG 48)
385 (XMM12_REG 49) 391 (XMM13_REG 49)
386 (XMM13_REG 50) 392 (XMM14_REG 50)
387 (XMM14_REG 51) 393 (XMM15_REG 51)
388 (XMM15_REG 52) 394 (XMM16_REG 52)
389 (XMM16_REG 53) 395 (XMM17_REG 53)
390 (XMM17_REG 54) 396 (XMM18_REG 54)
391 (XMM18_REG 55) 397 (XMM19_REG 55)
392 (XMM19_REG 56) 398 (XMM20_REG 56)
393 (XMM20_REG 57) 399 (XMM21_REG 57)
394 (XMM21_REG 58) 400 (XMM22_REG 58)
395 (XMM22_REG 59) 401 (XMM23_REG 59)
396 (XMM23_REG 60) 402 (XMM24_REG 60)
397 (XMM24_REG 61) 403 (XMM25_REG 61)
398 (XMM25_REG 62) 404 (XMM26_REG 62)
399 (XMM26_REG 63) 405 (XMM27_REG 63)
400 (XMM27_REG 64) 406 (XMM28_REG 64)
401 (XMM28_REG 65) 407 (XMM29_REG 65)
402 (XMM29_REG 66) 408 (XMM30_REG 66)
403 (XMM30_REG 67) 409 (XMM31_REG 67)
404 (XMM31_REG 68) 410 (MASK0_REG 68)
405 (MASK0_REG 69) 411 (MASK1_REG 69)
406 (MASK1_REG 70) 412 (MASK2_REG 70)
407 (MASK2_REG 71) 413 (MASK3_REG 71)
408 (MASK3_REG 72) 414 (MASK4_REG 72)
409 (MASK4_REG 73) 415 (MASK5_REG 73)
410 (MASK5_REG 74) 416 (MASK6_REG 74)
411 (MASK6_REG 75) 417 (MASK7_REG 75)
412 (MASK7_REG 76) 418 (FIRST_PSEUDO_REG 76)
413 (BND0_REG 77)
414 (BND1_REG 78)
415 (BND2_REG 79)
416 (BND3_REG 80)
417 (FIRST_PSEUDO_REG 81)
418 ]) 419 ])
419 420
420 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls 421 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
421 ;; from i386.c. 422 ;; from i386.c.
422 423
426 ;; "reload_completed && TARGET_64BIT". 427 ;; "reload_completed && TARGET_64BIT".
427 428
428 429
429 ;; Processor type. 430 ;; Processor type.
430 (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem, 431 (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
431 atom,slm,haswell,generic,amdfam10,bdver1,bdver2,bdver3, 432 atom,slm,glm,haswell,generic,amdfam10,bdver1,bdver2,bdver3,
432 bdver4,btver2,znver1" 433 bdver4,btver2,znver1"
433 (const (symbol_ref "ix86_schedule"))) 434 (const (symbol_ref "ix86_schedule")))
434 435
435 ;; A basic instruction type. Refinements due to arguments to be 436 ;; A basic instruction type. Refinements due to arguments to be
436 ;; provided in other attributes. 437 ;; provided in other attributes.
447 ssemul,sseimul,ssediv,sselog,sselog1, 448 ssemul,sseimul,ssediv,sselog,sselog1,
448 sseishft,sseishft1,ssecmp,ssecomi, 449 sseishft,sseishft1,ssecmp,ssecomi,
449 ssecvt,ssecvt1,sseicvt,sseins, 450 ssecvt,ssecvt1,sseicvt,sseins,
450 sseshuf,sseshuf1,ssemuladd,sse4arg, 451 sseshuf,sseshuf1,ssemuladd,sse4arg,
451 lwp,mskmov,msklog, 452 lwp,mskmov,msklog,
452 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft, 453 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
453 mpxmov,mpxmk,mpxchk,mpxld,mpxst"
454 (const_string "other")) 454 (const_string "other"))
455 455
456 ;; Main data type used by the insn 456 ;; Main data type used by the insn
457 (define_attr "mode" 457 (define_attr "mode"
458 "unknown,none,QI,HI,SI,DI,TI,OI,XI,SF,DF,XF,TF,V16SF,V8SF,V4DF,V4SF, 458 "unknown,none,QI,HI,SI,DI,TI,OI,XI,SF,DF,XF,TF,V16SF,V8SF,V4DF,V4SF,
477 (const_string "integer"))) 477 (const_string "integer")))
478 478
479 ;; The (bounding maximum) length of an instruction immediate. 479 ;; The (bounding maximum) length of an instruction immediate.
480 (define_attr "length_immediate" "" 480 (define_attr "length_immediate" ""
481 (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave, 481 (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,
482 bitmanip,imulx,msklog,mskmov,mpxmk,mpxmov,mpxchk, 482 bitmanip,imulx,msklog,mskmov")
483 mpxld,mpxst")
484 (const_int 0) 483 (const_int 0)
485 (eq_attr "unit" "i387,sse,mmx") 484 (eq_attr "unit" "i387,sse,mmx")
486 (const_int 0) 485 (const_int 0)
487 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,ishiftx,ishift1, 486 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,ishiftx,ishift1,
488 rotate,rotatex,rotate1,imul,icmp,push,pop") 487 rotate,rotatex,rotate1,imul,icmp,push,pop")
533 (define_attr "prefix_rep" "" 532 (define_attr "prefix_rep" ""
534 (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1") 533 (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
535 (const_int 0) 534 (const_int 0)
536 (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF")) 535 (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
537 (const_int 1) 536 (const_int 1)
538 (and (eq_attr "type" "ibr,call,callv")
539 (match_test "ix86_bnd_prefixed_insn_p (insn)"))
540 (const_int 1)
541 ] 537 ]
542 (const_int 0))) 538 (const_int 0)))
543 539
544 ;; Set when 0f opcode prefix is used. 540 ;; Set when 0f opcode prefix is used.
545 (define_attr "prefix_0f" "" 541 (define_attr "prefix_0f" ""
546 (if_then_else 542 (if_then_else
547 (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip,msklog,mskmov, 543 (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip,msklog,mskmov")
548 mpxmk,mpxmov,mpxchk,mpxld,mpxst")
549 (eq_attr "unit" "sse,mmx")) 544 (eq_attr "unit" "sse,mmx"))
550 (const_int 1) 545 (const_int 1)
551 (const_int 0))) 546 (const_int 0)))
552 547
553 ;; Set when REX opcode prefix is used. 548 ;; Set when REX opcode prefix is used.
578 (const_int 2) 573 (const_int 2)
579 (eq_attr "type" "sseiadd1,ssecvt1") 574 (eq_attr "type" "sseiadd1,ssecvt1")
580 (const_int 1) 575 (const_int 1)
581 ] 576 ]
582 (const_int 0))) 577 (const_int 0)))
583
584 ;; Set when BND opcode prefix may be used.
585 (define_attr "maybe_prefix_bnd" "" (const_int 0))
586 578
587 ;; Prefix used: original, VEX or maybe VEX. 579 ;; Prefix used: original, VEX or maybe VEX.
588 (define_attr "prefix" "orig,vex,maybe_vex,evex,maybe_evex" 580 (define_attr "prefix" "orig,vex,maybe_vex,evex,maybe_evex"
589 (cond [(eq_attr "mode" "OI,V8SF,V4DF") 581 (cond [(eq_attr "mode" "OI,V8SF,V4DF")
590 (const_string "vex") 582 (const_string "vex")
648 (and (eq_attr "type" "alu,alu1,icmp,test") 640 (and (eq_attr "type" "alu,alu1,icmp,test")
649 (match_operand 0 "ax_reg_operand")) 641 (match_operand 0 "ax_reg_operand"))
650 (symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))") 642 (symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))")
651 ] 643 ]
652 (const_int 1))) 644 (const_int 1)))
653
654 (define_attr "modrm_class" "none,incdec,op0,op01,op02,pushpop,unknown"
655 (cond [(eq_attr "modrm" "0")
656 (const_string "none")
657 (eq_attr "type" "alu,imul,ishift")
658 (const_string "op02")
659 (eq_attr "type" "imov,imovx,lea,alu1,icmp")
660 (const_string "op01")
661 (eq_attr "type" "incdec")
662 (const_string "incdec")
663 (eq_attr "type" "push,pop")
664 (const_string "pushpop")]
665 (const_string "unknown")))
666 645
667 ;; The (bounding maximum) length of an instruction in bytes. 646 ;; The (bounding maximum) length of an instruction in bytes.
668 ;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences. 647 ;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
669 ;; Later we may want to split them and compute proper length as for 648 ;; Later we may want to split them and compute proper length as for
670 ;; other insns. 649 ;; other insns.
708 ;; if the instruction is complex. 687 ;; if the instruction is complex.
709 688
710 (define_attr "memory" "none,load,store,both,unknown" 689 (define_attr "memory" "none,load,store,both,unknown"
711 (cond [(eq_attr "type" "other,multi,str,lwp") 690 (cond [(eq_attr "type" "other,multi,str,lwp")
712 (const_string "unknown") 691 (const_string "unknown")
713 (eq_attr "type" "lea,fcmov,fpspc,mpxmk,mpxchk") 692 (eq_attr "type" "lea,fcmov,fpspc")
714 (const_string "none") 693 (const_string "none")
715 (eq_attr "type" "fistp,leave") 694 (eq_attr "type" "fistp,leave")
716 (const_string "both") 695 (const_string "both")
717 (eq_attr "type" "frndint") 696 (eq_attr "type" "frndint")
718 (const_string "load") 697 (const_string "load")
719 (eq_attr "type" "mpxld")
720 (const_string "load")
721 (eq_attr "type" "mpxst")
722 (const_string "store")
723 (eq_attr "type" "push") 698 (eq_attr "type" "push")
724 (if_then_else (match_operand 1 "memory_operand") 699 (if_then_else (match_operand 1 "memory_operand")
725 (const_string "both") 700 (const_string "both")
726 (const_string "store")) 701 (const_string "store"))
727 (eq_attr "type" "pop") 702 (eq_attr "type" "pop")
747 (const_string "load")) 722 (const_string "load"))
748 (eq_attr "type" "callv") 723 (eq_attr "type" "callv")
749 (if_then_else (match_operand 1 "constant_call_address_operand") 724 (if_then_else (match_operand 1 "constant_call_address_operand")
750 (const_string "none") 725 (const_string "none")
751 (const_string "load")) 726 (const_string "load"))
752 (and (eq_attr "type" "alu1,negnot,ishift1,sselog1,sseshuf1") 727 (and (eq_attr "type" "alu1,negnot,ishift1,rotate1,sselog1,sseshuf1")
753 (match_operand 1 "memory_operand")) 728 (match_operand 1 "memory_operand"))
754 (const_string "both") 729 (const_string "both")
755 (and (match_operand 0 "memory_operand") 730 (and (match_operand 0 "memory_operand")
756 (match_operand 1 "memory_operand")) 731 (match_operand 1 "memory_operand"))
757 (const_string "both") 732 (const_string "both")
758 (match_operand 0 "memory_operand") 733 (match_operand 0 "memory_operand")
759 (const_string "store") 734 (const_string "store")
760 (match_operand 1 "memory_operand") 735 (match_operand 1 "memory_operand")
761 (const_string "load") 736 (const_string "load")
762 (and (eq_attr "type" 737 (and (eq_attr "type"
763 "!alu1,negnot,ishift1, 738 "!alu1,negnot,ishift1,rotate1,
764 imov,imovx,icmp,test,bitmanip, 739 imov,imovx,icmp,test,bitmanip,
765 fmov,fcmp,fsgn, 740 fmov,fcmp,fsgn,
766 sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt, 741 sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,
767 sselog1,sseshuf1,sseadd1,sseiadd1,sseishft1, 742 sselog1,sseshuf1,sseadd1,sseiadd1,sseishft1,
768 mmx,mmxmov,mmxcmp,mmxcvt,mskmov,msklog,mpxmov") 743 mmx,mmxmov,mmxcmp,mmxcvt,mskmov,msklog")
769 (match_operand 2 "memory_operand")) 744 (match_operand 2 "memory_operand"))
770 (const_string "load") 745 (const_string "load")
771 (and (eq_attr "type" "icmov,ssemuladd,sse4arg") 746 (and (eq_attr "type" "icmov,ssemuladd,sse4arg")
772 (match_operand 3 "memory_operand")) 747 (match_operand 3 "memory_operand"))
773 (const_string "load") 748 (const_string "load")
795 (define_attr "fp_int_src" "false,true" 770 (define_attr "fp_int_src" "false,true"
796 (const_string "false")) 771 (const_string "false"))
797 772
798 ;; Defines rounding mode of an FP operation. 773 ;; Defines rounding mode of an FP operation.
799 774
800 (define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any" 775 (define_attr "i387_cw" "trunc,floor,ceil,uninitialized,any"
801 (const_string "any")) 776 (const_string "any"))
802 777
803 ;; Define attribute to classify add/sub insns that consumes carry flag (CF) 778 ;; Define attribute to classify add/sub insns that consumes carry flag (CF)
804 (define_attr "use_carry" "0,1" (const_string "0")) 779 (define_attr "use_carry" "0,1" (const_string "0"))
805 780
806 ;; Define attribute to indicate unaligned ssemov insns 781 ;; Define attribute to indicate unaligned ssemov insns
807 (define_attr "movu" "0,1" (const_string "0")) 782 (define_attr "movu" "0,1" (const_string "0"))
808 783
809 ;; Used to control the "enabled" attribute on a per-instruction basis. 784 ;; Used to control the "enabled" attribute on a per-instruction basis.
810 (define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64, 785 (define_attr "isa" "base,x64,x64_sse2,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
811 sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx, 786 sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
812 avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f, 787 avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
813 avx512bw,noavx512bw,avx512dq,noavx512dq, 788 avx512bw,noavx512bw,avx512dq,noavx512dq,
814 avx512vl,noavx512vl,x64_avx512dq,x64_avx512bw" 789 avx512vl,noavx512vl,x64_avx512dq,x64_avx512bw"
815 (const_string "base")) 790 (const_string "base"))
816 791
817 (define_attr "enabled" "" 792 (define_attr "enabled" ""
818 (cond [(eq_attr "isa" "x64") (symbol_ref "TARGET_64BIT") 793 (cond [(eq_attr "isa" "x64") (symbol_ref "TARGET_64BIT")
794 (eq_attr "isa" "x64_sse2")
795 (symbol_ref "TARGET_64BIT && TARGET_SSE2")
819 (eq_attr "isa" "x64_sse4") 796 (eq_attr "isa" "x64_sse4")
820 (symbol_ref "TARGET_64BIT && TARGET_SSE4_1") 797 (symbol_ref "TARGET_64BIT && TARGET_SSE4_1")
821 (eq_attr "isa" "x64_sse4_noavx") 798 (eq_attr "isa" "x64_sse4_noavx")
822 (symbol_ref "TARGET_64BIT && TARGET_SSE4_1 && !TARGET_AVX") 799 (symbol_ref "TARGET_64BIT && TARGET_SSE4_1 && !TARGET_AVX")
823 (eq_attr "isa" "x64_avx") 800 (eq_attr "isa" "x64_avx")
941 918
942 ;; Mapping of abs neg operators 919 ;; Mapping of abs neg operators
943 (define_code_iterator absneg [abs neg]) 920 (define_code_iterator absneg [abs neg])
944 921
945 ;; Base name for x87 insn mnemonic. 922 ;; Base name for x87 insn mnemonic.
946 (define_code_attr absneg_mnemonic [(abs "abs") (neg "chs")]) 923 (define_code_attr absneg_mnemonic [(abs "fabs") (neg "fchs")])
947 924
948 ;; Used in signed and unsigned widening multiplications. 925 ;; Used in signed and unsigned widening multiplications.
949 (define_code_iterator any_extend [sign_extend zero_extend]) 926 (define_code_iterator any_extend [sign_extend zero_extend])
950 927
951 ;; Prefix for insn menmonic. 928 ;; Prefix for insn menmonic.
962 (define_code_attr trunsuffix [(ss_truncate "s") (truncate "") (us_truncate "us")]) 939 (define_code_attr trunsuffix [(ss_truncate "s") (truncate "") (us_truncate "us")])
963 940
964 ;; Used in signed and unsigned fix. 941 ;; Used in signed and unsigned fix.
965 (define_code_iterator any_fix [fix unsigned_fix]) 942 (define_code_iterator any_fix [fix unsigned_fix])
966 (define_code_attr fixsuffix [(fix "") (unsigned_fix "u")]) 943 (define_code_attr fixsuffix [(fix "") (unsigned_fix "u")])
944 (define_code_attr fixunssuffix [(fix "") (unsigned_fix "uns")])
945 (define_code_attr fixprefix [(fix "s") (unsigned_fix "u")])
967 946
968 ;; Used in signed and unsigned float. 947 ;; Used in signed and unsigned float.
969 (define_code_iterator any_float [float unsigned_float]) 948 (define_code_iterator any_float [float unsigned_float])
970 (define_code_attr floatsuffix [(float "") (unsigned_float "u")]) 949 (define_code_attr floatsuffix [(float "") (unsigned_float "u")])
950 (define_code_attr floatunssuffix [(float "") (unsigned_float "uns")])
951 (define_code_attr floatprefix [(float "s") (unsigned_float "u")])
971 952
972 ;; All integer modes. 953 ;; All integer modes.
973 (define_mode_iterator SWI1248x [QI HI SI DI]) 954 (define_mode_iterator SWI1248x [QI HI SI DI])
974 955
975 ;; All integer modes without QImode. 956 ;; All integer modes without QImode.
1047 1028
1048 ;; Half mode for double word integer modes. 1029 ;; Half mode for double word integer modes.
1049 (define_mode_iterator DWIH [(SI "!TARGET_64BIT") 1030 (define_mode_iterator DWIH [(SI "!TARGET_64BIT")
1050 (DI "TARGET_64BIT")]) 1031 (DI "TARGET_64BIT")])
1051 1032
1052 ;; Bound modes.
1053 (define_mode_iterator BND [(BND32 "!TARGET_LP64")
1054 (BND64 "TARGET_LP64")])
1055
1056 ;; Pointer mode corresponding to bound mode.
1057 (define_mode_attr bnd_ptr [(BND32 "SI") (BND64 "DI")])
1058
1059 ;; MPX check types
1060 (define_int_iterator BNDCHECK [UNSPEC_BNDCL UNSPEC_BNDCU UNSPEC_BNDCN])
1061
1062 ;; Check name
1063 (define_int_attr bndcheck [(UNSPEC_BNDCL "cl")
1064 (UNSPEC_BNDCU "cu")
1065 (UNSPEC_BNDCN "cn")])
1066
1067 ;; Instruction suffix for integer modes. 1033 ;; Instruction suffix for integer modes.
1068 (define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")]) 1034 (define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
1069 1035
1070 ;; Instruction suffix for masks. 1036 ;; Instruction suffix for masks.
1071 (define_mode_attr mskmodesuffix [(QI "b") (HI "w") (SI "d") (DI "q")]) 1037 (define_mode_attr mskmodesuffix [(QI "b") (HI "w") (SI "d") (DI "q")])
1193 (define_mode_attr avx512fvecmode 1159 (define_mode_attr avx512fvecmode
1194 [(QI "V64QI") (HI "V32HI") (SI "V16SI") (DI "V8DI") (SF "V16SF") (DF "V8DF")]) 1160 [(QI "V64QI") (HI "V32HI") (SI "V16SI") (DI "V8DI") (SF "V16SF") (DF "V8DF")])
1195 1161
1196 ;; Instruction suffix for REX 64bit operators. 1162 ;; Instruction suffix for REX 64bit operators.
1197 (define_mode_attr rex64suffix [(SI "") (DI "{q}")]) 1163 (define_mode_attr rex64suffix [(SI "") (DI "{q}")])
1164 (define_mode_attr rex64namesuffix [(SI "") (DI "q")])
1198 1165
1199 ;; This mode iterator allows :P to be used for patterns that operate on 1166 ;; This mode iterator allows :P to be used for patterns that operate on
1200 ;; pointer-sized quantities. Exactly one of the two alternatives will match. 1167 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
1201 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) 1168 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
1202 1169
1221 (include "btver2.md") 1188 (include "btver2.md")
1222 (include "znver1.md") 1189 (include "znver1.md")
1223 (include "geode.md") 1190 (include "geode.md")
1224 (include "atom.md") 1191 (include "atom.md")
1225 (include "slm.md") 1192 (include "slm.md")
1193 (include "glm.md")
1226 (include "core2.md") 1194 (include "core2.md")
1227 (include "haswell.md") 1195 (include "haswell.md")
1228 1196
1229 1197
1230 ;; Operand and operator predicates and constraints 1198 ;; Operand and operator predicates and constraints
1272 (define_expand "cmp<mode>_1" 1240 (define_expand "cmp<mode>_1"
1273 [(set (reg:CC FLAGS_REG) 1241 [(set (reg:CC FLAGS_REG)
1274 (compare:CC (match_operand:SWI48 0 "nonimmediate_operand") 1242 (compare:CC (match_operand:SWI48 0 "nonimmediate_operand")
1275 (match_operand:SWI48 1 "<general_operand>")))]) 1243 (match_operand:SWI48 1 "<general_operand>")))])
1276 1244
1245 (define_mode_iterator SWI1248_AVX512BWDQ2_64
1246 [(QI "TARGET_AVX512DQ") (HI "TARGET_AVX512DQ")
1247 (SI "TARGET_AVX512BW") (DI "TARGET_AVX512BW && TARGET_64BIT")])
1248
1249 (define_insn "*cmp<mode>_ccz_1"
1250 [(set (reg FLAGS_REG)
1251 (compare (match_operand:SWI1248_AVX512BWDQ2_64 0
1252 "nonimmediate_operand" "<r>,?m<r>,$k")
1253 (match_operand:SWI1248_AVX512BWDQ2_64 1 "const0_operand")))]
1254 "ix86_match_ccmode (insn, CCZmode)"
1255 "@
1256 test{<imodesuffix>}\t%0, %0
1257 cmp{<imodesuffix>}\t{%1, %0|%0, %1}
1258 ktest<mskmodesuffix>\t%0, %0"
1259 [(set_attr "type" "test,icmp,msklog")
1260 (set_attr "length_immediate" "0,1,*")
1261 (set_attr "prefix" "*,*,vex")
1262 (set_attr "mode" "<MODE>")])
1263
1277 (define_insn "*cmp<mode>_ccno_1" 1264 (define_insn "*cmp<mode>_ccno_1"
1278 [(set (reg FLAGS_REG) 1265 [(set (reg FLAGS_REG)
1279 (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>,?m<r>") 1266 (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>,?m<r>")
1280 (match_operand:SWI 1 "const0_operand")))] 1267 (match_operand:SWI 1 "const0_operand")))]
1281 "ix86_match_ccmode (insn, CCNOmode)" 1268 "ix86_match_ccmode (insn, CCNOmode)"
1282 "@ 1269 "@
1283 test{<imodesuffix>}\t%0, %0 1270 test{<imodesuffix>}\t%0, %0
1284 cmp{<imodesuffix>}\t{%1, %0|%0, %1}" 1271 cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
1285 [(set_attr "type" "test,icmp") 1272 [(set_attr "type" "test,icmp")
1286 (set_attr "length_immediate" "0,1") 1273 (set_attr "length_immediate" "0,1")
1287 (set_attr "modrm_class" "op0,unknown")
1288 (set_attr "mode" "<MODE>")]) 1274 (set_attr "mode" "<MODE>")])
1289 1275
1290 (define_insn "*cmp<mode>_1" 1276 (define_insn "*cmp<mode>_1"
1291 [(set (reg FLAGS_REG) 1277 [(set (reg FLAGS_REG)
1292 (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>") 1278 (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
1473 ix86_expand_setcc (operands[0], GET_CODE (operands[1]), 1459 ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
1474 operands[2], operands[3]); 1460 operands[2], operands[3]);
1475 DONE; 1461 DONE;
1476 }) 1462 })
1477 1463
1478
1479 ;; FP compares, step 1: 1464 ;; FP compares, step 1:
1480 ;; Set the FP condition codes. 1465 ;; Set the FP condition codes and move fpsr to ax.
1481 ;; 1466
1482 ;; CCFPmode compare with exceptions 1467 ;; We may not use "#" to split and emit these
1483 ;; CCFPUmode compare with no exceptions 1468 ;; due to reg-stack pops killing fpsr.
1484
1485 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
1486 ;; used to manage the reg stack popping would not be preserved.
1487
1488 (define_insn "*cmp<mode>_0_i387"
1489 [(set (match_operand:HI 0 "register_operand" "=a")
1490 (unspec:HI
1491 [(compare:CCFP
1492 (match_operand:X87MODEF 1 "register_operand" "f")
1493 (match_operand:X87MODEF 2 "const0_operand"))]
1494 UNSPEC_FNSTSW))]
1495 "TARGET_80387"
1496 "* return output_fp_compare (insn, operands, false, false);"
1497 [(set_attr "type" "multi")
1498 (set_attr "unit" "i387")
1499 (set_attr "mode" "<MODE>")])
1500
1501 (define_insn_and_split "*cmp<mode>_0_cc_i387"
1502 [(set (reg:CCFP FLAGS_REG)
1503 (compare:CCFP
1504 (match_operand:X87MODEF 1 "register_operand" "f")
1505 (match_operand:X87MODEF 2 "const0_operand")))
1506 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1507 "TARGET_80387 && TARGET_SAHF && !TARGET_CMOVE"
1508 "#"
1509 "&& reload_completed"
1510 [(set (match_dup 0)
1511 (unspec:HI
1512 [(compare:CCFP (match_dup 1)(match_dup 2))]
1513 UNSPEC_FNSTSW))
1514 (set (reg:CC FLAGS_REG)
1515 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1516 ""
1517 [(set_attr "type" "multi")
1518 (set_attr "unit" "i387")
1519 (set_attr "mode" "<MODE>")])
1520 1469
1521 (define_insn "*cmpxf_i387" 1470 (define_insn "*cmpxf_i387"
1522 [(set (match_operand:HI 0 "register_operand" "=a") 1471 [(set (match_operand:HI 0 "register_operand" "=a")
1523 (unspec:HI 1472 (unspec:HI
1524 [(compare:CCFP 1473 [(compare:CCFP
1525 (match_operand:XF 1 "register_operand" "f") 1474 (match_operand:XF 1 "register_operand" "f")
1526 (match_operand:XF 2 "register_operand" "f"))] 1475 (match_operand:XF 2 "reg_or_0_operand" "fC"))]
1527 UNSPEC_FNSTSW))] 1476 UNSPEC_FNSTSW))]
1528 "TARGET_80387" 1477 "TARGET_80387"
1529 "* return output_fp_compare (insn, operands, false, false);" 1478 "* return output_fp_compare (insn, operands, false, false);"
1530 [(set_attr "type" "multi") 1479 [(set_attr "type" "multi")
1531 (set_attr "unit" "i387") 1480 (set_attr "unit" "i387")
1532 (set_attr "mode" "XF")]) 1481 (set_attr "mode" "XF")])
1533 1482
1534 (define_insn_and_split "*cmpxf_cc_i387"
1535 [(set (reg:CCFP FLAGS_REG)
1536 (compare:CCFP
1537 (match_operand:XF 1 "register_operand" "f")
1538 (match_operand:XF 2 "register_operand" "f")))
1539 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1540 "TARGET_80387 && TARGET_SAHF && !TARGET_CMOVE"
1541 "#"
1542 "&& reload_completed"
1543 [(set (match_dup 0)
1544 (unspec:HI
1545 [(compare:CCFP (match_dup 1)(match_dup 2))]
1546 UNSPEC_FNSTSW))
1547 (set (reg:CC FLAGS_REG)
1548 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1549 ""
1550 [(set_attr "type" "multi")
1551 (set_attr "unit" "i387")
1552 (set_attr "mode" "XF")])
1553
1554 (define_insn "*cmp<mode>_i387" 1483 (define_insn "*cmp<mode>_i387"
1555 [(set (match_operand:HI 0 "register_operand" "=a") 1484 [(set (match_operand:HI 0 "register_operand" "=a")
1556 (unspec:HI 1485 (unspec:HI
1557 [(compare:CCFP 1486 [(compare:CCFP
1558 (match_operand:MODEF 1 "register_operand" "f") 1487 (match_operand:MODEF 1 "register_operand" "f")
1559 (match_operand:MODEF 2 "nonimmediate_operand" "fm"))] 1488 (match_operand:MODEF 2 "nonimm_or_0_operand" "fmC"))]
1560 UNSPEC_FNSTSW))] 1489 UNSPEC_FNSTSW))]
1561 "TARGET_80387" 1490 "TARGET_80387"
1562 "* return output_fp_compare (insn, operands, false, false);" 1491 "* return output_fp_compare (insn, operands, false, false);"
1563 [(set_attr "type" "multi") 1492 [(set_attr "type" "multi")
1564 (set_attr "unit" "i387") 1493 (set_attr "unit" "i387")
1565 (set_attr "mode" "<MODE>")]) 1494 (set_attr "mode" "<MODE>")])
1566 1495
1567 (define_insn_and_split "*cmp<mode>_cc_i387"
1568 [(set (reg:CCFP FLAGS_REG)
1569 (compare:CCFP
1570 (match_operand:MODEF 1 "register_operand" "f")
1571 (match_operand:MODEF 2 "nonimmediate_operand" "fm")))
1572 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1573 "TARGET_80387 && TARGET_SAHF && !TARGET_CMOVE"
1574 "#"
1575 "&& reload_completed"
1576 [(set (match_dup 0)
1577 (unspec:HI
1578 [(compare:CCFP (match_dup 1)(match_dup 2))]
1579 UNSPEC_FNSTSW))
1580 (set (reg:CC FLAGS_REG)
1581 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1582 ""
1583 [(set_attr "type" "multi")
1584 (set_attr "unit" "i387")
1585 (set_attr "mode" "<MODE>")])
1586
1587 (define_insn "*cmpu<mode>_i387"
1588 [(set (match_operand:HI 0 "register_operand" "=a")
1589 (unspec:HI
1590 [(compare:CCFPU
1591 (match_operand:X87MODEF 1 "register_operand" "f")
1592 (match_operand:X87MODEF 2 "register_operand" "f"))]
1593 UNSPEC_FNSTSW))]
1594 "TARGET_80387"
1595 "* return output_fp_compare (insn, operands, false, true);"
1596 [(set_attr "type" "multi")
1597 (set_attr "unit" "i387")
1598 (set_attr "mode" "<MODE>")])
1599
1600 (define_insn_and_split "*cmpu<mode>_cc_i387"
1601 [(set (reg:CCFPU FLAGS_REG)
1602 (compare:CCFPU
1603 (match_operand:X87MODEF 1 "register_operand" "f")
1604 (match_operand:X87MODEF 2 "register_operand" "f")))
1605 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1606 "TARGET_80387 && TARGET_SAHF && !TARGET_CMOVE"
1607 "#"
1608 "&& reload_completed"
1609 [(set (match_dup 0)
1610 (unspec:HI
1611 [(compare:CCFPU (match_dup 1)(match_dup 2))]
1612 UNSPEC_FNSTSW))
1613 (set (reg:CC FLAGS_REG)
1614 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1615 ""
1616 [(set_attr "type" "multi")
1617 (set_attr "unit" "i387")
1618 (set_attr "mode" "<MODE>")])
1619
1620 (define_insn "*cmp<X87MODEF:mode>_<SWI24:mode>_i387" 1496 (define_insn "*cmp<X87MODEF:mode>_<SWI24:mode>_i387"
1621 [(set (match_operand:HI 0 "register_operand" "=a") 1497 [(set (match_operand:HI 0 "register_operand" "=a")
1622 (unspec:HI 1498 (unspec:HI
1623 [(compare:CCFP 1499 [(compare:CCFP
1624 (match_operand:X87MODEF 1 "register_operand" "f") 1500 (match_operand:X87MODEF 1 "register_operand" "f")
1625 (float:X87MODEF 1501 (float:X87MODEF
1626 (match_operand:SWI24 2 "memory_operand" "m")))] 1502 (match_operand:SWI24 2 "nonimmediate_operand" "m")))]
1627 UNSPEC_FNSTSW))] 1503 UNSPEC_FNSTSW))]
1628 "TARGET_80387 1504 "TARGET_80387
1629 && (TARGET_USE_<SWI24:MODE>MODE_FIOP 1505 && (TARGET_USE_<SWI24:MODE>MODE_FIOP
1630 || optimize_function_for_size_p (cfun))" 1506 || optimize_function_for_size_p (cfun))"
1631 "* return output_fp_compare (insn, operands, false, false);" 1507 "* return output_fp_compare (insn, operands, false, false);"
1632 [(set_attr "type" "multi") 1508 [(set_attr "type" "multi")
1633 (set_attr "unit" "i387") 1509 (set_attr "unit" "i387")
1634 (set_attr "fp_int_src" "true") 1510 (set_attr "fp_int_src" "true")
1635 (set_attr "mode" "<SWI24:MODE>")]) 1511 (set_attr "mode" "<SWI24:MODE>")])
1636 1512
1637 (define_insn_and_split "*cmp<X87MODEF:mode>_<SWI24:mode>_cc_i387" 1513 (define_insn "*cmpu<mode>_i387"
1638 [(set (reg:CCFP FLAGS_REG) 1514 [(set (match_operand:HI 0 "register_operand" "=a")
1639 (compare:CCFP
1640 (match_operand:X87MODEF 1 "register_operand" "f")
1641 (float:X87MODEF
1642 (match_operand:SWI24 2 "memory_operand" "m"))))
1643 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1644 "TARGET_80387 && TARGET_SAHF && !TARGET_CMOVE
1645 && (TARGET_USE_<SWI24:MODE>MODE_FIOP
1646 || optimize_function_for_size_p (cfun))"
1647 "#"
1648 "&& reload_completed"
1649 [(set (match_dup 0)
1650 (unspec:HI 1515 (unspec:HI
1651 [(compare:CCFP 1516 [(unspec:CCFP
1652 (match_dup 1) 1517 [(compare:CCFP
1653 (float:X87MODEF (match_dup 2)))] 1518 (match_operand:X87MODEF 1 "register_operand" "f")
1654 UNSPEC_FNSTSW)) 1519 (match_operand:X87MODEF 2 "register_operand" "f"))]
1655 (set (reg:CC FLAGS_REG) 1520 UNSPEC_NOTRAP)]
1656 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))] 1521 UNSPEC_FNSTSW))]
1657 "" 1522 "TARGET_80387"
1523 "* return output_fp_compare (insn, operands, false, true);"
1658 [(set_attr "type" "multi") 1524 [(set_attr "type" "multi")
1659 (set_attr "unit" "i387") 1525 (set_attr "unit" "i387")
1660 (set_attr "fp_int_src" "true") 1526 (set_attr "mode" "<MODE>")])
1661 (set_attr "mode" "<SWI24:MODE>")]) 1527
1662 1528 ;; FP compares, step 2:
1663 ;; FP compares, step 2
1664 ;; Move the fpsw to ax.
1665
1666 (define_insn "x86_fnstsw_1"
1667 [(set (match_operand:HI 0 "register_operand" "=a")
1668 (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
1669 "TARGET_80387"
1670 "fnstsw\t%0"
1671 [(set_attr "length" "2")
1672 (set_attr "mode" "SI")
1673 (set_attr "unit" "i387")])
1674
1675 ;; FP compares, step 3
1676 ;; Get ax into flags, general case. 1529 ;; Get ax into flags, general case.
1677 1530
1678 (define_insn "x86_sahf_1" 1531 (define_insn "x86_sahf_1"
1679 [(set (reg:CC FLAGS_REG) 1532 [(set (reg:CC FLAGS_REG)
1680 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 1533 (unspec:CC [(match_operand:HI 0 "register_operand" "a")]
1692 (set_attr "athlon_decode" "vector") 1545 (set_attr "athlon_decode" "vector")
1693 (set_attr "amdfam10_decode" "direct") 1546 (set_attr "amdfam10_decode" "direct")
1694 (set_attr "bdver1_decode" "direct") 1547 (set_attr "bdver1_decode" "direct")
1695 (set_attr "mode" "SI")]) 1548 (set_attr "mode" "SI")])
1696 1549
1697 ;; Pentium Pro can do steps 1 through 3 in one go. 1550 ;; Pentium Pro can do both steps in one go.
1698 ;; (these instructions set flags directly) 1551 ;; (these instructions set flags directly)
1699 1552
1700 (define_mode_iterator FPCMP [CCFP CCFPU]) 1553 (define_subst_attr "unord" "unord_subst" "" "u")
1701 (define_mode_attr unord [(CCFP "") (CCFPU "u")]) 1554 (define_subst_attr "unordered" "unord_subst" "false" "true")
1702 1555
1703 (define_insn "*cmpi<FPCMP:unord><MODEF:mode>" 1556 (define_subst "unord_subst"
1704 [(set (reg:FPCMP FLAGS_REG) 1557 [(set (match_operand:CCFP 0)
1705 (compare:FPCMP 1558 (match_operand:CCFP 1))]
1559 ""
1560 [(set (match_dup 0)
1561 (unspec:CCFP
1562 [(match_dup 1)]
1563 UNSPEC_NOTRAP))])
1564
1565 (define_insn "*cmpi<unord>xf_i387"
1566 [(set (reg:CCFP FLAGS_REG)
1567 (compare:CCFP
1568 (match_operand:XF 0 "register_operand" "f")
1569 (match_operand:XF 1 "register_operand" "f")))]
1570 "TARGET_80387 && TARGET_CMOVE"
1571 "* return output_fp_compare (insn, operands, true, <unordered>);"
1572 [(set_attr "type" "fcmp")
1573 (set_attr "mode" "XF")
1574 (set_attr "athlon_decode" "vector")
1575 (set_attr "amdfam10_decode" "direct")
1576 (set_attr "bdver1_decode" "double")
1577 (set_attr "znver1_decode" "double")])
1578
1579 (define_insn "*cmpi<unord><MODEF:mode>"
1580 [(set (reg:CCFP FLAGS_REG)
1581 (compare:CCFP
1706 (match_operand:MODEF 0 "register_operand" "f,v") 1582 (match_operand:MODEF 0 "register_operand" "f,v")
1707 (match_operand:MODEF 1 "register_ssemem_operand" "f,vm")))] 1583 (match_operand:MODEF 1 "register_ssemem_operand" "f,vm")))]
1708 "(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH) 1584 "(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
1709 || (TARGET_80387 && TARGET_CMOVE)" 1585 || (TARGET_80387 && TARGET_CMOVE)"
1710 "@ 1586 "@
1711 * return output_fp_compare (insn, operands, true, \ 1587 * return output_fp_compare (insn, operands, true, <unordered>);
1712 <FPCMP:MODE>mode == CCFPUmode); 1588 %v<unord>comi<MODEF:ssemodesuffix>\t{%1, %0|%0, %1}"
1713 %v<FPCMP:unord>comi<MODEF:ssemodesuffix>\t{%1, %0|%0, %1}"
1714 [(set_attr "type" "fcmp,ssecomi") 1589 [(set_attr "type" "fcmp,ssecomi")
1715 (set_attr "prefix" "orig,maybe_vex") 1590 (set_attr "prefix" "orig,maybe_vex")
1716 (set_attr "mode" "<MODEF:MODE>") 1591 (set_attr "mode" "<MODEF:MODE>")
1717 (set_attr "prefix_rep" "*,0") 1592 (set_attr "prefix_rep" "*,0")
1718 (set (attr "prefix_data16") 1593 (set (attr "prefix_data16")
1735 (symbol_ref "true")) 1610 (symbol_ref "true"))
1736 (if_then_else 1611 (if_then_else
1737 (eq_attr "alternative" "0") 1612 (eq_attr "alternative" "0")
1738 (symbol_ref "true") 1613 (symbol_ref "true")
1739 (symbol_ref "false"))))]) 1614 (symbol_ref "false"))))])
1740
1741 (define_insn "*cmpi<unord>xf_i387"
1742 [(set (reg:FPCMP FLAGS_REG)
1743 (compare:FPCMP
1744 (match_operand:XF 0 "register_operand" "f")
1745 (match_operand:XF 1 "register_operand" "f")))]
1746 "TARGET_80387 && TARGET_CMOVE"
1747 "* return output_fp_compare (insn, operands, true,
1748 <MODE>mode == CCFPUmode);"
1749 [(set_attr "type" "fcmp")
1750 (set_attr "mode" "XF")
1751 (set_attr "athlon_decode" "vector")
1752 (set_attr "amdfam10_decode" "direct")
1753 (set_attr "bdver1_decode" "double")
1754 (set_attr "znver1_decode" "double")])
1755 1615
1756 ;; Push/pop instructions. 1616 ;; Push/pop instructions.
1757 1617
1758 (define_insn "*push<mode>2" 1618 (define_insn "*push<mode>2"
1759 [(set (match_operand:DWI 0 "push_operand" "=<") 1619 [(set (match_operand:DWI 0 "push_operand" "=<")
1987 (match_operand:SWI48 1 "const0_operand")) 1847 (match_operand:SWI48 1 "const0_operand"))
1988 (clobber (reg:CC FLAGS_REG))] 1848 (clobber (reg:CC FLAGS_REG))]
1989 "reload_completed" 1849 "reload_completed"
1990 "xor{l}\t%k0, %k0" 1850 "xor{l}\t%k0, %k0"
1991 [(set_attr "type" "alu1") 1851 [(set_attr "type" "alu1")
1992 (set_attr "modrm_class" "op0")
1993 (set_attr "mode" "SI") 1852 (set_attr "mode" "SI")
1994 (set_attr "length_immediate" "0")]) 1853 (set_attr "length_immediate" "0")])
1995 1854
1996 (define_insn "*mov<mode>_or" 1855 (define_insn "*mov<mode>_or"
1997 [(set (match_operand:SWI48 0 "register_operand" "=r") 1856 [(set (match_operand:SWI48 0 "register_operand" "=r")
2011 || register_operand (operands[1], XImode))" 1870 || register_operand (operands[1], XImode))"
2012 { 1871 {
2013 switch (get_attr_type (insn)) 1872 switch (get_attr_type (insn))
2014 { 1873 {
2015 case TYPE_SSELOG1: 1874 case TYPE_SSELOG1:
2016 return standard_sse_constant_opcode (insn, operands[1]); 1875 return standard_sse_constant_opcode (insn, operands);
2017 1876
2018 case TYPE_SSEMOV: 1877 case TYPE_SSEMOV:
2019 if (misaligned_operand (operands[0], XImode) 1878 if (misaligned_operand (operands[0], XImode)
2020 || misaligned_operand (operands[1], XImode)) 1879 || misaligned_operand (operands[1], XImode))
2021 return "vmovdqu32\t{%1, %0|%0, %1}"; 1880 return "vmovdqu32\t{%1, %0|%0, %1}";
2038 || register_operand (operands[1], OImode))" 1897 || register_operand (operands[1], OImode))"
2039 { 1898 {
2040 switch (get_attr_type (insn)) 1899 switch (get_attr_type (insn))
2041 { 1900 {
2042 case TYPE_SSELOG1: 1901 case TYPE_SSELOG1:
2043 return standard_sse_constant_opcode (insn, operands[1]); 1902 return standard_sse_constant_opcode (insn, operands);
2044 1903
2045 case TYPE_SSEMOV: 1904 case TYPE_SSEMOV:
2046 if (misaligned_operand (operands[0], OImode) 1905 if (misaligned_operand (operands[0], OImode)
2047 || misaligned_operand (operands[1], OImode)) 1906 || misaligned_operand (operands[1], OImode))
2048 { 1907 {
2084 ] 1943 ]
2085 (const_string "OI")))]) 1944 (const_string "OI")))])
2086 1945
2087 (define_insn "*movti_internal" 1946 (define_insn "*movti_internal"
2088 [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,v,v ,v ,m,?r,?Yd") 1947 [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,v,v ,v ,m,?r,?Yd")
2089 (match_operand:TI 1 "general_operand" "riFo,re,C,BC,vm,v,Ye,r"))] 1948 (match_operand:TI 1 "general_operand" "riFo,re,C,BC,vm,v,Yd,r"))]
2090 "(TARGET_64BIT 1949 "(TARGET_64BIT
2091 && !(MEM_P (operands[0]) && MEM_P (operands[1]))) 1950 && !(MEM_P (operands[0]) && MEM_P (operands[1])))
2092 || (TARGET_SSE 1951 || (TARGET_SSE
2093 && nonimmediate_or_sse_const_operand (operands[1], TImode) 1952 && nonimmediate_or_sse_const_operand (operands[1], TImode)
2094 && (register_operand (operands[0], TImode) 1953 && (register_operand (operands[0], TImode)
2098 { 1957 {
2099 case TYPE_MULTI: 1958 case TYPE_MULTI:
2100 return "#"; 1959 return "#";
2101 1960
2102 case TYPE_SSELOG1: 1961 case TYPE_SSELOG1:
2103 return standard_sse_constant_opcode (insn, operands[1]); 1962 return standard_sse_constant_opcode (insn, operands);
2104 1963
2105 case TYPE_SSEMOV: 1964 case TYPE_SSEMOV:
2106 /* TDmode values are passed as TImode on the stack. Moving them 1965 /* TDmode values are passed as TImode on the stack. Moving them
2107 to stack may result in unaligned memory access. */ 1966 to stack may result in unaligned memory access. */
2108 if (misaligned_operand (operands[0], TImode) 1967 if (misaligned_operand (operands[0], TImode)
2164 (match_test "TARGET_AVX") 2023 (match_test "TARGET_AVX")
2165 (const_string "TI") 2024 (const_string "TI")
2166 (match_test "optimize_function_for_size_p (cfun)") 2025 (match_test "optimize_function_for_size_p (cfun)")
2167 (const_string "V4SF") 2026 (const_string "V4SF")
2168 ] 2027 ]
2169 (const_string "TI")))]) 2028 (const_string "TI")))
2029 (set (attr "preferred_for_speed")
2030 (cond [(eq_attr "alternative" "6")
2031 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
2032 (eq_attr "alternative" "7")
2033 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
2034 ]
2035 (symbol_ref "true")))])
2170 2036
2171 (define_split 2037 (define_split
2172 [(set (match_operand:TI 0 "sse_reg_operand") 2038 [(set (match_operand:TI 0 "sse_reg_operand")
2173 (match_operand:TI 1 "general_reg_operand"))] 2039 (match_operand:TI 1 "general_reg_operand"))]
2174 "TARGET_64BIT && TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_TO_VEC 2040 "TARGET_64BIT && TARGET_SSE4_1
2175 && reload_completed" 2041 && reload_completed"
2176 [(set (match_dup 2) 2042 [(set (match_dup 2)
2177 (vec_merge:V2DI 2043 (vec_merge:V2DI
2178 (vec_duplicate:V2DI (match_dup 3)) 2044 (vec_duplicate:V2DI (match_dup 3))
2179 (match_dup 2) 2045 (match_dup 2)
2186 gen_lowpart (DImode, operands[1])); 2052 gen_lowpart (DImode, operands[1]));
2187 }) 2053 })
2188 2054
2189 (define_insn "*movdi_internal" 2055 (define_insn "*movdi_internal"
2190 [(set (match_operand:DI 0 "nonimmediate_operand" 2056 [(set (match_operand:DI 0 "nonimmediate_operand"
2191 "=r ,o ,r,r ,r,m ,*y,*y,?*y,?m,?r ,?*Ym,*v,*v,*v,m ,m,?r ,?*Yd,?r ,?*Yi,?*Ym,?*Yi,*k,*k ,*r,*m") 2057 "=r ,o ,r,r ,r,m ,*y,*y,?*y,?m,?r,?*y,*v,*v,*v,m ,m,?r ,?*Yd,?r,?*v,?*y,?*x,*k,*k ,*r,*m")
2192 (match_operand:DI 1 "general_operand" 2058 (match_operand:DI 1 "general_operand"
2193 "riFo,riF,Z,rem,i,re,C ,*y,m ,*y,*Yn,r ,C ,*v,m ,*v,v,*Ye,r ,*Yj,r ,*Yj ,*Yn ,*r,*km,*k,*k"))] 2059 "riFo,riF,Z,rem,i,re,C ,*y,m ,*y,*y,r ,C ,*v,m ,*v,v,*Yd,r ,*v,r ,*x ,*y ,*r,*km,*k,*k"))]
2194 "!(MEM_P (operands[0]) && MEM_P (operands[1]))" 2060 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
2195 { 2061 {
2196 switch (get_attr_type (insn)) 2062 switch (get_attr_type (insn))
2197 { 2063 {
2198 case TYPE_MSKMOV: 2064 case TYPE_MSKMOV:
2210 && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) 2076 && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
2211 return "movd\t{%1, %0|%0, %1}"; 2077 return "movd\t{%1, %0|%0, %1}";
2212 return "movq\t{%1, %0|%0, %1}"; 2078 return "movq\t{%1, %0|%0, %1}";
2213 2079
2214 case TYPE_SSELOG1: 2080 case TYPE_SSELOG1:
2215 return standard_sse_constant_opcode (insn, operands[1]); 2081 return standard_sse_constant_opcode (insn, operands);
2216 2082
2217 case TYPE_SSEMOV: 2083 case TYPE_SSEMOV:
2218 switch (get_attr_mode (insn)) 2084 switch (get_attr_mode (insn))
2219 { 2085 {
2220 case MODE_DI: 2086 case MODE_DI:
2221 /* Handle broken assemblers that require movd instead of movq. */ 2087 /* Handle broken assemblers that require movd instead of movq. */
2222 if (!HAVE_AS_IX86_INTERUNIT_MOVQ 2088 if (!HAVE_AS_IX86_INTERUNIT_MOVQ
2223 && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) 2089 && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
2224 return "%vmovd\t{%1, %0|%0, %1}"; 2090 return "%vmovd\t{%1, %0|%0, %1}";
2225 return "%vmovq\t{%1, %0|%0, %1}"; 2091 return "%vmovq\t{%1, %0|%0, %1}";
2092
2226 case MODE_TI: 2093 case MODE_TI:
2094 /* Handle AVX512 registers set. */
2095 if (EXT_REX_SSE_REG_P (operands[0])
2096 || EXT_REX_SSE_REG_P (operands[1]))
2097 return "vmovdqa64\t{%1, %0|%0, %1}";
2227 return "%vmovdqa\t{%1, %0|%0, %1}"; 2098 return "%vmovdqa\t{%1, %0|%0, %1}";
2228 case MODE_XI:
2229 return "vmovdqa64\t{%g1, %g0|%g0, %g1}";
2230 2099
2231 case MODE_V2SF: 2100 case MODE_V2SF:
2232 gcc_assert (!TARGET_AVX); 2101 gcc_assert (!TARGET_AVX);
2233 return "movlps\t{%1, %0|%0, %1}"; 2102 return "movlps\t{%1, %0|%0, %1}";
2234 case MODE_V4SF: 2103 case MODE_V4SF:
2263 } 2132 }
2264 } 2133 }
2265 [(set (attr "isa") 2134 [(set (attr "isa")
2266 (cond [(eq_attr "alternative" "0,1,17,18") 2135 (cond [(eq_attr "alternative" "0,1,17,18")
2267 (const_string "nox64") 2136 (const_string "nox64")
2268 (eq_attr "alternative" "2,3,4,5,10,11,19,20,23,25") 2137 (eq_attr "alternative" "2,3,4,5,10,11,23,25")
2269 (const_string "x64") 2138 (const_string "x64")
2139 (eq_attr "alternative" "19,20")
2140 (const_string "x64_sse2")
2141 (eq_attr "alternative" "21,22")
2142 (const_string "sse2")
2270 ] 2143 ]
2271 (const_string "*"))) 2144 (const_string "*")))
2272 (set (attr "type") 2145 (set (attr "type")
2273 (cond [(eq_attr "alternative" "0,1,17,18") 2146 (cond [(eq_attr "alternative" "0,1,17,18")
2274 (const_string "multi") 2147 (const_string "multi")
2316 (cond [(eq_attr "alternative" "2") 2189 (cond [(eq_attr "alternative" "2")
2317 (const_string "SI") 2190 (const_string "SI")
2318 (eq_attr "alternative" "12,13") 2191 (eq_attr "alternative" "12,13")
2319 (cond [(ior (match_operand 0 "ext_sse_reg_operand") 2192 (cond [(ior (match_operand 0 "ext_sse_reg_operand")
2320 (match_operand 1 "ext_sse_reg_operand")) 2193 (match_operand 1 "ext_sse_reg_operand"))
2321 (const_string "XI") 2194 (const_string "TI")
2322 (ior (not (match_test "TARGET_SSE2")) 2195 (ior (not (match_test "TARGET_SSE2"))
2323 (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")) 2196 (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
2324 (const_string "V4SF") 2197 (const_string "V4SF")
2325 (match_test "TARGET_AVX") 2198 (match_test "TARGET_AVX")
2326 (const_string "TI") 2199 (const_string "TI")
2332 (and (eq_attr "alternative" "14,15,16") 2205 (and (eq_attr "alternative" "14,15,16")
2333 (not (match_test "TARGET_SSE2"))) 2206 (not (match_test "TARGET_SSE2")))
2334 (const_string "V2SF") 2207 (const_string "V2SF")
2335 ] 2208 ]
2336 (const_string "DI"))) 2209 (const_string "DI")))
2210 (set (attr "preferred_for_speed")
2211 (cond [(eq_attr "alternative" "10,17,19")
2212 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
2213 (eq_attr "alternative" "11,18,20")
2214 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
2215 ]
2216 (symbol_ref "true")))
2337 (set (attr "enabled") 2217 (set (attr "enabled")
2338 (cond [(eq_attr "alternative" "15") 2218 (cond [(eq_attr "alternative" "15")
2339 (if_then_else 2219 (if_then_else
2340 (match_test "TARGET_STV && TARGET_SSE2") 2220 (match_test "TARGET_STV && TARGET_SSE2")
2341 (symbol_ref "false") 2221 (symbol_ref "false")
2349 (const_string "*")))]) 2229 (const_string "*")))])
2350 2230
2351 (define_split 2231 (define_split
2352 [(set (match_operand:<DWI> 0 "general_reg_operand") 2232 [(set (match_operand:<DWI> 0 "general_reg_operand")
2353 (match_operand:<DWI> 1 "sse_reg_operand"))] 2233 (match_operand:<DWI> 1 "sse_reg_operand"))]
2354 "TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_FROM_VEC 2234 "TARGET_SSE4_1
2355 && reload_completed" 2235 && reload_completed"
2356 [(set (match_dup 2) 2236 [(set (match_dup 2)
2357 (vec_select:DWIH 2237 (vec_select:DWIH
2358 (match_dup 3) 2238 (match_dup 3)
2359 (parallel [(const_int 1)])))] 2239 (parallel [(const_int 1)])))]
2373 "ix86_split_long_move (operands); DONE;") 2253 "ix86_split_long_move (operands); DONE;")
2374 2254
2375 (define_split 2255 (define_split
2376 [(set (match_operand:DI 0 "sse_reg_operand") 2256 [(set (match_operand:DI 0 "sse_reg_operand")
2377 (match_operand:DI 1 "general_reg_operand"))] 2257 (match_operand:DI 1 "general_reg_operand"))]
2378 "!TARGET_64BIT && TARGET_SSE4_1 && TARGET_INTER_UNIT_MOVES_TO_VEC 2258 "!TARGET_64BIT && TARGET_SSE4_1
2379 && reload_completed" 2259 && reload_completed"
2380 [(set (match_dup 2) 2260 [(set (match_dup 2)
2381 (vec_merge:V4SI 2261 (vec_merge:V4SI
2382 (vec_duplicate:V4SI (match_dup 3)) 2262 (vec_duplicate:V4SI (match_dup 3))
2383 (match_dup 2) 2263 (match_dup 2)
2412 operands[2] = gen_int_mode (shift, QImode); 2292 operands[2] = gen_int_mode (shift, QImode);
2413 }) 2293 })
2414 2294
2415 (define_insn "*movsi_internal" 2295 (define_insn "*movsi_internal"
2416 [(set (match_operand:SI 0 "nonimmediate_operand" 2296 [(set (match_operand:SI 0 "nonimmediate_operand"
2417 "=r,m ,*y,*y,?*y,?m,?r ,?*Ym,*v,*v,*v,m ,?r ,?*Yi,*k,*k ,*rm") 2297 "=r,m ,*y,*y,?*y,?m,?r,?*y,*v,*v,*v,m ,?r,?*v,*k,*k ,*rm")
2418 (match_operand:SI 1 "general_operand" 2298 (match_operand:SI 1 "general_operand"
2419 "g ,re,C ,*y,m ,*y,*Yn,r ,C ,*v,m ,*v,*Yj,r ,*r,*km,*k"))] 2299 "g ,re,C ,*y,m ,*y,*y,r ,C ,*v,m ,*v,*v,r ,*r,*km,*k"))]
2420 "!(MEM_P (operands[0]) && MEM_P (operands[1]))" 2300 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
2421 { 2301 {
2422 switch (get_attr_type (insn)) 2302 switch (get_attr_type (insn))
2423 { 2303 {
2424 case TYPE_SSELOG1: 2304 case TYPE_SSELOG1:
2425 return standard_sse_constant_opcode (insn, operands[1]); 2305 return standard_sse_constant_opcode (insn, operands);
2426 2306
2427 case TYPE_MSKMOV: 2307 case TYPE_MSKMOV:
2428 return "kmovd\t{%1, %0|%0, %1}"; 2308 return "kmovd\t{%1, %0|%0, %1}";
2429 2309
2430 case TYPE_SSEMOV: 2310 case TYPE_SSEMOV:
2475 2355
2476 default: 2356 default:
2477 gcc_unreachable (); 2357 gcc_unreachable ();
2478 } 2358 }
2479 } 2359 }
2480 [(set (attr "type") 2360 [(set (attr "isa")
2361 (cond [(eq_attr "alternative" "12,13")
2362 (const_string "sse2")
2363 ]
2364 (const_string "*")))
2365 (set (attr "type")
2481 (cond [(eq_attr "alternative" "2") 2366 (cond [(eq_attr "alternative" "2")
2482 (const_string "mmx") 2367 (const_string "mmx")
2483 (eq_attr "alternative" "3,4,5,6,7") 2368 (eq_attr "alternative" "3,4,5,6,7")
2484 (const_string "mmxmov") 2369 (const_string "mmxmov")
2485 (eq_attr "alternative" "8") 2370 (eq_attr "alternative" "8")
2520 2405
2521 (and (eq_attr "alternative" "10,11") 2406 (and (eq_attr "alternative" "10,11")
2522 (not (match_test "TARGET_SSE2"))) 2407 (not (match_test "TARGET_SSE2")))
2523 (const_string "SF") 2408 (const_string "SF")
2524 ] 2409 ]
2525 (const_string "SI")))]) 2410 (const_string "SI")))
2411 (set (attr "preferred_for_speed")
2412 (cond [(eq_attr "alternative" "6,12")
2413 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
2414 (eq_attr "alternative" "7,13")
2415 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
2416 ]
2417 (symbol_ref "true")))])
2526 2418
2527 (define_insn "*movhi_internal" 2419 (define_insn "*movhi_internal"
2528 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r ,r ,m ,k,k ,r,m") 2420 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r ,r ,m ,k,k ,r,m")
2529 (match_operand:HI 1 "general_operand" "r ,rn,rm,rn,r,km,k,k"))] 2421 (match_operand:HI 1 "general_operand" "r ,rn,rm,rn,r,km,k,k"))]
2530 "!(MEM_P (operands[0]) && MEM_P (operands[1]))" 2422 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
2839 (match_operand:SWI12 1 "const0_operand")) 2731 (match_operand:SWI12 1 "const0_operand"))
2840 (clobber (reg:CC FLAGS_REG))] 2732 (clobber (reg:CC FLAGS_REG))]
2841 "reload_completed" 2733 "reload_completed"
2842 "xor{<imodesuffix>}\t%0, %0" 2734 "xor{<imodesuffix>}\t%0, %0"
2843 [(set_attr "type" "alu1") 2735 [(set_attr "type" "alu1")
2844 (set_attr "modrm_class" "op0")
2845 (set_attr "mode" "<MODE>") 2736 (set_attr "mode" "<MODE>")
2846 (set_attr "length_immediate" "0")]) 2737 (set_attr "length_immediate" "0")])
2847 2738
2848 (define_expand "extv<mode>" 2739 (define_expand "extv<mode>"
2849 [(set (match_operand:SWI24 0 "register_operand") 2740 [(set (match_operand:SWI24 0 "register_operand")
3291 && memory_operand (operands[0], TFmode)))" 3182 && memory_operand (operands[0], TFmode)))"
3292 { 3183 {
3293 switch (get_attr_type (insn)) 3184 switch (get_attr_type (insn))
3294 { 3185 {
3295 case TYPE_SSELOG1: 3186 case TYPE_SSELOG1:
3296 return standard_sse_constant_opcode (insn, operands[1]); 3187 return standard_sse_constant_opcode (insn, operands);
3297 3188
3298 case TYPE_SSEMOV: 3189 case TYPE_SSEMOV:
3299 /* Handle misaligned load/store since we 3190 /* Handle misaligned load/store since we
3300 don't have movmisaligntf pattern. */ 3191 don't have movmisaligntf pattern. */
3301 if (misaligned_operand (operands[0], TFmode) 3192 if (misaligned_operand (operands[0], TFmode)
3432 "ix86_split_long_move (operands); DONE;") 3323 "ix86_split_long_move (operands); DONE;")
3433 3324
3434 ;; Possible store forwarding (partial memory) stall in alternatives 4, 6 and 7. 3325 ;; Possible store forwarding (partial memory) stall in alternatives 4, 6 and 7.
3435 (define_insn "*movdf_internal" 3326 (define_insn "*movdf_internal"
3436 [(set (match_operand:DF 0 "nonimmediate_operand" 3327 [(set (match_operand:DF 0 "nonimmediate_operand"
3437 "=Yf*f,m ,Yf*f,?r ,!o,?*r ,!o,!o,?r,?m,?r,?r,v,v,v,m,*x,*x,*x,m ,r ,Yi,r ,o ,r ,m") 3328 "=Yf*f,m ,Yf*f,?r ,!o,?*r ,!o,!o,?r,?m,?r,?r,v,v,v,m,*x,*x,*x,m ,r ,v,r ,o ,r ,m")
3438 (match_operand:DF 1 "general_operand" 3329 (match_operand:DF 1 "general_operand"
3439 "Yf*fm,Yf*f,G ,roF,r ,*roF,*r,F ,rm,rC,C ,F ,C,v,m,v,C ,*x,m ,*x,Yj,r ,roF,rF,rmF,rC"))] 3330 "Yf*fm,Yf*f,G ,roF,r ,*roF,*r,F ,rm,rC,C ,F ,C,v,m,v,C ,*x,m ,*x,v,r ,roF,rF,rmF,rC"))]
3440 "!(MEM_P (operands[0]) && MEM_P (operands[1])) 3331 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
3441 && (lra_in_progress || reload_completed 3332 && (lra_in_progress || reload_completed
3442 || !CONST_DOUBLE_P (operands[1]) 3333 || !CONST_DOUBLE_P (operands[1])
3443 || ((optimize_function_for_size_p (cfun) 3334 || ((optimize_function_for_size_p (cfun)
3444 || (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)) 3335 || (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC))
3468 return "movabs{q}\t{%1, %0|%0, %1}"; 3359 return "movabs{q}\t{%1, %0|%0, %1}";
3469 else 3360 else
3470 return "mov{q}\t{%1, %0|%0, %1}"; 3361 return "mov{q}\t{%1, %0|%0, %1}";
3471 3362
3472 case TYPE_SSELOG1: 3363 case TYPE_SSELOG1:
3473 return standard_sse_constant_opcode (insn, operands[1]); 3364 return standard_sse_constant_opcode (insn, operands);
3474 3365
3475 case TYPE_SSEMOV: 3366 case TYPE_SSEMOV:
3476 switch (get_attr_mode (insn)) 3367 switch (get_attr_mode (insn))
3477 { 3368 {
3478 case MODE_DF: 3369 case MODE_DF:
3479 if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1])) 3370 if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
3480 return "vmovsd\t{%1, %0, %0|%0, %0, %1}"; 3371 return "vmovsd\t{%d1, %0|%0, %d1}";
3481 return "%vmovsd\t{%1, %0|%0, %1}"; 3372 return "%vmovsd\t{%1, %0|%0, %1}";
3482 3373
3483 case MODE_V4SF: 3374 case MODE_V4SF:
3484 return "%vmovaps\t{%1, %0|%0, %1}"; 3375 return "%vmovaps\t{%1, %0|%0, %1}";
3485 case MODE_V8DF: 3376 case MODE_V8DF:
3510 } 3401 }
3511 } 3402 }
3512 [(set (attr "isa") 3403 [(set (attr "isa")
3513 (cond [(eq_attr "alternative" "3,4,5,6,7,22,23") 3404 (cond [(eq_attr "alternative" "3,4,5,6,7,22,23")
3514 (const_string "nox64") 3405 (const_string "nox64")
3515 (eq_attr "alternative" "8,9,10,11,20,21,24,25") 3406 (eq_attr "alternative" "8,9,10,11,24,25")
3516 (const_string "x64") 3407 (const_string "x64")
3517 (eq_attr "alternative" "12,13,14,15") 3408 (eq_attr "alternative" "12,13,14,15")
3518 (const_string "sse2") 3409 (const_string "sse2")
3410 (eq_attr "alternative" "20,21")
3411 (const_string "x64_sse2")
3519 ] 3412 ]
3520 (const_string "*"))) 3413 (const_string "*")))
3521 (set (attr "type") 3414 (set (attr "type")
3522 (cond [(eq_attr "alternative" "0,1,2") 3415 (cond [(eq_attr "alternative" "0,1,2")
3523 (const_string "fmov") 3416 (const_string "fmov")
3614 (cond [(eq_attr "alternative" "3,4") 3507 (cond [(eq_attr "alternative" "3,4")
3615 (symbol_ref "false")] 3508 (symbol_ref "false")]
3616 (symbol_ref "true"))) 3509 (symbol_ref "true")))
3617 (set (attr "preferred_for_speed") 3510 (set (attr "preferred_for_speed")
3618 (cond [(eq_attr "alternative" "3,4") 3511 (cond [(eq_attr "alternative" "3,4")
3619 (symbol_ref "TARGET_INTEGER_DFMODE_MOVES")] 3512 (symbol_ref "TARGET_INTEGER_DFMODE_MOVES")
3513 (eq_attr "alternative" "20")
3514 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
3515 (eq_attr "alternative" "21")
3516 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
3517 ]
3620 (symbol_ref "true"))) 3518 (symbol_ref "true")))
3621 (set (attr "enabled") 3519 (set (attr "enabled")
3622 (cond [(eq_attr "alternative" "22,23,24,25") 3520 (cond [(eq_attr "alternative" "22,23,24,25")
3623 (if_then_else 3521 (if_then_else
3624 (match_test "TARGET_HARD_DF_REGS") 3522 (match_test "TARGET_HARD_DF_REGS")
3636 [(const_int 0)] 3534 [(const_int 0)]
3637 "ix86_split_long_move (operands); DONE;") 3535 "ix86_split_long_move (operands); DONE;")
3638 3536
3639 (define_insn "*movsf_internal" 3537 (define_insn "*movsf_internal"
3640 [(set (match_operand:SF 0 "nonimmediate_operand" 3538 [(set (match_operand:SF 0 "nonimmediate_operand"
3641 "=Yf*f,m ,Yf*f,?r ,?m,v,v,v,m,?r,?Yi,!*y,!*y,!m,!r ,!*Ym,r ,m") 3539 "=Yf*f,m ,Yf*f,?r ,?m,v,v,v,m,?r,?v,!*y,!*y,!m,!r,!*y,r ,m")
3642 (match_operand:SF 1 "general_operand" 3540 (match_operand:SF 1 "general_operand"
3643 "Yf*fm,Yf*f,G ,rmF,rF,C,v,m,v,Yj,r ,*y ,m ,*y,*Yn,r ,rmF,rF"))] 3541 "Yf*fm,Yf*f,G ,rmF,rF,C,v,m,v,v ,r ,*y ,m ,*y,*y,r ,rmF,rF"))]
3644 "!(MEM_P (operands[0]) && MEM_P (operands[1])) 3542 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
3645 && (lra_in_progress || reload_completed 3543 && (lra_in_progress || reload_completed
3646 || !CONST_DOUBLE_P (operands[1]) 3544 || !CONST_DOUBLE_P (operands[1])
3647 || ((optimize_function_for_size_p (cfun) 3545 || ((optimize_function_for_size_p (cfun)
3648 || (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)) 3546 || (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC))
3662 3560
3663 case TYPE_IMOV: 3561 case TYPE_IMOV:
3664 return "mov{l}\t{%1, %0|%0, %1}"; 3562 return "mov{l}\t{%1, %0|%0, %1}";
3665 3563
3666 case TYPE_SSELOG1: 3564 case TYPE_SSELOG1:
3667 return standard_sse_constant_opcode (insn, operands[1]); 3565 return standard_sse_constant_opcode (insn, operands);
3668 3566
3669 case TYPE_SSEMOV: 3567 case TYPE_SSEMOV:
3670 switch (get_attr_mode (insn)) 3568 switch (get_attr_mode (insn))
3671 { 3569 {
3672 case MODE_SF: 3570 case MODE_SF:
3673 if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1])) 3571 if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
3674 return "vmovss\t{%1, %0, %0|%0, %0, %1}"; 3572 return "vmovss\t{%d1, %0|%0, %d1}";
3675 return "%vmovss\t{%1, %0|%0, %1}"; 3573 return "%vmovss\t{%1, %0|%0, %1}";
3676 3574
3677 case MODE_V16SF: 3575 case MODE_V16SF:
3678 return "vmovaps\t{%g1, %g0|%g0, %g1}"; 3576 return "vmovaps\t{%g1, %g0|%g0, %g1}";
3679 case MODE_V4SF: 3577 case MODE_V4SF:
3700 3598
3701 default: 3599 default:
3702 gcc_unreachable (); 3600 gcc_unreachable ();
3703 } 3601 }
3704 } 3602 }
3705 [(set (attr "type") 3603 [(set (attr "isa")
3604 (cond [(eq_attr "alternative" "14,15")
3605 (const_string "sse2")
3606 ]
3607 (const_string "*")))
3608 (set (attr "type")
3706 (cond [(eq_attr "alternative" "0,1,2") 3609 (cond [(eq_attr "alternative" "0,1,2")
3707 (const_string "fmov") 3610 (const_string "fmov")
3708 (eq_attr "alternative" "3,4,16,17") 3611 (eq_attr "alternative" "3,4,16,17")
3709 (const_string "imov") 3612 (const_string "imov")
3710 (eq_attr "alternative" "5") 3613 (eq_attr "alternative" "5")
3762 (const_string "V4SF") 3665 (const_string "V4SF")
3763 ] 3666 ]
3764 (const_string "SF")) 3667 (const_string "SF"))
3765 ] 3668 ]
3766 (const_string "SF"))) 3669 (const_string "SF")))
3670 (set (attr "preferred_for_speed")
3671 (cond [(eq_attr "alternative" "9,14")
3672 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
3673 (eq_attr "alternative" "10,15")
3674 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
3675 ]
3676 (symbol_ref "true")))
3767 (set (attr "enabled") 3677 (set (attr "enabled")
3768 (cond [(eq_attr "alternative" "16,17") 3678 (cond [(eq_attr "alternative" "16,17")
3769 (if_then_else 3679 (if_then_else
3770 (match_test "TARGET_HARD_SF_REGS") 3680 (match_test "TARGET_HARD_SF_REGS")
3771 (symbol_ref "false") 3681 (symbol_ref "false")
3775 ] 3685 ]
3776 (const_string "*")))]) 3686 (const_string "*")))])
3777 3687
3778 (define_split 3688 (define_split
3779 [(set (match_operand 0 "any_fp_register_operand") 3689 [(set (match_operand 0 "any_fp_register_operand")
3780 (match_operand 1 "nonimmediate_operand"))] 3690 (match_operand 1 "memory_operand"))]
3781 "reload_completed 3691 "reload_completed
3782 && (GET_MODE (operands[0]) == TFmode 3692 && (GET_MODE (operands[0]) == TFmode
3783 || GET_MODE (operands[0]) == XFmode 3693 || GET_MODE (operands[0]) == XFmode
3784 || GET_MODE (operands[0]) == DFmode 3694 || GET_MODE (operands[0]) == DFmode
3785 || GET_MODE (operands[0]) == SFmode) 3695 || GET_MODE (operands[0]) == SFmode)
3787 [(set (match_dup 0) (match_dup 2))] 3697 [(set (match_dup 0) (match_dup 2))]
3788 "operands[2] = find_constant_src (curr_insn);") 3698 "operands[2] = find_constant_src (curr_insn);")
3789 3699
3790 (define_split 3700 (define_split
3791 [(set (match_operand 0 "any_fp_register_operand") 3701 [(set (match_operand 0 "any_fp_register_operand")
3792 (float_extend (match_operand 1 "nonimmediate_operand")))] 3702 (float_extend (match_operand 1 "memory_operand")))]
3793 "reload_completed 3703 "reload_completed
3794 && (GET_MODE (operands[0]) == TFmode 3704 && (GET_MODE (operands[0]) == TFmode
3795 || GET_MODE (operands[0]) == XFmode 3705 || GET_MODE (operands[0]) == XFmode
3796 || GET_MODE (operands[0]) == DFmode) 3706 || GET_MODE (operands[0]) == DFmode)
3797 && ix86_standard_x87sse_constant_load_p (insn, operands[0])" 3707 && ix86_standard_x87sse_constant_load_p (insn, operands[0])"
3813 operands[1] = CONST0_RTX (<MODE>mode); 3723 operands[1] = CONST0_RTX (<MODE>mode);
3814 else 3724 else
3815 operands[1] = CONST1_RTX (<MODE>mode); 3725 operands[1] = CONST1_RTX (<MODE>mode);
3816 }) 3726 })
3817 3727
3818 (define_insn "swapxf" 3728 (define_insn "*swapxf"
3819 [(set (match_operand:XF 0 "register_operand" "+f") 3729 [(set (match_operand:XF 0 "register_operand" "+f")
3820 (match_operand:XF 1 "register_operand" "+f")) 3730 (match_operand:XF 1 "register_operand" "+f"))
3821 (set (match_dup 1) 3731 (set (match_dup 1)
3822 (match_dup 0))] 3732 (match_dup 0))]
3823 "TARGET_80387" 3733 "TARGET_80387"
3827 else 3737 else
3828 return "fxch\t%0"; 3738 return "fxch\t%0";
3829 } 3739 }
3830 [(set_attr "type" "fxch") 3740 [(set_attr "type" "fxch")
3831 (set_attr "mode" "XF")]) 3741 (set_attr "mode" "XF")])
3832
3833 (define_insn "*swap<mode>"
3834 [(set (match_operand:MODEF 0 "fp_register_operand" "+f")
3835 (match_operand:MODEF 1 "fp_register_operand" "+f"))
3836 (set (match_dup 1)
3837 (match_dup 0))]
3838 "TARGET_80387 || reload_completed"
3839 {
3840 if (STACK_TOP_P (operands[0]))
3841 return "fxch\t%1";
3842 else
3843 return "fxch\t%0";
3844 }
3845 [(set_attr "type" "fxch")
3846 (set_attr "mode" "<MODE>")])
3847 3742
3743
3848 ;; Zero extension instructions 3744 ;; Zero extension instructions
3849 3745
3850 (define_expand "zero_extendsidi2" 3746 (define_expand "zero_extendsidi2"
3851 [(set (match_operand:DI 0 "nonimmediate_operand") 3747 [(set (match_operand:DI 0 "nonimmediate_operand")
3852 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]) 3748 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))])
3853 3749
3854 (define_insn "*zero_extendsidi2" 3750 (define_insn "*zero_extendsidi2"
3855 [(set (match_operand:DI 0 "nonimmediate_operand" 3751 [(set (match_operand:DI 0 "nonimmediate_operand"
3856 "=r,?r,?o,r ,o,?*Ym,?!*y,?r ,?*Yi,*x,*x,*v,*r") 3752 "=r,?r,?o,r ,o,?*y,?!*y,$r,$v,$x,*x,*v,*r")
3857 (zero_extend:DI 3753 (zero_extend:DI
3858 (match_operand:SI 1 "x86_64_zext_operand" 3754 (match_operand:SI 1 "x86_64_zext_operand"
3859 "0 ,rm,r ,rmWz,0,r ,m ,*Yj,r ,m ,*x,*v,*k")))] 3755 "0 ,rm,r ,rmWz,0,r ,m ,v ,r ,m ,*x,*v,*k")))]
3860 "" 3756 ""
3861 { 3757 {
3862 switch (get_attr_type (insn)) 3758 switch (get_attr_type (insn))
3863 { 3759 {
3864 case TYPE_IMOVX: 3760 case TYPE_IMOVX:
3898 [(set (attr "isa") 3794 [(set (attr "isa")
3899 (cond [(eq_attr "alternative" "0,1,2") 3795 (cond [(eq_attr "alternative" "0,1,2")
3900 (const_string "nox64") 3796 (const_string "nox64")
3901 (eq_attr "alternative" "3") 3797 (eq_attr "alternative" "3")
3902 (const_string "x64") 3798 (const_string "x64")
3903 (eq_attr "alternative" "9") 3799 (eq_attr "alternative" "7,8,9")
3904 (const_string "sse2") 3800 (const_string "sse2")
3905 (eq_attr "alternative" "10") 3801 (eq_attr "alternative" "10")
3906 (const_string "sse4") 3802 (const_string "sse4")
3907 (eq_attr "alternative" "11") 3803 (eq_attr "alternative" "11")
3908 (const_string "avx512f") 3804 (const_string "avx512f")
3944 (match_test "TARGET_64BIT")) 3840 (match_test "TARGET_64BIT"))
3945 (const_string "TI") 3841 (const_string "TI")
3946 (eq_attr "alternative" "8,10,11") 3842 (eq_attr "alternative" "8,10,11")
3947 (const_string "TI") 3843 (const_string "TI")
3948 ] 3844 ]
3949 (const_string "SI")))]) 3845 (const_string "SI")))
3846 (set (attr "preferred_for_speed")
3847 (cond [(eq_attr "alternative" "7")
3848 (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
3849 (eq_attr "alternative" "5,8")
3850 (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
3851 ]
3852 (symbol_ref "true")))])
3950 3853
3951 (define_split 3854 (define_split
3952 [(set (match_operand:DI 0 "memory_operand") 3855 [(set (match_operand:DI 0 "memory_operand")
3953 (zero_extend:DI (match_operand:SI 1 "memory_operand")))] 3856 (zero_extend:DI (match_operand:SI 1 "memory_operand")))]
3954 "reload_completed" 3857 "reload_completed"
3969 "!TARGET_64BIT && reload_completed 3872 "!TARGET_64BIT && reload_completed
3970 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" 3873 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
3971 [(set (match_dup 3) (match_dup 1)) 3874 [(set (match_dup 3) (match_dup 1))
3972 (set (match_dup 4) (const_int 0))] 3875 (set (match_dup 4) (const_int 0))]
3973 "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);") 3876 "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
3974
3975 (define_peephole2
3976 [(set (match_operand:DI 0 "general_reg_operand")
3977 (zero_extend:DI (match_operand:SI 1 "nonimmediate_gr_operand")))
3978 (set (match_operand:DI 2 "sse_reg_operand") (match_dup 0))]
3979 "TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC
3980 && peep2_reg_dead_p (2, operands[0])"
3981 [(set (match_dup 2)
3982 (zero_extend:DI (match_dup 1)))])
3983 3877
3984 (define_mode_attr kmov_isa 3878 (define_mode_attr kmov_isa
3985 [(QI "avx512dq") (HI "avx512f") (SI "avx512bw") (DI "avx512bw")]) 3879 [(QI "avx512dq") (HI "avx512f") (SI "avx512bw") (DI "avx512bw")])
3986 3880
3987 (define_insn "zero_extend<mode>di2" 3881 (define_insn "zero_extend<mode>di2"
4420 DONE; 4314 DONE;
4421 } 4315 }
4422 operands[1] = validize_mem (force_const_mem (SFmode, operands[1])); 4316 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
4423 } 4317 }
4424 }) 4318 })
4319
4320 (define_insn "*extendsfdf2"
4321 [(set (match_operand:DF 0 "nonimm_ssenomem_operand" "=f,m,v")
4322 (float_extend:DF
4323 (match_operand:SF 1 "nonimmediate_operand" "fm,f,vm")))]
4324 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
4325 {
4326 switch (which_alternative)
4327 {
4328 case 0:
4329 case 1:
4330 return output_387_reg_move (insn, operands);
4331
4332 case 2:
4333 return "%vcvtss2sd\t{%1, %d0|%d0, %1}";
4334
4335 default:
4336 gcc_unreachable ();
4337 }
4338 }
4339 [(set_attr "type" "fmov,fmov,ssecvt")
4340 (set_attr "prefix" "orig,orig,maybe_vex")
4341 (set_attr "mode" "SF,XF,DF")
4342 (set (attr "enabled")
4343 (if_then_else
4344 (match_test ("TARGET_SSE2 && TARGET_SSE_MATH"))
4345 (if_then_else
4346 (eq_attr "alternative" "0,1")
4347 (symbol_ref "TARGET_MIX_SSE_I387")
4348 (symbol_ref "true"))
4349 (if_then_else
4350 (eq_attr "alternative" "0,1")
4351 (symbol_ref "true")
4352 (symbol_ref "false"))))])
4425 4353
4426 /* For converting SF(xmm2) to DF(xmm1), use the following code instead of 4354 /* For converting SF(xmm2) to DF(xmm1), use the following code instead of
4427 cvtss2sd: 4355 cvtss2sd:
4428 unpcklps xmm2,xmm2 ; packed conversion might crash on signaling NaNs 4356 unpcklps xmm2,xmm2 ; packed conversion might crash on signaling NaNs
4429 cvtps2pd xmm2,xmm1 4357 cvtps2pd xmm2,xmm1
4488 && optimize_insn_for_speed_p ()" 4416 && optimize_insn_for_speed_p ()"
4489 [(set (match_dup 2) (match_dup 1)) 4417 [(set (match_dup 2) (match_dup 1))
4490 (set (match_dup 0) (float_extend:DF (match_dup 2)))] 4418 (set (match_dup 0) (float_extend:DF (match_dup 2)))]
4491 "operands[2] = lowpart_subreg (SFmode, operands[0], DFmode);") 4419 "operands[2] = lowpart_subreg (SFmode, operands[0], DFmode);")
4492 4420
4493 (define_insn "*extendsfdf2" 4421 ;; Break partial reg stall for cvtss2sd. This splitter should split
4494 [(set (match_operand:DF 0 "nonimm_ssenomem_operand" "=f,m,v") 4422 ;; late in the pass sequence (after register rename pass),
4423 ;; so allocated registers won't change anymore.
4424
4425 (define_split
4426 [(set (match_operand:DF 0 "sse_reg_operand")
4495 (float_extend:DF 4427 (float_extend:DF
4496 (match_operand:SF 1 "nonimmediate_operand" "fm,f,vm")))] 4428 (match_operand:SF 1 "nonimmediate_operand")))]
4497 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" 4429 "TARGET_SSE_PARTIAL_REG_DEPENDENCY && epilogue_completed
4498 { 4430 && optimize_function_for_speed_p (cfun)
4499 switch (which_alternative) 4431 && (!REG_P (operands[1])
4500 { 4432 || REGNO (operands[0]) != REGNO (operands[1]))
4501 case 0: 4433 && (!EXT_REX_SSE_REG_P (operands[0])
4502 case 1: 4434 || TARGET_AVX512VL)"
4503 return output_387_reg_move (insn, operands); 4435 [(set (match_dup 0)
4504 4436 (vec_merge:V2DF
4505 case 2: 4437 (vec_duplicate:V2DF
4506 return "%vcvtss2sd\t{%1, %d0|%d0, %1}"; 4438 (float_extend:DF
4507 4439 (match_dup 1)))
4508 default: 4440 (match_dup 0)
4509 gcc_unreachable (); 4441 (const_int 1)))]
4510 } 4442 {
4511 } 4443 operands[0] = lowpart_subreg (V2DFmode, operands[0], DFmode);
4512 [(set_attr "type" "fmov,fmov,ssecvt") 4444 emit_move_insn (operands[0], CONST0_RTX (V2DFmode));
4513 (set_attr "prefix" "orig,orig,maybe_vex") 4445 })
4514 (set_attr "mode" "SF,XF,DF")
4515 (set (attr "enabled")
4516 (if_then_else
4517 (match_test ("TARGET_SSE2 && TARGET_SSE_MATH"))
4518 (if_then_else
4519 (eq_attr "alternative" "0,1")
4520 (symbol_ref "TARGET_MIX_SSE_I387")
4521 (symbol_ref "true"))
4522 (if_then_else
4523 (eq_attr "alternative" "0,1")
4524 (symbol_ref "true")
4525 (symbol_ref "false"))))])
4526 4446
4527 (define_expand "extend<mode>xf2" 4447 (define_expand "extend<mode>xf2"
4528 [(set (match_operand:XF 0 "nonimmediate_operand") 4448 [(set (match_operand:XF 0 "nonimmediate_operand")
4529 (float_extend:XF (match_operand:MODEF 1 "general_operand")))] 4449 (float_extend:XF (match_operand:MODEF 1 "general_operand")))]
4530 "TARGET_80387" 4450 "TARGET_80387"
4559 ;; insn. So we pretend we can output to a reg in order to get better 4479 ;; insn. So we pretend we can output to a reg in order to get better
4560 ;; register preferencing, but we really use a stack slot. 4480 ;; register preferencing, but we really use a stack slot.
4561 4481
4562 ;; Conversion from DFmode to SFmode. 4482 ;; Conversion from DFmode to SFmode.
4563 4483
4564 (define_expand "truncdfsf2" 4484 (define_insn "truncdfsf2"
4565 [(set (match_operand:SF 0 "nonimmediate_operand") 4485 [(set (match_operand:SF 0 "nonimm_ssenomem_operand" "=m,f,v")
4566 (float_truncate:SF 4486 (float_truncate:SF
4567 (match_operand:DF 1 "nonimmediate_operand")))] 4487 (match_operand:DF 1 "register_ssemem_operand" "f,f,vm")))]
4568 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" 4488 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
4569 { 4489 {
4570 if (TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387) 4490 switch (which_alternative)
4571 ;
4572 else if (flag_unsafe_math_optimizations)
4573 ;
4574 else
4575 { 4491 {
4576 rtx temp = assign_386_stack_local (SFmode, SLOT_TEMP); 4492 case 0:
4577 emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp)); 4493 case 1:
4578 DONE; 4494 return output_387_reg_move (insn, operands);
4495
4496 case 2:
4497 return "%vcvtsd2ss\t{%1, %d0|%d0, %1}";
4498
4499 default:
4500 gcc_unreachable ();
4579 } 4501 }
4580 }) 4502 }
4503 [(set_attr "type" "fmov,fmov,ssecvt")
4504 (set_attr "mode" "SF")
4505 (set (attr "enabled")
4506 (if_then_else
4507 (match_test ("TARGET_SSE2 && TARGET_SSE_MATH"))
4508 (cond [(eq_attr "alternative" "0")
4509 (symbol_ref "TARGET_MIX_SSE_I387")
4510 (eq_attr "alternative" "1")
4511 (symbol_ref "TARGET_MIX_SSE_I387
4512 && flag_unsafe_math_optimizations")
4513 ]
4514 (symbol_ref "true"))
4515 (cond [(eq_attr "alternative" "0")
4516 (symbol_ref "true")
4517 (eq_attr "alternative" "1")
4518 (symbol_ref "flag_unsafe_math_optimizations")
4519 ]
4520 (symbol_ref "false"))))])
4581 4521
4582 /* For converting DF(xmm2) to SF(xmm1), use the following code instead of 4522 /* For converting DF(xmm2) to SF(xmm1), use the following code instead of
4583 cvtsd2ss: 4523 cvtsd2ss:
4584 unpcklpd xmm2,xmm2 ; packed conversion might crash on signaling NaNs 4524 unpcklpd xmm2,xmm2 ; packed conversion might crash on signaling NaNs
4585 cvtpd2ps xmm2,xmm1 4525 cvtpd2ps xmm2,xmm1
4586 We do the conversion post reload to avoid producing of 128bit spills 4526 We do the conversion post reload to avoid producing of 128bit spills
4587 that might lead to ICE on 32bit target. The sequence unlikely combine 4527 that might lead to ICE on 32bit target. The sequence unlikely combine
4588 anyway. */ 4528 anyway. */
4589 (define_split 4529 (define_split
4590 [(set (match_operand:SF 0 "sse_reg_operand") 4530 [(set (match_operand:SF 0 "sse_reg_operand")
4591 (float_truncate:SF 4531 (float_truncate:SF
4592 (match_operand:DF 1 "nonimmediate_operand")))] 4532 (match_operand:DF 1 "nonimmediate_operand")))]
4593 "TARGET_USE_VECTOR_FP_CONVERTS 4533 "TARGET_USE_VECTOR_FP_CONVERTS
4594 && optimize_insn_for_speed_p () 4534 && optimize_insn_for_speed_p ()
4595 && reload_completed 4535 && reload_completed
4596 && (!EXT_REX_SSE_REG_P (operands[0]) 4536 && (!EXT_REX_SSE_REG_P (operands[0])
4623 else 4563 else
4624 emit_insn (gen_vec_concatv2df (operands[4], operands[1], 4564 emit_insn (gen_vec_concatv2df (operands[4], operands[1],
4625 CONST0_RTX (DFmode))); 4565 CONST0_RTX (DFmode)));
4626 }) 4566 })
4627 4567
4628 ;; It's more profitable to split and then extend in the same register. 4568 ;; It's more profitable to split and then truncate in the same register.
4629 (define_peephole2 4569 (define_peephole2
4630 [(set (match_operand:SF 0 "sse_reg_operand") 4570 [(set (match_operand:SF 0 "sse_reg_operand")
4631 (float_truncate:SF 4571 (float_truncate:SF
4632 (match_operand:DF 1 "memory_operand")))] 4572 (match_operand:DF 1 "memory_operand")))]
4633 "TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS 4573 "TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS
4634 && optimize_insn_for_speed_p ()" 4574 && optimize_insn_for_speed_p ()"
4635 [(set (match_dup 2) (match_dup 1)) 4575 [(set (match_dup 2) (match_dup 1))
4636 (set (match_dup 0) (float_truncate:SF (match_dup 2)))] 4576 (set (match_dup 0) (float_truncate:SF (match_dup 2)))]
4637 "operands[2] = lowpart_subreg (DFmode, operands[0], SFmode);") 4577 "operands[2] = lowpart_subreg (DFmode, operands[0], SFmode);")
4638 4578
4639 (define_expand "truncdfsf2_with_temp" 4579 ;; Break partial reg stall for cvtsd2ss. This splitter should split
4640 [(parallel [(set (match_operand:SF 0) 4580 ;; late in the pass sequence (after register rename pass),
4641 (float_truncate:SF (match_operand:DF 1))) 4581 ;; so allocated registers won't change anymore.
4642 (clobber (match_operand:SF 2))])]) 4582
4643 4583 (define_split
4644 ;; SSE alternative doesn't depend on flag_unsafe_math_optimizations, 4584 [(set (match_operand:SF 0 "sse_reg_operand")
4645 ;; because nothing we do there is unsafe.
4646 (define_insn "*truncdfsf_fast_mixed"
4647 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm,v")
4648 (float_truncate:SF 4585 (float_truncate:SF
4649 (match_operand:DF 1 "nonimmediate_operand" "f ,vm")))] 4586 (match_operand:DF 1 "nonimmediate_operand")))]
4650 "TARGET_SSE2 && TARGET_SSE_MATH" 4587 "TARGET_SSE_PARTIAL_REG_DEPENDENCY && epilogue_completed
4651 { 4588 && optimize_function_for_speed_p (cfun)
4652 switch (which_alternative) 4589 && (!REG_P (operands[1])
4653 { 4590 || REGNO (operands[0]) != REGNO (operands[1]))
4654 case 0: 4591 && (!EXT_REX_SSE_REG_P (operands[0])
4655 return output_387_reg_move (insn, operands); 4592 || TARGET_AVX512VL)"
4656 case 1: 4593 [(set (match_dup 0)
4657 return "%vcvtsd2ss\t{%1, %d0|%d0, %1}"; 4594 (vec_merge:V4SF
4658 default: 4595 (vec_duplicate:V4SF
4659 gcc_unreachable (); 4596 (float_truncate:SF
4660 } 4597 (match_dup 1)))
4661 } 4598 (match_dup 0)
4662 [(set_attr "type" "fmov,ssecvt") 4599 (const_int 1)))]
4663 (set_attr "prefix" "orig,maybe_vex") 4600 {
4664 (set_attr "mode" "SF") 4601 operands[0] = lowpart_subreg (V4SFmode, operands[0], SFmode);
4665 (set (attr "enabled") 4602 emit_move_insn (operands[0], CONST0_RTX (V4SFmode));
4666 (cond [(eq_attr "alternative" "0") 4603 })
4667 (symbol_ref "TARGET_MIX_SSE_I387
4668 && flag_unsafe_math_optimizations")
4669 ]
4670 (symbol_ref "true")))])
4671
4672 (define_insn "*truncdfsf_fast_i387"
4673 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
4674 (float_truncate:SF
4675 (match_operand:DF 1 "nonimmediate_operand" "f")))]
4676 "TARGET_80387 && flag_unsafe_math_optimizations"
4677 "* return output_387_reg_move (insn, operands);"
4678 [(set_attr "type" "fmov")
4679 (set_attr "mode" "SF")])
4680
4681 (define_insn "*truncdfsf_mixed"
4682 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,v ,?f,?v,?*r")
4683 (float_truncate:SF
4684 (match_operand:DF 1 "nonimmediate_operand" "f ,vm,f ,f ,f")))
4685 (clobber (match_operand:SF 2 "memory_operand" "=X,X ,m ,m ,m"))]
4686 "TARGET_MIX_SSE_I387"
4687 {
4688 switch (which_alternative)
4689 {
4690 case 0:
4691 return output_387_reg_move (insn, operands);
4692 case 1:
4693 return "%vcvtsd2ss\t{%1, %d0|%d0, %1}";
4694
4695 default:
4696 return "#";
4697 }
4698 }
4699 [(set_attr "isa" "*,sse2,*,*,*")
4700 (set_attr "type" "fmov,ssecvt,multi,multi,multi")
4701 (set_attr "unit" "*,*,i387,i387,i387")
4702 (set_attr "prefix" "orig,maybe_vex,orig,orig,orig")
4703 (set_attr "mode" "SF")])
4704
4705 (define_insn "*truncdfsf_i387"
4706 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?v,?*r")
4707 (float_truncate:SF
4708 (match_operand:DF 1 "nonimmediate_operand" "f ,f ,f ,f")))
4709 (clobber (match_operand:SF 2 "memory_operand" "=X,m ,m ,m"))]
4710 "TARGET_80387"
4711 {
4712 switch (which_alternative)
4713 {
4714 case 0:
4715 return output_387_reg_move (insn, operands);
4716
4717 default:
4718 return "#";
4719 }
4720 }
4721 [(set_attr "type" "fmov,multi,multi,multi")
4722 (set_attr "unit" "*,i387,i387,i387")
4723 (set_attr "mode" "SF")])
4724
4725 (define_insn "*truncdfsf2_i387_1"
4726 [(set (match_operand:SF 0 "memory_operand" "=m")
4727 (float_truncate:SF
4728 (match_operand:DF 1 "register_operand" "f")))]
4729 "TARGET_80387
4730 && !(TARGET_SSE2 && TARGET_SSE_MATH)
4731 && !TARGET_MIX_SSE_I387"
4732 "* return output_387_reg_move (insn, operands);"
4733 [(set_attr "type" "fmov")
4734 (set_attr "mode" "SF")])
4735
4736 (define_split
4737 [(set (match_operand:SF 0 "register_operand")
4738 (float_truncate:SF
4739 (match_operand:DF 1 "fp_register_operand")))
4740 (clobber (match_operand 2))]
4741 "reload_completed"
4742 [(set (match_dup 2) (match_dup 1))
4743 (set (match_dup 0) (match_dup 2))]
4744 "operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1]));")
4745 4604
4746 ;; Conversion from XFmode to {SF,DF}mode 4605 ;; Conversion from XFmode to {SF,DF}mode
4747 4606
4748 (define_expand "truncxf<mode>2" 4607 (define_insn "truncxf<mode>2"
4749 [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand") 4608 [(set (match_operand:MODEF 0 "nonimmediate_operand" "=m,f")
4750 (float_truncate:MODEF
4751 (match_operand:XF 1 "register_operand")))
4752 (clobber (match_dup 2))])]
4753 "TARGET_80387"
4754 {
4755 if (flag_unsafe_math_optimizations)
4756 {
4757 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (<MODE>mode);
4758 emit_insn (gen_truncxf<mode>2_i387_noop (reg, operands[1]));
4759 if (reg != operands[0])
4760 emit_move_insn (operands[0], reg);
4761 DONE;
4762 }
4763 else
4764 operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
4765 })
4766
4767 (define_insn "*truncxfsf2_mixed"
4768 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?v,?*r")
4769 (float_truncate:SF
4770 (match_operand:XF 1 "register_operand" "f ,f ,f ,f")))
4771 (clobber (match_operand:SF 2 "memory_operand" "=X,m ,m ,m"))]
4772 "TARGET_80387"
4773 {
4774 gcc_assert (!which_alternative);
4775 return output_387_reg_move (insn, operands);
4776 }
4777 [(set_attr "type" "fmov,multi,multi,multi")
4778 (set_attr "unit" "*,i387,i387,i387")
4779 (set_attr "mode" "SF")])
4780
4781 (define_insn "*truncxfdf2_mixed"
4782 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f,?v,?*r")
4783 (float_truncate:DF
4784 (match_operand:XF 1 "register_operand" "f ,f ,f ,f")))
4785 (clobber (match_operand:DF 2 "memory_operand" "=X,m ,m ,m"))]
4786 "TARGET_80387"
4787 {
4788 gcc_assert (!which_alternative);
4789 return output_387_reg_move (insn, operands);
4790 }
4791 [(set_attr "isa" "*,*,sse2,*")
4792 (set_attr "type" "fmov,multi,multi,multi")
4793 (set_attr "unit" "*,i387,i387,i387")
4794 (set_attr "mode" "DF")])
4795
4796 (define_insn "truncxf<mode>2_i387_noop"
4797 [(set (match_operand:MODEF 0 "register_operand" "=f")
4798 (float_truncate:MODEF 4609 (float_truncate:MODEF
4799 (match_operand:XF 1 "register_operand" "f")))] 4610 (match_operand:XF 1 "register_operand" "f,f")))]
4800 "TARGET_80387 && flag_unsafe_math_optimizations"
4801 "* return output_387_reg_move (insn, operands);"
4802 [(set_attr "type" "fmov")
4803 (set_attr "mode" "<MODE>")])
4804
4805 (define_insn "*truncxf<mode>2_i387"
4806 [(set (match_operand:MODEF 0 "memory_operand" "=m")
4807 (float_truncate:MODEF
4808 (match_operand:XF 1 "register_operand" "f")))]
4809 "TARGET_80387" 4611 "TARGET_80387"
4810 "* return output_387_reg_move (insn, operands);" 4612 "* return output_387_reg_move (insn, operands);"
4811 [(set_attr "type" "fmov") 4613 [(set_attr "type" "fmov")
4812 (set_attr "mode" "<MODE>")]) 4614 (set_attr "mode" "<MODE>")
4813 4615 (set (attr "enabled")
4814 (define_split 4616 (cond [(eq_attr "alternative" "1")
4815 [(set (match_operand:MODEF 0 "register_operand") 4617 (symbol_ref "flag_unsafe_math_optimizations")
4816 (float_truncate:MODEF 4618 ]
4817 (match_operand:XF 1 "register_operand"))) 4619 (symbol_ref "true")))])
4818 (clobber (match_operand:MODEF 2 "memory_operand"))]
4819 "TARGET_80387 && reload_completed"
4820 [(set (match_dup 2) (float_truncate:MODEF (match_dup 1)))
4821 (set (match_dup 0) (match_dup 2))])
4822
4823 (define_split
4824 [(set (match_operand:MODEF 0 "memory_operand")
4825 (float_truncate:MODEF
4826 (match_operand:XF 1 "register_operand")))
4827 (clobber (match_operand:MODEF 2 "memory_operand"))]
4828 "TARGET_80387"
4829 [(set (match_dup 0) (float_truncate:MODEF (match_dup 1)))])
4830 4620
4831 ;; Signed conversion to DImode. 4621 ;; Signed conversion to DImode.
4832 4622
4833 (define_expand "fix_truncxfdi2" 4623 (define_expand "fix_truncxfdi2"
4834 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand") 4624 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand")
4836 (clobber (reg:CC FLAGS_REG))])] 4626 (clobber (reg:CC FLAGS_REG))])]
4837 "TARGET_80387" 4627 "TARGET_80387"
4838 { 4628 {
4839 if (TARGET_FISTTP) 4629 if (TARGET_FISTTP)
4840 { 4630 {
4841 emit_insn (gen_fix_truncdi_fisttp_i387_1 (operands[0], operands[1])); 4631 emit_insn (gen_fix_truncdi_i387_fisttp (operands[0], operands[1]));
4842 DONE; 4632 DONE;
4843 } 4633 }
4844 }) 4634 })
4845 4635
4846 (define_expand "fix_trunc<mode>di2" 4636 (define_expand "fix_trunc<mode>di2"
4850 "TARGET_80387 || (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))" 4640 "TARGET_80387 || (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))"
4851 { 4641 {
4852 if (TARGET_FISTTP 4642 if (TARGET_FISTTP
4853 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)) 4643 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
4854 { 4644 {
4855 emit_insn (gen_fix_truncdi_fisttp_i387_1 (operands[0], operands[1])); 4645 emit_insn (gen_fix_truncdi_i387_fisttp (operands[0], operands[1]));
4856 DONE; 4646 DONE;
4857 } 4647 }
4858 if (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode)) 4648 if (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))
4859 { 4649 {
4860 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode); 4650 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4873 (clobber (reg:CC FLAGS_REG))])] 4663 (clobber (reg:CC FLAGS_REG))])]
4874 "TARGET_80387" 4664 "TARGET_80387"
4875 { 4665 {
4876 if (TARGET_FISTTP) 4666 if (TARGET_FISTTP)
4877 { 4667 {
4878 emit_insn (gen_fix_truncsi_fisttp_i387_1 (operands[0], operands[1])); 4668 emit_insn (gen_fix_truncsi_i387_fisttp (operands[0], operands[1]));
4879 DONE; 4669 DONE;
4880 } 4670 }
4881 }) 4671 })
4882 4672
4883 (define_expand "fix_trunc<mode>si2" 4673 (define_expand "fix_trunc<mode>si2"
4887 "TARGET_80387 || SSE_FLOAT_MODE_P (<MODE>mode)" 4677 "TARGET_80387 || SSE_FLOAT_MODE_P (<MODE>mode)"
4888 { 4678 {
4889 if (TARGET_FISTTP 4679 if (TARGET_FISTTP
4890 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)) 4680 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
4891 { 4681 {
4892 emit_insn (gen_fix_truncsi_fisttp_i387_1 (operands[0], operands[1])); 4682 emit_insn (gen_fix_truncsi_i387_fisttp (operands[0], operands[1]));
4893 DONE; 4683 DONE;
4894 } 4684 }
4895 if (SSE_FLOAT_MODE_P (<MODE>mode)) 4685 if (SSE_FLOAT_MODE_P (<MODE>mode))
4896 { 4686 {
4897 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode); 4687 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4911 "TARGET_80387 4701 "TARGET_80387
4912 && !(SSE_FLOAT_MODE_P (<MODE>mode) && (!TARGET_FISTTP || TARGET_SSE_MATH))" 4702 && !(SSE_FLOAT_MODE_P (<MODE>mode) && (!TARGET_FISTTP || TARGET_SSE_MATH))"
4913 { 4703 {
4914 if (TARGET_FISTTP) 4704 if (TARGET_FISTTP)
4915 { 4705 {
4916 emit_insn (gen_fix_trunchi_fisttp_i387_1 (operands[0], operands[1])); 4706 emit_insn (gen_fix_trunchi_i387_fisttp (operands[0], operands[1]));
4917 DONE; 4707 DONE;
4918 } 4708 }
4919 }) 4709 })
4710
4711 ;; Unsigned conversion to DImode
4712
4713 (define_insn "fixuns_trunc<mode>di2"
4714 [(set (match_operand:DI 0 "register_operand" "=r")
4715 (unsigned_fix:DI
4716 (match_operand:MODEF 1 "nonimmediate_operand" "vm")))]
4717 "TARGET_64BIT && TARGET_AVX512F && TARGET_SSE_MATH"
4718 "vcvtt<ssemodesuffix>2usi\t{%1, %0|%0, %1}"
4719 [(set_attr "type" "sseicvt")
4720 (set_attr "prefix" "evex")
4721 (set_attr "mode" "DI")])
4920 4722
4921 ;; Unsigned conversion to SImode. 4723 ;; Unsigned conversion to SImode.
4922 4724
4923 (define_expand "fixuns_trunc<mode>si2" 4725 (define_expand "fixuns_trunc<mode>si2"
4924 [(parallel 4726 [(parallel
4926 (unsigned_fix:SI 4728 (unsigned_fix:SI
4927 (match_operand:MODEF 1 "nonimmediate_operand"))) 4729 (match_operand:MODEF 1 "nonimmediate_operand")))
4928 (use (match_dup 2)) 4730 (use (match_dup 2))
4929 (clobber (match_scratch:<ssevecmode> 3)) 4731 (clobber (match_scratch:<ssevecmode> 3))
4930 (clobber (match_scratch:<ssevecmode> 4))])] 4732 (clobber (match_scratch:<ssevecmode> 4))])]
4931 "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH" 4733 "(!TARGET_64BIT || TARGET_AVX512F) && TARGET_SSE2 && TARGET_SSE_MATH"
4932 { 4734 {
4933 machine_mode mode = <MODE>mode; 4735 machine_mode mode = <MODE>mode;
4934 machine_mode vecmode = <ssevecmode>mode; 4736 machine_mode vecmode = <ssevecmode>mode;
4935 REAL_VALUE_TYPE TWO31r; 4737 REAL_VALUE_TYPE TWO31r;
4936 rtx two31; 4738 rtx two31;
4937 4739
4740 if (TARGET_AVX512F)
4741 {
4742 emit_insn (gen_fixuns_trunc<mode>si2_avx512f (operands[0], operands[1]));
4743 DONE;
4744 }
4745
4938 if (optimize_insn_for_size_p ()) 4746 if (optimize_insn_for_size_p ())
4939 FAIL; 4747 FAIL;
4940 4748
4941 real_ldexp (&TWO31r, &dconst1, 31); 4749 real_ldexp (&TWO31r, &dconst1, 31);
4942 two31 = const_double_from_real_value (TWO31r, mode); 4750 two31 = const_double_from_real_value (TWO31r, mode);
4943 two31 = ix86_build_const_vector (vecmode, true, two31); 4751 two31 = ix86_build_const_vector (vecmode, true, two31);
4944 operands[2] = force_reg (vecmode, two31); 4752 operands[2] = force_reg (vecmode, two31);
4945 }) 4753 })
4754
4755 (define_insn "fixuns_trunc<mode>si2_avx512f"
4756 [(set (match_operand:SI 0 "register_operand" "=r")
4757 (unsigned_fix:SI
4758 (match_operand:MODEF 1 "nonimmediate_operand" "vm")))]
4759 "TARGET_AVX512F && TARGET_SSE_MATH"
4760 "vcvtt<ssemodesuffix>2usi\t{%1, %0|%0, %1}"
4761 [(set_attr "type" "sseicvt")
4762 (set_attr "prefix" "evex")
4763 (set_attr "mode" "SI")])
4764
4765 (define_insn "*fixuns_trunc<mode>si2_avx512f_zext"
4766 [(set (match_operand:DI 0 "register_operand" "=r")
4767 (zero_extend:DI
4768 (unsigned_fix:SI
4769 (match_operand:MODEF 1 "nonimmediate_operand" "vm"))))]
4770 "TARGET_64BIT && TARGET_AVX512F && TARGET_SSE_MATH"
4771 "vcvtt<ssemodesuffix>2usi\t{%1, %k0|%k0, %1}"
4772 [(set_attr "type" "sseicvt")
4773 (set_attr "prefix" "evex")
4774 (set_attr "mode" "SI")])
4946 4775
4947 (define_insn_and_split "*fixuns_trunc<mode>_1" 4776 (define_insn_and_split "*fixuns_trunc<mode>_1"
4948 [(set (match_operand:SI 0 "register_operand" "=&x,&x") 4777 [(set (match_operand:SI 0 "register_operand" "=&x,&x")
4949 (unsigned_fix:SI 4778 (unsigned_fix:SI
4950 (match_operand:MODEF 3 "nonimmediate_operand" "xm,xm"))) 4779 (match_operand:MODEF 3 "nonimmediate_operand" "xm,xm")))
5001 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) 4830 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode)
5002 && optimize_insn_for_speed_p ()" 4831 && optimize_insn_for_speed_p ()"
5003 [(set (match_dup 2) (match_dup 1)) 4832 [(set (match_dup 2) (match_dup 1))
5004 (set (match_dup 0) (fix:SWI48 (match_dup 2)))]) 4833 (set (match_dup 0) (fix:SWI48 (match_dup 2)))])
5005 4834
5006 (define_insn_and_split "fix_trunc<mode>_fisttp_i387_1"
5007 [(set (match_operand:SWI248x 0 "nonimmediate_operand")
5008 (fix:SWI248x (match_operand 1 "register_operand")))]
5009 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
5010 && TARGET_FISTTP
5011 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
5012 && (TARGET_64BIT || <MODE>mode != DImode))
5013 && TARGET_SSE_MATH)
5014 && can_create_pseudo_p ()"
5015 "#"
5016 "&& 1"
5017 [(const_int 0)]
5018 {
5019 if (memory_operand (operands[0], VOIDmode))
5020 emit_insn (gen_fix_trunc<mode>_i387_fisttp (operands[0], operands[1]));
5021 else
5022 {
5023 operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
5024 emit_insn (gen_fix_trunc<mode>_i387_fisttp_with_temp (operands[0],
5025 operands[1],
5026 operands[2]));
5027 }
5028 DONE;
5029 }
5030 [(set_attr "type" "fisttp")
5031 (set_attr "mode" "<MODE>")])
5032
5033 (define_insn "fix_trunc<mode>_i387_fisttp" 4835 (define_insn "fix_trunc<mode>_i387_fisttp"
5034 [(set (match_operand:SWI248x 0 "memory_operand" "=m") 4836 [(set (match_operand:SWI248x 0 "nonimmediate_operand" "=m")
5035 (fix:SWI248x (match_operand 1 "register_operand" "f"))) 4837 (fix:SWI248x (match_operand 1 "register_operand" "f")))
5036 (clobber (match_scratch:XF 2 "=&1f"))] 4838 (clobber (match_scratch:XF 2 "=&f"))]
5037 "X87_FLOAT_MODE_P (GET_MODE (operands[1])) 4839 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
5038 && TARGET_FISTTP 4840 && TARGET_FISTTP
5039 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1])) 4841 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
5040 && (TARGET_64BIT || <MODE>mode != DImode)) 4842 && (TARGET_64BIT || <MODE>mode != DImode))
5041 && TARGET_SSE_MATH)" 4843 && TARGET_SSE_MATH)"
5042 "* return output_fix_trunc (insn, operands, true);" 4844 "* return output_fix_trunc (insn, operands, true);"
5043 [(set_attr "type" "fisttp") 4845 [(set_attr "type" "fisttp")
5044 (set_attr "mode" "<MODE>")]) 4846 (set_attr "mode" "<MODE>")])
5045 4847
5046 (define_insn "fix_trunc<mode>_i387_fisttp_with_temp"
5047 [(set (match_operand:SWI248x 0 "nonimmediate_operand" "=m,?r")
5048 (fix:SWI248x (match_operand 1 "register_operand" "f,f")))
5049 (clobber (match_operand:SWI248x 2 "memory_operand" "=X,m"))
5050 (clobber (match_scratch:XF 3 "=&1f,&1f"))]
5051 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
5052 && TARGET_FISTTP
5053 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
5054 && (TARGET_64BIT || <MODE>mode != DImode))
5055 && TARGET_SSE_MATH)"
5056 "#"
5057 [(set_attr "type" "fisttp")
5058 (set_attr "mode" "<MODE>")])
5059
5060 (define_split
5061 [(set (match_operand:SWI248x 0 "register_operand")
5062 (fix:SWI248x (match_operand 1 "register_operand")))
5063 (clobber (match_operand:SWI248x 2 "memory_operand"))
5064 (clobber (match_scratch 3))]
5065 "reload_completed"
5066 [(parallel [(set (match_dup 2) (fix:SWI248x (match_dup 1)))
5067 (clobber (match_dup 3))])
5068 (set (match_dup 0) (match_dup 2))])
5069
5070 (define_split
5071 [(set (match_operand:SWI248x 0 "memory_operand")
5072 (fix:SWI248x (match_operand 1 "register_operand")))
5073 (clobber (match_operand:SWI248x 2 "memory_operand"))
5074 (clobber (match_scratch 3))]
5075 "reload_completed"
5076 [(parallel [(set (match_dup 0) (fix:SWI248x (match_dup 1)))
5077 (clobber (match_dup 3))])])
5078
5079 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description 4848 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
5080 ;; of the machinery. Please note the clobber of FLAGS_REG. In i387 control 4849 ;; of the machinery. Please note the clobber of FLAGS_REG. In i387 control
5081 ;; word calculation (inserted by LCM in mode switching pass) a FLAGS_REG 4850 ;; word calculation (inserted by LCM in mode switching pass) a FLAGS_REG
5082 ;; clobbering insns can be used. Look at emit_i387_cw_initialization () 4851 ;; clobbering insns can be used. Look at emit_i387_cw_initialization ()
5083 ;; function in i386.c. 4852 ;; function in i386.c.
5096 { 4865 {
5097 ix86_optimize_mode_switching[I387_TRUNC] = 1; 4866 ix86_optimize_mode_switching[I387_TRUNC] = 1;
5098 4867
5099 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED); 4868 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
5100 operands[3] = assign_386_stack_local (HImode, SLOT_CW_TRUNC); 4869 operands[3] = assign_386_stack_local (HImode, SLOT_CW_TRUNC);
5101 if (memory_operand (operands[0], VOIDmode)) 4870
5102 emit_insn (gen_fix_trunc<mode>_i387 (operands[0], operands[1], 4871 emit_insn (gen_fix_trunc<mode>_i387 (operands[0], operands[1],
5103 operands[2], operands[3])); 4872 operands[2], operands[3]));
5104 else
5105 {
5106 operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
5107 emit_insn (gen_fix_trunc<mode>_i387_with_temp (operands[0], operands[1],
5108 operands[2], operands[3],
5109 operands[4]));
5110 }
5111 DONE; 4873 DONE;
5112 } 4874 }
5113 [(set_attr "type" "fistp") 4875 [(set_attr "type" "fistp")
5114 (set_attr "i387_cw" "trunc") 4876 (set_attr "i387_cw" "trunc")
5115 (set_attr "mode" "<MODE>")]) 4877 (set_attr "mode" "<MODE>")])
5116 4878
5117 (define_insn "fix_truncdi_i387" 4879 (define_insn "fix_truncdi_i387"
5118 [(set (match_operand:DI 0 "memory_operand" "=m") 4880 [(set (match_operand:DI 0 "nonimmediate_operand" "=m")
5119 (fix:DI (match_operand 1 "register_operand" "f"))) 4881 (fix:DI (match_operand 1 "register_operand" "f")))
5120 (use (match_operand:HI 2 "memory_operand" "m")) 4882 (use (match_operand:HI 2 "memory_operand" "m"))
5121 (use (match_operand:HI 3 "memory_operand" "m")) 4883 (use (match_operand:HI 3 "memory_operand" "m"))
5122 (clobber (match_scratch:XF 4 "=&1f"))] 4884 (clobber (match_scratch:XF 4 "=&f"))]
5123 "X87_FLOAT_MODE_P (GET_MODE (operands[1])) 4885 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
5124 && !TARGET_FISTTP 4886 && !TARGET_FISTTP
5125 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))" 4887 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
5126 "* return output_fix_trunc (insn, operands, false);" 4888 "* return output_fix_trunc (insn, operands, false);"
5127 [(set_attr "type" "fistp") 4889 [(set_attr "type" "fistp")
5128 (set_attr "i387_cw" "trunc") 4890 (set_attr "i387_cw" "trunc")
5129 (set_attr "mode" "DI")]) 4891 (set_attr "mode" "DI")])
5130 4892
5131 (define_insn "fix_truncdi_i387_with_temp"
5132 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
5133 (fix:DI (match_operand 1 "register_operand" "f,f")))
5134 (use (match_operand:HI 2 "memory_operand" "m,m"))
5135 (use (match_operand:HI 3 "memory_operand" "m,m"))
5136 (clobber (match_operand:DI 4 "memory_operand" "=X,m"))
5137 (clobber (match_scratch:XF 5 "=&1f,&1f"))]
5138 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
5139 && !TARGET_FISTTP
5140 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
5141 "#"
5142 [(set_attr "type" "fistp")
5143 (set_attr "i387_cw" "trunc")
5144 (set_attr "mode" "DI")])
5145
5146 (define_split
5147 [(set (match_operand:DI 0 "register_operand")
5148 (fix:DI (match_operand 1 "register_operand")))
5149 (use (match_operand:HI 2 "memory_operand"))
5150 (use (match_operand:HI 3 "memory_operand"))
5151 (clobber (match_operand:DI 4 "memory_operand"))
5152 (clobber (match_scratch 5))]
5153 "reload_completed"
5154 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
5155 (use (match_dup 2))
5156 (use (match_dup 3))
5157 (clobber (match_dup 5))])
5158 (set (match_dup 0) (match_dup 4))])
5159
5160 (define_split
5161 [(set (match_operand:DI 0 "memory_operand")
5162 (fix:DI (match_operand 1 "register_operand")))
5163 (use (match_operand:HI 2 "memory_operand"))
5164 (use (match_operand:HI 3 "memory_operand"))
5165 (clobber (match_operand:DI 4 "memory_operand"))
5166 (clobber (match_scratch 5))]
5167 "reload_completed"
5168 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
5169 (use (match_dup 2))
5170 (use (match_dup 3))
5171 (clobber (match_dup 5))])])
5172
5173 (define_insn "fix_trunc<mode>_i387" 4893 (define_insn "fix_trunc<mode>_i387"
5174 [(set (match_operand:SWI24 0 "memory_operand" "=m") 4894 [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m")
5175 (fix:SWI24 (match_operand 1 "register_operand" "f"))) 4895 (fix:SWI24 (match_operand 1 "register_operand" "f")))
5176 (use (match_operand:HI 2 "memory_operand" "m")) 4896 (use (match_operand:HI 2 "memory_operand" "m"))
5177 (use (match_operand:HI 3 "memory_operand" "m"))] 4897 (use (match_operand:HI 3 "memory_operand" "m"))]
5178 "X87_FLOAT_MODE_P (GET_MODE (operands[1])) 4898 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
5179 && !TARGET_FISTTP 4899 && !TARGET_FISTTP
5181 "* return output_fix_trunc (insn, operands, false);" 4901 "* return output_fix_trunc (insn, operands, false);"
5182 [(set_attr "type" "fistp") 4902 [(set_attr "type" "fistp")
5183 (set_attr "i387_cw" "trunc") 4903 (set_attr "i387_cw" "trunc")
5184 (set_attr "mode" "<MODE>")]) 4904 (set_attr "mode" "<MODE>")])
5185 4905
5186 (define_insn "fix_trunc<mode>_i387_with_temp"
5187 [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r")
5188 (fix:SWI24 (match_operand 1 "register_operand" "f,f")))
5189 (use (match_operand:HI 2 "memory_operand" "m,m"))
5190 (use (match_operand:HI 3 "memory_operand" "m,m"))
5191 (clobber (match_operand:SWI24 4 "memory_operand" "=X,m"))]
5192 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
5193 && !TARGET_FISTTP
5194 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
5195 "#"
5196 [(set_attr "type" "fistp")
5197 (set_attr "i387_cw" "trunc")
5198 (set_attr "mode" "<MODE>")])
5199
5200 (define_split
5201 [(set (match_operand:SWI24 0 "register_operand")
5202 (fix:SWI24 (match_operand 1 "register_operand")))
5203 (use (match_operand:HI 2 "memory_operand"))
5204 (use (match_operand:HI 3 "memory_operand"))
5205 (clobber (match_operand:SWI24 4 "memory_operand"))]
5206 "reload_completed"
5207 [(parallel [(set (match_dup 4) (fix:SWI24 (match_dup 1)))
5208 (use (match_dup 2))
5209 (use (match_dup 3))])
5210 (set (match_dup 0) (match_dup 4))])
5211
5212 (define_split
5213 [(set (match_operand:SWI24 0 "memory_operand")
5214 (fix:SWI24 (match_operand 1 "register_operand")))
5215 (use (match_operand:HI 2 "memory_operand"))
5216 (use (match_operand:HI 3 "memory_operand"))
5217 (clobber (match_operand:SWI24 4 "memory_operand"))]
5218 "reload_completed"
5219 [(parallel [(set (match_dup 0) (fix:SWI24 (match_dup 1)))
5220 (use (match_dup 2))
5221 (use (match_dup 3))])])
5222
5223 (define_insn "x86_fnstcw_1" 4906 (define_insn "x86_fnstcw_1"
5224 [(set (match_operand:HI 0 "memory_operand" "=m") 4907 [(set (match_operand:HI 0 "memory_operand" "=m")
5225 (unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))] 4908 (unspec:HI [(const_int 0)] UNSPEC_FSTCW))]
5226 "TARGET_80387" 4909 "TARGET_80387"
5227 "fnstcw\t%0" 4910 "fnstcw\t%0"
5228 [(set (attr "length") 4911 [(set (attr "length")
5229 (symbol_ref "ix86_attr_length_address_default (insn) + 2")) 4912 (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
5230 (set_attr "mode" "HI") 4913 (set_attr "mode" "HI")
5231 (set_attr "unit" "i387") 4914 (set_attr "unit" "i387")
5232 (set_attr "bdver1_decode" "vector")])
5233
5234 (define_insn "x86_fldcw_1"
5235 [(set (reg:HI FPCR_REG)
5236 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
5237 "TARGET_80387"
5238 "fldcw\t%0"
5239 [(set (attr "length")
5240 (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
5241 (set_attr "mode" "HI")
5242 (set_attr "unit" "i387")
5243 (set_attr "athlon_decode" "vector")
5244 (set_attr "amdfam10_decode" "vector")
5245 (set_attr "bdver1_decode" "vector")]) 4915 (set_attr "bdver1_decode" "vector")])
5246 4916
5247 ;; Conversion between fixed point and floating point. 4917 ;; Conversion between fixed point and floating point.
5248 4918
5249 ;; Even though we only accept memory inputs, the backend _really_ 4919 ;; Even though we only accept memory inputs, the backend _really_
5270 [(set_attr "type" "fmov") 4940 [(set_attr "type" "fmov")
5271 (set_attr "mode" "XF") 4941 (set_attr "mode" "XF")
5272 (set_attr "znver1_decode" "double") 4942 (set_attr "znver1_decode" "double")
5273 (set_attr "fp_int_src" "true")]) 4943 (set_attr "fp_int_src" "true")])
5274 4944
5275 (define_expand "float<SWI48:mode><MODEF:mode>2" 4945 (define_expand "float<SWI48x:mode><MODEF:mode>2"
5276 [(set (match_operand:MODEF 0 "register_operand") 4946 [(set (match_operand:MODEF 0 "register_operand")
5277 (float:MODEF (match_operand:SWI48 1 "nonimmediate_operand")))] 4947 (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand")))]
5278 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)" 4948 "(TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI48x:MODE>mode))
5279 { 4949 || (SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
5280 if (!(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH) 4950 && ((<SWI48x:MODE>mode != DImode) || TARGET_64BIT))")
5281 && !X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI48:MODE>mode)) 4951
5282 { 4952 (define_insn "*float<SWI48:mode><MODEF:mode>2"
5283 rtx reg = gen_reg_rtx (XFmode); 4953 [(set (match_operand:MODEF 0 "register_operand" "=f,v,v")
5284 rtx (*insn)(rtx, rtx);
5285
5286 emit_insn (gen_float<SWI48:mode>xf2 (reg, operands[1]));
5287
5288 if (<MODEF:MODE>mode == SFmode)
5289 insn = gen_truncxfsf2;
5290 else if (<MODEF:MODE>mode == DFmode)
5291 insn = gen_truncxfdf2;
5292 else
5293 gcc_unreachable ();
5294
5295 emit_insn (insn (operands[0], reg));
5296 DONE;
5297 }
5298 })
5299
5300 (define_insn "*float<SWI48:mode><MODEF:mode>2_mixed"
5301 [(set (match_operand:MODEF 0 "register_operand" "=f,Yc,v")
5302 (float:MODEF 4954 (float:MODEF
5303 (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))] 4955 (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
5304 "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH" 4956 "(TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI48:MODE>mode))
4957 || (SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)"
5305 "@ 4958 "@
5306 fild%Z1\t%1 4959 fild%Z1\t%1
5307 %vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1} 4960 %vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}
5308 %vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}" 4961 %vcvtsi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %d0|%d0, %1}"
5309 [(set_attr "type" "fmov,sseicvt,sseicvt") 4962 [(set_attr "type" "fmov,sseicvt,sseicvt")
5320 (set_attr "amdfam10_decode" "*,vector,double") 4973 (set_attr "amdfam10_decode" "*,vector,double")
5321 (set_attr "bdver1_decode" "*,double,direct") 4974 (set_attr "bdver1_decode" "*,double,direct")
5322 (set_attr "znver1_decode" "double,*,*") 4975 (set_attr "znver1_decode" "double,*,*")
5323 (set_attr "fp_int_src" "true") 4976 (set_attr "fp_int_src" "true")
5324 (set (attr "enabled") 4977 (set (attr "enabled")
5325 (cond [(eq_attr "alternative" "0") 4978 (if_then_else
5326 (symbol_ref "TARGET_MIX_SSE_I387 4979 (match_test ("SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"))
5327 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, 4980 (if_then_else
5328 <SWI48:MODE>mode)") 4981 (eq_attr "alternative" "0")
5329 ] 4982 (symbol_ref "TARGET_MIX_SSE_I387
5330 (symbol_ref "true")))]) 4983 && X87_ENABLE_FLOAT (<MODEF:MODE>mode,
5331 4984 <SWI48:MODE>mode)")
5332 (define_insn "*float<SWI48x:mode><MODEF:mode>2_i387" 4985 (symbol_ref "true"))
4986 (if_then_else
4987 (eq_attr "alternative" "0")
4988 (symbol_ref "true")
4989 (symbol_ref "false"))))
4990 (set (attr "preferred_for_speed")
4991 (cond [(eq_attr "alternative" "1")
4992 (symbol_ref "TARGET_INTER_UNIT_CONVERSIONS")]
4993 (symbol_ref "true")))])
4994
4995 (define_insn "*floatdi<MODEF:mode>2_i387"
5333 [(set (match_operand:MODEF 0 "register_operand" "=f") 4996 [(set (match_operand:MODEF 0 "register_operand" "=f")
5334 (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand" "m")))] 4997 (float:MODEF (match_operand:DI 1 "nonimmediate_operand" "m")))]
5335 "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI48x:MODE>mode)" 4998 "!TARGET_64BIT
4999 && TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, DImode)"
5336 "fild%Z1\t%1" 5000 "fild%Z1\t%1"
5337 [(set_attr "type" "fmov") 5001 [(set_attr "type" "fmov")
5338 (set_attr "mode" "<MODEF:MODE>") 5002 (set_attr "mode" "<MODEF:MODE>")
5339 (set_attr "znver1_decode" "double") 5003 (set_attr "znver1_decode" "double")
5340 (set_attr "fp_int_src" "true")]) 5004 (set_attr "fp_int_src" "true")])
5365 else 5029 else
5366 emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4])); 5030 emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
5367 DONE; 5031 DONE;
5368 }) 5032 })
5369 5033
5034 ;; Avoid store forwarding (partial memory) stall penalty
5035 ;; by passing DImode value through XMM registers. */
5036
5037 (define_split
5038 [(set (match_operand:X87MODEF 0 "register_operand")
5039 (float:X87MODEF
5040 (match_operand:DI 1 "register_operand")))]
5041 "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES_TO_VEC
5042 && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5043 && TARGET_SSE2 && optimize_function_for_speed_p (cfun)
5044 && can_create_pseudo_p ()"
5045 [(const_int 0)]
5046 {
5047 emit_insn (gen_floatdi<mode>2_i387_with_xmm
5048 (operands[0], operands[1],
5049 assign_386_stack_local (DImode, SLOT_TEMP)));
5050 DONE;
5051 })
5052
5053 (define_insn_and_split "floatdi<X87MODEF:mode>2_i387_with_xmm"
5054 [(set (match_operand:X87MODEF 0 "register_operand" "=f")
5055 (float:X87MODEF
5056 (match_operand:DI 1 "register_operand" "r")))
5057 (clobber (match_scratch:V4SI 3 "=x"))
5058 (clobber (match_scratch:V4SI 4 "=x"))
5059 (clobber (match_operand:DI 2 "memory_operand" "=m"))]
5060 "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES_TO_VEC
5061 && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5062 && TARGET_SSE2 && optimize_function_for_speed_p (cfun)"
5063 "#"
5064 "&& reload_completed"
5065 [(set (match_dup 2) (match_dup 3))
5066 (set (match_dup 0) (float:X87MODEF (match_dup 2)))]
5067 {
5068 /* The DImode arrived in a pair of integral registers (e.g. %edx:%eax).
5069 Assemble the 64-bit DImode value in an xmm register. */
5070 emit_insn (gen_sse2_loadld (operands[3], CONST0_RTX (V4SImode),
5071 gen_lowpart (SImode, operands[1])));
5072 emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode),
5073 gen_highpart (SImode, operands[1])));
5074 emit_insn (gen_vec_interleave_lowv4si (operands[3], operands[3],
5075 operands[4]));
5076
5077 operands[3] = gen_lowpart (DImode, operands[3]);
5078 }
5079 [(set_attr "type" "multi")
5080 (set_attr "mode" "<X87MODEF:MODE>")
5081 (set_attr "unit" "i387")
5082 (set_attr "fp_int_src" "true")])
5083
5370 ;; Avoid partial SSE register dependency stalls. This splitter should split 5084 ;; Avoid partial SSE register dependency stalls. This splitter should split
5371 ;; late in the pass sequence (after register rename pass), so allocated 5085 ;; late in the pass sequence (after register rename pass), so allocated
5372 ;; registers won't change anymore 5086 ;; registers won't change anymore
5373 5087
5374 (define_split 5088 (define_split
5390 5104
5391 operands[0] = lowpart_subreg (vmode, operands[0], <MODEF:MODE>mode); 5105 operands[0] = lowpart_subreg (vmode, operands[0], <MODEF:MODE>mode);
5392 emit_move_insn (operands[0], CONST0_RTX (vmode)); 5106 emit_move_insn (operands[0], CONST0_RTX (vmode));
5393 }) 5107 })
5394 5108
5395 ;; Break partial reg stall for cvtsd2ss. This splitter should split
5396 ;; late in the pass sequence (after register rename pass),
5397 ;; so allocated registers won't change anymore.
5398
5399 (define_split
5400 [(set (match_operand:SF 0 "sse_reg_operand")
5401 (float_truncate:SF
5402 (match_operand:DF 1 "nonimmediate_operand")))]
5403 "TARGET_SSE_PARTIAL_REG_DEPENDENCY && epilogue_completed
5404 && optimize_function_for_speed_p (cfun)
5405 && (!REG_P (operands[1])
5406 || REGNO (operands[0]) != REGNO (operands[1]))
5407 && (!EXT_REX_SSE_REG_P (operands[0])
5408 || TARGET_AVX512VL)"
5409 [(set (match_dup 0)
5410 (vec_merge:V4SF
5411 (vec_duplicate:V4SF
5412 (float_truncate:SF
5413 (match_dup 1)))
5414 (match_dup 0)
5415 (const_int 1)))]
5416 {
5417 operands[0] = lowpart_subreg (V4SFmode, operands[0], SFmode);
5418 emit_move_insn (operands[0], CONST0_RTX (V4SFmode));
5419 })
5420
5421 ;; Break partial reg stall for cvtss2sd. This splitter should split
5422 ;; late in the pass sequence (after register rename pass),
5423 ;; so allocated registers won't change anymore.
5424
5425 (define_split
5426 [(set (match_operand:DF 0 "sse_reg_operand")
5427 (float_extend:DF
5428 (match_operand:SF 1 "nonimmediate_operand")))]
5429 "TARGET_SSE_PARTIAL_REG_DEPENDENCY && epilogue_completed
5430 && optimize_function_for_speed_p (cfun)
5431 && (!REG_P (operands[1])
5432 || REGNO (operands[0]) != REGNO (operands[1]))
5433 && (!EXT_REX_SSE_REG_P (operands[0])
5434 || TARGET_AVX512VL)"
5435 [(set (match_dup 0)
5436 (vec_merge:V2DF
5437 (vec_duplicate:V2DF
5438 (float_extend:DF
5439 (match_dup 1)))
5440 (match_dup 0)
5441 (const_int 1)))]
5442 {
5443 operands[0] = lowpart_subreg (V2DFmode, operands[0], DFmode);
5444 emit_move_insn (operands[0], CONST0_RTX (V2DFmode));
5445 })
5446
5447 ;; Avoid store forwarding (partial memory) stall penalty
5448 ;; by passing DImode value through XMM registers. */
5449
5450 (define_insn "floatdi<X87MODEF:mode>2_i387_with_xmm"
5451 [(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
5452 (float:X87MODEF
5453 (match_operand:DI 1 "nonimmediate_operand" "m,?r")))
5454 (clobber (match_scratch:V4SI 3 "=X,x"))
5455 (clobber (match_scratch:V4SI 4 "=X,x"))
5456 (clobber (match_operand:DI 2 "memory_operand" "=X,m"))]
5457 "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5458 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC
5459 && !TARGET_64BIT && optimize_function_for_speed_p (cfun)"
5460 "#"
5461 [(set_attr "type" "multi")
5462 (set_attr "mode" "<X87MODEF:MODE>")
5463 (set_attr "unit" "i387")
5464 (set_attr "fp_int_src" "true")])
5465
5466 (define_split
5467 [(set (match_operand:X87MODEF 0 "fp_register_operand")
5468 (float:X87MODEF (match_operand:DI 1 "register_operand")))
5469 (clobber (match_scratch:V4SI 3))
5470 (clobber (match_scratch:V4SI 4))
5471 (clobber (match_operand:DI 2 "memory_operand"))]
5472 "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5473 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC
5474 && !TARGET_64BIT && optimize_function_for_speed_p (cfun)
5475 && reload_completed"
5476 [(set (match_dup 2) (match_dup 3))
5477 (set (match_dup 0) (float:X87MODEF (match_dup 2)))]
5478 {
5479 /* The DImode arrived in a pair of integral registers (e.g. %edx:%eax).
5480 Assemble the 64-bit DImode value in an xmm register. */
5481 emit_insn (gen_sse2_loadld (operands[3], CONST0_RTX (V4SImode),
5482 gen_lowpart (SImode, operands[1])));
5483 emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode),
5484 gen_highpart (SImode, operands[1])));
5485 emit_insn (gen_vec_interleave_lowv4si (operands[3], operands[3],
5486 operands[4]));
5487
5488 operands[3] = gen_lowpart (DImode, operands[3]);
5489 })
5490
5491 (define_split
5492 [(set (match_operand:X87MODEF 0 "fp_register_operand")
5493 (float:X87MODEF (match_operand:DI 1 "memory_operand")))
5494 (clobber (match_scratch:V4SI 3))
5495 (clobber (match_scratch:V4SI 4))
5496 (clobber (match_operand:DI 2 "memory_operand"))]
5497 "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5498 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC
5499 && !TARGET_64BIT && optimize_function_for_speed_p (cfun)
5500 && reload_completed"
5501 [(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
5502
5503 (define_expand "floatuns<SWI12:mode><MODEF:mode>2" 5109 (define_expand "floatuns<SWI12:mode><MODEF:mode>2"
5504 [(set (match_operand:MODEF 0 "register_operand") 5110 [(set (match_operand:MODEF 0 "register_operand")
5505 (unsigned_float:MODEF 5111 (unsigned_float:MODEF
5506 (match_operand:SWI12 1 "nonimmediate_operand")))] 5112 (match_operand:SWI12 1 "nonimmediate_operand")))]
5507 "!TARGET_64BIT 5113 "!TARGET_64BIT
5510 operands[1] = convert_to_mode (SImode, operands[1], 1); 5116 operands[1] = convert_to_mode (SImode, operands[1], 1);
5511 emit_insn (gen_floatsi<MODEF:mode>2 (operands[0], operands[1])); 5117 emit_insn (gen_floatsi<MODEF:mode>2 (operands[0], operands[1]));
5512 DONE; 5118 DONE;
5513 }) 5119 })
5514 5120
5121 (define_insn "*floatuns<SWI48:mode><MODEF:mode>2_avx512"
5122 [(set (match_operand:MODEF 0 "register_operand" "=v")
5123 (unsigned_float:MODEF
5124 (match_operand:SWI48 1 "nonimmediate_operand" "rm")))]
5125 "TARGET_AVX512F && TARGET_SSE_MATH"
5126 "vcvtusi2<MODEF:ssemodesuffix><SWI48:rex64suffix>\t{%1, %0, %0|%0, %0, %1}"
5127 [(set_attr "type" "sseicvt")
5128 (set_attr "prefix" "evex")
5129 (set_attr "mode" "<MODEF:MODE>")])
5130
5515 ;; Avoid store forwarding (partial memory) stall penalty by extending 5131 ;; Avoid store forwarding (partial memory) stall penalty by extending
5516 ;; SImode value to DImode through XMM register instead of pushing two 5132 ;; SImode value to DImode through XMM register instead of pushing two
5517 ;; SImode values to stack. Also note that fild loads from memory only. 5133 ;; SImode values to stack. Also note that fild loads from memory only.
5518 5134
5519 (define_insn_and_split "*floatunssi<mode>2_i387_with_xmm" 5135 (define_insn_and_split "floatunssi<mode>2_i387_with_xmm"
5520 [(set (match_operand:X87MODEF 0 "register_operand" "=f") 5136 [(set (match_operand:X87MODEF 0 "register_operand" "=f")
5521 (unsigned_float:X87MODEF 5137 (unsigned_float:X87MODEF
5522 (match_operand:SI 1 "nonimmediate_operand" "rm"))) 5138 (match_operand:SI 1 "nonimmediate_operand" "rm")))
5523 (clobber (match_scratch:DI 3 "=x")) 5139 (clobber (match_operand:DI 2 "memory_operand" "=m"))
5524 (clobber (match_operand:DI 2 "memory_operand" "=m"))] 5140 (clobber (match_scratch:DI 3 "=x"))]
5525 "!TARGET_64BIT 5141 "!TARGET_64BIT
5526 && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode) 5142 && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5527 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC" 5143 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC"
5528 "#" 5144 "#"
5529 "&& reload_completed" 5145 "&& reload_completed"
5534 "" 5150 ""
5535 [(set_attr "type" "multi") 5151 [(set_attr "type" "multi")
5536 (set_attr "mode" "<MODE>")]) 5152 (set_attr "mode" "<MODE>")])
5537 5153
5538 (define_expand "floatunssi<mode>2" 5154 (define_expand "floatunssi<mode>2"
5539 [(parallel 5155 [(set (match_operand:X87MODEF 0 "register_operand")
5540 [(set (match_operand:X87MODEF 0 "register_operand") 5156 (unsigned_float:X87MODEF
5541 (unsigned_float:X87MODEF 5157 (match_operand:SI 1 "nonimmediate_operand")))]
5542 (match_operand:SI 1 "nonimmediate_operand"))) 5158 "(!TARGET_64BIT
5543 (clobber (match_scratch:DI 3)) 5159 && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
5544 (clobber (match_dup 2))])] 5160 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC)
5545 "!TARGET_64BIT 5161 || ((!TARGET_64BIT || TARGET_AVX512F)
5546 && ((TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode) 5162 && SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
5547 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC) 5163 {
5548 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))" 5164 if (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
5549 { 5165 {
5550 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 5166 emit_insn (gen_floatunssi<mode>2_i387_with_xmm
5167 (operands[0], operands[1],
5168 assign_386_stack_local (DImode, SLOT_TEMP)));
5169 DONE;
5170 }
5171 if (!TARGET_AVX512F)
5551 { 5172 {
5552 ix86_expand_convert_uns_si<mode>_sse (operands[0], operands[1]); 5173 ix86_expand_convert_uns_si<mode>_sse (operands[0], operands[1]);
5553 DONE; 5174 DONE;
5554 } 5175 }
5555 else
5556 operands[2] = assign_386_stack_local (DImode, SLOT_TEMP);
5557 }) 5176 })
5558 5177
5559 (define_expand "floatunsdisf2" 5178 (define_expand "floatunsdisf2"
5560 [(use (match_operand:SF 0 "register_operand")) 5179 [(set (match_operand:SF 0 "register_operand")
5561 (use (match_operand:DI 1 "nonimmediate_operand"))] 5180 (unsigned_float:SF
5181 (match_operand:DI 1 "nonimmediate_operand")))]
5562 "TARGET_64BIT && TARGET_SSE && TARGET_SSE_MATH" 5182 "TARGET_64BIT && TARGET_SSE && TARGET_SSE_MATH"
5563 "x86_emit_floatuns (operands); DONE;") 5183 {
5184 if (!TARGET_AVX512F)
5185 {
5186 x86_emit_floatuns (operands);
5187 DONE;
5188 }
5189 })
5564 5190
5565 (define_expand "floatunsdidf2" 5191 (define_expand "floatunsdidf2"
5566 [(use (match_operand:DF 0 "register_operand")) 5192 [(set (match_operand:DF 0 "register_operand")
5567 (use (match_operand:DI 1 "nonimmediate_operand"))] 5193 (unsigned_float:DF
5568 "(TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK) 5194 (match_operand:DI 1 "nonimmediate_operand")))]
5195 "(TARGET_KEEPS_VECTOR_ALIGNED_STACK || TARGET_AVX512F)
5569 && TARGET_SSE2 && TARGET_SSE_MATH" 5196 && TARGET_SSE2 && TARGET_SSE_MATH"
5570 { 5197 {
5571 if (TARGET_64BIT) 5198 if (!TARGET_64BIT)
5572 x86_emit_floatuns (operands); 5199 {
5573 else 5200 ix86_expand_convert_uns_didf_sse (operands[0], operands[1]);
5574 ix86_expand_convert_uns_didf_sse (operands[0], operands[1]); 5201 DONE;
5575 DONE; 5202 }
5203 if (!TARGET_AVX512F)
5204 {
5205 x86_emit_floatuns (operands);
5206 DONE;
5207 }
5576 }) 5208 })
5577 5209
5578 ;; Load effective address instructions 5210 ;; Load effective address instructions
5579 5211
5580 (define_insn_and_split "*lea<mode>" 5212 (define_insn_and_split "*lea<mode>"
6821 [(set_attr "type" "alu") 6453 [(set_attr "type" "alu")
6822 (set_attr "use_carry" "1") 6454 (set_attr "use_carry" "1")
6823 (set_attr "pent_pair" "pu") 6455 (set_attr "pent_pair" "pu")
6824 (set_attr "mode" "<MODE>")]) 6456 (set_attr "mode" "<MODE>")])
6825 6457
6458 (define_insn "*add<mode>3_carry_0"
6459 [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
6460 (plus:SWI
6461 (match_operator:SWI 3 "ix86_carry_flag_operator"
6462 [(match_operand 2 "flags_reg_operand") (const_int 0)])
6463 (match_operand:SWI 1 "nonimmediate_operand" "0")))
6464 (clobber (reg:CC FLAGS_REG))]
6465 "ix86_unary_operator_ok (PLUS, <MODE>mode, operands)"
6466 "adc{<imodesuffix>}\t{$0, %0|%0, 0}"
6467 [(set_attr "type" "alu")
6468 (set_attr "use_carry" "1")
6469 (set_attr "pent_pair" "pu")
6470 (set_attr "mode" "<MODE>")])
6471
6826 (define_insn "*addsi3_carry_zext" 6472 (define_insn "*addsi3_carry_zext"
6827 [(set (match_operand:DI 0 "register_operand" "=r") 6473 [(set (match_operand:DI 0 "register_operand" "=r")
6828 (zero_extend:DI 6474 (zero_extend:DI
6829 (plus:SI 6475 (plus:SI
6830 (plus:SI (match_operator:SI 3 "ix86_carry_flag_operator" 6476 (plus:SI (match_operator:SI 3 "ix86_carry_flag_operator"
6832 (match_operand:SI 1 "register_operand" "%0")) 6478 (match_operand:SI 1 "register_operand" "%0"))
6833 (match_operand:SI 2 "x86_64_general_operand" "rme")))) 6479 (match_operand:SI 2 "x86_64_general_operand" "rme"))))
6834 (clobber (reg:CC FLAGS_REG))] 6480 (clobber (reg:CC FLAGS_REG))]
6835 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" 6481 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
6836 "adc{l}\t{%2, %k0|%k0, %2}" 6482 "adc{l}\t{%2, %k0|%k0, %2}"
6483 [(set_attr "type" "alu")
6484 (set_attr "use_carry" "1")
6485 (set_attr "pent_pair" "pu")
6486 (set_attr "mode" "SI")])
6487
6488 (define_insn "*addsi3_carry_zext_0"
6489 [(set (match_operand:DI 0 "register_operand" "=r")
6490 (zero_extend:DI
6491 (plus:SI (match_operator:SI 2 "ix86_carry_flag_operator"
6492 [(reg FLAGS_REG) (const_int 0)])
6493 (match_operand:SI 1 "register_operand" "0"))))
6494 (clobber (reg:CC FLAGS_REG))]
6495 "TARGET_64BIT"
6496 "adc{l}\t{$0, %k0|%k0, 0}"
6837 [(set_attr "type" "alu") 6497 [(set_attr "type" "alu")
6838 (set_attr "use_carry" "1") 6498 (set_attr "use_carry" "1")
6839 (set_attr "pent_pair" "pu") 6499 (set_attr "pent_pair" "pu")
6840 (set_attr "mode" "SI")]) 6500 (set_attr "mode" "SI")])
6841 6501
6893 [(set_attr "type" "alu") 6553 [(set_attr "type" "alu")
6894 (set_attr "use_carry" "1") 6554 (set_attr "use_carry" "1")
6895 (set_attr "pent_pair" "pu") 6555 (set_attr "pent_pair" "pu")
6896 (set_attr "mode" "<MODE>")]) 6556 (set_attr "mode" "<MODE>")])
6897 6557
6558 (define_insn "*sub<mode>3_carry_0"
6559 [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
6560 (minus:SWI
6561 (match_operand:SWI 1 "nonimmediate_operand" "0")
6562 (match_operator:SWI 3 "ix86_carry_flag_operator"
6563 [(match_operand 2 "flags_reg_operand") (const_int 0)])))
6564 (clobber (reg:CC FLAGS_REG))]
6565 "ix86_unary_operator_ok (MINUS, <MODE>mode, operands)"
6566 "sbb{<imodesuffix>}\t{$0, %0|%0, 0}"
6567 [(set_attr "type" "alu")
6568 (set_attr "use_carry" "1")
6569 (set_attr "pent_pair" "pu")
6570 (set_attr "mode" "<MODE>")])
6571
6898 (define_insn "*subsi3_carry_zext" 6572 (define_insn "*subsi3_carry_zext"
6899 [(set (match_operand:DI 0 "register_operand" "=r") 6573 [(set (match_operand:DI 0 "register_operand" "=r")
6900 (zero_extend:DI 6574 (zero_extend:DI
6901 (minus:SI 6575 (minus:SI
6902 (minus:SI 6576 (minus:SI
6905 [(reg FLAGS_REG) (const_int 0)])) 6579 [(reg FLAGS_REG) (const_int 0)]))
6906 (match_operand:SI 2 "x86_64_general_operand" "rme")))) 6580 (match_operand:SI 2 "x86_64_general_operand" "rme"))))
6907 (clobber (reg:CC FLAGS_REG))] 6581 (clobber (reg:CC FLAGS_REG))]
6908 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)" 6582 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6909 "sbb{l}\t{%2, %k0|%k0, %2}" 6583 "sbb{l}\t{%2, %k0|%k0, %2}"
6584 [(set_attr "type" "alu")
6585 (set_attr "use_carry" "1")
6586 (set_attr "pent_pair" "pu")
6587 (set_attr "mode" "SI")])
6588
6589 (define_insn "*subsi3_carry_zext_0"
6590 [(set (match_operand:DI 0 "register_operand" "=r")
6591 (zero_extend:DI
6592 (minus:SI
6593 (match_operand:SI 1 "register_operand" "0")
6594 (match_operator:SI 2 "ix86_carry_flag_operator"
6595 [(reg FLAGS_REG) (const_int 0)]))))
6596 (clobber (reg:CC FLAGS_REG))]
6597 "TARGET_64BIT"
6598 "sbb{l}\t{$0, %k0|%k0, 0}"
6910 [(set_attr "type" "alu") 6599 [(set_attr "type" "alu")
6911 (set_attr "use_carry" "1") 6600 (set_attr "use_carry" "1")
6912 (set_attr "pent_pair" "pu") 6601 (set_attr "pent_pair" "pu")
6913 (set_attr "mode" "SI")]) 6602 (set_attr "mode" "SI")])
6914 6603
7575 (set_attr "amdfam10_decode" "direct") 7264 (set_attr "amdfam10_decode" "direct")
7576 (set_attr "bdver1_decode" "direct") 7265 (set_attr "bdver1_decode" "direct")
7577 (set_attr "mode" "QI")]) 7266 (set_attr "mode" "QI")])
7578 7267
7579 (define_expand "<s>mul<mode>3_highpart" 7268 (define_expand "<s>mul<mode>3_highpart"
7580 [(parallel [(set (match_operand:SWI48 0 "register_operand") 7269 [(parallel [(set (match_operand:DWIH 0 "register_operand")
7581 (truncate:SWI48 7270 (truncate:DWIH
7582 (lshiftrt:<DWI> 7271 (lshiftrt:<DWI>
7583 (mult:<DWI> 7272 (mult:<DWI>
7584 (any_extend:<DWI> 7273 (any_extend:<DWI>
7585 (match_operand:SWI48 1 "nonimmediate_operand")) 7274 (match_operand:DWIH 1 "nonimmediate_operand"))
7586 (any_extend:<DWI> 7275 (any_extend:<DWI>
7587 (match_operand:SWI48 2 "register_operand"))) 7276 (match_operand:DWIH 2 "register_operand")))
7588 (match_dup 3)))) 7277 (match_dup 3))))
7589 (clobber (match_scratch:SWI48 4)) 7278 (clobber (match_scratch:DWIH 4))
7590 (clobber (reg:CC FLAGS_REG))])] 7279 (clobber (reg:CC FLAGS_REG))])]
7591 "" 7280 ""
7592 "operands[3] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));") 7281 "operands[3] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
7593 7282
7594 (define_insn "*<s>muldi3_highpart_1" 7283 (define_insn "*<s>muldi3_highpart_1"
9223 operands[1] = gen_lowpart (QImode, operands[1]); 8912 operands[1] = gen_lowpart (QImode, operands[1]);
9224 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); 8913 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
9225 }) 8914 })
9226 8915
9227 (define_insn "*andndi3_doubleword" 8916 (define_insn "*andndi3_doubleword"
9228 [(set (match_operand:DI 0 "register_operand" "=r,&r") 8917 [(set (match_operand:DI 0 "register_operand" "=&r,r,r,&r")
9229 (and:DI 8918 (and:DI
9230 (not:DI (match_operand:DI 1 "register_operand" "r,0")) 8919 (not:DI (match_operand:DI 1 "register_operand" "r,0,r,0"))
9231 (match_operand:DI 2 "nonimmediate_operand" "rm,rm"))) 8920 (match_operand:DI 2 "nonimmediate_operand" "rm,rm,0,rm")))
9232 (clobber (reg:CC FLAGS_REG))] 8921 (clobber (reg:CC FLAGS_REG))]
9233 "!TARGET_64BIT && TARGET_STV && TARGET_SSE2" 8922 "!TARGET_64BIT && TARGET_STV && TARGET_SSE2"
9234 "#" 8923 "#"
9235 [(set_attr "isa" "bmi,*")]) 8924 [(set_attr "isa" "bmi,bmi,bmi,*")])
9236 8925
9237 (define_split 8926 (define_split
9238 [(set (match_operand:DI 0 "register_operand") 8927 [(set (match_operand:DI 0 "register_operand")
9239 (and:DI 8928 (and:DI
9240 (not:DI (match_operand:DI 1 "register_operand")) 8929 (not:DI (match_operand:DI 1 "register_operand"))
9981 [(set (match_operand:X87MODEF 0 "register_operand" "=f") 9670 [(set (match_operand:X87MODEF 0 "register_operand" "=f")
9982 (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))] 9671 (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
9983 "TARGET_80387 9672 "TARGET_80387
9984 && (reload_completed 9673 && (reload_completed
9985 || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))" 9674 || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
9986 "f<absneg_mnemonic>" 9675 "<absneg_mnemonic>"
9987 [(set_attr "type" "fsgn") 9676 [(set_attr "type" "fsgn")
9988 (set_attr "mode" "<MODE>")]) 9677 (set_attr "mode" "<MODE>")])
9989
9990 (define_insn "*<code>extendsfdf2"
9991 [(set (match_operand:DF 0 "register_operand" "=f")
9992 (absneg:DF (float_extend:DF
9993 (match_operand:SF 1 "register_operand" "0"))))]
9994 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
9995 "f<absneg_mnemonic>"
9996 [(set_attr "type" "fsgn")
9997 (set_attr "mode" "DF")])
9998
9999 (define_insn "*<code>extendsfxf2"
10000 [(set (match_operand:XF 0 "register_operand" "=f")
10001 (absneg:XF (float_extend:XF
10002 (match_operand:SF 1 "register_operand" "0"))))]
10003 "TARGET_80387"
10004 "f<absneg_mnemonic>"
10005 [(set_attr "type" "fsgn")
10006 (set_attr "mode" "XF")])
10007
10008 (define_insn "*<code>extenddfxf2"
10009 [(set (match_operand:XF 0 "register_operand" "=f")
10010 (absneg:XF (float_extend:XF
10011 (match_operand:DF 1 "register_operand" "0"))))]
10012 "TARGET_80387"
10013 "f<absneg_mnemonic>"
10014 [(set_attr "type" "fsgn")
10015 (set_attr "mode" "XF")])
10016 9678
10017 ;; Copysign instructions 9679 ;; Copysign instructions
10018 9680
10019 (define_mode_iterator CSGNMODE [SF DF TF]) 9681 (define_mode_iterator CSGNMODE [SF DF TF])
10020 (define_mode_attr CSGNVMODE [(SF "V4SF") (DF "V2DF") (TF "TF")]) 9682 (define_mode_attr CSGNVMODE [(SF "V4SF") (DF "V2DF") (TF "TF")])
10028 "ix86_expand_copysign (operands); DONE;") 9690 "ix86_expand_copysign (operands); DONE;")
10029 9691
10030 (define_insn_and_split "copysign<mode>3_const" 9692 (define_insn_and_split "copysign<mode>3_const"
10031 [(set (match_operand:CSGNMODE 0 "register_operand" "=Yv") 9693 [(set (match_operand:CSGNMODE 0 "register_operand" "=Yv")
10032 (unspec:CSGNMODE 9694 (unspec:CSGNMODE
10033 [(match_operand:<CSGNVMODE> 1 "vector_move_operand" "YvmC") 9695 [(match_operand:<CSGNVMODE> 1 "nonimm_or_0_operand" "YvmC")
10034 (match_operand:CSGNMODE 2 "register_operand" "0") 9696 (match_operand:CSGNMODE 2 "register_operand" "0")
10035 (match_operand:<CSGNVMODE> 3 "nonimmediate_operand" "Yvm")] 9697 (match_operand:<CSGNVMODE> 3 "nonimmediate_operand" "Yvm")]
10036 UNSPEC_COPYSIGN))] 9698 UNSPEC_COPYSIGN))]
10037 "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 9699 "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
10038 || (TARGET_SSE && (<MODE>mode == TFmode))" 9700 || (TARGET_SSE && (<MODE>mode == TFmode))"
10207 (ashift:SDWIM (match_operand:SDWIM 1 "<ashl_input_operand>") 9869 (ashift:SDWIM (match_operand:SDWIM 1 "<ashl_input_operand>")
10208 (match_operand:QI 2 "nonmemory_operand")))] 9870 (match_operand:QI 2 "nonmemory_operand")))]
10209 "" 9871 ""
10210 "ix86_expand_binary_operator (ASHIFT, <MODE>mode, operands); DONE;") 9872 "ix86_expand_binary_operator (ASHIFT, <MODE>mode, operands); DONE;")
10211 9873
9874 (define_insn_and_split "*ashl<dwi>3_doubleword_mask"
9875 [(set (match_operand:<DWI> 0 "register_operand")
9876 (ashift:<DWI>
9877 (match_operand:<DWI> 1 "register_operand")
9878 (subreg:QI
9879 (and:SI
9880 (match_operand:SI 2 "register_operand" "c")
9881 (match_operand:SI 3 "const_int_operand")) 0)))
9882 (clobber (reg:CC FLAGS_REG))]
9883 "(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT)) == 0
9884 && can_create_pseudo_p ()"
9885 "#"
9886 "&& 1"
9887 [(parallel
9888 [(set (match_dup 6)
9889 (ior:DWIH (ashift:DWIH (match_dup 6) (match_dup 2))
9890 (lshiftrt:DWIH (match_dup 5)
9891 (minus:QI (match_dup 8) (match_dup 2)))))
9892 (clobber (reg:CC FLAGS_REG))])
9893 (parallel
9894 [(set (match_dup 4)
9895 (ashift:DWIH (match_dup 5) (match_dup 2)))
9896 (clobber (reg:CC FLAGS_REG))])]
9897 {
9898 split_double_mode (<DWI>mode, &operands[0], 2, &operands[4], &operands[6]);
9899
9900 operands[8] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);
9901
9902 if ((INTVAL (operands[3]) & ((<MODE_SIZE> * BITS_PER_UNIT) - 1))
9903 != ((<MODE_SIZE> * BITS_PER_UNIT) - 1))
9904 {
9905 rtx tem = gen_reg_rtx (SImode);
9906 emit_insn (gen_andsi3 (tem, operands[2], operands[3]));
9907 operands[2] = tem;
9908 }
9909
9910 operands[2] = gen_lowpart (QImode, operands[2]);
9911
9912 if (!rtx_equal_p (operands[6], operands[7]))
9913 emit_move_insn (operands[6], operands[7]);
9914 })
9915
9916 (define_insn_and_split "*ashl<dwi>3_doubleword_mask_1"
9917 [(set (match_operand:<DWI> 0 "register_operand")
9918 (ashift:<DWI>
9919 (match_operand:<DWI> 1 "register_operand")
9920 (and:QI
9921 (match_operand:QI 2 "register_operand" "c")
9922 (match_operand:QI 3 "const_int_operand"))))
9923 (clobber (reg:CC FLAGS_REG))]
9924 "(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT)) == 0
9925 && can_create_pseudo_p ()"
9926 "#"
9927 "&& 1"
9928 [(parallel
9929 [(set (match_dup 6)
9930 (ior:DWIH (ashift:DWIH (match_dup 6) (match_dup 2))
9931 (lshiftrt:DWIH (match_dup 5)
9932 (minus:QI (match_dup 8) (match_dup 2)))))
9933 (clobber (reg:CC FLAGS_REG))])
9934 (parallel
9935 [(set (match_dup 4)
9936 (ashift:DWIH (match_dup 5) (match_dup 2)))
9937 (clobber (reg:CC FLAGS_REG))])]
9938 {
9939 split_double_mode (<DWI>mode, &operands[0], 2, &operands[4], &operands[6]);
9940
9941 operands[8] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);
9942
9943 if ((INTVAL (operands[3]) & ((<MODE_SIZE> * BITS_PER_UNIT) - 1))
9944 != ((<MODE_SIZE> * BITS_PER_UNIT) - 1))
9945 {
9946 rtx tem = gen_reg_rtx (QImode);
9947 emit_insn (gen_andqi3 (tem, operands[2], operands[3]));
9948 operands[2] = tem;
9949 }
9950
9951 if (!rtx_equal_p (operands[6], operands[7]))
9952 emit_move_insn (operands[6], operands[7]);
9953 })
9954
10212 (define_insn "*ashl<mode>3_doubleword" 9955 (define_insn "*ashl<mode>3_doubleword"
10213 [(set (match_operand:DWI 0 "register_operand" "=&r") 9956 [(set (match_operand:DWI 0 "register_operand" "=&r")
10214 (ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "0n") 9957 (ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "0n")
10215 (match_operand:QI 2 "nonmemory_operand" "<S>c"))) 9958 (match_operand:QI 2 "nonmemory_operand" "<S>c")))
10216 (clobber (reg:CC FLAGS_REG))] 9959 (clobber (reg:CC FLAGS_REG))]
10326 [(set (match_operand:SWI48 0 "nonimmediate_operand") 10069 [(set (match_operand:SWI48 0 "nonimmediate_operand")
10327 (ashift:SWI48 10070 (ashift:SWI48
10328 (match_operand:SWI48 1 "nonimmediate_operand") 10071 (match_operand:SWI48 1 "nonimmediate_operand")
10329 (subreg:QI 10072 (subreg:QI
10330 (and:SI 10073 (and:SI
10331 (match_operand:SI 2 "register_operand") 10074 (match_operand:SI 2 "register_operand" "c,r")
10332 (match_operand:SI 3 "const_int_operand")) 0))) 10075 (match_operand:SI 3 "const_int_operand")) 0)))
10333 (clobber (reg:CC FLAGS_REG))] 10076 (clobber (reg:CC FLAGS_REG))]
10334 "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands) 10077 "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
10335 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) 10078 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
10336 == GET_MODE_BITSIZE (<MODE>mode)-1 10079 == GET_MODE_BITSIZE (<MODE>mode)-1
10340 [(parallel 10083 [(parallel
10341 [(set (match_dup 0) 10084 [(set (match_dup 0)
10342 (ashift:SWI48 (match_dup 1) 10085 (ashift:SWI48 (match_dup 1)
10343 (match_dup 2))) 10086 (match_dup 2)))
10344 (clobber (reg:CC FLAGS_REG))])] 10087 (clobber (reg:CC FLAGS_REG))])]
10345 "operands[2] = gen_lowpart (QImode, operands[2]);") 10088 "operands[2] = gen_lowpart (QImode, operands[2]);"
10089 [(set_attr "isa" "*,bmi2")])
10346 10090
10347 (define_insn_and_split "*ashl<mode>3_mask_1" 10091 (define_insn_and_split "*ashl<mode>3_mask_1"
10348 [(set (match_operand:SWI48 0 "nonimmediate_operand") 10092 [(set (match_operand:SWI48 0 "nonimmediate_operand")
10349 (ashift:SWI48 10093 (ashift:SWI48
10350 (match_operand:SWI48 1 "nonimmediate_operand") 10094 (match_operand:SWI48 1 "nonimmediate_operand")
10351 (and:QI 10095 (and:QI
10352 (match_operand:QI 2 "register_operand") 10096 (match_operand:QI 2 "register_operand" "c,r")
10353 (match_operand:QI 3 "const_int_operand")))) 10097 (match_operand:QI 3 "const_int_operand"))))
10354 (clobber (reg:CC FLAGS_REG))] 10098 (clobber (reg:CC FLAGS_REG))]
10355 "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands) 10099 "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
10356 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) 10100 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
10357 == GET_MODE_BITSIZE (<MODE>mode)-1 10101 == GET_MODE_BITSIZE (<MODE>mode)-1
10360 "&& 1" 10104 "&& 1"
10361 [(parallel 10105 [(parallel
10362 [(set (match_dup 0) 10106 [(set (match_dup 0)
10363 (ashift:SWI48 (match_dup 1) 10107 (ashift:SWI48 (match_dup 1)
10364 (match_dup 2))) 10108 (match_dup 2)))
10365 (clobber (reg:CC FLAGS_REG))])]) 10109 (clobber (reg:CC FLAGS_REG))])]
10110 ""
10111 [(set_attr "isa" "*,bmi2")])
10366 10112
10367 (define_insn "*bmi2_ashl<mode>3_1" 10113 (define_insn "*bmi2_ashl<mode>3_1"
10368 [(set (match_operand:SWI48 0 "register_operand" "=r") 10114 [(set (match_operand:SWI48 0 "register_operand" "=r")
10369 (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") 10115 (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
10370 (match_operand:SWI48 2 "register_operand" "r")))] 10116 (match_operand:SWI48 2 "register_operand" "r")))]
10620 && (TARGET_SHIFT1 10366 && (TARGET_SHIFT1
10621 || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))" 10367 || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))"
10622 { 10368 {
10623 switch (get_attr_type (insn)) 10369 switch (get_attr_type (insn))
10624 { 10370 {
10625 case TYPE_ALU: 10371 case TYPE_ALU1:
10626 gcc_assert (operands[1] == const1_rtx); 10372 gcc_assert (operands[1] == const1_rtx);
10627 return "add{b}\t%0, %0"; 10373 return "add{b}\t%0, %0";
10628 10374
10629 default: 10375 default:
10630 if (operands[1] == const1_rtx 10376 if (operands[1] == const1_rtx
10636 } 10382 }
10637 [(set (attr "type") 10383 [(set (attr "type")
10638 (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD") 10384 (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
10639 (match_operand 0 "register_operand")) 10385 (match_operand 0 "register_operand"))
10640 (match_operand 1 "const1_operand")) 10386 (match_operand 1 "const1_operand"))
10641 (const_string "alu") 10387 (const_string "alu1")
10642 ] 10388 ]
10643 (const_string "ishift1"))) 10389 (const_string "ishift1")))
10644 (set (attr "length_immediate") 10390 (set (attr "length_immediate")
10645 (if_then_else 10391 (if_then_else
10646 (ior (eq_attr "type" "alu") 10392 (ior (eq_attr "type" "alu1")
10647 (and (eq_attr "type" "ishift1") 10393 (and (eq_attr "type" "ishift1")
10648 (and (match_operand 1 "const1_operand") 10394 (and (match_operand 1 "const1_operand")
10649 (ior (match_test "TARGET_SHIFT1") 10395 (ior (match_test "TARGET_SHIFT1")
10650 (match_test "optimize_function_for_size_p (cfun)"))))) 10396 (match_test "optimize_function_for_size_p (cfun)")))))
10651 (const_string "0") 10397 (const_string "0")
10846 [(set (match_operand:SWI48 0 "nonimmediate_operand") 10592 [(set (match_operand:SWI48 0 "nonimmediate_operand")
10847 (any_shiftrt:SWI48 10593 (any_shiftrt:SWI48
10848 (match_operand:SWI48 1 "nonimmediate_operand") 10594 (match_operand:SWI48 1 "nonimmediate_operand")
10849 (subreg:QI 10595 (subreg:QI
10850 (and:SI 10596 (and:SI
10851 (match_operand:SI 2 "register_operand") 10597 (match_operand:SI 2 "register_operand" "c,r")
10852 (match_operand:SI 3 "const_int_operand")) 0))) 10598 (match_operand:SI 3 "const_int_operand")) 0)))
10853 (clobber (reg:CC FLAGS_REG))] 10599 (clobber (reg:CC FLAGS_REG))]
10854 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) 10600 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
10855 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) 10601 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
10856 == GET_MODE_BITSIZE (<MODE>mode)-1 10602 == GET_MODE_BITSIZE (<MODE>mode)-1
10860 [(parallel 10606 [(parallel
10861 [(set (match_dup 0) 10607 [(set (match_dup 0)
10862 (any_shiftrt:SWI48 (match_dup 1) 10608 (any_shiftrt:SWI48 (match_dup 1)
10863 (match_dup 2))) 10609 (match_dup 2)))
10864 (clobber (reg:CC FLAGS_REG))])] 10610 (clobber (reg:CC FLAGS_REG))])]
10865 "operands[2] = gen_lowpart (QImode, operands[2]);") 10611 "operands[2] = gen_lowpart (QImode, operands[2]);"
10612 [(set_attr "isa" "*,bmi2")])
10866 10613
10867 (define_insn_and_split "*<shift_insn><mode>3_mask_1" 10614 (define_insn_and_split "*<shift_insn><mode>3_mask_1"
10868 [(set (match_operand:SWI48 0 "nonimmediate_operand") 10615 [(set (match_operand:SWI48 0 "nonimmediate_operand")
10869 (any_shiftrt:SWI48 10616 (any_shiftrt:SWI48
10870 (match_operand:SWI48 1 "nonimmediate_operand") 10617 (match_operand:SWI48 1 "nonimmediate_operand")
10871 (and:QI 10618 (and:QI
10872 (match_operand:QI 2 "register_operand") 10619 (match_operand:QI 2 "register_operand" "c,r")
10873 (match_operand:QI 3 "const_int_operand")))) 10620 (match_operand:QI 3 "const_int_operand"))))
10874 (clobber (reg:CC FLAGS_REG))] 10621 (clobber (reg:CC FLAGS_REG))]
10875 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) 10622 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
10876 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) 10623 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
10877 == GET_MODE_BITSIZE (<MODE>mode)-1 10624 == GET_MODE_BITSIZE (<MODE>mode)-1
10880 "&& 1" 10627 "&& 1"
10881 [(parallel 10628 [(parallel
10882 [(set (match_dup 0) 10629 [(set (match_dup 0)
10883 (any_shiftrt:SWI48 (match_dup 1) 10630 (any_shiftrt:SWI48 (match_dup 1)
10884 (match_dup 2))) 10631 (match_dup 2)))
10885 (clobber (reg:CC FLAGS_REG))])]) 10632 (clobber (reg:CC FLAGS_REG))])]
10633 ""
10634 [(set_attr "isa" "*,bmi2")])
10635
10636 (define_insn_and_split "*<shift_insn><dwi>3_doubleword_mask"
10637 [(set (match_operand:<DWI> 0 "register_operand")
10638 (any_shiftrt:<DWI>
10639 (match_operand:<DWI> 1 "register_operand")
10640 (subreg:QI
10641 (and:SI
10642 (match_operand:SI 2 "register_operand" "c")
10643 (match_operand:SI 3 "const_int_operand")) 0)))
10644 (clobber (reg:CC FLAGS_REG))]
10645 "(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT)) == 0
10646 && can_create_pseudo_p ()"
10647 "#"
10648 "&& 1"
10649 [(parallel
10650 [(set (match_dup 4)
10651 (ior:DWIH (lshiftrt:DWIH (match_dup 4) (match_dup 2))
10652 (ashift:DWIH (match_dup 7)
10653 (minus:QI (match_dup 8) (match_dup 2)))))
10654 (clobber (reg:CC FLAGS_REG))])
10655 (parallel
10656 [(set (match_dup 6)
10657 (any_shiftrt:DWIH (match_dup 7) (match_dup 2)))
10658 (clobber (reg:CC FLAGS_REG))])]
10659 {
10660 split_double_mode (<DWI>mode, &operands[0], 2, &operands[4], &operands[6]);
10661
10662 operands[8] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);
10663
10664 if ((INTVAL (operands[3]) & ((<MODE_SIZE> * BITS_PER_UNIT) - 1))
10665 != ((<MODE_SIZE> * BITS_PER_UNIT) - 1))
10666 {
10667 rtx tem = gen_reg_rtx (SImode);
10668 emit_insn (gen_andsi3 (tem, operands[2], operands[3]));
10669 operands[2] = tem;
10670 }
10671
10672 operands[2] = gen_lowpart (QImode, operands[2]);
10673
10674 if (!rtx_equal_p (operands[4], operands[5]))
10675 emit_move_insn (operands[4], operands[5]);
10676 })
10677
10678 (define_insn_and_split "*<shift_insn><dwi>3_doubleword_mask_1"
10679 [(set (match_operand:<DWI> 0 "register_operand")
10680 (any_shiftrt:<DWI>
10681 (match_operand:<DWI> 1 "register_operand")
10682 (and:QI
10683 (match_operand:QI 2 "register_operand" "c")
10684 (match_operand:QI 3 "const_int_operand"))))
10685 (clobber (reg:CC FLAGS_REG))]
10686 "(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT)) == 0
10687 && can_create_pseudo_p ()"
10688 "#"
10689 "&& 1"
10690 [(parallel
10691 [(set (match_dup 4)
10692 (ior:DWIH (lshiftrt:DWIH (match_dup 4) (match_dup 2))
10693 (ashift:DWIH (match_dup 7)
10694 (minus:QI (match_dup 8) (match_dup 2)))))
10695 (clobber (reg:CC FLAGS_REG))])
10696 (parallel
10697 [(set (match_dup 6)
10698 (any_shiftrt:DWIH (match_dup 7) (match_dup 2)))
10699 (clobber (reg:CC FLAGS_REG))])]
10700 {
10701 split_double_mode (<DWI>mode, &operands[0], 2, &operands[4], &operands[6]);
10702
10703 operands[8] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);
10704
10705 if ((INTVAL (operands[3]) & ((<MODE_SIZE> * BITS_PER_UNIT) - 1))
10706 != ((<MODE_SIZE> * BITS_PER_UNIT) - 1))
10707 {
10708 rtx tem = gen_reg_rtx (QImode);
10709 emit_insn (gen_andqi3 (tem, operands[2], operands[3]));
10710 operands[2] = tem;
10711 }
10712
10713 if (!rtx_equal_p (operands[4], operands[5]))
10714 emit_move_insn (operands[4], operands[5]);
10715 })
10886 10716
10887 (define_insn_and_split "*<shift_insn><mode>3_doubleword" 10717 (define_insn_and_split "*<shift_insn><mode>3_doubleword"
10888 [(set (match_operand:DWI 0 "register_operand" "=&r") 10718 [(set (match_operand:DWI 0 "register_operand" "=&r")
10889 (any_shiftrt:DWI (match_operand:DWI 1 "register_operand" "0") 10719 (any_shiftrt:DWI (match_operand:DWI 1 "register_operand" "0")
10890 (match_operand:QI 2 "nonmemory_operand" "<S>c"))) 10720 (match_operand:QI 2 "nonmemory_operand" "<S>c")))
11325 [(set (match_operand:SWI48 0 "nonimmediate_operand") 11155 [(set (match_operand:SWI48 0 "nonimmediate_operand")
11326 (any_rotate:SWI48 11156 (any_rotate:SWI48
11327 (match_operand:SWI48 1 "nonimmediate_operand") 11157 (match_operand:SWI48 1 "nonimmediate_operand")
11328 (subreg:QI 11158 (subreg:QI
11329 (and:SI 11159 (and:SI
11330 (match_operand:SI 2 "register_operand") 11160 (match_operand:SI 2 "register_operand" "c")
11331 (match_operand:SI 3 "const_int_operand")) 0))) 11161 (match_operand:SI 3 "const_int_operand")) 0)))
11332 (clobber (reg:CC FLAGS_REG))] 11162 (clobber (reg:CC FLAGS_REG))]
11333 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) 11163 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
11334 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) 11164 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
11335 == GET_MODE_BITSIZE (<MODE>mode)-1 11165 == GET_MODE_BITSIZE (<MODE>mode)-1
11346 (define_insn_and_split "*<rotate_insn><mode>3_mask_1" 11176 (define_insn_and_split "*<rotate_insn><mode>3_mask_1"
11347 [(set (match_operand:SWI48 0 "nonimmediate_operand") 11177 [(set (match_operand:SWI48 0 "nonimmediate_operand")
11348 (any_rotate:SWI48 11178 (any_rotate:SWI48
11349 (match_operand:SWI48 1 "nonimmediate_operand") 11179 (match_operand:SWI48 1 "nonimmediate_operand")
11350 (and:QI 11180 (and:QI
11351 (match_operand:QI 2 "register_operand") 11181 (match_operand:QI 2 "register_operand" "c")
11352 (match_operand:QI 3 "const_int_operand")))) 11182 (match_operand:QI 3 "const_int_operand"))))
11353 (clobber (reg:CC FLAGS_REG))] 11183 (clobber (reg:CC FLAGS_REG))]
11354 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) 11184 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
11355 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) 11185 && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
11356 == GET_MODE_BITSIZE (<MODE>mode)-1 11186 == GET_MODE_BITSIZE (<MODE>mode)-1
11610 (const_string "0") 11440 (const_string "0")
11611 (const_string "*"))) 11441 (const_string "*")))
11612 (set_attr "mode" "QI")]) 11442 (set_attr "mode" "QI")])
11613 11443
11614 (define_split 11444 (define_split
11615 [(set (match_operand:HI 0 "register_operand") 11445 [(set (match_operand:HI 0 "QIreg_operand")
11616 (any_rotate:HI (match_dup 0) (const_int 8))) 11446 (any_rotate:HI (match_dup 0) (const_int 8)))
11617 (clobber (reg:CC FLAGS_REG))] 11447 (clobber (reg:CC FLAGS_REG))]
11618 "reload_completed 11448 "reload_completed
11619 && (TARGET_USE_XCHGB || optimize_function_for_size_p (cfun))" 11449 && (TARGET_USE_XCHGB || optimize_function_for_size_p (cfun))"
11620 [(parallel [(set (strict_low_part (match_dup 0)) 11450 [(parallel [(set (strict_low_part (match_dup 0))
12202 (and (ge (minus (match_dup 0) (pc)) 12032 (and (ge (minus (match_dup 0) (pc))
12203 (const_int -126)) 12033 (const_int -126))
12204 (lt (minus (match_dup 0) (pc)) 12034 (lt (minus (match_dup 0) (pc))
12205 (const_int 128))) 12035 (const_int 128)))
12206 (const_int 2) 12036 (const_int 2)
12207 (const_int 6))) 12037 (const_int 6)))])
12208 (set_attr "maybe_prefix_bnd" "1")])
12209 12038
12210 ;; In general it is not safe to assume too much about CCmode registers, 12039 ;; In general it is not safe to assume too much about CCmode registers,
12211 ;; so simplify-rtx stops when it sees a second one. Under certain 12040 ;; so simplify-rtx stops when it sees a second one. Under certain
12212 ;; conditions this is safe on x86, so help combine not create 12041 ;; conditions this is safe on x86, so help combine not create
12213 ;; 12042 ;;
12271 (and (ge (minus (match_dup 0) (pc)) 12100 (and (ge (minus (match_dup 0) (pc))
12272 (const_int -126)) 12101 (const_int -126))
12273 (lt (minus (match_dup 0) (pc)) 12102 (lt (minus (match_dup 0) (pc))
12274 (const_int 128))) 12103 (const_int 128)))
12275 (const_int 2) 12104 (const_int 2)
12276 (const_int 5))) 12105 (const_int 5)))])
12277 (set_attr "maybe_prefix_bnd" "1")])
12278 12106
12279 (define_expand "indirect_jump" 12107 (define_expand "indirect_jump"
12280 [(set (pc) (match_operand 0 "indirect_branch_operand"))] 12108 [(set (pc) (match_operand 0 "indirect_branch_operand"))]
12281 "" 12109 ""
12282 { 12110 {
12283 if (TARGET_X32) 12111 if (TARGET_X32 || TARGET_INDIRECT_BRANCH_REGISTER)
12284 operands[0] = convert_memory_address (word_mode, operands[0]); 12112 operands[0] = convert_memory_address (word_mode, operands[0]);
12113 cfun->machine->has_local_indirect_jump = true;
12285 }) 12114 })
12286 12115
12287 (define_insn "*indirect_jump" 12116 (define_insn "*indirect_jump"
12288 [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rBw"))] 12117 [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rBw"))]
12289 "" 12118 ""
12290 "%!jmp\t%A0" 12119 "* return ix86_output_indirect_jmp (operands[0]);"
12291 [(set_attr "type" "ibr") 12120 [(set (attr "type")
12292 (set_attr "length_immediate" "0") 12121 (if_then_else (match_test "(cfun->machine->indirect_branch_type
12293 (set_attr "maybe_prefix_bnd" "1")]) 12122 != indirect_branch_keep)")
12123 (const_string "multi")
12124 (const_string "ibr")))
12125 (set_attr "length_immediate" "0")])
12294 12126
12295 (define_expand "tablejump" 12127 (define_expand "tablejump"
12296 [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand")) 12128 [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand"))
12297 (use (label_ref (match_operand 1)))])] 12129 (use (label_ref (match_operand 1)))])]
12298 "" 12130 ""
12327 12159
12328 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0, 12160 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
12329 OPTAB_DIRECT); 12161 OPTAB_DIRECT);
12330 } 12162 }
12331 12163
12332 if (TARGET_X32) 12164 if (TARGET_X32 || TARGET_INDIRECT_BRANCH_REGISTER)
12333 operands[0] = convert_memory_address (word_mode, operands[0]); 12165 operands[0] = convert_memory_address (word_mode, operands[0]);
12166 cfun->machine->has_local_indirect_jump = true;
12334 }) 12167 })
12335 12168
12336 (define_insn "*tablejump_1" 12169 (define_insn "*tablejump_1"
12337 [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rBw")) 12170 [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rBw"))
12338 (use (label_ref (match_operand 1)))] 12171 (use (label_ref (match_operand 1)))]
12339 "" 12172 ""
12340 "%!jmp\t%A0" 12173 "* return ix86_output_indirect_jmp (operands[0]);"
12341 [(set_attr "type" "ibr") 12174 [(set (attr "type")
12342 (set_attr "length_immediate" "0") 12175 (if_then_else (match_test "(cfun->machine->indirect_branch_type
12343 (set_attr "maybe_prefix_bnd" "1")]) 12176 != indirect_branch_keep)")
12177 (const_string "multi")
12178 (const_string "ibr")))
12179 (set_attr "length_immediate" "0")])
12344 12180
12345 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap. 12181 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
12346 12182
12347 (define_peephole2 12183 (define_peephole2
12348 [(set (reg FLAGS_REG) (match_operand 0)) 12184 [(set (reg FLAGS_REG) (match_operand 0))
12373 (set (match_operand 3 "any_QIreg_operand") 12209 (set (match_operand 3 "any_QIreg_operand")
12374 (zero_extend (match_dup 1)))] 12210 (zero_extend (match_dup 1)))]
12375 "(peep2_reg_dead_p (3, operands[1]) 12211 "(peep2_reg_dead_p (3, operands[1])
12376 || operands_match_p (operands[1], operands[3])) 12212 || operands_match_p (operands[1], operands[3]))
12377 && ! reg_overlap_mentioned_p (operands[3], operands[0]) 12213 && ! reg_overlap_mentioned_p (operands[3], operands[0])
12214 && ! reg_overlap_mentioned_p (operands[3], operands[4])
12378 && ! reg_set_p (operands[3], operands[4]) 12215 && ! reg_set_p (operands[3], operands[4])
12379 && peep2_regno_dead_p (0, FLAGS_REG)" 12216 && peep2_regno_dead_p (0, FLAGS_REG)"
12380 [(parallel [(set (match_dup 5) (match_dup 0)) 12217 [(parallel [(set (match_dup 5) (match_dup 0))
12381 (match_dup 4)]) 12218 (match_dup 4)])
12382 (set (strict_low_part (match_dup 6)) 12219 (set (strict_low_part (match_dup 6))
12398 (zero_extend (match_dup 2)))] 12235 (zero_extend (match_dup 2)))]
12399 "(peep2_reg_dead_p (4, operands[2]) 12236 "(peep2_reg_dead_p (4, operands[2])
12400 || operands_match_p (operands[2], operands[4])) 12237 || operands_match_p (operands[2], operands[4]))
12401 && ! reg_overlap_mentioned_p (operands[4], operands[0]) 12238 && ! reg_overlap_mentioned_p (operands[4], operands[0])
12402 && ! reg_overlap_mentioned_p (operands[4], operands[1]) 12239 && ! reg_overlap_mentioned_p (operands[4], operands[1])
12240 && ! reg_overlap_mentioned_p (operands[4], operands[5])
12403 && ! reg_set_p (operands[4], operands[5]) 12241 && ! reg_set_p (operands[4], operands[5])
12404 && refers_to_regno_p (FLAGS_REG, operands[1], (rtx *)NULL) 12242 && refers_to_regno_p (FLAGS_REG, operands[1], (rtx *)NULL)
12405 && peep2_regno_dead_p (0, FLAGS_REG)" 12243 && peep2_regno_dead_p (0, FLAGS_REG)"
12406 [(set (match_dup 6) (match_dup 0)) 12244 [(set (match_dup 6) (match_dup 0))
12407 (parallel [(set (match_dup 7) (match_dup 1)) 12245 (parallel [(set (match_dup 7) (match_dup 1))
12447 (zero_extend (match_dup 1))) 12285 (zero_extend (match_dup 1)))
12448 (clobber (reg:CC FLAGS_REG))])] 12286 (clobber (reg:CC FLAGS_REG))])]
12449 "(peep2_reg_dead_p (3, operands[1]) 12287 "(peep2_reg_dead_p (3, operands[1])
12450 || operands_match_p (operands[1], operands[3])) 12288 || operands_match_p (operands[1], operands[3]))
12451 && ! reg_overlap_mentioned_p (operands[3], operands[0]) 12289 && ! reg_overlap_mentioned_p (operands[3], operands[0])
12290 && ! reg_overlap_mentioned_p (operands[3], operands[4])
12452 && ! reg_set_p (operands[3], operands[4]) 12291 && ! reg_set_p (operands[3], operands[4])
12453 && peep2_regno_dead_p (0, FLAGS_REG)" 12292 && peep2_regno_dead_p (0, FLAGS_REG)"
12454 [(parallel [(set (match_dup 5) (match_dup 0)) 12293 [(parallel [(set (match_dup 5) (match_dup 0))
12455 (match_dup 4)]) 12294 (match_dup 4)])
12456 (set (strict_low_part (match_dup 6)) 12295 (set (strict_low_part (match_dup 6))
12473 (clobber (reg:CC FLAGS_REG))])] 12312 (clobber (reg:CC FLAGS_REG))])]
12474 "(peep2_reg_dead_p (4, operands[2]) 12313 "(peep2_reg_dead_p (4, operands[2])
12475 || operands_match_p (operands[2], operands[4])) 12314 || operands_match_p (operands[2], operands[4]))
12476 && ! reg_overlap_mentioned_p (operands[4], operands[0]) 12315 && ! reg_overlap_mentioned_p (operands[4], operands[0])
12477 && ! reg_overlap_mentioned_p (operands[4], operands[1]) 12316 && ! reg_overlap_mentioned_p (operands[4], operands[1])
12317 && ! reg_overlap_mentioned_p (operands[4], operands[5])
12478 && ! reg_set_p (operands[4], operands[5]) 12318 && ! reg_set_p (operands[4], operands[5])
12479 && refers_to_regno_p (FLAGS_REG, operands[1], (rtx *)NULL) 12319 && refers_to_regno_p (FLAGS_REG, operands[1], (rtx *)NULL)
12480 && peep2_regno_dead_p (0, FLAGS_REG)" 12320 && peep2_regno_dead_p (0, FLAGS_REG)"
12481 [(set (match_dup 6) (match_dup 0)) 12321 [(set (match_dup 6) (match_dup 0))
12482 (parallel [(set (match_dup 7) (match_dup 1)) 12322 (parallel [(set (match_dup 7) (match_dup 1))
12552 [(call (mem:QI 12392 [(call (mem:QI
12553 (mem:SI (plus:SI 12393 (mem:SI (plus:SI
12554 (match_operand:SI 0 "register_no_elim_operand" "U") 12394 (match_operand:SI 0 "register_no_elim_operand" "U")
12555 (match_operand:SI 1 "GOT32_symbol_operand")))) 12395 (match_operand:SI 1 "GOT32_symbol_operand"))))
12556 (match_operand 2))] 12396 (match_operand 2))]
12557 "!TARGET_MACHO && !TARGET_64BIT && SIBLING_CALL_P (insn)" 12397 "!TARGET_MACHO
12398 && !TARGET_64BIT
12399 && !TARGET_INDIRECT_BRANCH_REGISTER
12400 && SIBLING_CALL_P (insn)"
12558 { 12401 {
12559 rtx fnaddr = gen_rtx_PLUS (SImode, operands[0], operands[1]); 12402 rtx fnaddr = gen_rtx_PLUS (SImode, operands[0], operands[1]);
12560 fnaddr = gen_const_mem (SImode, fnaddr); 12403 fnaddr = gen_const_mem (SImode, fnaddr);
12561 return ix86_output_call_insn (insn, fnaddr); 12404 return ix86_output_call_insn (insn, fnaddr);
12562 } 12405 }
12571 12414
12572 (define_insn "*sibcall_memory" 12415 (define_insn "*sibcall_memory"
12573 [(call (mem:QI (match_operand:W 0 "memory_operand" "m")) 12416 [(call (mem:QI (match_operand:W 0 "memory_operand" "m"))
12574 (match_operand 1)) 12417 (match_operand 1))
12575 (unspec [(const_int 0)] UNSPEC_PEEPSIB)] 12418 (unspec [(const_int 0)] UNSPEC_PEEPSIB)]
12576 "!TARGET_X32" 12419 "!TARGET_X32 && !TARGET_INDIRECT_BRANCH_REGISTER"
12577 "* return ix86_output_call_insn (insn, operands[0]);" 12420 "* return ix86_output_call_insn (insn, operands[0]);"
12578 [(set_attr "type" "call")]) 12421 [(set_attr "type" "call")])
12579 12422
12580 (define_peephole2 12423 (define_peephole2
12581 [(set (match_operand:W 0 "register_operand") 12424 [(set (match_operand:W 0 "register_operand")
12582 (match_operand:W 1 "memory_operand")) 12425 (match_operand:W 1 "memory_operand"))
12583 (call (mem:QI (match_dup 0)) 12426 (call (mem:QI (match_dup 0))
12584 (match_operand 3))] 12427 (match_operand 3))]
12585 "!TARGET_X32 && SIBLING_CALL_P (peep2_next_insn (1)) 12428 "!TARGET_X32
12429 && !TARGET_INDIRECT_BRANCH_REGISTER
12430 && SIBLING_CALL_P (peep2_next_insn (1))
12586 && !reg_mentioned_p (operands[0], 12431 && !reg_mentioned_p (operands[0],
12587 CALL_INSN_FUNCTION_USAGE (peep2_next_insn (1)))" 12432 CALL_INSN_FUNCTION_USAGE (peep2_next_insn (1)))"
12588 [(parallel [(call (mem:QI (match_dup 1)) 12433 [(parallel [(call (mem:QI (match_dup 1))
12589 (match_dup 3)) 12434 (match_dup 3))
12590 (unspec [(const_int 0)] UNSPEC_PEEPSIB)])]) 12435 (unspec [(const_int 0)] UNSPEC_PEEPSIB)])])
12593 [(set (match_operand:W 0 "register_operand") 12438 [(set (match_operand:W 0 "register_operand")
12594 (match_operand:W 1 "memory_operand")) 12439 (match_operand:W 1 "memory_operand"))
12595 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 12440 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
12596 (call (mem:QI (match_dup 0)) 12441 (call (mem:QI (match_dup 0))
12597 (match_operand 3))] 12442 (match_operand 3))]
12598 "!TARGET_X32 && SIBLING_CALL_P (peep2_next_insn (2)) 12443 "!TARGET_X32
12444 && !TARGET_INDIRECT_BRANCH_REGISTER
12445 && SIBLING_CALL_P (peep2_next_insn (2))
12599 && !reg_mentioned_p (operands[0], 12446 && !reg_mentioned_p (operands[0],
12600 CALL_INSN_FUNCTION_USAGE (peep2_next_insn (2)))" 12447 CALL_INSN_FUNCTION_USAGE (peep2_next_insn (2)))"
12601 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 12448 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
12602 (parallel [(call (mem:QI (match_dup 1)) 12449 (parallel [(call (mem:QI (match_dup 1))
12603 (match_dup 3)) 12450 (match_dup 3))
12615 operands[2], operands[3], false); 12462 operands[2], operands[3], false);
12616 DONE; 12463 DONE;
12617 }) 12464 })
12618 12465
12619 (define_insn "*call_pop" 12466 (define_insn "*call_pop"
12620 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lmBz")) 12467 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lBwBz"))
12621 (match_operand 1)) 12468 (match_operand 1))
12622 (set (reg:SI SP_REG) 12469 (set (reg:SI SP_REG)
12623 (plus:SI (reg:SI SP_REG) 12470 (plus:SI (reg:SI SP_REG)
12624 (match_operand:SI 2 "immediate_operand" "i")))] 12471 (match_operand:SI 2 "immediate_operand" "i")))]
12625 "!TARGET_64BIT && !SIBLING_CALL_P (insn)" 12472 "!TARGET_64BIT && !SIBLING_CALL_P (insn)"
12635 "!TARGET_64BIT && SIBLING_CALL_P (insn)" 12482 "!TARGET_64BIT && SIBLING_CALL_P (insn)"
12636 "* return ix86_output_call_insn (insn, operands[0]);" 12483 "* return ix86_output_call_insn (insn, operands[0]);"
12637 [(set_attr "type" "call")]) 12484 [(set_attr "type" "call")])
12638 12485
12639 (define_insn "*sibcall_pop_memory" 12486 (define_insn "*sibcall_pop_memory"
12640 [(call (mem:QI (match_operand:SI 0 "memory_operand" "m")) 12487 [(call (mem:QI (match_operand:SI 0 "memory_operand" "Bs"))
12641 (match_operand 1)) 12488 (match_operand 1))
12642 (set (reg:SI SP_REG) 12489 (set (reg:SI SP_REG)
12643 (plus:SI (reg:SI SP_REG) 12490 (plus:SI (reg:SI SP_REG)
12644 (match_operand:SI 2 "immediate_operand" "i"))) 12491 (match_operand:SI 2 "immediate_operand" "i")))
12645 (unspec [(const_int 0)] UNSPEC_PEEPSIB)] 12492 (unspec [(const_int 0)] UNSPEC_PEEPSIB)]
12689 12536
12690 (define_peephole2 12537 (define_peephole2
12691 [(set (match_operand:W 0 "register_operand") 12538 [(set (match_operand:W 0 "register_operand")
12692 (match_operand:W 1 "memory_operand")) 12539 (match_operand:W 1 "memory_operand"))
12693 (set (pc) (match_dup 0))] 12540 (set (pc) (match_dup 0))]
12694 "!TARGET_X32 && peep2_reg_dead_p (2, operands[0])" 12541 "!TARGET_X32
12542 && !TARGET_INDIRECT_BRANCH_REGISTER
12543 && peep2_reg_dead_p (2, operands[0])"
12695 [(set (pc) (match_dup 1))]) 12544 [(set (pc) (match_dup 1))])
12696 12545
12697 ;; Call subroutine, returning value in operand 0 12546 ;; Call subroutine, returning value in operand 0
12698 12547
12699 (define_expand "call_value" 12548 (define_expand "call_value"
12749 (call (mem:QI 12598 (call (mem:QI
12750 (mem:SI (plus:SI 12599 (mem:SI (plus:SI
12751 (match_operand:SI 1 "register_no_elim_operand" "U") 12600 (match_operand:SI 1 "register_no_elim_operand" "U")
12752 (match_operand:SI 2 "GOT32_symbol_operand")))) 12601 (match_operand:SI 2 "GOT32_symbol_operand"))))
12753 (match_operand 3)))] 12602 (match_operand 3)))]
12754 "!TARGET_MACHO && !TARGET_64BIT && SIBLING_CALL_P (insn)" 12603 "!TARGET_MACHO
12604 && !TARGET_64BIT
12605 && !TARGET_INDIRECT_BRANCH_REGISTER
12606 && SIBLING_CALL_P (insn)"
12755 { 12607 {
12756 rtx fnaddr = gen_rtx_PLUS (SImode, operands[1], operands[2]); 12608 rtx fnaddr = gen_rtx_PLUS (SImode, operands[1], operands[2]);
12757 fnaddr = gen_const_mem (SImode, fnaddr); 12609 fnaddr = gen_const_mem (SImode, fnaddr);
12758 return ix86_output_call_insn (insn, fnaddr); 12610 return ix86_output_call_insn (insn, fnaddr);
12759 } 12611 }
12770 (define_insn "*sibcall_value_memory" 12622 (define_insn "*sibcall_value_memory"
12771 [(set (match_operand 0) 12623 [(set (match_operand 0)
12772 (call (mem:QI (match_operand:W 1 "memory_operand" "m")) 12624 (call (mem:QI (match_operand:W 1 "memory_operand" "m"))
12773 (match_operand 2))) 12625 (match_operand 2)))
12774 (unspec [(const_int 0)] UNSPEC_PEEPSIB)] 12626 (unspec [(const_int 0)] UNSPEC_PEEPSIB)]
12775 "!TARGET_X32" 12627 "!TARGET_X32 && !TARGET_INDIRECT_BRANCH_REGISTER"
12776 "* return ix86_output_call_insn (insn, operands[1]);" 12628 "* return ix86_output_call_insn (insn, operands[1]);"
12777 [(set_attr "type" "callv")]) 12629 [(set_attr "type" "callv")])
12778 12630
12779 (define_peephole2 12631 (define_peephole2
12780 [(set (match_operand:W 0 "register_operand") 12632 [(set (match_operand:W 0 "register_operand")
12781 (match_operand:W 1 "memory_operand")) 12633 (match_operand:W 1 "memory_operand"))
12782 (set (match_operand 2) 12634 (set (match_operand 2)
12783 (call (mem:QI (match_dup 0)) 12635 (call (mem:QI (match_dup 0))
12784 (match_operand 3)))] 12636 (match_operand 3)))]
12785 "!TARGET_X32 && SIBLING_CALL_P (peep2_next_insn (1)) 12637 "!TARGET_X32
12638 && !TARGET_INDIRECT_BRANCH_REGISTER
12639 && SIBLING_CALL_P (peep2_next_insn (1))
12786 && !reg_mentioned_p (operands[0], 12640 && !reg_mentioned_p (operands[0],
12787 CALL_INSN_FUNCTION_USAGE (peep2_next_insn (1)))" 12641 CALL_INSN_FUNCTION_USAGE (peep2_next_insn (1)))"
12788 [(parallel [(set (match_dup 2) 12642 [(parallel [(set (match_dup 2)
12789 (call (mem:QI (match_dup 1)) 12643 (call (mem:QI (match_dup 1))
12790 (match_dup 3))) 12644 (match_dup 3)))
12795 (match_operand:W 1 "memory_operand")) 12649 (match_operand:W 1 "memory_operand"))
12796 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 12650 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
12797 (set (match_operand 2) 12651 (set (match_operand 2)
12798 (call (mem:QI (match_dup 0)) 12652 (call (mem:QI (match_dup 0))
12799 (match_operand 3)))] 12653 (match_operand 3)))]
12800 "!TARGET_X32 && SIBLING_CALL_P (peep2_next_insn (2)) 12654 "!TARGET_X32
12655 && !TARGET_INDIRECT_BRANCH_REGISTER
12656 && SIBLING_CALL_P (peep2_next_insn (2))
12801 && !reg_mentioned_p (operands[0], 12657 && !reg_mentioned_p (operands[0],
12802 CALL_INSN_FUNCTION_USAGE (peep2_next_insn (2)))" 12658 CALL_INSN_FUNCTION_USAGE (peep2_next_insn (2)))"
12803 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 12659 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
12804 (parallel [(set (match_dup 2) 12660 (parallel [(set (match_dup 2)
12805 (call (mem:QI (match_dup 1)) 12661 (call (mem:QI (match_dup 1))
12820 DONE; 12676 DONE;
12821 }) 12677 })
12822 12678
12823 (define_insn "*call_value_pop" 12679 (define_insn "*call_value_pop"
12824 [(set (match_operand 0) 12680 [(set (match_operand 0)
12825 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lmBz")) 12681 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lBwBz"))
12826 (match_operand 2))) 12682 (match_operand 2)))
12827 (set (reg:SI SP_REG) 12683 (set (reg:SI SP_REG)
12828 (plus:SI (reg:SI SP_REG) 12684 (plus:SI (reg:SI SP_REG)
12829 (match_operand:SI 3 "immediate_operand" "i")))] 12685 (match_operand:SI 3 "immediate_operand" "i")))]
12830 "!TARGET_64BIT && !SIBLING_CALL_P (insn)" 12686 "!TARGET_64BIT && !SIBLING_CALL_P (insn)"
13030 }) 12886 })
13031 12887
13032 (define_insn "simple_return_internal" 12888 (define_insn "simple_return_internal"
13033 [(simple_return)] 12889 [(simple_return)]
13034 "reload_completed" 12890 "reload_completed"
13035 "%!ret" 12891 "* return ix86_output_function_return (false);"
13036 [(set_attr "length" "1") 12892 [(set_attr "length" "1")
13037 (set_attr "atom_unit" "jeu") 12893 (set_attr "atom_unit" "jeu")
13038 (set_attr "length_immediate" "0") 12894 (set_attr "length_immediate" "0")
13039 (set_attr "modrm" "0") 12895 (set_attr "modrm" "0")])
13040 (set_attr "maybe_prefix_bnd" "1")])
13041 12896
13042 (define_insn "interrupt_return" 12897 (define_insn "interrupt_return"
13043 [(simple_return) 12898 [(simple_return)
13044 (unspec [(const_int 0)] UNSPEC_INTERRUPT_RETURN)] 12899 (unspec [(const_int 0)] UNSPEC_INTERRUPT_RETURN)]
13045 "reload_completed" 12900 "reload_completed"
13052 12907
13053 (define_insn "simple_return_internal_long" 12908 (define_insn "simple_return_internal_long"
13054 [(simple_return) 12909 [(simple_return)
13055 (unspec [(const_int 0)] UNSPEC_REP)] 12910 (unspec [(const_int 0)] UNSPEC_REP)]
13056 "reload_completed" 12911 "reload_completed"
13057 { 12912 "* return ix86_output_function_return (true);"
13058 if (ix86_bnd_prefixed_insn_p (insn))
13059 return "%!ret";
13060
13061 return "rep%; ret";
13062 }
13063 [(set_attr "length" "2") 12913 [(set_attr "length" "2")
13064 (set_attr "atom_unit" "jeu") 12914 (set_attr "atom_unit" "jeu")
13065 (set_attr "length_immediate" "0") 12915 (set_attr "length_immediate" "0")
13066 (set_attr "prefix_rep" "1") 12916 (set_attr "prefix_rep" "1")
13067 (set_attr "modrm" "0")]) 12917 (set_attr "modrm" "0")])
13068 12918
13069 (define_insn "simple_return_pop_internal" 12919 (define_insn_and_split "simple_return_pop_internal"
13070 [(simple_return) 12920 [(simple_return)
13071 (use (match_operand:SI 0 "const_int_operand"))] 12921 (use (match_operand:SI 0 "const_int_operand"))]
13072 "reload_completed" 12922 "reload_completed"
13073 "%!ret\t%0" 12923 "%!ret\t%0"
12924 "&& cfun->machine->function_return_type != indirect_branch_keep"
12925 [(const_int 0)]
12926 "ix86_split_simple_return_pop_internal (operands[0]); DONE;"
13074 [(set_attr "length" "3") 12927 [(set_attr "length" "3")
13075 (set_attr "atom_unit" "jeu") 12928 (set_attr "atom_unit" "jeu")
13076 (set_attr "length_immediate" "2") 12929 (set_attr "length_immediate" "2")
13077 (set_attr "modrm" "0") 12930 (set_attr "modrm" "0")])
13078 (set_attr "maybe_prefix_bnd" "1")]) 12931
13079 12932 (define_expand "simple_return_indirect_internal"
13080 (define_insn "simple_return_indirect_internal" 12933 [(parallel
12934 [(simple_return)
12935 (use (match_operand 0 "register_operand"))])])
12936
12937 (define_insn "*simple_return_indirect_internal<mode>"
13081 [(simple_return) 12938 [(simple_return)
13082 (use (match_operand:SI 0 "register_operand" "r"))] 12939 (use (match_operand:W 0 "register_operand" "r"))]
13083 "reload_completed" 12940 "reload_completed"
13084 "%!jmp\t%A0" 12941 "* return ix86_output_indirect_function_return (operands[0]);"
13085 [(set_attr "type" "ibr") 12942 [(set (attr "type")
13086 (set_attr "length_immediate" "0") 12943 (if_then_else (match_test "(cfun->machine->indirect_branch_type
13087 (set_attr "maybe_prefix_bnd" "1")]) 12944 != indirect_branch_keep)")
12945 (const_string "multi")
12946 (const_string "ibr")))
12947 (set_attr "length_immediate" "0")])
13088 12948
13089 (define_insn "nop" 12949 (define_insn "nop"
13090 [(const_int 0)] 12950 [(const_int 0)]
13091 "" 12951 ""
13092 "nop" 12952 "nop"
13185 (unspec:DI [(const_int 0)] UNSPEC_SET_GOT))] 13045 (unspec:DI [(const_int 0)] UNSPEC_SET_GOT))]
13186 "TARGET_64BIT" 13046 "TARGET_64BIT"
13187 "lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}" 13047 "lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}"
13188 [(set_attr "type" "lea") 13048 [(set_attr "type" "lea")
13189 (set_attr "length_address" "4") 13049 (set_attr "length_address" "4")
13190 (set_attr "modrm_class" "unknown")
13191 (set_attr "mode" "DI")]) 13050 (set_attr "mode" "DI")])
13192 13051
13193 (define_insn "set_rip_rex64" 13052 (define_insn "set_rip_rex64"
13194 [(set (match_operand:DI 0 "register_operand" "=r") 13053 [(set (match_operand:DI 0 "register_operand" "=r")
13195 (unspec:DI [(label_ref (match_operand 1))] UNSPEC_SET_RIP))] 13054 (unspec:DI [(label_ref (match_operand 1))] UNSPEC_SET_RIP))]
13230 /* Tricky bit: we write the address of the handler to which we will 13089 /* Tricky bit: we write the address of the handler to which we will
13231 be returning into someone else's stack frame, one word below the 13090 be returning into someone else's stack frame, one word below the
13232 stack address we wish to restore. */ 13091 stack address we wish to restore. */
13233 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa); 13092 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13234 tmp = plus_constant (Pmode, tmp, -UNITS_PER_WORD); 13093 tmp = plus_constant (Pmode, tmp, -UNITS_PER_WORD);
13235 tmp = gen_rtx_MEM (Pmode, tmp); 13094 /* Return address is always in word_mode. */
13095 tmp = gen_rtx_MEM (word_mode, tmp);
13096 if (GET_MODE (ra) != word_mode)
13097 ra = convert_to_mode (word_mode, ra, 1);
13236 emit_move_insn (tmp, ra); 13098 emit_move_insn (tmp, ra);
13237 13099
13238 emit_jump_insn (gen_eh_return_internal ()); 13100 emit_jump_insn (gen_eh_return_internal ());
13239 emit_barrier (); 13101 emit_barrier ();
13240 DONE; 13102 DONE;
13722 "blsr\t{%1, %0|%0, %1}" 13584 "blsr\t{%1, %0|%0, %1}"
13723 [(set_attr "type" "bitmanip") 13585 [(set_attr "type" "bitmanip")
13724 (set_attr "btver2_decode" "double") 13586 (set_attr "btver2_decode" "double")
13725 (set_attr "mode" "<MODE>")]) 13587 (set_attr "mode" "<MODE>")])
13726 13588
13589 (define_insn "*bmi_blsr_<mode>_cmp"
13590 [(set (reg:CCZ FLAGS_REG)
13591 (compare:CCZ
13592 (and:SWI48
13593 (plus:SWI48
13594 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
13595 (const_int -1))
13596 (match_dup 1))
13597 (const_int 0)))
13598 (set (match_operand:SWI48 0 "register_operand" "=r")
13599 (and:SWI48
13600 (plus:SWI48
13601 (match_dup 1)
13602 (const_int -1))
13603 (match_dup 1)))]
13604 "TARGET_BMI"
13605 "blsr\t{%1, %0|%0, %1}"
13606 [(set_attr "type" "bitmanip")
13607 (set_attr "btver2_decode" "double")
13608 (set_attr "mode" "<MODE>")])
13609
13610 (define_insn "*bmi_blsr_<mode>_ccz"
13611 [(set (reg:CCZ FLAGS_REG)
13612 (compare:CCZ
13613 (and:SWI48
13614 (plus:SWI48
13615 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
13616 (const_int -1))
13617 (match_dup 1))
13618 (const_int 0)))
13619 (clobber (match_scratch:SWI48 0 "=r"))]
13620 "TARGET_BMI"
13621 "blsr\t{%1, %0|%0, %1}"
13622 [(set_attr "type" "bitmanip")
13623 (set_attr "btver2_decode" "double")
13624 (set_attr "mode" "<MODE>")])
13625
13727 ;; BMI2 instructions. 13626 ;; BMI2 instructions.
13728 (define_expand "bmi2_bzhi_<mode>3" 13627 (define_expand "bmi2_bzhi_<mode>3"
13729 [(parallel 13628 [(parallel
13730 [(set (match_operand:SWI48 0 "register_operand") 13629 [(set (match_operand:SWI48 0 "register_operand")
13731 (zero_extract:SWI48 13630 (zero_extract:SWI48
14065 (bswap:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,m,r")))] 13964 (bswap:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,m,r")))]
14066 "TARGET_MOVBE 13965 "TARGET_MOVBE
14067 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" 13966 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
14068 "@ 13967 "@
14069 bswap\t%0 13968 bswap\t%0
14070 movbe\t{%1, %0|%0, %1} 13969 movbe{<imodesuffix>}\t{%1, %0|%0, %1}
14071 movbe\t{%1, %0|%0, %1}" 13970 movbe{<imodesuffix>}\t{%1, %0|%0, %1}"
14072 [(set_attr "type" "bitmanip,imov,imov") 13971 [(set_attr "type" "bitmanip,imov,imov")
14073 (set_attr "modrm" "0,1,1") 13972 (set_attr "modrm" "0,1,1")
14074 (set_attr "prefix_0f" "*,1,1") 13973 (set_attr "prefix_0f" "*,1,1")
14075 (set_attr "prefix_extra" "*,1,1") 13974 (set_attr "prefix_extra" "*,1,1")
14076 (set_attr "mode" "<MODE>")]) 13975 (set_attr "mode" "<MODE>")])
14082 "bswap\t%0" 13981 "bswap\t%0"
14083 [(set_attr "type" "bitmanip") 13982 [(set_attr "type" "bitmanip")
14084 (set_attr "modrm" "0") 13983 (set_attr "modrm" "0")
14085 (set_attr "mode" "<MODE>")]) 13984 (set_attr "mode" "<MODE>")])
14086 13985
14087 (define_insn "*bswaphi_lowpart_1" 13986 (define_expand "bswaphi2"
13987 [(set (match_operand:HI 0 "register_operand")
13988 (bswap:HI (match_operand:HI 1 "nonimmediate_operand")))]
13989 "TARGET_MOVBE")
13990
13991 (define_insn "*bswaphi2_movbe"
13992 [(set (match_operand:HI 0 "nonimmediate_operand" "=Q,r,m")
13993 (bswap:HI (match_operand:HI 1 "nonimmediate_operand" "0,m,r")))]
13994 "TARGET_MOVBE
13995 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
13996 "@
13997 xchg{b}\t{%h0, %b0|%b0, %h0}
13998 movbe{w}\t{%1, %0|%0, %1}
13999 movbe{w}\t{%1, %0|%0, %1}"
14000 [(set_attr "type" "imov")
14001 (set_attr "modrm" "*,1,1")
14002 (set_attr "prefix_0f" "*,1,1")
14003 (set_attr "prefix_extra" "*,1,1")
14004 (set_attr "pent_pair" "np,*,*")
14005 (set_attr "athlon_decode" "vector,*,*")
14006 (set_attr "amdfam10_decode" "double,*,*")
14007 (set_attr "bdver1_decode" "double,*,*")
14008 (set_attr "mode" "QI,HI,HI")])
14009
14010 (define_peephole2
14011 [(set (match_operand:HI 0 "general_reg_operand")
14012 (bswap:HI (match_dup 0)))]
14013 "TARGET_MOVBE
14014 && !(TARGET_USE_XCHGB || optimize_function_for_size_p (cfun))
14015 && peep2_regno_dead_p (0, FLAGS_REG)"
14016 [(parallel [(set (match_dup 0) (rotate:HI (match_dup 0) (const_int 8)))
14017 (clobber (reg:CC FLAGS_REG))])])
14018
14019 (define_insn "bswaphi_lowpart"
14088 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+Q,r")) 14020 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+Q,r"))
14089 (bswap:HI (match_dup 0))) 14021 (bswap:HI (match_dup 0)))
14090 (clobber (reg:CC FLAGS_REG))] 14022 (clobber (reg:CC FLAGS_REG))]
14091 "TARGET_USE_XCHGB || optimize_function_for_size_p (cfun)" 14023 ""
14092 "@ 14024 "@
14093 xchg{b}\t{%h0, %b0|%b0, %h0} 14025 xchg{b}\t{%h0, %b0|%b0, %h0}
14094 rol{w}\t{$8, %0|%0, 8}" 14026 rol{w}\t{$8, %0|%0, 8}"
14095 [(set_attr "length" "2,4") 14027 [(set (attr "preferred_for_size")
14028 (cond [(eq_attr "alternative" "0")
14029 (symbol_ref "true")]
14030 (symbol_ref "false")))
14031 (set (attr "preferred_for_speed")
14032 (cond [(eq_attr "alternative" "0")
14033 (symbol_ref "TARGET_USE_XCHGB")]
14034 (symbol_ref "!TARGET_USE_XCHGB")))
14035 (set_attr "length" "2,4")
14096 (set_attr "mode" "QI,HI")]) 14036 (set_attr "mode" "QI,HI")])
14097
14098 (define_insn "bswaphi_lowpart"
14099 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
14100 (bswap:HI (match_dup 0)))
14101 (clobber (reg:CC FLAGS_REG))]
14102 ""
14103 "rol{w}\t{$8, %0|%0, 8}"
14104 [(set_attr "length" "4")
14105 (set_attr "mode" "HI")])
14106 14037
14107 (define_expand "paritydi2" 14038 (define_expand "paritydi2"
14108 [(set (match_operand:DI 0 "register_operand") 14039 [(set (match_operand:DI 0 "register_operand")
14109 (parity:DI (match_operand:DI 1 "register_operand")))] 14040 (parity:DI (match_operand:DI 1 "register_operand")))]
14110 "! TARGET_POPCNT" 14041 "! TARGET_POPCNT"
14271 (reg:P SP_REG)] 14202 (reg:P SP_REG)]
14272 UNSPEC_TLS_GD)] 14203 UNSPEC_TLS_GD)]
14273 "TARGET_64BIT" 14204 "TARGET_64BIT"
14274 { 14205 {
14275 if (!TARGET_X32) 14206 if (!TARGET_X32)
14276 fputs (ASM_BYTE "0x66\n", asm_out_file); 14207 /* The .loc directive has effect for 'the immediately following assembly
14208 instruction'. So for a sequence:
14209 .loc f l
14210 .byte x
14211 insn1
14212 the 'immediately following assembly instruction' is insn1.
14213 We want to emit an insn prefix here, but if we use .byte (as shown in
14214 'ELF Handling For Thread-Local Storage'), a preceding .loc will point
14215 inside the insn sequence, rather than to the start. After relaxation
14216 of the sequence by the linker, the .loc might point inside an insn.
14217 Use data16 prefix instead, which doesn't have this problem. */
14218 fputs ("\tdata16", asm_out_file);
14277 output_asm_insn 14219 output_asm_insn
14278 ("lea{q}\t{%E1@tlsgd(%%rip), %%rdi|rdi, %E1@tlsgd[rip]}", operands); 14220 ("lea{q}\t{%E1@tlsgd(%%rip), %%rdi|rdi, %E1@tlsgd[rip]}", operands);
14279 if (TARGET_SUN_TLS || flag_plt || !HAVE_AS_IX86_TLS_GET_ADDR_GOT) 14221 if (TARGET_SUN_TLS || flag_plt || !HAVE_AS_IX86_TLS_GET_ADDR_GOT)
14280 fputs (ASM_SHORT "0x6666\n", asm_out_file); 14222 fputs (ASM_SHORT "0x6666\n", asm_out_file);
14281 else 14223 else
14678 ;; SImode if the target mode DFmode, but only SImode if the target mode 14620 ;; SImode if the target mode DFmode, but only SImode if the target mode
14679 ;; is SFmode. 14621 ;; is SFmode.
14680 14622
14681 ;; Gcc is slightly more smart about handling normal two address instructions 14623 ;; Gcc is slightly more smart about handling normal two address instructions
14682 ;; so use special patterns for add and mull. 14624 ;; so use special patterns for add and mull.
14625
14626 (define_insn "*fop_xf_comm_i387"
14627 [(set (match_operand:XF 0 "register_operand" "=f")
14628 (match_operator:XF 3 "binary_fp_operator"
14629 [(match_operand:XF 1 "register_operand" "%0")
14630 (match_operand:XF 2 "register_operand" "f")]))]
14631 "TARGET_80387
14632 && COMMUTATIVE_ARITH_P (operands[3])"
14633 "* return output_387_binary_op (insn, operands);"
14634 [(set (attr "type")
14635 (if_then_else (match_operand:XF 3 "mult_operator")
14636 (const_string "fmul")
14637 (const_string "fop")))
14638 (set_attr "mode" "XF")])
14683 14639
14684 (define_insn "*fop_<mode>_comm" 14640 (define_insn "*fop_<mode>_comm"
14685 [(set (match_operand:MODEF 0 "register_operand" "=f,x,v") 14641 [(set (match_operand:MODEF 0 "register_operand" "=f,x,v")
14686 (match_operator:MODEF 3 "binary_fp_operator" 14642 (match_operator:MODEF 3 "binary_fp_operator"
14687 [(match_operand:MODEF 1 "nonimmediate_operand" "%0,0,v") 14643 [(match_operand:MODEF 1 "nonimmediate_operand" "%0,0,v")
14714 (eq_attr "alternative" "0") 14670 (eq_attr "alternative" "0")
14715 (symbol_ref "true") 14671 (symbol_ref "true")
14716 (symbol_ref "false"))))]) 14672 (symbol_ref "false"))))])
14717 14673
14718 (define_insn "*rcpsf2_sse" 14674 (define_insn "*rcpsf2_sse"
14719 [(set (match_operand:SF 0 "register_operand" "=x") 14675 [(set (match_operand:SF 0 "register_operand" "=x,x")
14720 (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")] 14676 (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
14721 UNSPEC_RCP))] 14677 UNSPEC_RCP))]
14722 "TARGET_SSE && TARGET_SSE_MATH" 14678 "TARGET_SSE && TARGET_SSE_MATH"
14723 "%vrcpss\t{%1, %d0|%d0, %1}" 14679 "@
14680 %vrcpss\t{%d1, %0|%0, %d1}
14681 %vrcpss\t{%1, %d0|%d0, %1}"
14724 [(set_attr "type" "sse") 14682 [(set_attr "type" "sse")
14725 (set_attr "atom_sse_attr" "rcp") 14683 (set_attr "atom_sse_attr" "rcp")
14726 (set_attr "btver2_sse_attr" "rcp") 14684 (set_attr "btver2_sse_attr" "rcp")
14727 (set_attr "prefix" "maybe_vex") 14685 (set_attr "prefix" "maybe_vex")
14728 (set_attr "mode" "SF")]) 14686 (set_attr "mode" "SF")])
14687
14688 (define_insn "*fop_xf_1_i387"
14689 [(set (match_operand:XF 0 "register_operand" "=f,f")
14690 (match_operator:XF 3 "binary_fp_operator"
14691 [(match_operand:XF 1 "register_operand" "0,f")
14692 (match_operand:XF 2 "register_operand" "f,0")]))]
14693 "TARGET_80387
14694 && !COMMUTATIVE_ARITH_P (operands[3])"
14695 "* return output_387_binary_op (insn, operands);"
14696 [(set (attr "type")
14697 (if_then_else (match_operand:XF 3 "div_operator")
14698 (const_string "fdiv")
14699 (const_string "fop")))
14700 (set_attr "mode" "XF")])
14729 14701
14730 (define_insn "*fop_<mode>_1" 14702 (define_insn "*fop_<mode>_1"
14731 [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,v") 14703 [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,v")
14732 (match_operator:MODEF 3 "binary_fp_operator" 14704 (match_operator:MODEF 3 "binary_fp_operator"
14733 [(match_operand:MODEF 1 14705 [(match_operand:MODEF 1
14761 (if_then_else 14733 (if_then_else
14762 (eq_attr "alternative" "0,1") 14734 (eq_attr "alternative" "0,1")
14763 (symbol_ref "true") 14735 (symbol_ref "true")
14764 (symbol_ref "false"))))]) 14736 (symbol_ref "false"))))])
14765 14737
14766 ;; ??? Add SSE splitters for these! 14738 (define_insn "*fop_<X87MODEF:mode>_2_i387"
14767 (define_insn "*fop_<MODEF:mode>_2_i387" 14739 [(set (match_operand:X87MODEF 0 "register_operand" "=f")
14768 [(set (match_operand:MODEF 0 "register_operand" "=f") 14740 (match_operator:X87MODEF 3 "binary_fp_operator"
14769 (match_operator:MODEF 3 "binary_fp_operator" 14741 [(float:X87MODEF
14770 [(float:MODEF
14771 (match_operand:SWI24 1 "nonimmediate_operand" "m")) 14742 (match_operand:SWI24 1 "nonimmediate_operand" "m"))
14772 (match_operand:MODEF 2 "register_operand" "0")]))] 14743 (match_operand:X87MODEF 2 "register_operand" "0")]))]
14773 "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI24:MODE>mode) 14744 "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI24:MODE>mode)
14774 && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH) 14745 && !(SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
14775 && (TARGET_USE_<SWI24:MODE>MODE_FIOP 14746 && (TARGET_USE_<SWI24:MODE>MODE_FIOP
14776 || optimize_function_for_size_p (cfun))" 14747 || optimize_function_for_size_p (cfun))"
14777 "* return output_387_binary_op (insn, operands);" 14748 "* return output_387_binary_op (insn, operands);"
14778 [(set (attr "type") 14749 [(set (attr "type")
14779 (cond [(match_operand:MODEF 3 "mult_operator") 14750 (cond [(match_operand:X87MODEF 3 "mult_operator")
14780 (const_string "fmul") 14751 (const_string "fmul")
14781 (match_operand:MODEF 3 "div_operator") 14752 (match_operand:X87MODEF 3 "div_operator")
14782 (const_string "fdiv") 14753 (const_string "fdiv")
14783 ] 14754 ]
14784 (const_string "fop"))) 14755 (const_string "fop")))
14785 (set_attr "fp_int_src" "true") 14756 (set_attr "fp_int_src" "true")
14786 (set_attr "mode" "<SWI24:MODE>")]) 14757 (set_attr "mode" "<SWI24:MODE>")])
14787 14758
14788 (define_insn "*fop_<MODEF:mode>_3_i387" 14759 (define_insn "*fop_<X87MODEF:mode>_3_i387"
14789 [(set (match_operand:MODEF 0 "register_operand" "=f") 14760 [(set (match_operand:X87MODEF 0 "register_operand" "=f")
14790 (match_operator:MODEF 3 "binary_fp_operator" 14761 (match_operator:X87MODEF 3 "binary_fp_operator"
14791 [(match_operand:MODEF 1 "register_operand" "0") 14762 [(match_operand:X87MODEF 1 "register_operand" "0")
14792 (float:MODEF 14763 (float:X87MODEF
14793 (match_operand:SWI24 2 "nonimmediate_operand" "m"))]))] 14764 (match_operand:SWI24 2 "nonimmediate_operand" "m"))]))]
14794 "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI24:MODE>mode) 14765 "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI24:MODE>mode)
14795 && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH) 14766 && !(SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
14796 && (TARGET_USE_<SWI24:MODE>MODE_FIOP 14767 && (TARGET_USE_<SWI24:MODE>MODE_FIOP
14797 || optimize_function_for_size_p (cfun))" 14768 || optimize_function_for_size_p (cfun))"
14798 "* return output_387_binary_op (insn, operands);" 14769 "* return output_387_binary_op (insn, operands);"
14799 [(set (attr "type") 14770 [(set (attr "type")
14800 (cond [(match_operand:MODEF 3 "mult_operator") 14771 (cond [(match_operand:X87MODEF 3 "mult_operator")
14801 (const_string "fmul") 14772 (const_string "fmul")
14802 (match_operand:MODEF 3 "div_operator") 14773 (match_operand:X87MODEF 3 "div_operator")
14803 (const_string "fdiv") 14774 (const_string "fdiv")
14804 ] 14775 ]
14805 (const_string "fop"))) 14776 (const_string "fop")))
14806 (set_attr "fp_int_src" "true") 14777 (set_attr "fp_int_src" "true")
14778 (set_attr "mode" "<MODE>")])
14779
14780 (define_insn "*fop_xf_4_i387"
14781 [(set (match_operand:XF 0 "register_operand" "=f,f")
14782 (match_operator:XF 3 "binary_fp_operator"
14783 [(float_extend:XF
14784 (match_operand:MODEF 1 "nonimmediate_operand" "fm,0"))
14785 (match_operand:XF 2 "register_operand" "0,f")]))]
14786 "TARGET_80387"
14787 "* return output_387_binary_op (insn, operands);"
14788 [(set (attr "type")
14789 (cond [(match_operand:XF 3 "mult_operator")
14790 (const_string "fmul")
14791 (match_operand:XF 3 "div_operator")
14792 (const_string "fdiv")
14793 ]
14794 (const_string "fop")))
14807 (set_attr "mode" "<MODE>")]) 14795 (set_attr "mode" "<MODE>")])
14808 14796
14809 (define_insn "*fop_df_4_i387" 14797 (define_insn "*fop_df_4_i387"
14810 [(set (match_operand:DF 0 "register_operand" "=f,f") 14798 [(set (match_operand:DF 0 "register_operand" "=f,f")
14811 (match_operator:DF 3 "binary_fp_operator" 14799 (match_operator:DF 3 "binary_fp_operator"
14814 (match_operand:DF 2 "register_operand" "0,f")]))] 14802 (match_operand:DF 2 "register_operand" "0,f")]))]
14815 "TARGET_80387 && X87_ENABLE_ARITH (DFmode) 14803 "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
14816 && !(SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)" 14804 && !(SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)"
14817 "* return output_387_binary_op (insn, operands);" 14805 "* return output_387_binary_op (insn, operands);"
14818 [(set (attr "type") 14806 [(set (attr "type")
14819 (cond [(match_operand:DF 3 "mult_operator") 14807 (cond [(match_operand:DF 3 "mult_operator")
14820 (const_string "fmul") 14808 (const_string "fmul")
14821 (match_operand:DF 3 "div_operator") 14809 (match_operand:DF 3 "div_operator")
14822 (const_string "fdiv") 14810 (const_string "fdiv")
14823 ] 14811 ]
14824 (const_string "fop"))) 14812 (const_string "fop")))
14825 (set_attr "mode" "SF")]) 14813 (set_attr "mode" "SF")])
14814
14815 (define_insn "*fop_xf_5_i387"
14816 [(set (match_operand:XF 0 "register_operand" "=f,f")
14817 (match_operator:XF 3 "binary_fp_operator"
14818 [(match_operand:XF 1 "register_operand" "0,f")
14819 (float_extend:XF
14820 (match_operand:MODEF 2 "nonimmediate_operand" "fm,0"))]))]
14821 "TARGET_80387"
14822 "* return output_387_binary_op (insn, operands);"
14823 [(set (attr "type")
14824 (cond [(match_operand:XF 3 "mult_operator")
14825 (const_string "fmul")
14826 (match_operand:XF 3 "div_operator")
14827 (const_string "fdiv")
14828 ]
14829 (const_string "fop")))
14830 (set_attr "mode" "<MODE>")])
14826 14831
14827 (define_insn "*fop_df_5_i387" 14832 (define_insn "*fop_df_5_i387"
14828 [(set (match_operand:DF 0 "register_operand" "=f,f") 14833 [(set (match_operand:DF 0 "register_operand" "=f,f")
14829 (match_operator:DF 3 "binary_fp_operator" 14834 (match_operator:DF 3 "binary_fp_operator"
14830 [(match_operand:DF 1 "register_operand" "0,f") 14835 [(match_operand:DF 1 "register_operand" "0,f")
14832 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] 14837 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14833 "TARGET_80387 && X87_ENABLE_ARITH (DFmode) 14838 "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
14834 && !(SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)" 14839 && !(SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)"
14835 "* return output_387_binary_op (insn, operands);" 14840 "* return output_387_binary_op (insn, operands);"
14836 [(set (attr "type") 14841 [(set (attr "type")
14837 (cond [(match_operand:DF 3 "mult_operator") 14842 (cond [(match_operand:DF 3 "mult_operator")
14838 (const_string "fmul") 14843 (const_string "fmul")
14839 (match_operand:DF 3 "div_operator") 14844 (match_operand:DF 3 "div_operator")
14840 (const_string "fdiv") 14845 (const_string "fdiv")
14841 ] 14846 ]
14842 (const_string "fop"))) 14847 (const_string "fop")))
14843 (set_attr "mode" "SF")]) 14848 (set_attr "mode" "SF")])
14849
14850 (define_insn "*fop_xf_6_i387"
14851 [(set (match_operand:XF 0 "register_operand" "=f,f")
14852 (match_operator:XF 3 "binary_fp_operator"
14853 [(float_extend:XF
14854 (match_operand:MODEF 1 "register_operand" "0,f"))
14855 (float_extend:XF
14856 (match_operand:MODEF 2 "nonimmediate_operand" "fm,0"))]))]
14857 "TARGET_80387"
14858 "* return output_387_binary_op (insn, operands);"
14859 [(set (attr "type")
14860 (cond [(match_operand:XF 3 "mult_operator")
14861 (const_string "fmul")
14862 (match_operand:XF 3 "div_operator")
14863 (const_string "fdiv")
14864 ]
14865 (const_string "fop")))
14866 (set_attr "mode" "<MODE>")])
14844 14867
14845 (define_insn "*fop_df_6_i387" 14868 (define_insn "*fop_df_6_i387"
14846 [(set (match_operand:DF 0 "register_operand" "=f,f") 14869 [(set (match_operand:DF 0 "register_operand" "=f,f")
14847 (match_operator:DF 3 "binary_fp_operator" 14870 (match_operator:DF 3 "binary_fp_operator"
14848 [(float_extend:DF 14871 [(float_extend:DF
14851 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] 14874 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14852 "TARGET_80387 && X87_ENABLE_ARITH (DFmode) 14875 "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
14853 && !(SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)" 14876 && !(SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)"
14854 "* return output_387_binary_op (insn, operands);" 14877 "* return output_387_binary_op (insn, operands);"
14855 [(set (attr "type") 14878 [(set (attr "type")
14856 (cond [(match_operand:DF 3 "mult_operator") 14879 (cond [(match_operand:DF 3 "mult_operator")
14857 (const_string "fmul") 14880 (const_string "fmul")
14858 (match_operand:DF 3 "div_operator") 14881 (match_operand:DF 3 "div_operator")
14859 (const_string "fdiv") 14882 (const_string "fdiv")
14860 ] 14883 ]
14861 (const_string "fop"))) 14884 (const_string "fop")))
14862 (set_attr "mode" "SF")]) 14885 (set_attr "mode" "SF")])
14863
14864 (define_insn "*fop_xf_comm_i387"
14865 [(set (match_operand:XF 0 "register_operand" "=f")
14866 (match_operator:XF 3 "binary_fp_operator"
14867 [(match_operand:XF 1 "register_operand" "%0")
14868 (match_operand:XF 2 "register_operand" "f")]))]
14869 "TARGET_80387
14870 && COMMUTATIVE_ARITH_P (operands[3])"
14871 "* return output_387_binary_op (insn, operands);"
14872 [(set (attr "type")
14873 (if_then_else (match_operand:XF 3 "mult_operator")
14874 (const_string "fmul")
14875 (const_string "fop")))
14876 (set_attr "mode" "XF")])
14877
14878 (define_insn "*fop_xf_1_i387"
14879 [(set (match_operand:XF 0 "register_operand" "=f,f")
14880 (match_operator:XF 3 "binary_fp_operator"
14881 [(match_operand:XF 1 "register_operand" "0,f")
14882 (match_operand:XF 2 "register_operand" "f,0")]))]
14883 "TARGET_80387
14884 && !COMMUTATIVE_ARITH_P (operands[3])"
14885 "* return output_387_binary_op (insn, operands);"
14886 [(set (attr "type")
14887 (if_then_else (match_operand:XF 3 "div_operator")
14888 (const_string "fdiv")
14889 (const_string "fop")))
14890 (set_attr "mode" "XF")])
14891
14892 (define_insn "*fop_xf_2_i387"
14893 [(set (match_operand:XF 0 "register_operand" "=f")
14894 (match_operator:XF 3 "binary_fp_operator"
14895 [(float:XF
14896 (match_operand:SWI24 1 "nonimmediate_operand" "m"))
14897 (match_operand:XF 2 "register_operand" "0")]))]
14898 "TARGET_80387
14899 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
14900 "* return output_387_binary_op (insn, operands);"
14901 [(set (attr "type")
14902 (cond [(match_operand:XF 3 "mult_operator")
14903 (const_string "fmul")
14904 (match_operand:XF 3 "div_operator")
14905 (const_string "fdiv")
14906 ]
14907 (const_string "fop")))
14908 (set_attr "fp_int_src" "true")
14909 (set_attr "mode" "<MODE>")])
14910
14911 (define_insn "*fop_xf_3_i387"
14912 [(set (match_operand:XF 0 "register_operand" "=f")
14913 (match_operator:XF 3 "binary_fp_operator"
14914 [(match_operand:XF 1 "register_operand" "0")
14915 (float:XF
14916 (match_operand:SWI24 2 "nonimmediate_operand" "m"))]))]
14917 "TARGET_80387
14918 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
14919 "* return output_387_binary_op (insn, operands);"
14920 [(set (attr "type")
14921 (cond [(match_operand:XF 3 "mult_operator")
14922 (const_string "fmul")
14923 (match_operand:XF 3 "div_operator")
14924 (const_string "fdiv")
14925 ]
14926 (const_string "fop")))
14927 (set_attr "fp_int_src" "true")
14928 (set_attr "mode" "<MODE>")])
14929
14930 (define_insn "*fop_xf_4_i387"
14931 [(set (match_operand:XF 0 "register_operand" "=f,f")
14932 (match_operator:XF 3 "binary_fp_operator"
14933 [(float_extend:XF
14934 (match_operand:MODEF 1 "nonimmediate_operand" "fm,0"))
14935 (match_operand:XF 2 "register_operand" "0,f")]))]
14936 "TARGET_80387"
14937 "* return output_387_binary_op (insn, operands);"
14938 [(set (attr "type")
14939 (cond [(match_operand:XF 3 "mult_operator")
14940 (const_string "fmul")
14941 (match_operand:XF 3 "div_operator")
14942 (const_string "fdiv")
14943 ]
14944 (const_string "fop")))
14945 (set_attr "mode" "<MODE>")])
14946
14947 (define_insn "*fop_xf_5_i387"
14948 [(set (match_operand:XF 0 "register_operand" "=f,f")
14949 (match_operator:XF 3 "binary_fp_operator"
14950 [(match_operand:XF 1 "register_operand" "0,f")
14951 (float_extend:XF
14952 (match_operand:MODEF 2 "nonimmediate_operand" "fm,0"))]))]
14953 "TARGET_80387"
14954 "* return output_387_binary_op (insn, operands);"
14955 [(set (attr "type")
14956 (cond [(match_operand:XF 3 "mult_operator")
14957 (const_string "fmul")
14958 (match_operand:XF 3 "div_operator")
14959 (const_string "fdiv")
14960 ]
14961 (const_string "fop")))
14962 (set_attr "mode" "<MODE>")])
14963
14964 (define_insn "*fop_xf_6_i387"
14965 [(set (match_operand:XF 0 "register_operand" "=f,f")
14966 (match_operator:XF 3 "binary_fp_operator"
14967 [(float_extend:XF
14968 (match_operand:MODEF 1 "register_operand" "0,f"))
14969 (float_extend:XF
14970 (match_operand:MODEF 2 "nonimmediate_operand" "fm,0"))]))]
14971 "TARGET_80387"
14972 "* return output_387_binary_op (insn, operands);"
14973 [(set (attr "type")
14974 (cond [(match_operand:XF 3 "mult_operator")
14975 (const_string "fmul")
14976 (match_operand:XF 3 "div_operator")
14977 (const_string "fdiv")
14978 ]
14979 (const_string "fop")))
14980 (set_attr "mode" "<MODE>")])
14981 14886
14982 ;; FPU special functions. 14887 ;; FPU special functions.
14983 14888
14984 ;; This pattern implements a no-op XFmode truncation for 14889 ;; This pattern implements a no-op XFmode truncation for
14985 ;; all fancy i386 XFmode math functions. 14890 ;; all fancy i386 XFmode math functions.
14986 14891
14987 (define_insn "truncxf<mode>2_i387_noop_unspec" 14892 (define_insn "truncxf<mode>2_i387_noop_unspec"
14988 [(set (match_operand:MODEF 0 "register_operand" "=f") 14893 [(set (match_operand:MODEF 0 "nonimmediate_operand" "=mf")
14989 (unspec:MODEF [(match_operand:XF 1 "register_operand" "f")] 14894 (unspec:MODEF [(match_operand:XF 1 "register_operand" "f")]
14990 UNSPEC_TRUNC_NOOP))] 14895 UNSPEC_TRUNC_NOOP))]
14991 "TARGET_USE_FANCY_MATH_387" 14896 "TARGET_USE_FANCY_MATH_387"
14992 "* return output_387_reg_move (insn, operands);" 14897 "* return output_387_reg_move (insn, operands);"
14993 [(set_attr "type" "fmov") 14898 [(set_attr "type" "fmov")
15002 (set_attr "mode" "XF") 14907 (set_attr "mode" "XF")
15003 (set_attr "athlon_decode" "direct") 14908 (set_attr "athlon_decode" "direct")
15004 (set_attr "amdfam10_decode" "direct") 14909 (set_attr "amdfam10_decode" "direct")
15005 (set_attr "bdver1_decode" "direct")]) 14910 (set_attr "bdver1_decode" "direct")])
15006 14911
15007 (define_insn "sqrt_extend<mode>xf2_i387"
15008 [(set (match_operand:XF 0 "register_operand" "=f")
15009 (sqrt:XF
15010 (float_extend:XF
15011 (match_operand:MODEF 1 "register_operand" "0"))))]
15012 "TARGET_USE_FANCY_MATH_387"
15013 "fsqrt"
15014 [(set_attr "type" "fpspc")
15015 (set_attr "mode" "XF")
15016 (set_attr "athlon_decode" "direct")
15017 (set_attr "amdfam10_decode" "direct")
15018 (set_attr "bdver1_decode" "direct")])
15019
15020 (define_insn "*rsqrtsf2_sse" 14912 (define_insn "*rsqrtsf2_sse"
15021 [(set (match_operand:SF 0 "register_operand" "=x") 14913 [(set (match_operand:SF 0 "register_operand" "=x,x")
15022 (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")] 14914 (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
15023 UNSPEC_RSQRT))] 14915 UNSPEC_RSQRT))]
15024 "TARGET_SSE && TARGET_SSE_MATH" 14916 "TARGET_SSE && TARGET_SSE_MATH"
15025 "%vrsqrtss\t{%1, %d0|%d0, %1}" 14917 "@
14918 %vrsqrtss\t{%d1, %0|%0, %d1}
14919 %vrsqrtss\t{%1, %d0|%d0, %1}"
15026 [(set_attr "type" "sse") 14920 [(set_attr "type" "sse")
15027 (set_attr "atom_sse_attr" "rcp") 14921 (set_attr "atom_sse_attr" "rcp")
15028 (set_attr "btver2_sse_attr" "rcp") 14922 (set_attr "btver2_sse_attr" "rcp")
15029 (set_attr "prefix" "maybe_vex") 14923 (set_attr "prefix" "maybe_vex")
15030 (set_attr "mode" "SF")]) 14924 (set_attr "mode" "SF")])
15038 ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 1); 14932 ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 1);
15039 DONE; 14933 DONE;
15040 }) 14934 })
15041 14935
15042 (define_insn "*sqrt<mode>2_sse" 14936 (define_insn "*sqrt<mode>2_sse"
15043 [(set (match_operand:MODEF 0 "register_operand" "=v") 14937 [(set (match_operand:MODEF 0 "register_operand" "=v,v")
15044 (sqrt:MODEF 14938 (sqrt:MODEF
15045 (match_operand:MODEF 1 "nonimmediate_operand" "vm")))] 14939 (match_operand:MODEF 1 "nonimmediate_operand" "v,m")))]
15046 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" 14940 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
15047 "%vsqrt<ssemodesuffix>\t{%1, %d0|%d0, %1}" 14941 "@
14942 %vsqrt<ssemodesuffix>\t{%d1, %0|%0, %d1}
14943 %vsqrt<ssemodesuffix>\t{%1, %d0|%d0, %1}"
15048 [(set_attr "type" "sse") 14944 [(set_attr "type" "sse")
15049 (set_attr "atom_sse_attr" "sqrt") 14945 (set_attr "atom_sse_attr" "sqrt")
15050 (set_attr "btver2_sse_attr" "sqrt") 14946 (set_attr "btver2_sse_attr" "sqrt")
15051 (set_attr "prefix" "maybe_vex") 14947 (set_attr "prefix" "maybe_vex")
15052 (set_attr "mode" "<MODE>") 14948 (set_attr "mode" "<MODE>")
15073 } 14969 }
15074 14970
15075 if (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)) 14971 if (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
15076 { 14972 {
15077 rtx op0 = gen_reg_rtx (XFmode); 14973 rtx op0 = gen_reg_rtx (XFmode);
15078 rtx op1 = force_reg (<MODE>mode, operands[1]); 14974 rtx op1 = gen_reg_rtx (XFmode);
15079 14975
15080 emit_insn (gen_sqrt_extend<mode>xf2_i387 (op0, op1)); 14976 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
14977 emit_insn (gen_sqrtxf2 (op0, op1));
15081 emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0)); 14978 emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
15082 DONE; 14979 DONE;
15083 } 14980 }
15084 }) 14981 })
14982
14983 (define_insn "x86_fnstsw_1"
14984 [(set (match_operand:HI 0 "register_operand" "=a")
14985 (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
14986 "TARGET_80387"
14987 "fnstsw\t%0"
14988 [(set_attr "length" "2")
14989 (set_attr "mode" "SI")
14990 (set_attr "unit" "i387")])
15085 14991
15086 (define_insn "fpremxf4_i387" 14992 (define_insn "fpremxf4_i387"
15087 [(set (match_operand:XF 0 "register_operand" "=f") 14993 [(set (match_operand:XF 0 "register_operand" "=f")
15088 (unspec:XF [(match_operand:XF 2 "register_operand" "0") 14994 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15089 (match_operand:XF 3 "register_operand" "1")] 14995 (match_operand:XF 3 "register_operand" "1")]
15090 UNSPEC_FPREM_F)) 14996 UNSPEC_FPREM_F))
15091 (set (match_operand:XF 1 "register_operand" "=u") 14997 (set (match_operand:XF 1 "register_operand" "=f")
15092 (unspec:XF [(match_dup 2) (match_dup 3)] 14998 (unspec:XF [(match_dup 2) (match_dup 3)]
15093 UNSPEC_FPREM_U)) 14999 UNSPEC_FPREM_U))
15094 (set (reg:CCFP FPSR_REG) 15000 (set (reg:CCFP FPSR_REG)
15095 (unspec:CCFP [(match_dup 2) (match_dup 3)] 15001 (unspec:CCFP [(match_dup 2) (match_dup 3)]
15096 UNSPEC_C2_FLAG))] 15002 UNSPEC_C2_FLAG))]
15161 (define_insn "fprem1xf4_i387" 15067 (define_insn "fprem1xf4_i387"
15162 [(set (match_operand:XF 0 "register_operand" "=f") 15068 [(set (match_operand:XF 0 "register_operand" "=f")
15163 (unspec:XF [(match_operand:XF 2 "register_operand" "0") 15069 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15164 (match_operand:XF 3 "register_operand" "1")] 15070 (match_operand:XF 3 "register_operand" "1")]
15165 UNSPEC_FPREM1_F)) 15071 UNSPEC_FPREM1_F))
15166 (set (match_operand:XF 1 "register_operand" "=u") 15072 (set (match_operand:XF 1 "register_operand" "=f")
15167 (unspec:XF [(match_dup 2) (match_dup 3)] 15073 (unspec:XF [(match_dup 2) (match_dup 3)]
15168 UNSPEC_FPREM1_U)) 15074 UNSPEC_FPREM1_U))
15169 (set (reg:CCFP FPSR_REG) 15075 (set (reg:CCFP FPSR_REG)
15170 (unspec:CCFP [(match_dup 2) (match_dup 3)] 15076 (unspec:CCFP [(match_dup 2) (match_dup 3)]
15171 UNSPEC_C2_FLAG))] 15077 UNSPEC_C2_FLAG))]
15240 15146
15241 (define_int_attr sincos 15147 (define_int_attr sincos
15242 [(UNSPEC_SIN "sin") 15148 [(UNSPEC_SIN "sin")
15243 (UNSPEC_COS "cos")]) 15149 (UNSPEC_COS "cos")])
15244 15150
15245 (define_insn "*<sincos>xf2_i387" 15151 (define_insn "<sincos>xf2"
15246 [(set (match_operand:XF 0 "register_operand" "=f") 15152 [(set (match_operand:XF 0 "register_operand" "=f")
15247 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 15153 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15248 SINCOS))] 15154 SINCOS))]
15249 "TARGET_USE_FANCY_MATH_387 15155 "TARGET_USE_FANCY_MATH_387
15250 && flag_unsafe_math_optimizations" 15156 && flag_unsafe_math_optimizations"
15251 "f<sincos>" 15157 "f<sincos>"
15252 [(set_attr "type" "fpspc") 15158 [(set_attr "type" "fpspc")
15253 (set_attr "znver1_decode" "vector") 15159 (set_attr "znver1_decode" "vector")
15254 (set_attr "mode" "XF")]) 15160 (set_attr "mode" "XF")])
15255 15161
15256 (define_insn "*<sincos>_extend<mode>xf2_i387" 15162 (define_expand "<sincos><mode>2"
15257 [(set (match_operand:XF 0 "register_operand" "=f") 15163 [(set (match_operand:MODEF 0 "register_operand")
15258 (unspec:XF [(float_extend:XF 15164 (unspec:MODEF [(match_operand:MODEF 1 "general_operand")]
15259 (match_operand:MODEF 1 "register_operand" "0"))] 15165 SINCOS))]
15260 SINCOS))]
15261 "TARGET_USE_FANCY_MATH_387 15166 "TARGET_USE_FANCY_MATH_387
15262 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15167 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15263 || TARGET_MIX_SSE_I387) 15168 || TARGET_MIX_SSE_I387)
15264 && flag_unsafe_math_optimizations" 15169 && flag_unsafe_math_optimizations"
15265 "f<sincos>" 15170 {
15266 [(set_attr "type" "fpspc") 15171 rtx op0 = gen_reg_rtx (XFmode);
15267 (set_attr "znver1_decode" "vector") 15172 rtx op1 = gen_reg_rtx (XFmode);
15268 (set_attr "mode" "XF")]) 15173
15269 15174 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15270 ;; When sincos pattern is defined, sin and cos builtin functions will be 15175 emit_insn (gen_<sincos>xf2 (op0, op1));
15271 ;; expanded to sincos pattern with one of its outputs left unused. 15176 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15272 ;; CSE pass will figure out if two sincos patterns can be combined, 15177 DONE;
15273 ;; otherwise sincos pattern will be split back to sin or cos pattern, 15178 })
15274 ;; depending on the unused output.
15275 15179
15276 (define_insn "sincosxf3" 15180 (define_insn "sincosxf3"
15277 [(set (match_operand:XF 0 "register_operand" "=f") 15181 [(set (match_operand:XF 0 "register_operand" "=f")
15278 (unspec:XF [(match_operand:XF 2 "register_operand" "0")] 15182 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15279 UNSPEC_SINCOS_COS)) 15183 UNSPEC_SINCOS_COS))
15280 (set (match_operand:XF 1 "register_operand" "=u") 15184 (set (match_operand:XF 1 "register_operand" "=f")
15281 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] 15185 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15282 "TARGET_USE_FANCY_MATH_387 15186 "TARGET_USE_FANCY_MATH_387
15283 && flag_unsafe_math_optimizations" 15187 && flag_unsafe_math_optimizations"
15284 "fsincos" 15188 "fsincos"
15285 [(set_attr "type" "fpspc") 15189 [(set_attr "type" "fpspc")
15286 (set_attr "znver1_decode" "vector") 15190 (set_attr "znver1_decode" "vector")
15287 (set_attr "mode" "XF")]) 15191 (set_attr "mode" "XF")])
15288 15192
15289 (define_split 15193 (define_expand "sincos<mode>3"
15290 [(set (match_operand:XF 0 "register_operand") 15194 [(use (match_operand:MODEF 0 "register_operand"))
15291 (unspec:XF [(match_operand:XF 2 "register_operand")] 15195 (use (match_operand:MODEF 1 "register_operand"))
15292 UNSPEC_SINCOS_COS)) 15196 (use (match_operand:MODEF 2 "general_operand"))]
15293 (set (match_operand:XF 1 "register_operand")
15294 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15295 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15296 && can_create_pseudo_p ()"
15297 [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))])
15298
15299 (define_split
15300 [(set (match_operand:XF 0 "register_operand")
15301 (unspec:XF [(match_operand:XF 2 "register_operand")]
15302 UNSPEC_SINCOS_COS))
15303 (set (match_operand:XF 1 "register_operand")
15304 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15305 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15306 && can_create_pseudo_p ()"
15307 [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))])
15308
15309 (define_insn "sincos_extend<mode>xf3_i387"
15310 [(set (match_operand:XF 0 "register_operand" "=f")
15311 (unspec:XF [(float_extend:XF
15312 (match_operand:MODEF 2 "register_operand" "0"))]
15313 UNSPEC_SINCOS_COS))
15314 (set (match_operand:XF 1 "register_operand" "=u")
15315 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
15316 "TARGET_USE_FANCY_MATH_387 15197 "TARGET_USE_FANCY_MATH_387
15317 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15198 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15318 || TARGET_MIX_SSE_I387) 15199 || TARGET_MIX_SSE_I387)
15319 && flag_unsafe_math_optimizations" 15200 && flag_unsafe_math_optimizations"
15320 "fsincos"
15321 [(set_attr "type" "fpspc")
15322 (set_attr "znver1_decode" "vector")
15323 (set_attr "mode" "XF")])
15324
15325 (define_split
15326 [(set (match_operand:XF 0 "register_operand")
15327 (unspec:XF [(float_extend:XF
15328 (match_operand:MODEF 2 "register_operand"))]
15329 UNSPEC_SINCOS_COS))
15330 (set (match_operand:XF 1 "register_operand")
15331 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
15332 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15333 && can_create_pseudo_p ()"
15334 [(set (match_dup 1)
15335 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))])
15336
15337 (define_split
15338 [(set (match_operand:XF 0 "register_operand")
15339 (unspec:XF [(float_extend:XF
15340 (match_operand:MODEF 2 "register_operand"))]
15341 UNSPEC_SINCOS_COS))
15342 (set (match_operand:XF 1 "register_operand")
15343 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
15344 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15345 && can_create_pseudo_p ()"
15346 [(set (match_dup 0)
15347 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))])
15348
15349 (define_expand "sincos<mode>3"
15350 [(use (match_operand:MODEF 0 "register_operand"))
15351 (use (match_operand:MODEF 1 "register_operand"))
15352 (use (match_operand:MODEF 2 "register_operand"))]
15353 "TARGET_USE_FANCY_MATH_387
15354 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15355 || TARGET_MIX_SSE_I387)
15356 && flag_unsafe_math_optimizations"
15357 { 15201 {
15358 rtx op0 = gen_reg_rtx (XFmode); 15202 rtx op0 = gen_reg_rtx (XFmode);
15359 rtx op1 = gen_reg_rtx (XFmode); 15203 rtx op1 = gen_reg_rtx (XFmode);
15360 15204 rtx op2 = gen_reg_rtx (XFmode);
15361 emit_insn (gen_sincos_extend<mode>xf3_i387 (op0, op1, operands[2])); 15205
15362 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0)); 15206 emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
15363 emit_insn (gen_truncxf<mode>2_i387_noop (operands[1], op1)); 15207 emit_insn (gen_sincosxf3 (op0, op1, op2));
15208 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15209 emit_insn (gen_truncxf<mode>2 (operands[1], op1));
15364 DONE; 15210 DONE;
15365 }) 15211 })
15366 15212
15367 (define_insn "fptanxf4_i387" 15213 (define_insn "fptanxf4_i387"
15368 [(set (match_operand:XF 0 "register_operand" "=f") 15214 [(set (match_operand:SF 0 "register_operand" "=f")
15369 (match_operand:XF 3 "const_double_operand" "F")) 15215 (match_operand:SF 3 "const1_operand"))
15370 (set (match_operand:XF 1 "register_operand" "=u") 15216 (set (match_operand:XF 1 "register_operand" "=f")
15371 (unspec:XF [(match_operand:XF 2 "register_operand" "0")] 15217 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15372 UNSPEC_TAN))] 15218 UNSPEC_TAN))]
15373 "TARGET_USE_FANCY_MATH_387 15219 "TARGET_USE_FANCY_MATH_387
15374 && flag_unsafe_math_optimizations 15220 && flag_unsafe_math_optimizations"
15375 && standard_80387_constant_p (operands[3]) == 2"
15376 "fptan"
15377 [(set_attr "type" "fpspc")
15378 (set_attr "znver1_decode" "vector")
15379 (set_attr "mode" "XF")])
15380
15381 (define_insn "fptan_extend<mode>xf4_i387"
15382 [(set (match_operand:MODEF 0 "register_operand" "=f")
15383 (match_operand:MODEF 3 "const_double_operand" "F"))
15384 (set (match_operand:XF 1 "register_operand" "=u")
15385 (unspec:XF [(float_extend:XF
15386 (match_operand:MODEF 2 "register_operand" "0"))]
15387 UNSPEC_TAN))]
15388 "TARGET_USE_FANCY_MATH_387
15389 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15390 || TARGET_MIX_SSE_I387)
15391 && flag_unsafe_math_optimizations
15392 && standard_80387_constant_p (operands[3]) == 2"
15393 "fptan" 15221 "fptan"
15394 [(set_attr "type" "fpspc") 15222 [(set_attr "type" "fpspc")
15395 (set_attr "znver1_decode" "vector") 15223 (set_attr "znver1_decode" "vector")
15396 (set_attr "mode" "XF")]) 15224 (set_attr "mode" "XF")])
15397 15225
15399 [(use (match_operand:XF 0 "register_operand")) 15227 [(use (match_operand:XF 0 "register_operand"))
15400 (use (match_operand:XF 1 "register_operand"))] 15228 (use (match_operand:XF 1 "register_operand"))]
15401 "TARGET_USE_FANCY_MATH_387 15229 "TARGET_USE_FANCY_MATH_387
15402 && flag_unsafe_math_optimizations" 15230 && flag_unsafe_math_optimizations"
15403 { 15231 {
15404 rtx one = gen_reg_rtx (XFmode); 15232 rtx one = gen_reg_rtx (SFmode);
15405 rtx op2 = CONST1_RTX (XFmode); /* fld1 */ 15233 emit_insn (gen_fptanxf4_i387 (one, operands[0], operands[1],
15406 15234 CONST1_RTX (SFmode)));
15407 emit_insn (gen_fptanxf4_i387 (one, operands[0], operands[1], op2));
15408 DONE; 15235 DONE;
15409 }) 15236 })
15410 15237
15411 (define_expand "tan<mode>2" 15238 (define_expand "tan<mode>2"
15412 [(use (match_operand:MODEF 0 "register_operand")) 15239 [(use (match_operand:MODEF 0 "register_operand"))
15413 (use (match_operand:MODEF 1 "register_operand"))] 15240 (use (match_operand:MODEF 1 "general_operand"))]
15414 "TARGET_USE_FANCY_MATH_387 15241 "TARGET_USE_FANCY_MATH_387
15415 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15242 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15416 || TARGET_MIX_SSE_I387) 15243 || TARGET_MIX_SSE_I387)
15417 && flag_unsafe_math_optimizations" 15244 && flag_unsafe_math_optimizations"
15418 { 15245 {
15419 rtx op0 = gen_reg_rtx (XFmode); 15246 rtx op0 = gen_reg_rtx (XFmode);
15420 15247 rtx op1 = gen_reg_rtx (XFmode);
15421 rtx one = gen_reg_rtx (<MODE>mode); 15248
15422 rtx op2 = CONST1_RTX (<MODE>mode); /* fld1 */ 15249 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15423 15250 emit_insn (gen_tanxf2 (op0, op1));
15424 emit_insn (gen_fptan_extend<mode>xf4_i387 (one, op0, 15251 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15425 operands[1], op2));
15426 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
15427 DONE; 15252 DONE;
15428 }) 15253 })
15429 15254
15430 (define_insn "*fpatanxf3_i387" 15255 (define_insn "atan2xf3"
15431 [(set (match_operand:XF 0 "register_operand" "=f") 15256 [(set (match_operand:XF 0 "register_operand" "=f")
15432 (unspec:XF [(match_operand:XF 1 "register_operand" "0") 15257 (unspec:XF [(match_operand:XF 1 "register_operand" "0")
15433 (match_operand:XF 2 "register_operand" "u")] 15258 (match_operand:XF 2 "register_operand" "f")]
15434 UNSPEC_FPATAN)) 15259 UNSPEC_FPATAN))
15435 (clobber (match_scratch:XF 3 "=2"))] 15260 (clobber (match_scratch:XF 3 "=2"))]
15436 "TARGET_USE_FANCY_MATH_387 15261 "TARGET_USE_FANCY_MATH_387
15437 && flag_unsafe_math_optimizations" 15262 && flag_unsafe_math_optimizations"
15438 "fpatan" 15263 "fpatan"
15439 [(set_attr "type" "fpspc") 15264 [(set_attr "type" "fpspc")
15440 (set_attr "znver1_decode" "vector") 15265 (set_attr "znver1_decode" "vector")
15441 (set_attr "mode" "XF")]) 15266 (set_attr "mode" "XF")])
15442 15267
15443 (define_insn "fpatan_extend<mode>xf3_i387" 15268 (define_expand "atan2<mode>3"
15444 [(set (match_operand:XF 0 "register_operand" "=f") 15269 [(use (match_operand:MODEF 0 "register_operand"))
15445 (unspec:XF [(float_extend:XF 15270 (use (match_operand:MODEF 1 "general_operand"))
15446 (match_operand:MODEF 1 "register_operand" "0")) 15271 (use (match_operand:MODEF 2 "general_operand"))]
15447 (float_extend:XF
15448 (match_operand:MODEF 2 "register_operand" "u"))]
15449 UNSPEC_FPATAN))
15450 (clobber (match_scratch:XF 3 "=2"))]
15451 "TARGET_USE_FANCY_MATH_387 15272 "TARGET_USE_FANCY_MATH_387
15452 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15273 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15453 || TARGET_MIX_SSE_I387) 15274 || TARGET_MIX_SSE_I387)
15454 && flag_unsafe_math_optimizations" 15275 && flag_unsafe_math_optimizations"
15455 "fpatan"
15456 [(set_attr "type" "fpspc")
15457 (set_attr "znver1_decode" "vector")
15458 (set_attr "mode" "XF")])
15459
15460 (define_expand "atan2xf3"
15461 [(parallel [(set (match_operand:XF 0 "register_operand")
15462 (unspec:XF [(match_operand:XF 2 "register_operand")
15463 (match_operand:XF 1 "register_operand")]
15464 UNSPEC_FPATAN))
15465 (clobber (match_scratch:XF 3))])]
15466 "TARGET_USE_FANCY_MATH_387
15467 && flag_unsafe_math_optimizations")
15468
15469 (define_expand "atan2<mode>3"
15470 [(use (match_operand:MODEF 0 "register_operand"))
15471 (use (match_operand:MODEF 1 "register_operand"))
15472 (use (match_operand:MODEF 2 "register_operand"))]
15473 "TARGET_USE_FANCY_MATH_387
15474 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15475 || TARGET_MIX_SSE_I387)
15476 && flag_unsafe_math_optimizations"
15477 { 15276 {
15478 rtx op0 = gen_reg_rtx (XFmode); 15277 rtx op0 = gen_reg_rtx (XFmode);
15479 15278 rtx op1 = gen_reg_rtx (XFmode);
15480 emit_insn (gen_fpatan_extend<mode>xf3_i387 (op0, operands[2], operands[1])); 15279 rtx op2 = gen_reg_rtx (XFmode);
15481 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0)); 15280
15281 emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
15282 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15283
15284 emit_insn (gen_atan2xf3 (op0, op2, op1));
15285 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15482 DONE; 15286 DONE;
15483 }) 15287 })
15484 15288
15485 (define_expand "atanxf2" 15289 (define_expand "atanxf2"
15486 [(parallel [(set (match_operand:XF 0 "register_operand") 15290 [(parallel [(set (match_operand:XF 0 "register_operand")
15488 (match_operand:XF 1 "register_operand")] 15292 (match_operand:XF 1 "register_operand")]
15489 UNSPEC_FPATAN)) 15293 UNSPEC_FPATAN))
15490 (clobber (match_scratch:XF 3))])] 15294 (clobber (match_scratch:XF 3))])]
15491 "TARGET_USE_FANCY_MATH_387 15295 "TARGET_USE_FANCY_MATH_387
15492 && flag_unsafe_math_optimizations" 15296 && flag_unsafe_math_optimizations"
15493 { 15297 "operands[2] = force_reg (XFmode, CONST1_RTX (XFmode));")
15494 operands[2] = gen_reg_rtx (XFmode);
15495 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15496 })
15497 15298
15498 (define_expand "atan<mode>2" 15299 (define_expand "atan<mode>2"
15499 [(use (match_operand:MODEF 0 "register_operand")) 15300 [(use (match_operand:MODEF 0 "register_operand"))
15500 (use (match_operand:MODEF 1 "register_operand"))] 15301 (use (match_operand:MODEF 1 "general_operand"))]
15501 "TARGET_USE_FANCY_MATH_387 15302 "TARGET_USE_FANCY_MATH_387
15502 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15303 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15503 || TARGET_MIX_SSE_I387) 15304 || TARGET_MIX_SSE_I387)
15504 && flag_unsafe_math_optimizations" 15305 && flag_unsafe_math_optimizations"
15505 { 15306 {
15506 rtx op0 = gen_reg_rtx (XFmode); 15307 rtx op0 = gen_reg_rtx (XFmode);
15507 15308 rtx op1 = gen_reg_rtx (XFmode);
15508 rtx op2 = gen_reg_rtx (<MODE>mode); 15309
15509 emit_move_insn (op2, CONST1_RTX (<MODE>mode)); /* fld1 */ 15310 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15510 15311 emit_insn (gen_atanxf2 (op0, op1));
15511 emit_insn (gen_fpatan_extend<mode>xf3_i387 (op0, op2, operands[1])); 15312 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15512 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
15513 DONE; 15313 DONE;
15514 }) 15314 })
15515 15315
15516 (define_expand "asinxf2" 15316 (define_expand "asinxf2"
15517 [(set (match_dup 2) 15317 [(set (match_dup 2)
15529 int i; 15329 int i;
15530 15330
15531 for (i = 2; i < 6; i++) 15331 for (i = 2; i < 6; i++)
15532 operands[i] = gen_reg_rtx (XFmode); 15332 operands[i] = gen_reg_rtx (XFmode);
15533 15333
15534 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */ 15334 emit_move_insn (operands[3], CONST1_RTX (XFmode));
15535 }) 15335 })
15536 15336
15537 (define_expand "asin<mode>2" 15337 (define_expand "asin<mode>2"
15538 [(use (match_operand:MODEF 0 "register_operand")) 15338 [(use (match_operand:MODEF 0 "register_operand"))
15539 (use (match_operand:MODEF 1 "general_operand"))] 15339 (use (match_operand:MODEF 1 "general_operand"))]
15545 rtx op0 = gen_reg_rtx (XFmode); 15345 rtx op0 = gen_reg_rtx (XFmode);
15546 rtx op1 = gen_reg_rtx (XFmode); 15346 rtx op1 = gen_reg_rtx (XFmode);
15547 15347
15548 emit_insn (gen_extend<mode>xf2 (op1, operands[1])); 15348 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15549 emit_insn (gen_asinxf2 (op0, op1)); 15349 emit_insn (gen_asinxf2 (op0, op1));
15550 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0)); 15350 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15551 DONE; 15351 DONE;
15552 }) 15352 })
15553 15353
15554 (define_expand "acosxf2" 15354 (define_expand "acosxf2"
15555 [(set (match_dup 2) 15355 [(set (match_dup 2)
15567 int i; 15367 int i;
15568 15368
15569 for (i = 2; i < 6; i++) 15369 for (i = 2; i < 6; i++)
15570 operands[i] = gen_reg_rtx (XFmode); 15370 operands[i] = gen_reg_rtx (XFmode);
15571 15371
15572 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */ 15372 emit_move_insn (operands[3], CONST1_RTX (XFmode));
15573 }) 15373 })
15574 15374
15575 (define_expand "acos<mode>2" 15375 (define_expand "acos<mode>2"
15576 [(use (match_operand:MODEF 0 "register_operand")) 15376 [(use (match_operand:MODEF 0 "register_operand"))
15577 (use (match_operand:MODEF 1 "general_operand"))] 15377 (use (match_operand:MODEF 1 "general_operand"))]
15583 rtx op0 = gen_reg_rtx (XFmode); 15383 rtx op0 = gen_reg_rtx (XFmode);
15584 rtx op1 = gen_reg_rtx (XFmode); 15384 rtx op1 = gen_reg_rtx (XFmode);
15585 15385
15586 emit_insn (gen_extend<mode>xf2 (op1, operands[1])); 15386 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15587 emit_insn (gen_acosxf2 (op0, op1)); 15387 emit_insn (gen_acosxf2 (op0, op1));
15588 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0)); 15388 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15589 DONE; 15389 DONE;
15590 }) 15390 })
15591 15391
15592 (define_insn "fyl2xxf3_i387" 15392 (define_insn "fyl2xxf3_i387"
15593 [(set (match_operand:XF 0 "register_operand" "=f") 15393 [(set (match_operand:XF 0 "register_operand" "=f")
15594 (unspec:XF [(match_operand:XF 1 "register_operand" "0") 15394 (unspec:XF [(match_operand:XF 1 "register_operand" "0")
15595 (match_operand:XF 2 "register_operand" "u")] 15395 (match_operand:XF 2 "register_operand" "f")]
15596 UNSPEC_FYL2X)) 15396 UNSPEC_FYL2X))
15597 (clobber (match_scratch:XF 3 "=2"))] 15397 (clobber (match_scratch:XF 3 "=2"))]
15598 "TARGET_USE_FANCY_MATH_387 15398 "TARGET_USE_FANCY_MATH_387
15599 && flag_unsafe_math_optimizations" 15399 && flag_unsafe_math_optimizations"
15600 "fyl2x" 15400 "fyl2x"
15601 [(set_attr "type" "fpspc") 15401 [(set_attr "type" "fpspc")
15602 (set_attr "znver1_decode" "vector") 15402 (set_attr "znver1_decode" "vector")
15603 (set_attr "mode" "XF")]) 15403 (set_attr "mode" "XF")])
15604 15404
15605 (define_insn "fyl2x_extend<mode>xf3_i387"
15606 [(set (match_operand:XF 0 "register_operand" "=f")
15607 (unspec:XF [(float_extend:XF
15608 (match_operand:MODEF 1 "register_operand" "0"))
15609 (match_operand:XF 2 "register_operand" "u")]
15610 UNSPEC_FYL2X))
15611 (clobber (match_scratch:XF 3 "=2"))]
15612 "TARGET_USE_FANCY_MATH_387
15613 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15614 || TARGET_MIX_SSE_I387)
15615 && flag_unsafe_math_optimizations"
15616 "fyl2x"
15617 [(set_attr "type" "fpspc")
15618 (set_attr "znver1_decode" "vector")
15619 (set_attr "mode" "XF")])
15620
15621 (define_expand "logxf2" 15405 (define_expand "logxf2"
15622 [(parallel [(set (match_operand:XF 0 "register_operand") 15406 [(parallel [(set (match_operand:XF 0 "register_operand")
15623 (unspec:XF [(match_operand:XF 1 "register_operand") 15407 (unspec:XF [(match_operand:XF 1 "register_operand")
15624 (match_dup 2)] UNSPEC_FYL2X)) 15408 (match_dup 2)] UNSPEC_FYL2X))
15625 (clobber (match_scratch:XF 3))])] 15409 (clobber (match_scratch:XF 3))])]
15626 "TARGET_USE_FANCY_MATH_387 15410 "TARGET_USE_FANCY_MATH_387
15627 && flag_unsafe_math_optimizations" 15411 && flag_unsafe_math_optimizations"
15628 { 15412 {
15629 operands[2] = gen_reg_rtx (XFmode); 15413 operands[2]
15630 emit_move_insn (operands[2], standard_80387_constant_rtx (4)); /* fldln2 */ 15414 = force_reg (XFmode, standard_80387_constant_rtx (4)); /* fldln2 */
15631 }) 15415 })
15632 15416
15633 (define_expand "log<mode>2" 15417 (define_expand "log<mode>2"
15634 [(use (match_operand:MODEF 0 "register_operand")) 15418 [(use (match_operand:MODEF 0 "register_operand"))
15635 (use (match_operand:MODEF 1 "register_operand"))] 15419 (use (match_operand:MODEF 1 "general_operand"))]
15636 "TARGET_USE_FANCY_MATH_387 15420 "TARGET_USE_FANCY_MATH_387
15637 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15421 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15638 || TARGET_MIX_SSE_I387) 15422 || TARGET_MIX_SSE_I387)
15639 && flag_unsafe_math_optimizations" 15423 && flag_unsafe_math_optimizations"
15640 { 15424 {
15641 rtx op0 = gen_reg_rtx (XFmode); 15425 rtx op0 = gen_reg_rtx (XFmode);
15642 15426 rtx op1 = gen_reg_rtx (XFmode);
15643 rtx op2 = gen_reg_rtx (XFmode); 15427
15644 emit_move_insn (op2, standard_80387_constant_rtx (4)); /* fldln2 */ 15428 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15645 15429 emit_insn (gen_logxf2 (op0, op1));
15646 emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2)); 15430 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15647 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
15648 DONE; 15431 DONE;
15649 }) 15432 })
15650 15433
15651 (define_expand "log10xf2" 15434 (define_expand "log10xf2"
15652 [(parallel [(set (match_operand:XF 0 "register_operand") 15435 [(parallel [(set (match_operand:XF 0 "register_operand")
15654 (match_dup 2)] UNSPEC_FYL2X)) 15437 (match_dup 2)] UNSPEC_FYL2X))
15655 (clobber (match_scratch:XF 3))])] 15438 (clobber (match_scratch:XF 3))])]
15656 "TARGET_USE_FANCY_MATH_387 15439 "TARGET_USE_FANCY_MATH_387
15657 && flag_unsafe_math_optimizations" 15440 && flag_unsafe_math_optimizations"
15658 { 15441 {
15659 operands[2] = gen_reg_rtx (XFmode); 15442 operands[2]
15660 emit_move_insn (operands[2], standard_80387_constant_rtx (3)); /* fldlg2 */ 15443 = force_reg (XFmode, standard_80387_constant_rtx (3)); /* fldlg2 */
15661 }) 15444 })
15662 15445
15663 (define_expand "log10<mode>2" 15446 (define_expand "log10<mode>2"
15664 [(use (match_operand:MODEF 0 "register_operand")) 15447 [(use (match_operand:MODEF 0 "register_operand"))
15665 (use (match_operand:MODEF 1 "register_operand"))] 15448 (use (match_operand:MODEF 1 "general_operand"))]
15666 "TARGET_USE_FANCY_MATH_387 15449 "TARGET_USE_FANCY_MATH_387
15667 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15450 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15668 || TARGET_MIX_SSE_I387) 15451 || TARGET_MIX_SSE_I387)
15669 && flag_unsafe_math_optimizations" 15452 && flag_unsafe_math_optimizations"
15670 { 15453 {
15671 rtx op0 = gen_reg_rtx (XFmode); 15454 rtx op0 = gen_reg_rtx (XFmode);
15672 15455 rtx op1 = gen_reg_rtx (XFmode);
15673 rtx op2 = gen_reg_rtx (XFmode); 15456
15674 emit_move_insn (op2, standard_80387_constant_rtx (3)); /* fldlg2 */ 15457 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15675 15458 emit_insn (gen_log10xf2 (op0, op1));
15676 emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2)); 15459 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15677 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
15678 DONE; 15460 DONE;
15679 }) 15461 })
15680 15462
15681 (define_expand "log2xf2" 15463 (define_expand "log2xf2"
15682 [(parallel [(set (match_operand:XF 0 "register_operand") 15464 [(parallel [(set (match_operand:XF 0 "register_operand")
15683 (unspec:XF [(match_operand:XF 1 "register_operand") 15465 (unspec:XF [(match_operand:XF 1 "register_operand")
15684 (match_dup 2)] UNSPEC_FYL2X)) 15466 (match_dup 2)] UNSPEC_FYL2X))
15685 (clobber (match_scratch:XF 3))])] 15467 (clobber (match_scratch:XF 3))])]
15686 "TARGET_USE_FANCY_MATH_387 15468 "TARGET_USE_FANCY_MATH_387
15687 && flag_unsafe_math_optimizations" 15469 && flag_unsafe_math_optimizations"
15688 { 15470 "operands[2] = force_reg (XFmode, CONST1_RTX (XFmode));")
15689 operands[2] = gen_reg_rtx (XFmode);
15690 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15691 })
15692 15471
15693 (define_expand "log2<mode>2" 15472 (define_expand "log2<mode>2"
15694 [(use (match_operand:MODEF 0 "register_operand")) 15473 [(use (match_operand:MODEF 0 "register_operand"))
15695 (use (match_operand:MODEF 1 "register_operand"))] 15474 (use (match_operand:MODEF 1 "general_operand"))]
15696 "TARGET_USE_FANCY_MATH_387 15475 "TARGET_USE_FANCY_MATH_387
15697 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15476 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15698 || TARGET_MIX_SSE_I387) 15477 || TARGET_MIX_SSE_I387)
15699 && flag_unsafe_math_optimizations" 15478 && flag_unsafe_math_optimizations"
15700 { 15479 {
15701 rtx op0 = gen_reg_rtx (XFmode); 15480 rtx op0 = gen_reg_rtx (XFmode);
15702 15481 rtx op1 = gen_reg_rtx (XFmode);
15703 rtx op2 = gen_reg_rtx (XFmode); 15482
15704 emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */ 15483 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15705 15484 emit_insn (gen_log2xf2 (op0, op1));
15706 emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2)); 15485 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15707 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
15708 DONE; 15486 DONE;
15709 }) 15487 })
15710 15488
15711 (define_insn "fyl2xp1xf3_i387" 15489 (define_insn "fyl2xp1xf3_i387"
15712 [(set (match_operand:XF 0 "register_operand" "=f") 15490 [(set (match_operand:XF 0 "register_operand" "=f")
15713 (unspec:XF [(match_operand:XF 1 "register_operand" "0") 15491 (unspec:XF [(match_operand:XF 1 "register_operand" "0")
15714 (match_operand:XF 2 "register_operand" "u")] 15492 (match_operand:XF 2 "register_operand" "f")]
15715 UNSPEC_FYL2XP1)) 15493 UNSPEC_FYL2XP1))
15716 (clobber (match_scratch:XF 3 "=2"))] 15494 (clobber (match_scratch:XF 3 "=2"))]
15717 "TARGET_USE_FANCY_MATH_387 15495 "TARGET_USE_FANCY_MATH_387
15718 && flag_unsafe_math_optimizations" 15496 && flag_unsafe_math_optimizations"
15719 "fyl2xp1" 15497 "fyl2xp1"
15720 [(set_attr "type" "fpspc") 15498 [(set_attr "type" "fpspc")
15721 (set_attr "znver1_decode" "vector") 15499 (set_attr "znver1_decode" "vector")
15722 (set_attr "mode" "XF")]) 15500 (set_attr "mode" "XF")])
15723 15501
15724 (define_insn "fyl2xp1_extend<mode>xf3_i387"
15725 [(set (match_operand:XF 0 "register_operand" "=f")
15726 (unspec:XF [(float_extend:XF
15727 (match_operand:MODEF 1 "register_operand" "0"))
15728 (match_operand:XF 2 "register_operand" "u")]
15729 UNSPEC_FYL2XP1))
15730 (clobber (match_scratch:XF 3 "=2"))]
15731 "TARGET_USE_FANCY_MATH_387
15732 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15733 || TARGET_MIX_SSE_I387)
15734 && flag_unsafe_math_optimizations"
15735 "fyl2xp1"
15736 [(set_attr "type" "fpspc")
15737 (set_attr "znver1_decode" "vector")
15738 (set_attr "mode" "XF")])
15739
15740 (define_expand "log1pxf2" 15502 (define_expand "log1pxf2"
15741 [(use (match_operand:XF 0 "register_operand")) 15503 [(use (match_operand:XF 0 "register_operand"))
15742 (use (match_operand:XF 1 "register_operand"))] 15504 (use (match_operand:XF 1 "register_operand"))]
15743 "TARGET_USE_FANCY_MATH_387 15505 "TARGET_USE_FANCY_MATH_387
15744 && flag_unsafe_math_optimizations" 15506 && flag_unsafe_math_optimizations"
15747 DONE; 15509 DONE;
15748 }) 15510 })
15749 15511
15750 (define_expand "log1p<mode>2" 15512 (define_expand "log1p<mode>2"
15751 [(use (match_operand:MODEF 0 "register_operand")) 15513 [(use (match_operand:MODEF 0 "register_operand"))
15752 (use (match_operand:MODEF 1 "register_operand"))] 15514 (use (match_operand:MODEF 1 "general_operand"))]
15753 "TARGET_USE_FANCY_MATH_387 15515 "TARGET_USE_FANCY_MATH_387
15754 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15516 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15755 || TARGET_MIX_SSE_I387) 15517 || TARGET_MIX_SSE_I387)
15756 && flag_unsafe_math_optimizations" 15518 && flag_unsafe_math_optimizations"
15757 { 15519 {
15758 rtx op0; 15520 rtx op0 = gen_reg_rtx (XFmode);
15759 15521 rtx op1 = gen_reg_rtx (XFmode);
15760 op0 = gen_reg_rtx (XFmode); 15522
15761 15523 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15762 operands[1] = gen_rtx_FLOAT_EXTEND (XFmode, operands[1]); 15524 emit_insn (gen_log1pxf2 (op0, op1));
15763 15525 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15764 ix86_emit_i387_log1p (op0, operands[1]);
15765 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
15766 DONE; 15526 DONE;
15767 }) 15527 })
15768 15528
15769 (define_insn "fxtractxf3_i387" 15529 (define_insn "fxtractxf3_i387"
15770 [(set (match_operand:XF 0 "register_operand" "=f") 15530 [(set (match_operand:XF 0 "register_operand" "=f")
15771 (unspec:XF [(match_operand:XF 2 "register_operand" "0")] 15531 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15772 UNSPEC_XTRACT_FRACT)) 15532 UNSPEC_XTRACT_FRACT))
15773 (set (match_operand:XF 1 "register_operand" "=u") 15533 (set (match_operand:XF 1 "register_operand" "=f")
15774 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))] 15534 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
15775 "TARGET_USE_FANCY_MATH_387 15535 "TARGET_USE_FANCY_MATH_387
15776 && flag_unsafe_math_optimizations"
15777 "fxtract"
15778 [(set_attr "type" "fpspc")
15779 (set_attr "znver1_decode" "vector")
15780 (set_attr "mode" "XF")])
15781
15782 (define_insn "fxtract_extend<mode>xf3_i387"
15783 [(set (match_operand:XF 0 "register_operand" "=f")
15784 (unspec:XF [(float_extend:XF
15785 (match_operand:MODEF 2 "register_operand" "0"))]
15786 UNSPEC_XTRACT_FRACT))
15787 (set (match_operand:XF 1 "register_operand" "=u")
15788 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_XTRACT_EXP))]
15789 "TARGET_USE_FANCY_MATH_387
15790 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15791 || TARGET_MIX_SSE_I387)
15792 && flag_unsafe_math_optimizations" 15536 && flag_unsafe_math_optimizations"
15793 "fxtract" 15537 "fxtract"
15794 [(set_attr "type" "fpspc") 15538 [(set_attr "type" "fpspc")
15795 (set_attr "znver1_decode" "vector") 15539 (set_attr "znver1_decode" "vector")
15796 (set_attr "mode" "XF")]) 15540 (set_attr "mode" "XF")])
15805 && flag_unsafe_math_optimizations" 15549 && flag_unsafe_math_optimizations"
15806 "operands[2] = gen_reg_rtx (XFmode);") 15550 "operands[2] = gen_reg_rtx (XFmode);")
15807 15551
15808 (define_expand "logb<mode>2" 15552 (define_expand "logb<mode>2"
15809 [(use (match_operand:MODEF 0 "register_operand")) 15553 [(use (match_operand:MODEF 0 "register_operand"))
15810 (use (match_operand:MODEF 1 "register_operand"))] 15554 (use (match_operand:MODEF 1 "general_operand"))]
15811 "TARGET_USE_FANCY_MATH_387 15555 "TARGET_USE_FANCY_MATH_387
15812 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15556 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15813 || TARGET_MIX_SSE_I387) 15557 || TARGET_MIX_SSE_I387)
15814 && flag_unsafe_math_optimizations" 15558 && flag_unsafe_math_optimizations"
15815 { 15559 {
15816 rtx op0 = gen_reg_rtx (XFmode); 15560 rtx op0 = gen_reg_rtx (XFmode);
15817 rtx op1 = gen_reg_rtx (XFmode); 15561 rtx op1 = gen_reg_rtx (XFmode);
15818 15562
15819 emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1])); 15563 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15820 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op1)); 15564 emit_insn (gen_logbxf2 (op0, op1));
15565 emit_insn (gen_truncxf<mode>2 (operands[0], op1));
15821 DONE; 15566 DONE;
15822 }) 15567 })
15823 15568
15824 (define_expand "ilogbxf2" 15569 (define_expand "ilogbxf2"
15825 [(use (match_operand:SI 0 "register_operand")) 15570 [(use (match_operand:SI 0 "register_operand"))
15840 DONE; 15585 DONE;
15841 }) 15586 })
15842 15587
15843 (define_expand "ilogb<mode>2" 15588 (define_expand "ilogb<mode>2"
15844 [(use (match_operand:SI 0 "register_operand")) 15589 [(use (match_operand:SI 0 "register_operand"))
15845 (use (match_operand:MODEF 1 "register_operand"))] 15590 (use (match_operand:MODEF 1 "general_operand"))]
15846 "TARGET_USE_FANCY_MATH_387 15591 "TARGET_USE_FANCY_MATH_387
15847 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15592 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15848 || TARGET_MIX_SSE_I387) 15593 || TARGET_MIX_SSE_I387)
15849 && flag_unsafe_math_optimizations" 15594 && flag_unsafe_math_optimizations"
15850 { 15595 {
15851 rtx op0, op1; 15596 rtx op0, op1, op2;
15852 15597
15853 if (optimize_insn_for_size_p ()) 15598 if (optimize_insn_for_size_p ())
15854 FAIL; 15599 FAIL;
15855 15600
15856 op0 = gen_reg_rtx (XFmode); 15601 op0 = gen_reg_rtx (XFmode);
15857 op1 = gen_reg_rtx (XFmode); 15602 op1 = gen_reg_rtx (XFmode);
15858 15603 op2 = gen_reg_rtx (XFmode);
15859 emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1])); 15604
15605 emit_insn (gen_extend<mode>xf2 (op2, operands[1]));
15606 emit_insn (gen_fxtractxf3_i387 (op0, op1, op2));
15860 emit_insn (gen_fix_truncxfsi2 (operands[0], op1)); 15607 emit_insn (gen_fix_truncxfsi2 (operands[0], op1));
15861 DONE; 15608 DONE;
15862 }) 15609 })
15863 15610
15864 (define_insn "*f2xm1xf2_i387" 15611 (define_insn "*f2xm1xf2_i387"
15875 (define_insn "fscalexf4_i387" 15622 (define_insn "fscalexf4_i387"
15876 [(set (match_operand:XF 0 "register_operand" "=f") 15623 [(set (match_operand:XF 0 "register_operand" "=f")
15877 (unspec:XF [(match_operand:XF 2 "register_operand" "0") 15624 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15878 (match_operand:XF 3 "register_operand" "1")] 15625 (match_operand:XF 3 "register_operand" "1")]
15879 UNSPEC_FSCALE_FRACT)) 15626 UNSPEC_FSCALE_FRACT))
15880 (set (match_operand:XF 1 "register_operand" "=u") 15627 (set (match_operand:XF 1 "register_operand" "=f")
15881 (unspec:XF [(match_dup 2) (match_dup 3)] 15628 (unspec:XF [(match_dup 2) (match_dup 3)]
15882 UNSPEC_FSCALE_EXP))] 15629 UNSPEC_FSCALE_EXP))]
15883 "TARGET_USE_FANCY_MATH_387 15630 "TARGET_USE_FANCY_MATH_387
15884 && flag_unsafe_math_optimizations" 15631 && flag_unsafe_math_optimizations"
15885 "fscale" 15632 "fscale"
15906 int i; 15653 int i;
15907 15654
15908 for (i = 3; i < 10; i++) 15655 for (i = 3; i < 10; i++)
15909 operands[i] = gen_reg_rtx (XFmode); 15656 operands[i] = gen_reg_rtx (XFmode);
15910 15657
15911 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */ 15658 emit_move_insn (operands[7], CONST1_RTX (XFmode));
15912 }) 15659 })
15913 15660
15914 (define_expand "expxf2" 15661 (define_expand "expxf2"
15915 [(use (match_operand:XF 0 "register_operand")) 15662 [(use (match_operand:XF 0 "register_operand"))
15916 (use (match_operand:XF 1 "register_operand"))] 15663 (use (match_operand:XF 1 "register_operand"))]
15917 "TARGET_USE_FANCY_MATH_387 15664 "TARGET_USE_FANCY_MATH_387
15918 && flag_unsafe_math_optimizations" 15665 && flag_unsafe_math_optimizations"
15919 { 15666 {
15920 rtx op2; 15667 rtx op2 = force_reg (XFmode, standard_80387_constant_rtx (5)); /* fldl2e */
15921
15922 op2 = gen_reg_rtx (XFmode);
15923 emit_move_insn (op2, standard_80387_constant_rtx (5)); /* fldl2e */
15924 15668
15925 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2)); 15669 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
15926 DONE; 15670 DONE;
15927 }) 15671 })
15928 15672
15932 "TARGET_USE_FANCY_MATH_387 15676 "TARGET_USE_FANCY_MATH_387
15933 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15677 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15934 || TARGET_MIX_SSE_I387) 15678 || TARGET_MIX_SSE_I387)
15935 && flag_unsafe_math_optimizations" 15679 && flag_unsafe_math_optimizations"
15936 { 15680 {
15937 rtx op0, op1; 15681 rtx op0 = gen_reg_rtx (XFmode);
15938 15682 rtx op1 = gen_reg_rtx (XFmode);
15939 op0 = gen_reg_rtx (XFmode);
15940 op1 = gen_reg_rtx (XFmode);
15941 15683
15942 emit_insn (gen_extend<mode>xf2 (op1, operands[1])); 15684 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15943 emit_insn (gen_expxf2 (op0, op1)); 15685 emit_insn (gen_expxf2 (op0, op1));
15944 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0)); 15686 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15945 DONE; 15687 DONE;
15946 }) 15688 })
15947 15689
15948 (define_expand "exp10xf2" 15690 (define_expand "exp10xf2"
15949 [(use (match_operand:XF 0 "register_operand")) 15691 [(use (match_operand:XF 0 "register_operand"))
15950 (use (match_operand:XF 1 "register_operand"))] 15692 (use (match_operand:XF 1 "register_operand"))]
15951 "TARGET_USE_FANCY_MATH_387 15693 "TARGET_USE_FANCY_MATH_387
15952 && flag_unsafe_math_optimizations" 15694 && flag_unsafe_math_optimizations"
15953 { 15695 {
15954 rtx op2; 15696 rtx op2 = force_reg (XFmode, standard_80387_constant_rtx (6)); /* fldl2t */
15955
15956 op2 = gen_reg_rtx (XFmode);
15957 emit_move_insn (op2, standard_80387_constant_rtx (6)); /* fldl2t */
15958 15697
15959 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2)); 15698 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
15960 DONE; 15699 DONE;
15961 }) 15700 })
15962 15701
15966 "TARGET_USE_FANCY_MATH_387 15705 "TARGET_USE_FANCY_MATH_387
15967 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15706 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15968 || TARGET_MIX_SSE_I387) 15707 || TARGET_MIX_SSE_I387)
15969 && flag_unsafe_math_optimizations" 15708 && flag_unsafe_math_optimizations"
15970 { 15709 {
15971 rtx op0, op1; 15710 rtx op0 = gen_reg_rtx (XFmode);
15972 15711 rtx op1 = gen_reg_rtx (XFmode);
15973 op0 = gen_reg_rtx (XFmode);
15974 op1 = gen_reg_rtx (XFmode);
15975 15712
15976 emit_insn (gen_extend<mode>xf2 (op1, operands[1])); 15713 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15977 emit_insn (gen_exp10xf2 (op0, op1)); 15714 emit_insn (gen_exp10xf2 (op0, op1));
15978 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0)); 15715 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
15979 DONE; 15716 DONE;
15980 }) 15717 })
15981 15718
15982 (define_expand "exp2xf2" 15719 (define_expand "exp2xf2"
15983 [(use (match_operand:XF 0 "register_operand")) 15720 [(use (match_operand:XF 0 "register_operand"))
15984 (use (match_operand:XF 1 "register_operand"))] 15721 (use (match_operand:XF 1 "register_operand"))]
15985 "TARGET_USE_FANCY_MATH_387 15722 "TARGET_USE_FANCY_MATH_387
15986 && flag_unsafe_math_optimizations" 15723 && flag_unsafe_math_optimizations"
15987 { 15724 {
15988 rtx op2; 15725 rtx op2 = force_reg (XFmode, CONST1_RTX (XFmode));
15989
15990 op2 = gen_reg_rtx (XFmode);
15991 emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */
15992 15726
15993 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2)); 15727 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
15994 DONE; 15728 DONE;
15995 }) 15729 })
15996 15730
16000 "TARGET_USE_FANCY_MATH_387 15734 "TARGET_USE_FANCY_MATH_387
16001 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15735 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16002 || TARGET_MIX_SSE_I387) 15736 || TARGET_MIX_SSE_I387)
16003 && flag_unsafe_math_optimizations" 15737 && flag_unsafe_math_optimizations"
16004 { 15738 {
16005 rtx op0, op1; 15739 rtx op0 = gen_reg_rtx (XFmode);
16006 15740 rtx op1 = gen_reg_rtx (XFmode);
16007 op0 = gen_reg_rtx (XFmode);
16008 op1 = gen_reg_rtx (XFmode);
16009 15741
16010 emit_insn (gen_extend<mode>xf2 (op1, operands[1])); 15742 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
16011 emit_insn (gen_exp2xf2 (op0, op1)); 15743 emit_insn (gen_exp2xf2 (op0, op1));
16012 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0)); 15744 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
16013 DONE; 15745 DONE;
16014 }) 15746 })
16015 15747
16016 (define_expand "expm1xf2" 15748 (define_expand "expm1xf2"
16017 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand") 15749 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand")
16018 (match_dup 2))) 15750 (match_dup 2)))
16019 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT)) 15751 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16020 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4))) 15752 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16021 (set (match_dup 9) (float_extend:XF (match_dup 13)))
16022 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1)) 15753 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16023 (parallel [(set (match_dup 7) 15754 (parallel [(set (match_dup 7)
16024 (unspec:XF [(match_dup 6) (match_dup 4)] 15755 (unspec:XF [(match_dup 6) (match_dup 4)]
16025 UNSPEC_FSCALE_FRACT)) 15756 UNSPEC_FSCALE_FRACT))
16026 (set (match_dup 8) 15757 (set (match_dup 8)
16030 (unspec:XF [(match_dup 9) (match_dup 8)] 15761 (unspec:XF [(match_dup 9) (match_dup 8)]
16031 UNSPEC_FSCALE_FRACT)) 15762 UNSPEC_FSCALE_FRACT))
16032 (set (match_dup 11) 15763 (set (match_dup 11)
16033 (unspec:XF [(match_dup 9) (match_dup 8)] 15764 (unspec:XF [(match_dup 9) (match_dup 8)]
16034 UNSPEC_FSCALE_EXP))]) 15765 UNSPEC_FSCALE_EXP))])
16035 (set (match_dup 12) (minus:XF (match_dup 10) 15766 (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
16036 (float_extend:XF (match_dup 13))))
16037 (set (match_operand:XF 0 "register_operand") 15767 (set (match_operand:XF 0 "register_operand")
16038 (plus:XF (match_dup 12) (match_dup 7)))] 15768 (plus:XF (match_dup 12) (match_dup 7)))]
16039 "TARGET_USE_FANCY_MATH_387 15769 "TARGET_USE_FANCY_MATH_387
16040 && flag_unsafe_math_optimizations" 15770 && flag_unsafe_math_optimizations"
16041 { 15771 {
16042 int i; 15772 int i;
16043 15773
16044 for (i = 2; i < 13; i++) 15774 for (i = 2; i < 13; i++)
16045 operands[i] = gen_reg_rtx (XFmode); 15775 operands[i] = gen_reg_rtx (XFmode);
16046 15776
16047 operands[13]
16048 = validize_mem (force_const_mem (SFmode, CONST1_RTX (SFmode))); /* fld1 */
16049
16050 emit_move_insn (operands[2], standard_80387_constant_rtx (5)); /* fldl2e */ 15777 emit_move_insn (operands[2], standard_80387_constant_rtx (5)); /* fldl2e */
15778 emit_move_insn (operands[9], CONST1_RTX (XFmode));
16051 }) 15779 })
16052 15780
16053 (define_expand "expm1<mode>2" 15781 (define_expand "expm1<mode>2"
16054 [(use (match_operand:MODEF 0 "register_operand")) 15782 [(use (match_operand:MODEF 0 "register_operand"))
16055 (use (match_operand:MODEF 1 "general_operand"))] 15783 (use (match_operand:MODEF 1 "general_operand"))]
16056 "TARGET_USE_FANCY_MATH_387 15784 "TARGET_USE_FANCY_MATH_387
16057 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15785 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16058 || TARGET_MIX_SSE_I387) 15786 || TARGET_MIX_SSE_I387)
16059 && flag_unsafe_math_optimizations" 15787 && flag_unsafe_math_optimizations"
16060 { 15788 {
16061 rtx op0, op1; 15789 rtx op0 = gen_reg_rtx (XFmode);
16062 15790 rtx op1 = gen_reg_rtx (XFmode);
16063 op0 = gen_reg_rtx (XFmode);
16064 op1 = gen_reg_rtx (XFmode);
16065 15791
16066 emit_insn (gen_extend<mode>xf2 (op1, operands[1])); 15792 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
16067 emit_insn (gen_expm1xf2 (op0, op1)); 15793 emit_insn (gen_expm1xf2 (op0, op1));
16068 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0)); 15794 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
16069 DONE; 15795 DONE;
16070 }) 15796 })
16071 15797
16072 (define_expand "ldexpxf3" 15798 (define_expand "ldexpxf3"
16073 [(match_operand:XF 0 "register_operand") 15799 [(match_operand:XF 0 "register_operand")
16074 (match_operand:XF 1 "register_operand") 15800 (match_operand:XF 1 "register_operand")
16075 (match_operand:SI 2 "register_operand")] 15801 (match_operand:SI 2 "register_operand")]
16076 "TARGET_USE_FANCY_MATH_387 15802 "TARGET_USE_FANCY_MATH_387
16077 && flag_unsafe_math_optimizations" 15803 && flag_unsafe_math_optimizations"
16078 { 15804 {
16079 rtx tmp1, tmp2; 15805 rtx tmp1 = gen_reg_rtx (XFmode);
16080 15806 rtx tmp2 = gen_reg_rtx (XFmode);
16081 tmp1 = gen_reg_rtx (XFmode);
16082 tmp2 = gen_reg_rtx (XFmode);
16083 15807
16084 emit_insn (gen_floatsixf2 (tmp1, operands[2])); 15808 emit_insn (gen_floatsixf2 (tmp1, operands[2]));
16085 emit_insn (gen_fscalexf4_i387 (operands[0], tmp2, 15809 emit_insn (gen_fscalexf4_i387 (operands[0], tmp2,
16086 operands[1], tmp1)); 15810 operands[1], tmp1));
16087 DONE; 15811 DONE;
16094 "TARGET_USE_FANCY_MATH_387 15818 "TARGET_USE_FANCY_MATH_387
16095 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15819 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16096 || TARGET_MIX_SSE_I387) 15820 || TARGET_MIX_SSE_I387)
16097 && flag_unsafe_math_optimizations" 15821 && flag_unsafe_math_optimizations"
16098 { 15822 {
16099 rtx op0, op1; 15823 rtx op0 = gen_reg_rtx (XFmode);
16100 15824 rtx op1 = gen_reg_rtx (XFmode);
16101 op0 = gen_reg_rtx (XFmode);
16102 op1 = gen_reg_rtx (XFmode);
16103 15825
16104 emit_insn (gen_extend<mode>xf2 (op1, operands[1])); 15826 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
16105 emit_insn (gen_ldexpxf3 (op0, op1, operands[2])); 15827 emit_insn (gen_ldexpxf3 (op0, op1, operands[2]));
16106 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0)); 15828 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
16107 DONE; 15829 DONE;
16108 }) 15830 })
16109 15831
16110 (define_expand "scalbxf3" 15832 (define_expand "scalbxf3"
16111 [(parallel [(set (match_operand:XF 0 " register_operand") 15833 [(parallel [(set (match_operand:XF 0 " register_operand")
16115 (set (match_dup 3) 15837 (set (match_dup 3)
16116 (unspec:XF [(match_dup 1) (match_dup 2)] 15838 (unspec:XF [(match_dup 1) (match_dup 2)]
16117 UNSPEC_FSCALE_EXP))])] 15839 UNSPEC_FSCALE_EXP))])]
16118 "TARGET_USE_FANCY_MATH_387 15840 "TARGET_USE_FANCY_MATH_387
16119 && flag_unsafe_math_optimizations" 15841 && flag_unsafe_math_optimizations"
16120 { 15842 "operands[3] = gen_reg_rtx (XFmode);")
16121 operands[3] = gen_reg_rtx (XFmode);
16122 })
16123 15843
16124 (define_expand "scalb<mode>3" 15844 (define_expand "scalb<mode>3"
16125 [(use (match_operand:MODEF 0 "register_operand")) 15845 [(use (match_operand:MODEF 0 "register_operand"))
16126 (use (match_operand:MODEF 1 "general_operand")) 15846 (use (match_operand:MODEF 1 "general_operand"))
16127 (use (match_operand:MODEF 2 "general_operand"))] 15847 (use (match_operand:MODEF 2 "general_operand"))]
16128 "TARGET_USE_FANCY_MATH_387 15848 "TARGET_USE_FANCY_MATH_387
16129 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15849 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16130 || TARGET_MIX_SSE_I387) 15850 || TARGET_MIX_SSE_I387)
16131 && flag_unsafe_math_optimizations" 15851 && flag_unsafe_math_optimizations"
16132 { 15852 {
16133 rtx op0, op1, op2; 15853 rtx op0 = gen_reg_rtx (XFmode);
16134 15854 rtx op1 = gen_reg_rtx (XFmode);
16135 op0 = gen_reg_rtx (XFmode); 15855 rtx op2 = gen_reg_rtx (XFmode);
16136 op1 = gen_reg_rtx (XFmode);
16137 op2 = gen_reg_rtx (XFmode);
16138 15856
16139 emit_insn (gen_extend<mode>xf2 (op1, operands[1])); 15857 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
16140 emit_insn (gen_extend<mode>xf2 (op2, operands[2])); 15858 emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
16141 emit_insn (gen_scalbxf3 (op0, op1, op2)); 15859 emit_insn (gen_scalbxf3 (op0, op1, op2));
16142 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0)); 15860 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
16143 DONE; 15861 DONE;
16144 }) 15862 })
16145 15863
16146 (define_expand "significandxf2" 15864 (define_expand "significandxf2"
16147 [(parallel [(set (match_operand:XF 0 "register_operand") 15865 [(parallel [(set (match_operand:XF 0 "register_operand")
16153 && flag_unsafe_math_optimizations" 15871 && flag_unsafe_math_optimizations"
16154 "operands[2] = gen_reg_rtx (XFmode);") 15872 "operands[2] = gen_reg_rtx (XFmode);")
16155 15873
16156 (define_expand "significand<mode>2" 15874 (define_expand "significand<mode>2"
16157 [(use (match_operand:MODEF 0 "register_operand")) 15875 [(use (match_operand:MODEF 0 "register_operand"))
16158 (use (match_operand:MODEF 1 "register_operand"))] 15876 (use (match_operand:MODEF 1 "general_operand"))]
16159 "TARGET_USE_FANCY_MATH_387 15877 "TARGET_USE_FANCY_MATH_387
16160 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15878 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16161 || TARGET_MIX_SSE_I387) 15879 || TARGET_MIX_SSE_I387)
16162 && flag_unsafe_math_optimizations" 15880 && flag_unsafe_math_optimizations"
16163 { 15881 {
16164 rtx op0 = gen_reg_rtx (XFmode); 15882 rtx op0 = gen_reg_rtx (XFmode);
16165 rtx op1 = gen_reg_rtx (XFmode); 15883 rtx op1 = gen_reg_rtx (XFmode);
16166 15884
16167 emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1])); 15885 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
16168 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0)); 15886 emit_insn (gen_significandxf2 (op0, op1));
15887 emit_insn (gen_truncxf<mode>2 (operands[0], op0));
16169 DONE; 15888 DONE;
16170 }) 15889 })
16171 15890
16172 15891
16173 (define_insn "sse4_1_round<mode>2" 15892 (define_insn "sse4_1_round<mode>2"
16174 [(set (match_operand:MODEF 0 "register_operand" "=x,v") 15893 [(set (match_operand:MODEF 0 "register_operand" "=x,v")
16175 (unspec:MODEF [(match_operand:MODEF 1 "register_operand" "x,v") 15894 (unspec:MODEF [(match_operand:MODEF 1 "nonimmediate_operand" "xm,vm")
16176 (match_operand:SI 2 "const_0_to_15_operand" "n,n")] 15895 (match_operand:SI 2 "const_0_to_15_operand" "n,n")]
16177 UNSPEC_ROUND))] 15896 UNSPEC_ROUND))]
16178 "TARGET_SSE4_1" 15897 "TARGET_SSE4_1"
16179 "@ 15898 "@
16180 %vround<ssemodesuffix>\t{%2, %1, %d0|%d0, %1, %2} 15899 %vround<ssemodesuffix>\t{%2, %1, %d0|%d0, %1, %2}
16194 "frndint" 15913 "frndint"
16195 [(set_attr "type" "fpspc") 15914 [(set_attr "type" "fpspc")
16196 (set_attr "znver1_decode" "vector") 15915 (set_attr "znver1_decode" "vector")
16197 (set_attr "mode" "XF")]) 15916 (set_attr "mode" "XF")])
16198 15917
16199 (define_insn "rint<mode>2_frndint"
16200 [(set (match_operand:MODEF 0 "register_operand" "=f")
16201 (unspec:MODEF [(match_operand:MODEF 1 "register_operand" "0")]
16202 UNSPEC_FRNDINT))]
16203 "TARGET_USE_FANCY_MATH_387"
16204 "frndint"
16205 [(set_attr "type" "fpspc")
16206 (set_attr "znver1_decode" "vector")
16207 (set_attr "mode" "<MODE>")])
16208
16209 (define_expand "rint<mode>2" 15918 (define_expand "rint<mode>2"
16210 [(use (match_operand:MODEF 0 "register_operand")) 15919 [(use (match_operand:MODEF 0 "register_operand"))
16211 (use (match_operand:MODEF 1 "register_operand"))] 15920 (use (match_operand:MODEF 1 "nonimmediate_operand"))]
16212 "(TARGET_USE_FANCY_MATH_387 15921 "TARGET_USE_FANCY_MATH_387
16213 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16214 || TARGET_MIX_SSE_I387))
16215 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" 15922 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
16216 { 15923 {
16217 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15924 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16218 { 15925 {
16219 if (TARGET_SSE4_1) 15926 if (TARGET_SSE4_1)
16221 (operands[0], operands[1], GEN_INT (ROUND_MXCSR))); 15928 (operands[0], operands[1], GEN_INT (ROUND_MXCSR)));
16222 else 15929 else
16223 ix86_expand_rint (operands[0], operands[1]); 15930 ix86_expand_rint (operands[0], operands[1]);
16224 } 15931 }
16225 else 15932 else
16226 emit_insn (gen_rint<mode>2_frndint (operands[0], operands[1])); 15933 {
15934 rtx op0 = gen_reg_rtx (XFmode);
15935 rtx op1 = gen_reg_rtx (XFmode);
15936
15937 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15938 emit_insn (gen_rintxf2 (op0, op1));
15939 emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
15940 }
15941 DONE;
15942 })
15943
15944 (define_expand "nearbyintxf2"
15945 [(set (match_operand:XF 0 "register_operand")
15946 (unspec:XF [(match_operand:XF 1 "register_operand")]
15947 UNSPEC_FRNDINT))]
15948 "TARGET_USE_FANCY_MATH_387
15949 && !flag_trapping_math")
15950
15951 (define_expand "nearbyint<mode>2"
15952 [(use (match_operand:MODEF 0 "register_operand"))
15953 (use (match_operand:MODEF 1 "nonimmediate_operand"))]
15954 "(TARGET_USE_FANCY_MATH_387
15955 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
15956 || TARGET_MIX_SSE_I387)
15957 && !flag_trapping_math)
15958 || (TARGET_SSE4_1 && TARGET_SSE_MATH)"
15959 {
15960 if (TARGET_SSE4_1 && TARGET_SSE_MATH)
15961 emit_insn (gen_sse4_1_round<mode>2
15962 (operands[0], operands[1], GEN_INT (ROUND_MXCSR
15963 | ROUND_NO_EXC)));
15964 else
15965 {
15966 rtx op0 = gen_reg_rtx (XFmode);
15967 rtx op1 = gen_reg_rtx (XFmode);
15968
15969 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
15970 emit_insn (gen_nearbyintxf2 (op0, op1));
15971 emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
15972 }
16227 DONE; 15973 DONE;
16228 }) 15974 })
16229 15975
16230 (define_expand "round<mode>2" 15976 (define_expand "round<mode>2"
16231 [(match_operand:X87MODEF 0 "register_operand") 15977 [(match_operand:X87MODEF 0 "register_operand")
16232 (match_operand:X87MODEF 1 "nonimmediate_operand")] 15978 (match_operand:X87MODEF 1 "nonimmediate_operand")]
16233 "(TARGET_USE_FANCY_MATH_387 15979 "(TARGET_USE_FANCY_MATH_387
16234 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 15980 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16235 || TARGET_MIX_SSE_I387) 15981 || TARGET_MIX_SSE_I387)
16236 && flag_unsafe_math_optimizations) 15982 && flag_unsafe_math_optimizations
15983 && (flag_fp_int_builtin_inexact || !flag_trapping_math))
16237 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH 15984 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
16238 && !flag_trapping_math && !flag_rounding_math)" 15985 && !flag_trapping_math && !flag_rounding_math)"
16239 { 15986 {
16240 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH 15987 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
16241 && !flag_trapping_math && !flag_rounding_math) 15988 && !flag_trapping_math && !flag_rounding_math)
16256 ix86_emit_i387_round (operands[0], operands[1]); 16003 ix86_emit_i387_round (operands[0], operands[1]);
16257 } 16004 }
16258 DONE; 16005 DONE;
16259 }) 16006 })
16260 16007
16261 (define_insn_and_split "*fistdi2_1" 16008 (define_insn "lrintxfdi2"
16262 [(set (match_operand:DI 0 "nonimmediate_operand") 16009 [(set (match_operand:DI 0 "nonimmediate_operand" "=m")
16263 (unspec:DI [(match_operand:XF 1 "register_operand")]
16264 UNSPEC_FIST))]
16265 "TARGET_USE_FANCY_MATH_387
16266 && can_create_pseudo_p ()"
16267 "#"
16268 "&& 1"
16269 [(const_int 0)]
16270 {
16271 if (memory_operand (operands[0], VOIDmode))
16272 emit_insn (gen_fistdi2 (operands[0], operands[1]));
16273 else
16274 {
16275 operands[2] = assign_386_stack_local (DImode, SLOT_TEMP);
16276 emit_insn (gen_fistdi2_with_temp (operands[0], operands[1],
16277 operands[2]));
16278 }
16279 DONE;
16280 }
16281 [(set_attr "type" "fpspc")
16282 (set_attr "mode" "DI")])
16283
16284 (define_insn "fistdi2"
16285 [(set (match_operand:DI 0 "memory_operand" "=m")
16286 (unspec:DI [(match_operand:XF 1 "register_operand" "f")] 16010 (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
16287 UNSPEC_FIST)) 16011 UNSPEC_FIST))
16288 (clobber (match_scratch:XF 2 "=&1f"))] 16012 (clobber (match_scratch:XF 2 "=&f"))]
16289 "TARGET_USE_FANCY_MATH_387" 16013 "TARGET_USE_FANCY_MATH_387"
16290 "* return output_fix_trunc (insn, operands, false);" 16014 "* return output_fix_trunc (insn, operands, false);"
16291 [(set_attr "type" "fpspc") 16015 [(set_attr "type" "fpspc")
16292 (set_attr "mode" "DI")]) 16016 (set_attr "mode" "DI")])
16293 16017
16294 (define_insn "fistdi2_with_temp" 16018 (define_insn "lrintxf<mode>2"
16295 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r") 16019 [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m")
16296 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
16297 UNSPEC_FIST))
16298 (clobber (match_operand:DI 2 "memory_operand" "=X,m"))
16299 (clobber (match_scratch:XF 3 "=&1f,&1f"))]
16300 "TARGET_USE_FANCY_MATH_387"
16301 "#"
16302 [(set_attr "type" "fpspc")
16303 (set_attr "mode" "DI")])
16304
16305 (define_split
16306 [(set (match_operand:DI 0 "register_operand")
16307 (unspec:DI [(match_operand:XF 1 "register_operand")]
16308 UNSPEC_FIST))
16309 (clobber (match_operand:DI 2 "memory_operand"))
16310 (clobber (match_scratch 3))]
16311 "reload_completed"
16312 [(parallel [(set (match_dup 2) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
16313 (clobber (match_dup 3))])
16314 (set (match_dup 0) (match_dup 2))])
16315
16316 (define_split
16317 [(set (match_operand:DI 0 "memory_operand")
16318 (unspec:DI [(match_operand:XF 1 "register_operand")]
16319 UNSPEC_FIST))
16320 (clobber (match_operand:DI 2 "memory_operand"))
16321 (clobber (match_scratch 3))]
16322 "reload_completed"
16323 [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
16324 (clobber (match_dup 3))])])
16325
16326 (define_insn_and_split "*fist<mode>2_1"
16327 [(set (match_operand:SWI24 0 "register_operand")
16328 (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
16329 UNSPEC_FIST))]
16330 "TARGET_USE_FANCY_MATH_387
16331 && can_create_pseudo_p ()"
16332 "#"
16333 "&& 1"
16334 [(const_int 0)]
16335 {
16336 operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
16337 emit_insn (gen_fist<mode>2_with_temp (operands[0], operands[1],
16338 operands[2]));
16339 DONE;
16340 }
16341 [(set_attr "type" "fpspc")
16342 (set_attr "mode" "<MODE>")])
16343
16344 (define_insn "fist<mode>2"
16345 [(set (match_operand:SWI24 0 "memory_operand" "=m")
16346 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")] 16020 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
16347 UNSPEC_FIST))] 16021 UNSPEC_FIST))]
16348 "TARGET_USE_FANCY_MATH_387" 16022 "TARGET_USE_FANCY_MATH_387"
16349 "* return output_fix_trunc (insn, operands, false);" 16023 "* return output_fix_trunc (insn, operands, false);"
16350 [(set_attr "type" "fpspc") 16024 [(set_attr "type" "fpspc")
16351 (set_attr "mode" "<MODE>")]) 16025 (set_attr "mode" "<MODE>")])
16352
16353 (define_insn "fist<mode>2_with_temp"
16354 [(set (match_operand:SWI24 0 "register_operand" "=r")
16355 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
16356 UNSPEC_FIST))
16357 (clobber (match_operand:SWI24 2 "memory_operand" "=m"))]
16358 "TARGET_USE_FANCY_MATH_387"
16359 "#"
16360 [(set_attr "type" "fpspc")
16361 (set_attr "mode" "<MODE>")])
16362
16363 (define_split
16364 [(set (match_operand:SWI24 0 "register_operand")
16365 (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
16366 UNSPEC_FIST))
16367 (clobber (match_operand:SWI24 2 "memory_operand"))]
16368 "reload_completed"
16369 [(set (match_dup 2) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))
16370 (set (match_dup 0) (match_dup 2))])
16371
16372 (define_split
16373 [(set (match_operand:SWI24 0 "memory_operand")
16374 (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
16375 UNSPEC_FIST))
16376 (clobber (match_operand:SWI24 2 "memory_operand"))]
16377 "reload_completed"
16378 [(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))])
16379
16380 (define_expand "lrintxf<mode>2"
16381 [(set (match_operand:SWI248x 0 "nonimmediate_operand")
16382 (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
16383 UNSPEC_FIST))]
16384 "TARGET_USE_FANCY_MATH_387")
16385 16026
16386 (define_expand "lrint<MODEF:mode><SWI48:mode>2" 16027 (define_expand "lrint<MODEF:mode><SWI48:mode>2"
16387 [(set (match_operand:SWI48 0 "nonimmediate_operand") 16028 [(set (match_operand:SWI48 0 "nonimmediate_operand")
16388 (unspec:SWI48 [(match_operand:MODEF 1 "register_operand")] 16029 (unspec:SWI48 [(match_operand:MODEF 1 "register_operand")]
16389 UNSPEC_FIX_NOTRUNC))] 16030 UNSPEC_FIX_NOTRUNC))]
16444 (UNSPEC_FRNDINT_TRUNC "TRUNC") 16085 (UNSPEC_FRNDINT_TRUNC "TRUNC")
16445 (UNSPEC_FIST_FLOOR "FLOOR") 16086 (UNSPEC_FIST_FLOOR "FLOOR")
16446 (UNSPEC_FIST_CEIL "CEIL")]) 16087 (UNSPEC_FIST_CEIL "CEIL")])
16447 16088
16448 ;; Rounding mode control word calculation could clobber FLAGS_REG. 16089 ;; Rounding mode control word calculation could clobber FLAGS_REG.
16449 (define_insn_and_split "frndint<mode>2_<rounding>" 16090 (define_insn_and_split "frndintxf2_<rounding>"
16450 [(set (match_operand:X87MODEF 0 "register_operand") 16091 [(set (match_operand:XF 0 "register_operand")
16451 (unspec:X87MODEF [(match_operand:X87MODEF 1 "register_operand")] 16092 (unspec:XF [(match_operand:XF 1 "register_operand")]
16452 FRNDINT_ROUNDING)) 16093 FRNDINT_ROUNDING))
16453 (clobber (reg:CC FLAGS_REG))] 16094 (clobber (reg:CC FLAGS_REG))]
16454 "TARGET_USE_FANCY_MATH_387 16095 "TARGET_USE_FANCY_MATH_387
16455 && (flag_fp_int_builtin_inexact || !flag_trapping_math) 16096 && (flag_fp_int_builtin_inexact || !flag_trapping_math)
16456 && can_create_pseudo_p ()" 16097 && can_create_pseudo_p ()"
16461 ix86_optimize_mode_switching[I387_<ROUNDING>] = 1; 16102 ix86_optimize_mode_switching[I387_<ROUNDING>] = 1;
16462 16103
16463 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED); 16104 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
16464 operands[3] = assign_386_stack_local (HImode, SLOT_CW_<ROUNDING>); 16105 operands[3] = assign_386_stack_local (HImode, SLOT_CW_<ROUNDING>);
16465 16106
16466 emit_insn (gen_frndint<mode>2_<rounding>_i387 (operands[0], operands[1], 16107 emit_insn (gen_frndintxf2_<rounding>_i387 (operands[0], operands[1],
16467 operands[2], operands[3])); 16108 operands[2], operands[3]));
16468 DONE; 16109 DONE;
16469 } 16110 }
16470 [(set_attr "type" "frndint") 16111 [(set_attr "type" "frndint")
16471 (set_attr "i387_cw" "<rounding>") 16112 (set_attr "i387_cw" "<rounding>")
16472 (set_attr "mode" "<MODE>")]) 16113 (set_attr "mode" "XF")])
16473 16114
16474 (define_insn "frndint<mode>2_<rounding>_i387" 16115 (define_insn "frndintxf2_<rounding>_i387"
16475 [(set (match_operand:X87MODEF 0 "register_operand" "=f") 16116 [(set (match_operand:XF 0 "register_operand" "=f")
16476 (unspec:X87MODEF [(match_operand:X87MODEF 1 "register_operand" "0")] 16117 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16477 FRNDINT_ROUNDING)) 16118 FRNDINT_ROUNDING))
16478 (use (match_operand:HI 2 "memory_operand" "m")) 16119 (use (match_operand:HI 2 "memory_operand" "m"))
16479 (use (match_operand:HI 3 "memory_operand" "m"))] 16120 (use (match_operand:HI 3 "memory_operand" "m"))]
16480 "TARGET_USE_FANCY_MATH_387 16121 "TARGET_USE_FANCY_MATH_387
16481 && (flag_fp_int_builtin_inexact || !flag_trapping_math)" 16122 && (flag_fp_int_builtin_inexact || !flag_trapping_math)"
16482 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2" 16123 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16483 [(set_attr "type" "frndint") 16124 [(set_attr "type" "frndint")
16484 (set_attr "i387_cw" "<rounding>") 16125 (set_attr "i387_cw" "<rounding>")
16485 (set_attr "mode" "<MODE>")]) 16126 (set_attr "mode" "XF")])
16486 16127
16487 (define_expand "<rounding_insn>xf2" 16128 (define_expand "<rounding_insn>xf2"
16488 [(parallel [(set (match_operand:XF 0 "register_operand") 16129 [(parallel [(set (match_operand:XF 0 "register_operand")
16489 (unspec:XF [(match_operand:XF 1 "register_operand")] 16130 (unspec:XF [(match_operand:XF 1 "register_operand")]
16490 FRNDINT_ROUNDING)) 16131 FRNDINT_ROUNDING))
16500 "(TARGET_USE_FANCY_MATH_387 16141 "(TARGET_USE_FANCY_MATH_387
16501 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) 16142 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16502 || TARGET_MIX_SSE_I387) 16143 || TARGET_MIX_SSE_I387)
16503 && (flag_fp_int_builtin_inexact || !flag_trapping_math)) 16144 && (flag_fp_int_builtin_inexact || !flag_trapping_math))
16504 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH 16145 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
16505 && (TARGET_SSE4_1 || !flag_trapping_math 16146 && (TARGET_SSE4_1 || flag_fp_int_builtin_inexact
16506 || flag_fp_int_builtin_inexact))" 16147 || !flag_trapping_math))"
16507 { 16148 {
16508 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH 16149 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
16509 && (TARGET_SSE4_1 || !flag_trapping_math || flag_fp_int_builtin_inexact)) 16150 && (TARGET_SSE4_1 || flag_fp_int_builtin_inexact || !flag_trapping_math))
16510 { 16151 {
16511 if (TARGET_SSE4_1) 16152 if (TARGET_SSE4_1)
16512 emit_insn (gen_sse4_1_round<mode>2 16153 emit_insn (gen_sse4_1_round<mode>2
16513 (operands[0], operands[1], GEN_INT (ROUND_<ROUNDING> 16154 (operands[0], operands[1], GEN_INT (ROUND_<ROUNDING>
16514 | ROUND_NO_EXC))); 16155 | ROUND_NO_EXC)));
16534 else 16175 else
16535 gcc_unreachable (); 16176 gcc_unreachable ();
16536 } 16177 }
16537 } 16178 }
16538 else 16179 else
16539 emit_insn (gen_frndint<mode>2_<rounding> (operands[0], operands[1])); 16180 {
16181 rtx op0 = gen_reg_rtx (XFmode);
16182 rtx op1 = gen_reg_rtx (XFmode);
16183
16184 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
16185 emit_insn (gen_frndintxf2_<rounding> (op0, op1));
16186 emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
16187 }
16540 DONE; 16188 DONE;
16541 }) 16189 })
16542 16190
16543 ;; Rounding mode control word calculation could clobber FLAGS_REG. 16191 ;; Rounding mode control word calculation could clobber FLAGS_REG.
16544 (define_insn_and_split "frndintxf2_mask_pm" 16192 (define_insn_and_split "*fist<mode>2_<rounding>_1"
16545 [(set (match_operand:XF 0 "register_operand") 16193 [(set (match_operand:SWI248x 0 "nonimmediate_operand")
16546 (unspec:XF [(match_operand:XF 1 "register_operand")] 16194 (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
16547 UNSPEC_FRNDINT_MASK_PM)) 16195 FIST_ROUNDING))
16548 (clobber (reg:CC FLAGS_REG))] 16196 (clobber (reg:CC FLAGS_REG))]
16549 "TARGET_USE_FANCY_MATH_387 16197 "TARGET_USE_FANCY_MATH_387
16550 && flag_unsafe_math_optimizations 16198 && flag_unsafe_math_optimizations
16551 && can_create_pseudo_p ()" 16199 && can_create_pseudo_p ()"
16552 "#" 16200 "#"
16553 "&& 1" 16201 "&& 1"
16554 [(const_int 0)] 16202 [(const_int 0)]
16555 { 16203 {
16556 ix86_optimize_mode_switching[I387_MASK_PM] = 1;
16557
16558 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
16559 operands[3] = assign_386_stack_local (HImode, SLOT_CW_MASK_PM);
16560
16561 emit_insn (gen_frndintxf2_mask_pm_i387 (operands[0], operands[1],
16562 operands[2], operands[3]));
16563 DONE;
16564 }
16565 [(set_attr "type" "frndint")
16566 (set_attr "i387_cw" "mask_pm")
16567 (set_attr "mode" "XF")])
16568
16569 (define_insn "frndintxf2_mask_pm_i387"
16570 [(set (match_operand:XF 0 "register_operand" "=f")
16571 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16572 UNSPEC_FRNDINT_MASK_PM))
16573 (use (match_operand:HI 2 "memory_operand" "m"))
16574 (use (match_operand:HI 3 "memory_operand" "m"))]
16575 "TARGET_USE_FANCY_MATH_387
16576 && flag_unsafe_math_optimizations"
16577 "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
16578 [(set_attr "type" "frndint")
16579 (set_attr "i387_cw" "mask_pm")
16580 (set_attr "mode" "XF")])
16581
16582 (define_expand "nearbyintxf2"
16583 [(parallel [(set (match_operand:XF 0 "register_operand")
16584 (unspec:XF [(match_operand:XF 1 "register_operand")]
16585 UNSPEC_FRNDINT_MASK_PM))
16586 (clobber (reg:CC FLAGS_REG))])]
16587 "TARGET_USE_FANCY_MATH_387
16588 && flag_unsafe_math_optimizations")
16589
16590 (define_expand "nearbyint<mode>2"
16591 [(use (match_operand:MODEF 0 "register_operand"))
16592 (use (match_operand:MODEF 1 "register_operand"))]
16593 "TARGET_USE_FANCY_MATH_387
16594 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16595 || TARGET_MIX_SSE_I387)
16596 && flag_unsafe_math_optimizations"
16597 {
16598 rtx op0 = gen_reg_rtx (XFmode);
16599 rtx op1 = gen_reg_rtx (XFmode);
16600
16601 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
16602 emit_insn (gen_frndintxf2_mask_pm (op0, op1));
16603
16604 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
16605 DONE;
16606 })
16607
16608 ;; Rounding mode control word calculation could clobber FLAGS_REG.
16609 (define_insn_and_split "*fist<mode>2_<rounding>_1"
16610 [(set (match_operand:SWI248x 0 "nonimmediate_operand")
16611 (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
16612 FIST_ROUNDING))
16613 (clobber (reg:CC FLAGS_REG))]
16614 "TARGET_USE_FANCY_MATH_387
16615 && flag_unsafe_math_optimizations
16616 && can_create_pseudo_p ()"
16617 "#"
16618 "&& 1"
16619 [(const_int 0)]
16620 {
16621 ix86_optimize_mode_switching[I387_<ROUNDING>] = 1; 16204 ix86_optimize_mode_switching[I387_<ROUNDING>] = 1;
16622 16205
16623 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED); 16206 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
16624 operands[3] = assign_386_stack_local (HImode, SLOT_CW_<ROUNDING>); 16207 operands[3] = assign_386_stack_local (HImode, SLOT_CW_<ROUNDING>);
16625 if (memory_operand (operands[0], VOIDmode)) 16208
16626 emit_insn (gen_fist<mode>2_<rounding> (operands[0], operands[1], 16209 emit_insn (gen_fist<mode>2_<rounding> (operands[0], operands[1],
16627 operands[2], operands[3])); 16210 operands[2], operands[3]));
16628 else
16629 {
16630 operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
16631 emit_insn (gen_fist<mode>2_<rounding>_with_temp
16632 (operands[0], operands[1], operands[2],
16633 operands[3], operands[4]));
16634 }
16635 DONE; 16211 DONE;
16636 } 16212 }
16637 [(set_attr "type" "fistp") 16213 [(set_attr "type" "fistp")
16638 (set_attr "i387_cw" "<rounding>") 16214 (set_attr "i387_cw" "<rounding>")
16639 (set_attr "mode" "<MODE>")]) 16215 (set_attr "mode" "<MODE>")])
16640 16216
16641 (define_insn "fistdi2_<rounding>" 16217 (define_insn "fistdi2_<rounding>"
16642 [(set (match_operand:DI 0 "memory_operand" "=m") 16218 [(set (match_operand:DI 0 "nonimmediate_operand" "=m")
16643 (unspec:DI [(match_operand:XF 1 "register_operand" "f")] 16219 (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
16644 FIST_ROUNDING)) 16220 FIST_ROUNDING))
16645 (use (match_operand:HI 2 "memory_operand" "m")) 16221 (use (match_operand:HI 2 "memory_operand" "m"))
16646 (use (match_operand:HI 3 "memory_operand" "m")) 16222 (use (match_operand:HI 3 "memory_operand" "m"))
16647 (clobber (match_scratch:XF 4 "=&1f"))] 16223 (clobber (match_scratch:XF 4 "=&f"))]
16648 "TARGET_USE_FANCY_MATH_387 16224 "TARGET_USE_FANCY_MATH_387
16649 && flag_unsafe_math_optimizations" 16225 && flag_unsafe_math_optimizations"
16650 "* return output_fix_trunc (insn, operands, false);" 16226 "* return output_fix_trunc (insn, operands, false);"
16651 [(set_attr "type" "fistp") 16227 [(set_attr "type" "fistp")
16652 (set_attr "i387_cw" "<rounding>") 16228 (set_attr "i387_cw" "<rounding>")
16653 (set_attr "mode" "DI")]) 16229 (set_attr "mode" "DI")])
16654 16230
16655 (define_insn "fistdi2_<rounding>_with_temp"
16656 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
16657 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
16658 FIST_ROUNDING))
16659 (use (match_operand:HI 2 "memory_operand" "m,m"))
16660 (use (match_operand:HI 3 "memory_operand" "m,m"))
16661 (clobber (match_operand:DI 4 "memory_operand" "=X,m"))
16662 (clobber (match_scratch:XF 5 "=&1f,&1f"))]
16663 "TARGET_USE_FANCY_MATH_387
16664 && flag_unsafe_math_optimizations"
16665 "#"
16666 [(set_attr "type" "fistp")
16667 (set_attr "i387_cw" "<rounding>")
16668 (set_attr "mode" "DI")])
16669
16670 (define_split
16671 [(set (match_operand:DI 0 "register_operand")
16672 (unspec:DI [(match_operand:XF 1 "register_operand")]
16673 FIST_ROUNDING))
16674 (use (match_operand:HI 2 "memory_operand"))
16675 (use (match_operand:HI 3 "memory_operand"))
16676 (clobber (match_operand:DI 4 "memory_operand"))
16677 (clobber (match_scratch 5))]
16678 "reload_completed"
16679 [(parallel [(set (match_dup 4)
16680 (unspec:DI [(match_dup 1)] FIST_ROUNDING))
16681 (use (match_dup 2))
16682 (use (match_dup 3))
16683 (clobber (match_dup 5))])
16684 (set (match_dup 0) (match_dup 4))])
16685
16686 (define_split
16687 [(set (match_operand:DI 0 "memory_operand")
16688 (unspec:DI [(match_operand:XF 1 "register_operand")]
16689 FIST_ROUNDING))
16690 (use (match_operand:HI 2 "memory_operand"))
16691 (use (match_operand:HI 3 "memory_operand"))
16692 (clobber (match_operand:DI 4 "memory_operand"))
16693 (clobber (match_scratch 5))]
16694 "reload_completed"
16695 [(parallel [(set (match_dup 0)
16696 (unspec:DI [(match_dup 1)] FIST_ROUNDING))
16697 (use (match_dup 2))
16698 (use (match_dup 3))
16699 (clobber (match_dup 5))])])
16700
16701 (define_insn "fist<mode>2_<rounding>" 16231 (define_insn "fist<mode>2_<rounding>"
16702 [(set (match_operand:SWI24 0 "memory_operand" "=m") 16232 [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m")
16703 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")] 16233 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
16704 FIST_ROUNDING)) 16234 FIST_ROUNDING))
16705 (use (match_operand:HI 2 "memory_operand" "m")) 16235 (use (match_operand:HI 2 "memory_operand" "m"))
16706 (use (match_operand:HI 3 "memory_operand" "m"))] 16236 (use (match_operand:HI 3 "memory_operand" "m"))]
16707 "TARGET_USE_FANCY_MATH_387 16237 "TARGET_USE_FANCY_MATH_387
16709 "* return output_fix_trunc (insn, operands, false);" 16239 "* return output_fix_trunc (insn, operands, false);"
16710 [(set_attr "type" "fistp") 16240 [(set_attr "type" "fistp")
16711 (set_attr "i387_cw" "<rounding>") 16241 (set_attr "i387_cw" "<rounding>")
16712 (set_attr "mode" "<MODE>")]) 16242 (set_attr "mode" "<MODE>")])
16713 16243
16714 (define_insn "fist<mode>2_<rounding>_with_temp"
16715 [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r")
16716 (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f,f")]
16717 FIST_ROUNDING))
16718 (use (match_operand:HI 2 "memory_operand" "m,m"))
16719 (use (match_operand:HI 3 "memory_operand" "m,m"))
16720 (clobber (match_operand:SWI24 4 "memory_operand" "=X,m"))]
16721 "TARGET_USE_FANCY_MATH_387
16722 && flag_unsafe_math_optimizations"
16723 "#"
16724 [(set_attr "type" "fistp")
16725 (set_attr "i387_cw" "<rounding>")
16726 (set_attr "mode" "<MODE>")])
16727
16728 (define_split
16729 [(set (match_operand:SWI24 0 "register_operand")
16730 (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
16731 FIST_ROUNDING))
16732 (use (match_operand:HI 2 "memory_operand"))
16733 (use (match_operand:HI 3 "memory_operand"))
16734 (clobber (match_operand:SWI24 4 "memory_operand"))]
16735 "reload_completed"
16736 [(parallel [(set (match_dup 4)
16737 (unspec:SWI24 [(match_dup 1)] FIST_ROUNDING))
16738 (use (match_dup 2))
16739 (use (match_dup 3))])
16740 (set (match_dup 0) (match_dup 4))])
16741
16742 (define_split
16743 [(set (match_operand:SWI24 0 "memory_operand")
16744 (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
16745 FIST_ROUNDING))
16746 (use (match_operand:HI 2 "memory_operand"))
16747 (use (match_operand:HI 3 "memory_operand"))
16748 (clobber (match_operand:SWI24 4 "memory_operand"))]
16749 "reload_completed"
16750 [(parallel [(set (match_dup 0)
16751 (unspec:SWI24 [(match_dup 1)] FIST_ROUNDING))
16752 (use (match_dup 2))
16753 (use (match_dup 3))])])
16754
16755 (define_expand "l<rounding_insn>xf<mode>2" 16244 (define_expand "l<rounding_insn>xf<mode>2"
16756 [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand") 16245 [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand")
16757 (unspec:SWI248x [(match_operand:XF 1 "register_operand")] 16246 (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
16758 FIST_ROUNDING)) 16247 FIST_ROUNDING))
16759 (clobber (reg:CC FLAGS_REG))])] 16248 (clobber (reg:CC FLAGS_REG))])]
16765 [(parallel [(set (match_operand:SWI48 0 "nonimmediate_operand") 16254 [(parallel [(set (match_operand:SWI48 0 "nonimmediate_operand")
16766 (unspec:SWI48 [(match_operand:MODEF 1 "register_operand")] 16255 (unspec:SWI48 [(match_operand:MODEF 1 "register_operand")]
16767 FIST_ROUNDING)) 16256 FIST_ROUNDING))
16768 (clobber (reg:CC FLAGS_REG))])] 16257 (clobber (reg:CC FLAGS_REG))])]
16769 "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH 16258 "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
16770 && !flag_trapping_math" 16259 && (TARGET_SSE4_1 || !flag_trapping_math)"
16771 { 16260 {
16772 if (TARGET_64BIT && optimize_insn_for_size_p ()) 16261 if (TARGET_SSE4_1)
16773 FAIL; 16262 {
16774 16263 rtx tmp = gen_reg_rtx (<MODEF:MODE>mode);
16775 if (ROUND_<ROUNDING> == ROUND_FLOOR) 16264
16265 emit_insn (gen_sse4_1_round<mode>2
16266 (tmp, operands[1], GEN_INT (ROUND_<ROUNDING>
16267 | ROUND_NO_EXC)));
16268 emit_insn (gen_fix_trunc<MODEF:mode><SWI48:mode>2
16269 (operands[0], tmp));
16270 }
16271 else if (ROUND_<ROUNDING> == ROUND_FLOOR)
16776 ix86_expand_lfloorceil (operands[0], operands[1], true); 16272 ix86_expand_lfloorceil (operands[0], operands[1], true);
16777 else if (ROUND_<ROUNDING> == ROUND_CEIL) 16273 else if (ROUND_<ROUNDING> == ROUND_CEIL)
16778 ix86_expand_lfloorceil (operands[0], operands[1], false); 16274 ix86_expand_lfloorceil (operands[0], operands[1], false);
16779 else 16275 else
16780 gcc_unreachable (); 16276 gcc_unreachable ();
16791 "fxam\n\tfnstsw\t%0" 16287 "fxam\n\tfnstsw\t%0"
16792 [(set_attr "type" "multi") 16288 [(set_attr "type" "multi")
16793 (set_attr "length" "4") 16289 (set_attr "length" "4")
16794 (set_attr "unit" "i387") 16290 (set_attr "unit" "i387")
16795 (set_attr "mode" "<MODE>")]) 16291 (set_attr "mode" "<MODE>")])
16796
16797 (define_insn_and_split "fxam<mode>2_i387_with_temp"
16798 [(set (match_operand:HI 0 "register_operand")
16799 (unspec:HI
16800 [(match_operand:MODEF 1 "memory_operand")]
16801 UNSPEC_FXAM_MEM))]
16802 "TARGET_USE_FANCY_MATH_387
16803 && can_create_pseudo_p ()"
16804 "#"
16805 "&& 1"
16806 [(set (match_dup 2)(match_dup 1))
16807 (set (match_dup 0)
16808 (unspec:HI [(match_dup 2)] UNSPEC_FXAM))]
16809 {
16810 operands[2] = gen_reg_rtx (<MODE>mode);
16811
16812 MEM_VOLATILE_P (operands[1]) = 1;
16813 }
16814 [(set_attr "type" "multi")
16815 (set_attr "unit" "i387")
16816 (set_attr "mode" "<MODE>")])
16817
16818 (define_expand "isinfxf2"
16819 [(use (match_operand:SI 0 "register_operand"))
16820 (use (match_operand:XF 1 "register_operand"))]
16821 "TARGET_USE_FANCY_MATH_387
16822 && ix86_libc_has_function (function_c99_misc)"
16823 {
16824 rtx mask = GEN_INT (0x45);
16825 rtx val = GEN_INT (0x05);
16826
16827 rtx scratch = gen_reg_rtx (HImode);
16828 rtx res = gen_reg_rtx (QImode);
16829
16830 emit_insn (gen_fxamxf2_i387 (scratch, operands[1]));
16831
16832 emit_insn (gen_andqi_ext_1 (scratch, scratch, mask));
16833 emit_insn (gen_cmpqi_ext_3 (scratch, val));
16834 ix86_expand_setcc (res, EQ,
16835 gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
16836 emit_insn (gen_zero_extendqisi2 (operands[0], res));
16837 DONE;
16838 })
16839
16840 (define_expand "isinf<mode>2"
16841 [(use (match_operand:SI 0 "register_operand"))
16842 (use (match_operand:MODEF 1 "nonimmediate_operand"))]
16843 "TARGET_USE_FANCY_MATH_387
16844 && ix86_libc_has_function (function_c99_misc)
16845 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
16846 {
16847 rtx mask = GEN_INT (0x45);
16848 rtx val = GEN_INT (0x05);
16849
16850 rtx scratch = gen_reg_rtx (HImode);
16851 rtx res = gen_reg_rtx (QImode);
16852
16853 /* Remove excess precision by forcing value through memory. */
16854 if (memory_operand (operands[1], VOIDmode))
16855 emit_insn (gen_fxam<mode>2_i387_with_temp (scratch, operands[1]));
16856 else
16857 {
16858 rtx temp = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
16859
16860 emit_move_insn (temp, operands[1]);
16861 emit_insn (gen_fxam<mode>2_i387_with_temp (scratch, temp));
16862 }
16863
16864 emit_insn (gen_andqi_ext_1 (scratch, scratch, mask));
16865 emit_insn (gen_cmpqi_ext_3 (scratch, val));
16866 ix86_expand_setcc (res, EQ,
16867 gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
16868 emit_insn (gen_zero_extendqisi2 (operands[0], res));
16869 DONE;
16870 })
16871 16292
16872 (define_expand "signbittf2" 16293 (define_expand "signbittf2"
16873 [(use (match_operand:SI 0 "register_operand")) 16294 [(use (match_operand:SI 0 "register_operand"))
16874 (use (match_operand:TF 1 "register_operand"))] 16295 (use (match_operand:TF 1 "register_operand"))]
16875 "TARGET_SSE" 16296 "TARGET_SSE"
17719 (const_int -1) 17140 (const_int -1)
17720 (const_int 0))) 17141 (const_int 0)))
17721 (clobber (reg:CC FLAGS_REG))] 17142 (clobber (reg:CC FLAGS_REG))]
17722 "" 17143 ""
17723 "sbb{<imodesuffix>}\t%0, %0" 17144 "sbb{<imodesuffix>}\t%0, %0"
17724 ; Since we don't have the proper number of operands for an alu insn, 17145 [(set_attr "type" "alu1")
17725 ; fill in all the blanks.
17726 [(set_attr "type" "alu")
17727 (set_attr "modrm_class" "op0")
17728 (set_attr "use_carry" "1") 17146 (set_attr "use_carry" "1")
17729 (set_attr "pent_pair" "pu") 17147 (set_attr "pent_pair" "pu")
17730 (set_attr "memory" "none")
17731 (set_attr "imm_disp" "false")
17732 (set_attr "mode" "<MODE>") 17148 (set_attr "mode" "<MODE>")
17733 (set_attr "length_immediate" "0")]) 17149 (set_attr "length_immediate" "0")])
17734 17150
17735 (define_insn "*x86_mov<mode>cc_0_m1_se" 17151 (define_insn "*x86_mov<mode>cc_0_m1_se"
17736 [(set (match_operand:SWI48 0 "register_operand" "=r") 17152 [(set (match_operand:SWI48 0 "register_operand" "=r")
17739 (const_int 1) 17155 (const_int 1)
17740 (const_int 0))) 17156 (const_int 0)))
17741 (clobber (reg:CC FLAGS_REG))] 17157 (clobber (reg:CC FLAGS_REG))]
17742 "" 17158 ""
17743 "sbb{<imodesuffix>}\t%0, %0" 17159 "sbb{<imodesuffix>}\t%0, %0"
17744 [(set_attr "type" "alu") 17160 [(set_attr "type" "alu1")
17745 (set_attr "modrm_class" "op0")
17746 (set_attr "use_carry" "1") 17161 (set_attr "use_carry" "1")
17747 (set_attr "pent_pair" "pu") 17162 (set_attr "pent_pair" "pu")
17748 (set_attr "memory" "none")
17749 (set_attr "imm_disp" "false")
17750 (set_attr "mode" "<MODE>") 17163 (set_attr "mode" "<MODE>")
17751 (set_attr "length_immediate" "0")]) 17164 (set_attr "length_immediate" "0")])
17752 17165
17753 (define_insn "*x86_mov<mode>cc_0_m1_neg" 17166 (define_insn "*x86_mov<mode>cc_0_m1_neg"
17754 [(set (match_operand:SWI48 0 "register_operand" "=r") 17167 [(set (match_operand:SWI48 0 "register_operand" "=r")
17755 (neg:SWI48 (match_operator 1 "ix86_carry_flag_operator" 17168 (neg:SWI48 (match_operator 1 "ix86_carry_flag_operator"
17756 [(reg FLAGS_REG) (const_int 0)]))) 17169 [(reg FLAGS_REG) (const_int 0)])))
17757 (clobber (reg:CC FLAGS_REG))] 17170 (clobber (reg:CC FLAGS_REG))]
17758 "" 17171 ""
17759 "sbb{<imodesuffix>}\t%0, %0" 17172 "sbb{<imodesuffix>}\t%0, %0"
17760 [(set_attr "type" "alu") 17173 [(set_attr "type" "alu1")
17761 (set_attr "modrm_class" "op0")
17762 (set_attr "use_carry" "1") 17174 (set_attr "use_carry" "1")
17763 (set_attr "pent_pair" "pu") 17175 (set_attr "pent_pair" "pu")
17764 (set_attr "memory" "none")
17765 (set_attr "imm_disp" "false")
17766 (set_attr "mode" "<MODE>") 17176 (set_attr "mode" "<MODE>")
17767 (set_attr "length_immediate" "0")]) 17177 (set_attr "length_immediate" "0")])
17768 17178
17769 (define_insn "*mov<mode>cc_noc" 17179 (define_insn "*mov<mode>cc_noc"
17770 [(set (match_operand:SWI248 0 "register_operand" "=r,r") 17180 [(set (match_operand:SWI248 0 "register_operand" "=r,r")
18306 (clobber (reg:CC FLAGS_REG))] 17716 (clobber (reg:CC FLAGS_REG))]
18307 "" 17717 ""
18308 "* return output_probe_stack_range (operands[0], operands[2]);" 17718 "* return output_probe_stack_range (operands[0], operands[2]);"
18309 [(set_attr "type" "multi")]) 17719 [(set_attr "type" "multi")])
18310 17720
18311 /* Additional processing for builtin_setjmp. Store the shadow stack pointer
18312 as a forth element in jmpbuf. */
18313 (define_expand "builtin_setjmp_setup"
18314 [(match_operand 0 "address_operand")]
18315 "TARGET_SHSTK"
18316 {
18317 if (flag_cf_protection & CF_RETURN)
18318 {
18319 rtx mem, reg_ssp;
18320
18321 mem = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
18322 3 * GET_MODE_SIZE (Pmode)));
18323 reg_ssp = gen_reg_rtx (Pmode);
18324 emit_insn (gen_rtx_SET (reg_ssp, const0_rtx));
18325 emit_insn ((Pmode == SImode)
18326 ? gen_rdsspsi (reg_ssp, reg_ssp)
18327 : gen_rdsspdi (reg_ssp, reg_ssp));
18328 emit_move_insn (mem, reg_ssp);
18329 }
18330 DONE;
18331 })
18332
18333 (define_expand "builtin_setjmp_receiver" 17721 (define_expand "builtin_setjmp_receiver"
18334 [(label_ref (match_operand 0))] 17722 [(label_ref (match_operand 0))]
18335 "!TARGET_64BIT && flag_pic" 17723 "!TARGET_64BIT && flag_pic"
18336 { 17724 {
18337 #if TARGET_MACHO 17725 #if TARGET_MACHO
18348 #endif 17736 #endif
18349 emit_insn (gen_set_got (pic_offset_table_rtx)); 17737 emit_insn (gen_set_got (pic_offset_table_rtx));
18350 DONE; 17738 DONE;
18351 }) 17739 })
18352 17740
18353 (define_expand "builtin_longjmp" 17741 (define_expand "save_stack_nonlocal"
18354 [(match_operand 0 "address_operand")] 17742 [(set (match_operand 0 "memory_operand")
18355 "TARGET_SHSTK" 17743 (match_operand 1 "register_operand"))]
18356 { 17744 ""
18357 rtx fp, lab, stack; 17745 {
18358 rtx jump, label, reg_adj, reg_ssp, reg_minus, mem_buf, tmp, clob; 17746 rtx stack_slot;
18359 machine_mode sa_mode = STACK_SAVEAREA_MODE (SAVE_NONLOCAL); 17747 if ((flag_cf_protection & CF_RETURN))
18360
18361 /* Adjust the shadow stack pointer (ssp) to the value saved in the
18362 jmp_buf. The saving was done in the builtin_setjmp_setup. */
18363 if (flag_cf_protection & CF_RETURN)
18364 { 17748 {
18365 /* Get current shadow stack pointer. The code below will check if 17749 /* Copy shadow stack pointer to the first slot and stack ppointer
18366 SHSTK feature is enabled. If it's not enabled RDSSP instruction 17750 to the second slot. */
17751 rtx ssp_slot = adjust_address (operands[0], word_mode, 0);
17752 stack_slot = adjust_address (operands[0], Pmode, UNITS_PER_WORD);
17753 rtx ssp = gen_reg_rtx (word_mode);
17754 emit_insn ((word_mode == SImode)
17755 ? gen_rdsspsi (ssp)
17756 : gen_rdsspdi (ssp));
17757 emit_move_insn (ssp_slot, ssp);
17758 }
17759 else
17760 stack_slot = adjust_address (operands[0], Pmode, 0);
17761 emit_move_insn (stack_slot, operands[1]);
17762 DONE;
17763 })
17764
17765 (define_expand "restore_stack_nonlocal"
17766 [(set (match_operand 0 "register_operand" "")
17767 (match_operand 1 "memory_operand" ""))]
17768 ""
17769 {
17770 rtx stack_slot;
17771 if ((flag_cf_protection & CF_RETURN))
17772 {
17773 /* Restore shadow stack pointer from the first slot and stack
17774 pointer from the second slot. */
17775 rtx ssp_slot = adjust_address (operands[1], word_mode, 0);
17776 stack_slot = adjust_address (operands[1], Pmode, UNITS_PER_WORD);
17777
17778 rtx flags, jump, noadj_label, inc_label, loop_label;
17779 rtx reg_adj, reg_ssp, tmp, clob;
17780
17781 /* Get the current shadow stack pointer. The code below will check if
17782 SHSTK feature is enabled. If it is not enabled the RDSSP instruction
18367 is a NOP. */ 17783 is a NOP. */
18368 reg_ssp = gen_reg_rtx (Pmode); 17784 reg_ssp = gen_reg_rtx (word_mode);
18369 emit_insn (gen_rtx_SET (reg_ssp, const0_rtx)); 17785 emit_insn (gen_rtx_SET (reg_ssp, const0_rtx));
18370 emit_insn ((Pmode == SImode) 17786 emit_insn ((word_mode == SImode)
18371 ? gen_rdsspsi (reg_ssp, reg_ssp) 17787 ? gen_rdsspsi (reg_ssp)
18372 : gen_rdsspdi (reg_ssp, reg_ssp)); 17788 : gen_rdsspdi (reg_ssp));
18373 mem_buf = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
18374 3 * GET_MODE_SIZE (Pmode))),
18375 17789
18376 /* Compare through substraction the saved and the current ssp to decide 17790 /* Compare through substraction the saved and the current ssp to decide
18377 if ssp has to be adjusted. */ 17791 if ssp has to be adjusted. */
18378 reg_minus = gen_reg_rtx (Pmode); 17792 tmp = gen_rtx_SET (reg_ssp, gen_rtx_MINUS (word_mode, reg_ssp,
18379 tmp = gen_rtx_SET (reg_minus, gen_rtx_MINUS (Pmode, reg_ssp, mem_buf)); 17793 ssp_slot));
18380 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG)); 17794 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
18381 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob)); 17795 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
18382 emit_insn (tmp); 17796 emit_insn (tmp);
18383 17797
18384 /* Jump over adjustment code. */ 17798 /* Compare and jump over adjustment code. */
18385 label = gen_label_rtx (); 17799 noadj_label = gen_label_rtx ();
18386 tmp = gen_rtx_REG (CCmode, FLAGS_REG); 17800 flags = gen_rtx_REG (CCZmode, FLAGS_REG);
18387 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); 17801 tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx);
18388 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 17802 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18389 gen_rtx_LABEL_REF (VOIDmode, label), 17803 gen_rtx_LABEL_REF (VOIDmode, noadj_label),
18390 pc_rtx); 17804 pc_rtx);
18391 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, tmp)); 17805 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
18392 JUMP_LABEL (jump) = label; 17806 JUMP_LABEL (jump) = noadj_label;
18393 17807
18394 /* Adjust the ssp. */ 17808 /* Compute the numebr of frames to adjust. */
18395 reg_adj = gen_reg_rtx (Pmode); 17809 reg_adj = gen_lowpart (ptr_mode, reg_ssp);
18396 tmp = gen_rtx_SET (reg_adj, 17810 tmp = gen_rtx_SET (reg_adj,
18397 gen_rtx_LSHIFTRT (Pmode, negate_rtx (Pmode, reg_minus), 17811 gen_rtx_LSHIFTRT (ptr_mode,
18398 GEN_INT (3))); 17812 negate_rtx (ptr_mode, reg_adj),
17813 GEN_INT ((word_mode == SImode)
17814 ? 2
17815 : 3)));
18399 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG)); 17816 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
18400 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob)); 17817 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
18401 emit_insn (tmp); 17818 emit_insn (tmp);
18402 emit_insn ((Pmode == SImode) 17819
18403 ? gen_incsspsi (reg_adj) 17820 /* Check if number of frames <= 255 so no loop is needed. */
18404 : gen_incsspdi (reg_adj)); 17821 tmp = gen_rtx_COMPARE (CCmode, reg_adj, GEN_INT (255));
18405 17822 flags = gen_rtx_REG (CCmode, FLAGS_REG);
18406 emit_label (label); 17823 emit_insn (gen_rtx_SET (flags, tmp));
18407 LABEL_NUSES (label) = 1; 17824
17825 inc_label = gen_label_rtx ();
17826 tmp = gen_rtx_LEU (VOIDmode, flags, const0_rtx);
17827 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
17828 gen_rtx_LABEL_REF (VOIDmode, inc_label),
17829 pc_rtx);
17830 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
17831 JUMP_LABEL (jump) = inc_label;
17832
17833 rtx reg_255 = gen_reg_rtx (word_mode);
17834 emit_move_insn (reg_255, GEN_INT (255));
17835
17836 /* Adjust the ssp in a loop. */
17837 loop_label = gen_label_rtx ();
17838 emit_label (loop_label);
17839 LABEL_NUSES (loop_label) = 1;
17840
17841 emit_insn ((word_mode == SImode)
17842 ? gen_incsspsi (reg_255)
17843 : gen_incsspdi (reg_255));
17844 tmp = gen_rtx_SET (reg_adj, gen_rtx_MINUS (ptr_mode,
17845 reg_adj,
17846 GEN_INT (255)));
17847 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
17848 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
17849 emit_insn (tmp);
17850
17851 tmp = gen_rtx_COMPARE (CCmode, reg_adj, GEN_INT (255));
17852 flags = gen_rtx_REG (CCmode, FLAGS_REG);
17853 emit_insn (gen_rtx_SET (flags, tmp));
17854
17855 /* Jump to the loop label. */
17856 tmp = gen_rtx_GTU (VOIDmode, flags, const0_rtx);
17857 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
17858 gen_rtx_LABEL_REF (VOIDmode, loop_label),
17859 pc_rtx);
17860 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
17861 JUMP_LABEL (jump) = loop_label;
17862
17863 emit_label (inc_label);
17864 LABEL_NUSES (inc_label) = 1;
17865 emit_insn ((word_mode == SImode)
17866 ? gen_incsspsi (reg_ssp)
17867 : gen_incsspdi (reg_ssp));
17868
17869 emit_label (noadj_label);
17870 LABEL_NUSES (noadj_label) = 1;
18408 } 17871 }
18409 17872 else
18410 /* This code is the same as in expand_buildin_longjmp. */ 17873 stack_slot = adjust_address (operands[1], Pmode, 0);
18411 fp = gen_rtx_MEM (Pmode, operands[0]); 17874 emit_move_insn (operands[0], stack_slot);
18412 lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 17875 DONE;
18413 GET_MODE_SIZE (Pmode)));
18414 stack = gen_rtx_MEM (sa_mode, plus_constant (Pmode, operands[0],
18415 2 * GET_MODE_SIZE (Pmode)));
18416 lab = copy_to_reg (lab);
18417
18418 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
18419 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
18420
18421 emit_move_insn (hard_frame_pointer_rtx, fp);
18422 emit_stack_restore (SAVE_NONLOCAL, stack);
18423
18424 emit_use (hard_frame_pointer_rtx);
18425 emit_use (stack_pointer_rtx);
18426 emit_indirect_jump (lab);
18427 }) 17876 })
18428 17877
18429 17878
18430 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode. 17879 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
18431 ;; Do not split instructions with mask registers. 17880 ;; Do not split instructions with mask registers.
18853 = gen_rtx_COMPARE (GET_MODE (operands[4]), 18302 = gen_rtx_COMPARE (GET_MODE (operands[4]),
18854 copy_rtx (operands[5]), 18303 copy_rtx (operands[5]),
18855 const0_rtx); 18304 const0_rtx);
18856 }) 18305 })
18857 18306
18307 ;; Likewise for cmpelim optimized pattern.
18308 (define_peephole2
18309 [(set (match_operand:SWI 0 "register_operand")
18310 (match_operand:SWI 1 "memory_operand"))
18311 (parallel [(set (reg FLAGS_REG)
18312 (compare (match_operator:SWI 3 "plusminuslogic_operator"
18313 [(match_dup 0)
18314 (match_operand:SWI 2 "<nonmemory_operand>")])
18315 (const_int 0)))
18316 (set (match_dup 0) (match_dup 3))])
18317 (set (match_dup 1) (match_dup 0))]
18318 "(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
18319 && peep2_reg_dead_p (3, operands[0])
18320 && !reg_overlap_mentioned_p (operands[0], operands[1])
18321 && !reg_overlap_mentioned_p (operands[0], operands[2])
18322 && ix86_match_ccmode (peep2_next_insn (1),
18323 (GET_CODE (operands[3]) == PLUS
18324 || GET_CODE (operands[3]) == MINUS)
18325 ? CCGOCmode : CCNOmode)"
18326 [(parallel [(set (match_dup 4) (match_dup 6))
18327 (set (match_dup 1) (match_dup 5))])]
18328 {
18329 operands[4] = SET_DEST (XVECEXP (PATTERN (peep2_next_insn (1)), 0, 0));
18330 operands[5]
18331 = gen_rtx_fmt_ee (GET_CODE (operands[3]), GET_MODE (operands[3]),
18332 copy_rtx (operands[1]), operands[2]);
18333 operands[6]
18334 = gen_rtx_COMPARE (GET_MODE (operands[4]), copy_rtx (operands[5]),
18335 const0_rtx);
18336 })
18337
18858 ;; Likewise for instances where we have a lea pattern. 18338 ;; Likewise for instances where we have a lea pattern.
18859 (define_peephole2 18339 (define_peephole2
18860 [(set (match_operand:SWI 0 "register_operand") 18340 [(set (match_operand:SWI 0 "register_operand")
18861 (match_operand:SWI 1 "memory_operand")) 18341 (match_operand:SWI 1 "memory_operand"))
18862 (set (match_operand:SWI 3 "register_operand") 18342 (set (match_operand:SWI 3 "register_operand")
18896 (match_operand:SWI 1 "memory_operand")])) 18376 (match_operand:SWI 1 "memory_operand")]))
18897 (clobber (reg:CC FLAGS_REG))]) 18377 (clobber (reg:CC FLAGS_REG))])
18898 (set (match_dup 1) (match_dup 0)) 18378 (set (match_dup 1) (match_dup 0))
18899 (set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))] 18379 (set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))]
18900 "(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ()) 18380 "(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
18901 && GET_CODE (operands[2]) != MINUS 18381 && COMMUTATIVE_ARITH_P (operands[2])
18902 && peep2_reg_dead_p (3, operands[0]) 18382 && peep2_reg_dead_p (3, operands[0])
18903 && !reg_overlap_mentioned_p (operands[0], operands[1]) 18383 && !reg_overlap_mentioned_p (operands[0], operands[1])
18904 && ix86_match_ccmode (peep2_next_insn (2), 18384 && ix86_match_ccmode (peep2_next_insn (2),
18905 GET_CODE (operands[2]) == PLUS 18385 GET_CODE (operands[2]) == PLUS
18906 ? CCGOCmode : CCNOmode)" 18386 ? CCGOCmode : CCNOmode)"
18913 copy_rtx (operands[1]), 18393 copy_rtx (operands[1]),
18914 operands[0]); 18394 operands[0]);
18915 operands[5] 18395 operands[5]
18916 = gen_rtx_COMPARE (GET_MODE (operands[3]), 18396 = gen_rtx_COMPARE (GET_MODE (operands[3]),
18917 copy_rtx (operands[4]), 18397 copy_rtx (operands[4]),
18398 const0_rtx);
18399 })
18400
18401 ;; Likewise for cmpelim optimized pattern.
18402 (define_peephole2
18403 [(parallel [(set (reg FLAGS_REG)
18404 (compare (match_operator:SWI 2 "plusminuslogic_operator"
18405 [(match_operand:SWI 0 "register_operand")
18406 (match_operand:SWI 1 "memory_operand")])
18407 (const_int 0)))
18408 (set (match_dup 0) (match_dup 2))])
18409 (set (match_dup 1) (match_dup 0))]
18410 "(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
18411 && COMMUTATIVE_ARITH_P (operands[2])
18412 && peep2_reg_dead_p (2, operands[0])
18413 && !reg_overlap_mentioned_p (operands[0], operands[1])
18414 && ix86_match_ccmode (peep2_next_insn (0),
18415 GET_CODE (operands[2]) == PLUS
18416 ? CCGOCmode : CCNOmode)"
18417 [(parallel [(set (match_dup 3) (match_dup 5))
18418 (set (match_dup 1) (match_dup 4))])]
18419 {
18420 operands[3] = SET_DEST (XVECEXP (PATTERN (peep2_next_insn (0)), 0, 0));
18421 operands[4]
18422 = gen_rtx_fmt_ee (GET_CODE (operands[2]), GET_MODE (operands[2]),
18423 copy_rtx (operands[1]), operands[0]);
18424 operands[5]
18425 = gen_rtx_COMPARE (GET_MODE (operands[3]), copy_rtx (operands[4]),
18918 const0_rtx); 18426 const0_rtx);
18919 }) 18427 })
18920 18428
18921 (define_peephole2 18429 (define_peephole2
18922 [(set (match_operand:SWI12 0 "register_operand") 18430 [(set (match_operand:SWI12 0 "register_operand")
19834 ; Clobber all floating-point registers on environment save and restore 19342 ; Clobber all floating-point registers on environment save and restore
19835 ; to ensure that the TOS value saved at fnstenv is valid after fldenv. 19343 ; to ensure that the TOS value saved at fnstenv is valid after fldenv.
19836 (define_insn "fnstenv" 19344 (define_insn "fnstenv"
19837 [(set (match_operand:BLK 0 "memory_operand" "=m") 19345 [(set (match_operand:BLK 0 "memory_operand" "=m")
19838 (unspec_volatile:BLK [(const_int 0)] UNSPECV_FNSTENV)) 19346 (unspec_volatile:BLK [(const_int 0)] UNSPECV_FNSTENV))
19839 (clobber (reg:HI FPCR_REG))
19840 (clobber (reg:XF ST0_REG)) 19347 (clobber (reg:XF ST0_REG))
19841 (clobber (reg:XF ST1_REG)) 19348 (clobber (reg:XF ST1_REG))
19842 (clobber (reg:XF ST2_REG)) 19349 (clobber (reg:XF ST2_REG))
19843 (clobber (reg:XF ST3_REG)) 19350 (clobber (reg:XF ST3_REG))
19844 (clobber (reg:XF ST4_REG)) 19351 (clobber (reg:XF ST4_REG))
19853 (symbol_ref "ix86_attr_length_address_default (insn) + 2"))]) 19360 (symbol_ref "ix86_attr_length_address_default (insn) + 2"))])
19854 19361
19855 (define_insn "fldenv" 19362 (define_insn "fldenv"
19856 [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")] 19363 [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")]
19857 UNSPECV_FLDENV) 19364 UNSPECV_FLDENV)
19858 (clobber (reg:CCFP FPSR_REG))
19859 (clobber (reg:HI FPCR_REG))
19860 (clobber (reg:XF ST0_REG)) 19365 (clobber (reg:XF ST0_REG))
19861 (clobber (reg:XF ST1_REG)) 19366 (clobber (reg:XF ST1_REG))
19862 (clobber (reg:XF ST2_REG)) 19367 (clobber (reg:XF ST2_REG))
19863 (clobber (reg:XF ST3_REG)) 19368 (clobber (reg:XF ST3_REG))
19864 (clobber (reg:XF ST4_REG)) 19369 (clobber (reg:XF ST4_REG))
20048 (set_attr "memory" "unknown")]) 19553 (set_attr "memory" "unknown")])
20049 19554
20050 ;; CET instructions 19555 ;; CET instructions
20051 (define_insn "rdssp<mode>" 19556 (define_insn "rdssp<mode>"
20052 [(set (match_operand:SWI48x 0 "register_operand" "=r") 19557 [(set (match_operand:SWI48x 0 "register_operand" "=r")
20053 (unspec_volatile:SWI48x 19558 (unspec_volatile:SWI48x [(const_int 0)] UNSPECV_NOP_RDSSP))]
20054 [(match_operand:SWI48x 1 "register_operand" "0")] 19559 "TARGET_SHSTK || (flag_cf_protection & CF_RETURN)"
20055 UNSPECV_NOP_RDSSP))] 19560 "xor{l}\t%k0, %k0\n\trdssp<mskmodesuffix>\t%0"
20056 "TARGET_SHSTK" 19561 [(set_attr "length" "6")
20057 "rdssp<mskmodesuffix>\t%0"
20058 [(set_attr "length" "4")
20059 (set_attr "type" "other")]) 19562 (set_attr "type" "other")])
20060 19563
20061 (define_insn "incssp<mode>" 19564 (define_insn "incssp<mode>"
20062 [(unspec_volatile [(match_operand:SWI48x 0 "register_operand" "r")] 19565 [(unspec_volatile [(match_operand:SWI48x 0 "register_operand" "r")]
20063 UNSPECV_INCSSP)] 19566 UNSPECV_INCSSP)]
20064 "TARGET_SHSTK" 19567 "TARGET_SHSTK || (flag_cf_protection & CF_RETURN)"
20065 "incssp<mskmodesuffix>\t%0" 19568 "incssp<mskmodesuffix>\t%0"
20066 [(set_attr "length" "4") 19569 [(set_attr "length" "4")
20067 (set_attr "type" "other")]) 19570 (set_attr "type" "other")])
20068 19571
20069 (define_insn "saveprevssp" 19572 (define_insn "saveprevssp"
20071 "TARGET_SHSTK" 19574 "TARGET_SHSTK"
20072 "saveprevssp" 19575 "saveprevssp"
20073 [(set_attr "length" "5") 19576 [(set_attr "length" "5")
20074 (set_attr "type" "other")]) 19577 (set_attr "type" "other")])
20075 19578
20076 (define_insn "rstorssp" 19579 (define_expand "rstorssp"
20077 [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 19580 [(unspec_volatile [(match_operand 0 "memory_operand")]
20078 UNSPECV_RSTORSSP)] 19581 UNSPECV_RSTORSSP)]
19582 "TARGET_SHSTK")
19583
19584 (define_insn "*rstorssp<mode>"
19585 [(unspec_volatile [(match_operand:P 0 "memory_operand" "m")]
19586 UNSPECV_RSTORSSP)]
20079 "TARGET_SHSTK" 19587 "TARGET_SHSTK"
20080 "rstorssp\t%0" 19588 "rstorssp\t%0"
20081 [(set_attr "length" "5") 19589 [(set_attr "length" "5")
20082 (set_attr "type" "other")]) 19590 (set_attr "type" "other")])
20083 19591
20084 (define_insn "wrss<mode>" 19592 (define_insn "wrss<mode>"
20085 [(unspec_volatile [(match_operand:SWI48x 0 "register_operand" "r") 19593 [(unspec_volatile [(match_operand:SWI48x 0 "register_operand" "r")
20086 (match_operand:SWI48x 1 "memory_operand" "m")] 19594 (match_operand:SWI48x 1 "memory_operand" "m")]
20087 UNSPECV_WRSS)] 19595 UNSPECV_WRSS)]
20088 "TARGET_SHSTK" 19596 "TARGET_SHSTK"
20089 "wrss<mskmodesuffix>\t%0, %1" 19597 "wrss<mskmodesuffix>\t%0, %1"
20090 [(set_attr "length" "3") 19598 [(set_attr "length" "3")
20091 (set_attr "type" "other")]) 19599 (set_attr "type" "other")])
20092 19600
20093 (define_insn "wruss<mode>" 19601 (define_insn "wruss<mode>"
20094 [(unspec_volatile [(match_operand:SWI48x 0 "register_operand" "r") 19602 [(unspec_volatile [(match_operand:SWI48x 0 "register_operand" "r")
20095 (match_operand:SWI48x 1 "memory_operand" "m")] 19603 (match_operand:SWI48x 1 "memory_operand" "m")]
20096 UNSPECV_WRUSS)] 19604 UNSPECV_WRUSS)]
20097 "TARGET_SHSTK" 19605 "TARGET_SHSTK"
20098 "wruss<mskmodesuffix>\t%0, %1" 19606 "wruss<mskmodesuffix>\t%0, %1"
20099 [(set_attr "length" "4") 19607 [(set_attr "length" "4")
20100 (set_attr "type" "other")]) 19608 (set_attr "type" "other")])
20101 19609
20104 "TARGET_SHSTK" 19612 "TARGET_SHSTK"
20105 "setssbsy" 19613 "setssbsy"
20106 [(set_attr "length" "4") 19614 [(set_attr "length" "4")
20107 (set_attr "type" "other")]) 19615 (set_attr "type" "other")])
20108 19616
20109 (define_insn "clrssbsy" 19617 (define_expand "clrssbsy"
20110 [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 19618 [(unspec_volatile [(match_operand 0 "memory_operand")]
20111 UNSPECV_CLRSSBSY)] 19619 UNSPECV_CLRSSBSY)]
19620 "TARGET_SHSTK")
19621
19622 (define_insn "*clrssbsy<mode>"
19623 [(unspec_volatile [(match_operand:P 0 "memory_operand" "m")]
19624 UNSPECV_CLRSSBSY)]
20112 "TARGET_SHSTK" 19625 "TARGET_SHSTK"
20113 "clrssbsy\t%0" 19626 "clrssbsy\t%0"
20114 [(set_attr "length" "4") 19627 [(set_attr "length" "4")
20115 (set_attr "type" "other")]) 19628 (set_attr "type" "other")])
20116 19629
20117 (define_insn "nop_endbr" 19630 (define_insn "nop_endbr"
20118 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_ENDBR)] 19631 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_ENDBR)]
20119 "TARGET_IBT" 19632 "(flag_cf_protection & CF_BRANCH)"
20120 "* 19633 {
20121 { return (TARGET_64BIT)? \"endbr64\" : \"endbr32\"; }" 19634 return TARGET_64BIT ? "endbr64" : "endbr32";
19635 }
20122 [(set_attr "length" "4") 19636 [(set_attr "length" "4")
20123 (set_attr "length_immediate" "0") 19637 (set_attr "length_immediate" "0")
20124 (set_attr "modrm" "0")]) 19638 (set_attr "modrm" "0")])
20125 19639
20126 ;; For RTM support 19640 ;; For RTM support
20245 "TARGET_CLZERO" 19759 "TARGET_CLZERO"
20246 "clzero" 19760 "clzero"
20247 [(set_attr "length" "3") 19761 [(set_attr "length" "3")
20248 (set_attr "memory" "unknown")]) 19762 (set_attr "memory" "unknown")])
20249 19763
20250 ;; MPX instructions
20251
20252 (define_expand "<mode>_mk"
20253 [(set (match_operand:BND 0 "register_operand")
20254 (unspec:BND
20255 [(mem:<bnd_ptr>
20256 (match_par_dup 3
20257 [(match_operand:<bnd_ptr> 1 "register_operand")
20258 (match_operand:<bnd_ptr> 2 "address_mpx_no_base_operand")]))]
20259 UNSPEC_BNDMK))]
20260 "TARGET_MPX"
20261 {
20262 operands[3] = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[1],
20263 operands[2]),
20264 UNSPEC_BNDMK_ADDR);
20265 })
20266
20267 (define_insn "*<mode>_mk"
20268 [(set (match_operand:BND 0 "register_operand" "=w")
20269 (unspec:BND
20270 [(match_operator:<bnd_ptr> 3 "bnd_mem_operator"
20271 [(unspec:<bnd_ptr>
20272 [(match_operand:<bnd_ptr> 1 "register_operand" "r")
20273 (match_operand:<bnd_ptr> 2 "address_mpx_no_base_operand" "Tb")]
20274 UNSPEC_BNDMK_ADDR)])]
20275 UNSPEC_BNDMK))]
20276 "TARGET_MPX"
20277 "bndmk\t{%3, %0|%0, %3}"
20278 [(set_attr "type" "mpxmk")])
20279
20280 (define_expand "mov<mode>"
20281 [(set (match_operand:BND 0 "general_operand")
20282 (match_operand:BND 1 "general_operand"))]
20283 "TARGET_MPX"
20284 "ix86_expand_move (<MODE>mode, operands); DONE;")
20285
20286 (define_insn "*mov<mode>_internal_mpx"
20287 [(set (match_operand:BND 0 "nonimmediate_operand" "=w,m")
20288 (match_operand:BND 1 "general_operand" "wm,w"))]
20289 "TARGET_MPX"
20290 "bndmov\t{%1, %0|%0, %1}"
20291 [(set_attr "type" "mpxmov")])
20292
20293 (define_expand "<mode>_<bndcheck>"
20294 [(parallel
20295 [(unspec
20296 [(match_operand:BND 0 "register_operand")
20297 (match_operand:<bnd_ptr> 1 "address_no_seg_operand")] BNDCHECK)
20298 (set (match_dup 2)
20299 (unspec:BLK [(match_dup 2)] UNSPEC_MPX_FENCE))])]
20300 "TARGET_MPX"
20301 {
20302 operands[2] = gen_rtx_MEM (BLKmode, operands[1]);
20303 MEM_VOLATILE_P (operands[2]) = 1;
20304 })
20305
20306 (define_insn "*<mode>_<bndcheck>"
20307 [(unspec
20308 [(match_operand:BND 0 "register_operand" "w")
20309 (match_operand:<bnd_ptr> 1 "address_no_seg_operand" "Ts")] BNDCHECK)
20310 (set (match_operand:BLK 2 "bnd_mem_operator")
20311 (unspec:BLK [(match_dup 2)] UNSPEC_MPX_FENCE))]
20312 "TARGET_MPX"
20313 "bnd<bndcheck>\t{%a1, %0|%0, %a1}"
20314 [(set_attr "type" "mpxchk")])
20315
20316 (define_expand "<mode>_ldx"
20317 [(parallel
20318 [(set (match_operand:BND 0 "register_operand")
20319 (unspec:BND
20320 [(mem:<bnd_ptr>
20321 (match_par_dup 3
20322 [(match_operand:<bnd_ptr> 1 "address_mpx_no_index_operand")
20323 (match_operand:<bnd_ptr> 2 "register_operand")]))]
20324 UNSPEC_BNDLDX))
20325 (use (mem:BLK (match_dup 1)))])]
20326 "TARGET_MPX"
20327 {
20328 /* Avoid registers which cannot be used as index. */
20329 if (!index_register_operand (operands[2], Pmode))
20330 operands[2] = copy_addr_to_reg (operands[2]);
20331
20332 operands[3] = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[1],
20333 operands[2]),
20334 UNSPEC_BNDLDX_ADDR);
20335 })
20336
20337 (define_insn "*<mode>_ldx"
20338 [(set (match_operand:BND 0 "register_operand" "=w")
20339 (unspec:BND
20340 [(match_operator:<bnd_ptr> 3 "bnd_mem_operator"
20341 [(unspec:<bnd_ptr>
20342 [(match_operand:<bnd_ptr> 1 "address_mpx_no_index_operand" "Ti")
20343 (match_operand:<bnd_ptr> 2 "register_operand" "l")]
20344 UNSPEC_BNDLDX_ADDR)])]
20345 UNSPEC_BNDLDX))
20346 (use (mem:BLK (match_dup 1)))]
20347 "TARGET_MPX"
20348 "bndldx\t{%3, %0|%0, %3}"
20349 [(set_attr "type" "mpxld")])
20350
20351 (define_expand "<mode>_stx"
20352 [(parallel
20353 [(unspec
20354 [(mem:<bnd_ptr>
20355 (match_par_dup 3
20356 [(match_operand:<bnd_ptr> 0 "address_mpx_no_index_operand")
20357 (match_operand:<bnd_ptr> 1 "register_operand")]))
20358 (match_operand:BND 2 "register_operand")]
20359 UNSPEC_BNDSTX)
20360 (set (match_dup 4)
20361 (unspec:BLK [(match_dup 4)] UNSPEC_MPX_FENCE))])]
20362 "TARGET_MPX"
20363 {
20364 /* Avoid registers which cannot be used as index. */
20365 if (!index_register_operand (operands[1], Pmode))
20366 operands[1] = copy_addr_to_reg (operands[1]);
20367
20368 operands[3] = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[0],
20369 operands[1]),
20370 UNSPEC_BNDLDX_ADDR);
20371 operands[4] = gen_rtx_MEM (BLKmode, operands[0]);
20372 MEM_VOLATILE_P (operands[4]) = 1;
20373 })
20374
20375 (define_insn "*<mode>_stx"
20376 [(unspec
20377 [(match_operator:<bnd_ptr> 3 "bnd_mem_operator"
20378 [(unspec:<bnd_ptr>
20379 [(match_operand:<bnd_ptr> 0 "address_mpx_no_index_operand" "Ti")
20380 (match_operand:<bnd_ptr> 1 "register_operand" "l")]
20381 UNSPEC_BNDLDX_ADDR)])
20382 (match_operand:BND 2 "register_operand" "w")]
20383 UNSPEC_BNDSTX)
20384 (set (match_operand:BLK 4 "bnd_mem_operator")
20385 (unspec:BLK [(match_dup 4)] UNSPEC_MPX_FENCE))]
20386 "TARGET_MPX"
20387 "bndstx\t{%2, %3|%3, %2}"
20388 [(set_attr "type" "mpxst")])
20389
20390 (define_insn "move_size_reloc_<mode>"
20391 [(set (match_operand:SWI48 0 "register_operand" "=r")
20392 (unspec:SWI48
20393 [(match_operand:SWI48 1 "symbol_operand")]
20394 UNSPEC_SIZEOF))]
20395 "TARGET_MPX"
20396 {
20397 if (x86_64_immediate_size_operand (operands[1], VOIDmode))
20398 return "mov{l}\t{%1@SIZE, %k0|%k0, %1@SIZE}";
20399 else
20400 return "movabs{q}\t{%1@SIZE, %0|%0, %1@SIZE}";
20401 }
20402 [(set_attr "type" "imov")
20403 (set_attr "mode" "<MODE>")])
20404
20405 ;; RDPKRU and WRPKRU 19764 ;; RDPKRU and WRPKRU
20406 19765
20407 (define_expand "rdpkru" 19766 (define_expand "rdpkru"
20408 [(parallel 19767 [(parallel
20409 [(set (match_operand:SI 0 "register_operand") 19768 [(set (match_operand:SI 0 "register_operand")
20445 [(set_attr "type" "other")]) 19804 [(set_attr "type" "other")])
20446 19805
20447 (define_insn "rdpid" 19806 (define_insn "rdpid"
20448 [(set (match_operand:SI 0 "register_operand" "=r") 19807 [(set (match_operand:SI 0 "register_operand" "=r")
20449 (unspec_volatile:SI [(const_int 0)] UNSPECV_RDPID))] 19808 (unspec_volatile:SI [(const_int 0)] UNSPECV_RDPID))]
20450 "TARGET_RDPID" 19809 "!TARGET_64BIT && TARGET_RDPID"
20451 "rdpid\t%0" 19810 "rdpid\t%0"
20452 [(set_attr "type" "other")]) 19811 [(set_attr "type" "other")])
19812
19813 (define_insn "rdpid_rex64"
19814 [(set (match_operand:DI 0 "register_operand" "=r")
19815 (unspec_volatile:DI [(const_int 0)] UNSPECV_RDPID))]
19816 "TARGET_64BIT && TARGET_RDPID"
19817 "rdpid\t%0"
19818 [(set_attr "type" "other")])
19819
19820 ;; Intirinsics for > i486
19821
19822 (define_insn "wbinvd"
19823 [(unspec_volatile [(const_int 0)] UNSPECV_WBINVD)]
19824 ""
19825 "wbinvd"
19826 [(set_attr "type" "other")])
19827
19828 (define_insn "wbnoinvd"
19829 [(unspec_volatile [(const_int 0)] UNSPECV_WBNOINVD)]
19830 "TARGET_WBNOINVD"
19831 "wbnoinvd"
19832 [(set_attr "type" "other")])
19833
19834 ;; MOVDIRI and MOVDIR64B
19835
19836 (define_insn "movdiri<mode>"
19837 [(unspec_volatile:SWI48 [(match_operand:SWI48 0 "memory_operand" "m")
19838 (match_operand:SWI48 1 "register_operand" "r")]
19839 UNSPECV_MOVDIRI)]
19840 "TARGET_MOVDIRI"
19841 "movdiri\t{%1, %0|%0, %1}"
19842 [(set_attr "type" "other")])
19843
19844 (define_insn "movdir64b_<mode>"
19845 [(unspec_volatile:XI [(match_operand:P 0 "register_operand" "r")
19846 (match_operand:XI 1 "memory_operand")]
19847 UNSPECV_MOVDIR64B)]
19848 "TARGET_MOVDIR64B"
19849 "movdir64b\t{%1, %0|%0, %1}"
19850 [(set_attr "type" "other")])
19851
19852 ;; WAITPKG
19853
19854 (define_insn "umwait"
19855 [(set (reg:CCC FLAGS_REG)
19856 (unspec_volatile:CCC [(match_operand:SI 0 "register_operand" "r")
19857 (match_operand:DI 1 "register_operand" "A")]
19858 UNSPECV_UMWAIT))]
19859 "!TARGET_64BIT && TARGET_WAITPKG"
19860 "umwait\t%0"
19861 [(set_attr "length" "3")])
19862
19863 (define_insn "umwait_rex64"
19864 [(set (reg:CCC FLAGS_REG)
19865 (unspec_volatile:CCC [(match_operand:SI 0 "register_operand" "r")
19866 (match_operand:SI 1 "register_operand" "a")
19867 (match_operand:SI 2 "register_operand" "d")]
19868 UNSPECV_UMWAIT))]
19869 "TARGET_64BIT && TARGET_WAITPKG"
19870 "umwait\t%0"
19871 [(set_attr "length" "3")])
19872
19873 (define_insn "umonitor_<mode>"
19874 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
19875 UNSPECV_UMONITOR)]
19876 "TARGET_WAITPKG"
19877 "umonitor\t%0"
19878 [(set (attr "length")
19879 (symbol_ref ("(Pmode != word_mode) + 3")))])
19880
19881 (define_insn "tpause"
19882 [(set (reg:CCC FLAGS_REG)
19883 (unspec_volatile:CCC [(match_operand:SI 0 "register_operand" "r")
19884 (match_operand:DI 1 "register_operand" "A")]
19885 UNSPECV_TPAUSE))]
19886 "!TARGET_64BIT && TARGET_WAITPKG"
19887 "tpause\t%0"
19888 [(set_attr "length" "3")])
19889
19890 (define_insn "tpause_rex64"
19891 [(set (reg:CCC FLAGS_REG)
19892 (unspec_volatile:CCC [(match_operand:SI 0 "register_operand" "r")
19893 (match_operand:SI 1 "register_operand" "a")
19894 (match_operand:SI 2 "register_operand" "d")]
19895 UNSPECV_TPAUSE))]
19896 "TARGET_64BIT && TARGET_WAITPKG"
19897 "tpause\t%0"
19898 [(set_attr "length" "3")])
19899
19900 (define_insn "cldemote"
19901 [(unspec_volatile[(match_operand 0 "address_operand" "p")]
19902 UNSPECV_CLDEMOTE)]
19903 "TARGET_CLDEMOTE"
19904 "cldemote\t%a0"
19905 [(set_attr "type" "other")
19906 (set_attr "memory" "unknown")])
19907
19908 (define_insn "speculation_barrier"
19909 [(unspec_volatile [(const_int 0)] UNSPECV_SPECULATION_BARRIER)]
19910 ""
19911 "lfence"
19912 [(set_attr "type" "other")
19913 (set_attr "length" "3")])
20453 19914
20454 (include "mmx.md") 19915 (include "mmx.md")
20455 (include "sse.md") 19916 (include "sse.md")
20456 (include "sync.md") 19917 (include "sync.md")