Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/arm/cortex-a8-neon.md @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | a06113de4d67 |
| children | 04ced10e8804 |
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| 65:65488c3d617d | 67:f6334be47118 |
|---|---|
| 1 ;; ARM Cortex-A8 NEON scheduling description. | 1 ;; ARM Cortex-A8 NEON scheduling description. |
| 2 ;; Copyright (C) 2007, 2008 Free Software Foundation, Inc. | 2 ;; Copyright (C) 2007, 2008, 2010 Free Software Foundation, Inc. |
| 3 ;; Contributed by CodeSourcery. | 3 ;; Contributed by CodeSourcery. |
| 4 | 4 |
| 5 ;; This file is part of GCC. | 5 ;; This file is part of GCC. |
| 6 | 6 |
| 7 ;; GCC is free software; you can redistribute it and/or modify it | 7 ;; GCC is free software; you can redistribute it and/or modify it |
| 180 (eq_attr "type" "f_cvt")) | 180 (eq_attr "type" "f_cvt")) |
| 181 "cortex_a8_vfp,cortex_a8_vfplite*6") | 181 "cortex_a8_vfp,cortex_a8_vfplite*6") |
| 182 | 182 |
| 183 ;; NEON -> core transfers. | 183 ;; NEON -> core transfers. |
| 184 | 184 |
| 185 (define_insn_reservation "neon_mrc" 20 | 185 (define_insn_reservation "cortex_a8_neon_mrc" 20 |
| 186 (and (eq_attr "tune" "cortexa8") | 186 (and (eq_attr "tune" "cortexa8") |
| 187 (eq_attr "neon_type" "neon_mrc")) | 187 (eq_attr "neon_type" "neon_mrc")) |
| 188 "cortex_a8_neon_ls") | 188 "cortex_a8_neon_ls") |
| 189 | 189 |
| 190 (define_insn_reservation "neon_mrrc" 21 | 190 (define_insn_reservation "cortex_a8_neon_mrrc" 21 |
| 191 (and (eq_attr "tune" "cortexa8") | 191 (and (eq_attr "tune" "cortexa8") |
| 192 (eq_attr "neon_type" "neon_mrrc")) | 192 (eq_attr "neon_type" "neon_mrrc")) |
| 193 "cortex_a8_neon_ls_2") | 193 "cortex_a8_neon_ls_2") |
| 194 | 194 |
| 195 ;; The remainder of this file is auto-generated by neon-schedgen. | 195 ;; The remainder of this file is auto-generated by neon-schedgen. |
| 196 | 196 |
| 197 ;; Instructions using this reservation read their source operands at N2, and | 197 ;; Instructions using this reservation read their source operands at N2, and |
| 198 ;; produce a result at N3. | 198 ;; produce a result at N3. |
| 199 (define_insn_reservation "neon_int_1" 3 | 199 (define_insn_reservation "cortex_a8_neon_int_1" 3 |
| 200 (and (eq_attr "tune" "cortexa8") | 200 (and (eq_attr "tune" "cortexa8") |
| 201 (eq_attr "neon_type" "neon_int_1")) | 201 (eq_attr "neon_type" "neon_int_1")) |
| 202 "cortex_a8_neon_dp") | 202 "cortex_a8_neon_dp") |
| 203 | 203 |
| 204 ;; Instructions using this reservation read their (D|Q)m operands at N1, | 204 ;; Instructions using this reservation read their (D|Q)m operands at N1, |
| 205 ;; their (D|Q)n operands at N2, and produce a result at N3. | 205 ;; their (D|Q)n operands at N2, and produce a result at N3. |
| 206 (define_insn_reservation "neon_int_2" 3 | 206 (define_insn_reservation "cortex_a8_neon_int_2" 3 |
| 207 (and (eq_attr "tune" "cortexa8") | 207 (and (eq_attr "tune" "cortexa8") |
| 208 (eq_attr "neon_type" "neon_int_2")) | 208 (eq_attr "neon_type" "neon_int_2")) |
| 209 "cortex_a8_neon_dp") | 209 "cortex_a8_neon_dp") |
| 210 | 210 |
| 211 ;; Instructions using this reservation read their source operands at N1, and | 211 ;; Instructions using this reservation read their source operands at N1, and |
| 212 ;; produce a result at N3. | 212 ;; produce a result at N3. |
| 213 (define_insn_reservation "neon_int_3" 3 | 213 (define_insn_reservation "cortex_a8_neon_int_3" 3 |
| 214 (and (eq_attr "tune" "cortexa8") | 214 (and (eq_attr "tune" "cortexa8") |
| 215 (eq_attr "neon_type" "neon_int_3")) | 215 (eq_attr "neon_type" "neon_int_3")) |
| 216 "cortex_a8_neon_dp") | 216 "cortex_a8_neon_dp") |
| 217 | 217 |
| 218 ;; Instructions using this reservation read their source operands at N2, and | 218 ;; Instructions using this reservation read their source operands at N2, and |
| 219 ;; produce a result at N4. | 219 ;; produce a result at N4. |
| 220 (define_insn_reservation "neon_int_4" 4 | 220 (define_insn_reservation "cortex_a8_neon_int_4" 4 |
| 221 (and (eq_attr "tune" "cortexa8") | 221 (and (eq_attr "tune" "cortexa8") |
| 222 (eq_attr "neon_type" "neon_int_4")) | 222 (eq_attr "neon_type" "neon_int_4")) |
| 223 "cortex_a8_neon_dp") | 223 "cortex_a8_neon_dp") |
| 224 | 224 |
| 225 ;; Instructions using this reservation read their (D|Q)m operands at N1, | 225 ;; Instructions using this reservation read their (D|Q)m operands at N1, |
| 226 ;; their (D|Q)n operands at N2, and produce a result at N4. | 226 ;; their (D|Q)n operands at N2, and produce a result at N4. |
| 227 (define_insn_reservation "neon_int_5" 4 | 227 (define_insn_reservation "cortex_a8_neon_int_5" 4 |
| 228 (and (eq_attr "tune" "cortexa8") | 228 (and (eq_attr "tune" "cortexa8") |
| 229 (eq_attr "neon_type" "neon_int_5")) | 229 (eq_attr "neon_type" "neon_int_5")) |
| 230 "cortex_a8_neon_dp") | 230 "cortex_a8_neon_dp") |
| 231 | 231 |
| 232 ;; Instructions using this reservation read their source operands at N1, and | 232 ;; Instructions using this reservation read their source operands at N1, and |
| 233 ;; produce a result at N4. | 233 ;; produce a result at N4. |
| 234 (define_insn_reservation "neon_vqneg_vqabs" 4 | 234 (define_insn_reservation "cortex_a8_neon_vqneg_vqabs" 4 |
| 235 (and (eq_attr "tune" "cortexa8") | 235 (and (eq_attr "tune" "cortexa8") |
| 236 (eq_attr "neon_type" "neon_vqneg_vqabs")) | 236 (eq_attr "neon_type" "neon_vqneg_vqabs")) |
| 237 "cortex_a8_neon_dp") | 237 "cortex_a8_neon_dp") |
| 238 | 238 |
| 239 ;; Instructions using this reservation produce a result at N3. | 239 ;; Instructions using this reservation produce a result at N3. |
| 240 (define_insn_reservation "neon_vmov" 3 | 240 (define_insn_reservation "cortex_a8_neon_vmov" 3 |
| 241 (and (eq_attr "tune" "cortexa8") | 241 (and (eq_attr "tune" "cortexa8") |
| 242 (eq_attr "neon_type" "neon_vmov")) | 242 (eq_attr "neon_type" "neon_vmov")) |
| 243 "cortex_a8_neon_dp") | 243 "cortex_a8_neon_dp") |
| 244 | 244 |
| 245 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 245 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 246 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | 246 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and |
| 247 ;; produce a result at N6. | 247 ;; produce a result at N6. |
| 248 (define_insn_reservation "neon_vaba" 6 | 248 (define_insn_reservation "cortex_a8_neon_vaba" 6 |
| 249 (and (eq_attr "tune" "cortexa8") | 249 (and (eq_attr "tune" "cortexa8") |
| 250 (eq_attr "neon_type" "neon_vaba")) | 250 (eq_attr "neon_type" "neon_vaba")) |
| 251 "cortex_a8_neon_dp") | 251 "cortex_a8_neon_dp") |
| 252 | 252 |
| 253 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 253 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 254 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | 254 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and |
| 255 ;; produce a result at N6 on cycle 2. | 255 ;; produce a result at N6 on cycle 2. |
| 256 (define_insn_reservation "neon_vaba_qqq" 7 | 256 (define_insn_reservation "cortex_a8_neon_vaba_qqq" 7 |
| 257 (and (eq_attr "tune" "cortexa8") | 257 (and (eq_attr "tune" "cortexa8") |
| 258 (eq_attr "neon_type" "neon_vaba_qqq")) | 258 (eq_attr "neon_type" "neon_vaba_qqq")) |
| 259 "cortex_a8_neon_dp_2") | 259 "cortex_a8_neon_dp_2") |
| 260 | 260 |
| 261 ;; Instructions using this reservation read their (D|Q)m operands at N1, | 261 ;; Instructions using this reservation read their (D|Q)m operands at N1, |
| 262 ;; their (D|Q)d operands at N3, and produce a result at N6. | 262 ;; their (D|Q)d operands at N3, and produce a result at N6. |
| 263 (define_insn_reservation "neon_vsma" 6 | 263 (define_insn_reservation "cortex_a8_neon_vsma" 6 |
| 264 (and (eq_attr "tune" "cortexa8") | 264 (and (eq_attr "tune" "cortexa8") |
| 265 (eq_attr "neon_type" "neon_vsma")) | 265 (eq_attr "neon_type" "neon_vsma")) |
| 266 "cortex_a8_neon_dp") | 266 "cortex_a8_neon_dp") |
| 267 | 267 |
| 268 ;; Instructions using this reservation read their source operands at N2, and | 268 ;; Instructions using this reservation read their source operands at N2, and |
| 269 ;; produce a result at N6. | 269 ;; produce a result at N6. |
| 270 (define_insn_reservation "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 | 270 (define_insn_reservation "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 |
| 271 (and (eq_attr "tune" "cortexa8") | 271 (and (eq_attr "tune" "cortexa8") |
| 272 (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) | 272 (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) |
| 273 "cortex_a8_neon_dp") | 273 "cortex_a8_neon_dp") |
| 274 | 274 |
| 275 ;; Instructions using this reservation read their source operands at N2, and | 275 ;; Instructions using this reservation read their source operands at N2, and |
| 276 ;; produce a result at N6 on cycle 2. | 276 ;; produce a result at N6 on cycle 2. |
| 277 (define_insn_reservation "neon_mul_qqq_8_16_32_ddd_32" 7 | 277 (define_insn_reservation "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" 7 |
| 278 (and (eq_attr "tune" "cortexa8") | 278 (and (eq_attr "tune" "cortexa8") |
| 279 (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) | 279 (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) |
| 280 "cortex_a8_neon_dp_2") | 280 "cortex_a8_neon_dp_2") |
| 281 | 281 |
| 282 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 282 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 283 ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2. | 283 ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2. |
| 284 (define_insn_reservation "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 | 284 (define_insn_reservation "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 |
| 285 (and (eq_attr "tune" "cortexa8") | 285 (and (eq_attr "tune" "cortexa8") |
| 286 (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) | 286 (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) |
| 287 "cortex_a8_neon_dp_2") | 287 "cortex_a8_neon_dp_2") |
| 288 | 288 |
| 289 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 289 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 290 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | 290 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and |
| 291 ;; produce a result at N6. | 291 ;; produce a result at N6. |
| 292 (define_insn_reservation "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 | 292 (define_insn_reservation "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 |
| 293 (and (eq_attr "tune" "cortexa8") | 293 (and (eq_attr "tune" "cortexa8") |
| 294 (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) | 294 (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) |
| 295 "cortex_a8_neon_dp") | 295 "cortex_a8_neon_dp") |
| 296 | 296 |
| 297 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 297 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 298 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | 298 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and |
| 299 ;; produce a result at N6 on cycle 2. | 299 ;; produce a result at N6 on cycle 2. |
| 300 (define_insn_reservation "neon_mla_qqq_8_16" 7 | 300 (define_insn_reservation "cortex_a8_neon_mla_qqq_8_16" 7 |
| 301 (and (eq_attr "tune" "cortexa8") | 301 (and (eq_attr "tune" "cortexa8") |
| 302 (eq_attr "neon_type" "neon_mla_qqq_8_16")) | 302 (eq_attr "neon_type" "neon_mla_qqq_8_16")) |
| 303 "cortex_a8_neon_dp_2") | 303 "cortex_a8_neon_dp_2") |
| 304 | 304 |
| 305 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 305 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 306 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | 306 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and |
| 307 ;; produce a result at N6 on cycle 2. | 307 ;; produce a result at N6 on cycle 2. |
| 308 (define_insn_reservation "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 | 308 (define_insn_reservation "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 |
| 309 (and (eq_attr "tune" "cortexa8") | 309 (and (eq_attr "tune" "cortexa8") |
| 310 (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) | 310 (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) |
| 311 "cortex_a8_neon_dp_2") | 311 "cortex_a8_neon_dp_2") |
| 312 | 312 |
| 313 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 313 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 314 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | 314 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and |
| 315 ;; produce a result at N6 on cycle 4. | 315 ;; produce a result at N6 on cycle 4. |
| 316 (define_insn_reservation "neon_mla_qqq_32_qqd_32_scalar" 9 | 316 (define_insn_reservation "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" 9 |
| 317 (and (eq_attr "tune" "cortexa8") | 317 (and (eq_attr "tune" "cortexa8") |
| 318 (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar")) | 318 (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar")) |
| 319 "cortex_a8_neon_dp_4") | 319 "cortex_a8_neon_dp_4") |
| 320 | 320 |
| 321 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 321 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 322 ;; their (D|Q)m operands at N1, and produce a result at N6. | 322 ;; their (D|Q)m operands at N1, and produce a result at N6. |
| 323 (define_insn_reservation "neon_mul_ddd_16_scalar_32_16_long_scalar" 6 | 323 (define_insn_reservation "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" 6 |
| 324 (and (eq_attr "tune" "cortexa8") | 324 (and (eq_attr "tune" "cortexa8") |
| 325 (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) | 325 (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) |
| 326 "cortex_a8_neon_dp") | 326 "cortex_a8_neon_dp") |
| 327 | 327 |
| 328 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 328 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 329 ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4. | 329 ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4. |
| 330 (define_insn_reservation "neon_mul_qqd_32_scalar" 9 | 330 (define_insn_reservation "cortex_a8_neon_mul_qqd_32_scalar" 9 |
| 331 (and (eq_attr "tune" "cortexa8") | 331 (and (eq_attr "tune" "cortexa8") |
| 332 (eq_attr "neon_type" "neon_mul_qqd_32_scalar")) | 332 (eq_attr "neon_type" "neon_mul_qqd_32_scalar")) |
| 333 "cortex_a8_neon_dp_4") | 333 "cortex_a8_neon_dp_4") |
| 334 | 334 |
| 335 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 335 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 336 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | 336 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and |
| 337 ;; produce a result at N6. | 337 ;; produce a result at N6. |
| 338 (define_insn_reservation "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 | 338 (define_insn_reservation "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 |
| 339 (and (eq_attr "tune" "cortexa8") | 339 (and (eq_attr "tune" "cortexa8") |
| 340 (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) | 340 (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) |
| 341 "cortex_a8_neon_dp") | 341 "cortex_a8_neon_dp") |
| 342 | 342 |
| 343 ;; Instructions using this reservation read their source operands at N1, and | 343 ;; Instructions using this reservation read their source operands at N1, and |
| 344 ;; produce a result at N3. | 344 ;; produce a result at N3. |
| 345 (define_insn_reservation "neon_shift_1" 3 | 345 (define_insn_reservation "cortex_a8_neon_shift_1" 3 |
| 346 (and (eq_attr "tune" "cortexa8") | 346 (and (eq_attr "tune" "cortexa8") |
| 347 (eq_attr "neon_type" "neon_shift_1")) | 347 (eq_attr "neon_type" "neon_shift_1")) |
| 348 "cortex_a8_neon_dp") | 348 "cortex_a8_neon_dp") |
| 349 | 349 |
| 350 ;; Instructions using this reservation read their source operands at N1, and | 350 ;; Instructions using this reservation read their source operands at N1, and |
| 351 ;; produce a result at N4. | 351 ;; produce a result at N4. |
| 352 (define_insn_reservation "neon_shift_2" 4 | 352 (define_insn_reservation "cortex_a8_neon_shift_2" 4 |
| 353 (and (eq_attr "tune" "cortexa8") | 353 (and (eq_attr "tune" "cortexa8") |
| 354 (eq_attr "neon_type" "neon_shift_2")) | 354 (eq_attr "neon_type" "neon_shift_2")) |
| 355 "cortex_a8_neon_dp") | 355 "cortex_a8_neon_dp") |
| 356 | 356 |
| 357 ;; Instructions using this reservation read their source operands at N1, and | 357 ;; Instructions using this reservation read their source operands at N1, and |
| 358 ;; produce a result at N3 on cycle 2. | 358 ;; produce a result at N3 on cycle 2. |
| 359 (define_insn_reservation "neon_shift_3" 4 | 359 (define_insn_reservation "cortex_a8_neon_shift_3" 4 |
| 360 (and (eq_attr "tune" "cortexa8") | 360 (and (eq_attr "tune" "cortexa8") |
| 361 (eq_attr "neon_type" "neon_shift_3")) | 361 (eq_attr "neon_type" "neon_shift_3")) |
| 362 "cortex_a8_neon_dp_2") | 362 "cortex_a8_neon_dp_2") |
| 363 | 363 |
| 364 ;; Instructions using this reservation read their source operands at N1, and | 364 ;; Instructions using this reservation read their source operands at N1, and |
| 365 ;; produce a result at N1. | 365 ;; produce a result at N1. |
| 366 (define_insn_reservation "neon_vshl_ddd" 1 | 366 (define_insn_reservation "cortex_a8_neon_vshl_ddd" 1 |
| 367 (and (eq_attr "tune" "cortexa8") | 367 (and (eq_attr "tune" "cortexa8") |
| 368 (eq_attr "neon_type" "neon_vshl_ddd")) | 368 (eq_attr "neon_type" "neon_vshl_ddd")) |
| 369 "cortex_a8_neon_dp") | 369 "cortex_a8_neon_dp") |
| 370 | 370 |
| 371 ;; Instructions using this reservation read their source operands at N1, and | 371 ;; Instructions using this reservation read their source operands at N1, and |
| 372 ;; produce a result at N4 on cycle 2. | 372 ;; produce a result at N4 on cycle 2. |
| 373 (define_insn_reservation "neon_vqshl_vrshl_vqrshl_qqq" 5 | 373 (define_insn_reservation "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" 5 |
| 374 (and (eq_attr "tune" "cortexa8") | 374 (and (eq_attr "tune" "cortexa8") |
| 375 (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq")) | 375 (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq")) |
| 376 "cortex_a8_neon_dp_2") | 376 "cortex_a8_neon_dp_2") |
| 377 | 377 |
| 378 ;; Instructions using this reservation read their (D|Q)m operands at N1, | 378 ;; Instructions using this reservation read their (D|Q)m operands at N1, |
| 379 ;; their (D|Q)d operands at N3, and produce a result at N6. | 379 ;; their (D|Q)d operands at N3, and produce a result at N6. |
| 380 (define_insn_reservation "neon_vsra_vrsra" 6 | 380 (define_insn_reservation "cortex_a8_neon_vsra_vrsra" 6 |
| 381 (and (eq_attr "tune" "cortexa8") | 381 (and (eq_attr "tune" "cortexa8") |
| 382 (eq_attr "neon_type" "neon_vsra_vrsra")) | 382 (eq_attr "neon_type" "neon_vsra_vrsra")) |
| 383 "cortex_a8_neon_dp") | 383 "cortex_a8_neon_dp") |
| 384 | 384 |
| 385 ;; Instructions using this reservation read their source operands at N2, and | 385 ;; Instructions using this reservation read their source operands at N2, and |
| 386 ;; produce a result at N5. | 386 ;; produce a result at N5. |
| 387 (define_insn_reservation "neon_fp_vadd_ddd_vabs_dd" 5 | 387 (define_insn_reservation "cortex_a8_neon_fp_vadd_ddd_vabs_dd" 5 |
| 388 (and (eq_attr "tune" "cortexa8") | 388 (and (eq_attr "tune" "cortexa8") |
| 389 (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")) | 389 (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")) |
| 390 "cortex_a8_neon_fadd") | 390 "cortex_a8_neon_fadd") |
| 391 | 391 |
| 392 ;; Instructions using this reservation read their source operands at N2, and | 392 ;; Instructions using this reservation read their source operands at N2, and |
| 393 ;; produce a result at N5 on cycle 2. | 393 ;; produce a result at N5 on cycle 2. |
| 394 (define_insn_reservation "neon_fp_vadd_qqq_vabs_qq" 6 | 394 (define_insn_reservation "cortex_a8_neon_fp_vadd_qqq_vabs_qq" 6 |
| 395 (and (eq_attr "tune" "cortexa8") | 395 (and (eq_attr "tune" "cortexa8") |
| 396 (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq")) | 396 (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq")) |
| 397 "cortex_a8_neon_fadd_2") | 397 "cortex_a8_neon_fadd_2") |
| 398 | 398 |
| 399 ;; Instructions using this reservation read their source operands at N1, and | 399 ;; Instructions using this reservation read their source operands at N1, and |
| 400 ;; produce a result at N5. | 400 ;; produce a result at N5. |
| 401 (define_insn_reservation "neon_fp_vsum" 5 | 401 (define_insn_reservation "cortex_a8_neon_fp_vsum" 5 |
| 402 (and (eq_attr "tune" "cortexa8") | 402 (and (eq_attr "tune" "cortexa8") |
| 403 (eq_attr "neon_type" "neon_fp_vsum")) | 403 (eq_attr "neon_type" "neon_fp_vsum")) |
| 404 "cortex_a8_neon_fadd") | 404 "cortex_a8_neon_fadd") |
| 405 | 405 |
| 406 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 406 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 407 ;; their (D|Q)m operands at N1, and produce a result at N5. | 407 ;; their (D|Q)m operands at N1, and produce a result at N5. |
| 408 (define_insn_reservation "neon_fp_vmul_ddd" 5 | 408 (define_insn_reservation "cortex_a8_neon_fp_vmul_ddd" 5 |
| 409 (and (eq_attr "tune" "cortexa8") | 409 (and (eq_attr "tune" "cortexa8") |
| 410 (eq_attr "neon_type" "neon_fp_vmul_ddd")) | 410 (eq_attr "neon_type" "neon_fp_vmul_ddd")) |
| 411 "cortex_a8_neon_dp") | 411 "cortex_a8_neon_dp") |
| 412 | 412 |
| 413 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 413 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 414 ;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2. | 414 ;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2. |
| 415 (define_insn_reservation "neon_fp_vmul_qqd" 6 | 415 (define_insn_reservation "cortex_a8_neon_fp_vmul_qqd" 6 |
| 416 (and (eq_attr "tune" "cortexa8") | 416 (and (eq_attr "tune" "cortexa8") |
| 417 (eq_attr "neon_type" "neon_fp_vmul_qqd")) | 417 (eq_attr "neon_type" "neon_fp_vmul_qqd")) |
| 418 "cortex_a8_neon_dp_2") | 418 "cortex_a8_neon_dp_2") |
| 419 | 419 |
| 420 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 420 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 421 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | 421 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and |
| 422 ;; produce a result at N9. | 422 ;; produce a result at N9. |
| 423 (define_insn_reservation "neon_fp_vmla_ddd" 9 | 423 (define_insn_reservation "cortex_a8_neon_fp_vmla_ddd" 9 |
| 424 (and (eq_attr "tune" "cortexa8") | 424 (and (eq_attr "tune" "cortexa8") |
| 425 (eq_attr "neon_type" "neon_fp_vmla_ddd")) | 425 (eq_attr "neon_type" "neon_fp_vmla_ddd")) |
| 426 "cortex_a8_neon_fmul_then_fadd") | 426 "cortex_a8_neon_fmul_then_fadd") |
| 427 | 427 |
| 428 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 428 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 429 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | 429 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and |
| 430 ;; produce a result at N9 on cycle 2. | 430 ;; produce a result at N9 on cycle 2. |
| 431 (define_insn_reservation "neon_fp_vmla_qqq" 10 | 431 (define_insn_reservation "cortex_a8_neon_fp_vmla_qqq" 10 |
| 432 (and (eq_attr "tune" "cortexa8") | 432 (and (eq_attr "tune" "cortexa8") |
| 433 (eq_attr "neon_type" "neon_fp_vmla_qqq")) | 433 (eq_attr "neon_type" "neon_fp_vmla_qqq")) |
| 434 "cortex_a8_neon_fmul_then_fadd_2") | 434 "cortex_a8_neon_fmul_then_fadd_2") |
| 435 | 435 |
| 436 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 436 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 437 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | 437 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and |
| 438 ;; produce a result at N9. | 438 ;; produce a result at N9. |
| 439 (define_insn_reservation "neon_fp_vmla_ddd_scalar" 9 | 439 (define_insn_reservation "cortex_a8_neon_fp_vmla_ddd_scalar" 9 |
| 440 (and (eq_attr "tune" "cortexa8") | 440 (and (eq_attr "tune" "cortexa8") |
| 441 (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar")) | 441 (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar")) |
| 442 "cortex_a8_neon_fmul_then_fadd") | 442 "cortex_a8_neon_fmul_then_fadd") |
| 443 | 443 |
| 444 ;; Instructions using this reservation read their (D|Q)n operands at N2, | 444 ;; Instructions using this reservation read their (D|Q)n operands at N2, |
| 445 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | 445 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and |
| 446 ;; produce a result at N9 on cycle 2. | 446 ;; produce a result at N9 on cycle 2. |
| 447 (define_insn_reservation "neon_fp_vmla_qqq_scalar" 10 | 447 (define_insn_reservation "cortex_a8_neon_fp_vmla_qqq_scalar" 10 |
| 448 (and (eq_attr "tune" "cortexa8") | 448 (and (eq_attr "tune" "cortexa8") |
| 449 (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar")) | 449 (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar")) |
| 450 "cortex_a8_neon_fmul_then_fadd_2") | 450 "cortex_a8_neon_fmul_then_fadd_2") |
| 451 | 451 |
| 452 ;; Instructions using this reservation read their source operands at N2, and | 452 ;; Instructions using this reservation read their source operands at N2, and |
| 453 ;; produce a result at N9. | 453 ;; produce a result at N9. |
| 454 (define_insn_reservation "neon_fp_vrecps_vrsqrts_ddd" 9 | 454 (define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" 9 |
| 455 (and (eq_attr "tune" "cortexa8") | 455 (and (eq_attr "tune" "cortexa8") |
| 456 (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd")) | 456 (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd")) |
| 457 "cortex_a8_neon_fmul_then_fadd") | 457 "cortex_a8_neon_fmul_then_fadd") |
| 458 | 458 |
| 459 ;; Instructions using this reservation read their source operands at N2, and | 459 ;; Instructions using this reservation read their source operands at N2, and |
| 460 ;; produce a result at N9 on cycle 2. | 460 ;; produce a result at N9 on cycle 2. |
| 461 (define_insn_reservation "neon_fp_vrecps_vrsqrts_qqq" 10 | 461 (define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" 10 |
| 462 (and (eq_attr "tune" "cortexa8") | 462 (and (eq_attr "tune" "cortexa8") |
| 463 (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq")) | 463 (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq")) |
| 464 "cortex_a8_neon_fmul_then_fadd_2") | 464 "cortex_a8_neon_fmul_then_fadd_2") |
| 465 | 465 |
| 466 ;; Instructions using this reservation read their source operands at N1, and | 466 ;; Instructions using this reservation read their source operands at N1, and |
| 467 ;; produce a result at N2. | 467 ;; produce a result at N2. |
| 468 (define_insn_reservation "neon_bp_simple" 2 | 468 (define_insn_reservation "cortex_a8_neon_bp_simple" 2 |
| 469 (and (eq_attr "tune" "cortexa8") | 469 (and (eq_attr "tune" "cortexa8") |
| 470 (eq_attr "neon_type" "neon_bp_simple")) | 470 (eq_attr "neon_type" "neon_bp_simple")) |
| 471 "cortex_a8_neon_perm") | 471 "cortex_a8_neon_perm") |
| 472 | 472 |
| 473 ;; Instructions using this reservation read their source operands at N1, and | 473 ;; Instructions using this reservation read their source operands at N1, and |
| 474 ;; produce a result at N2 on cycle 2. | 474 ;; produce a result at N2 on cycle 2. |
| 475 (define_insn_reservation "neon_bp_2cycle" 3 | 475 (define_insn_reservation "cortex_a8_neon_bp_2cycle" 3 |
| 476 (and (eq_attr "tune" "cortexa8") | 476 (and (eq_attr "tune" "cortexa8") |
| 477 (eq_attr "neon_type" "neon_bp_2cycle")) | 477 (eq_attr "neon_type" "neon_bp_2cycle")) |
| 478 "cortex_a8_neon_perm_2") | 478 "cortex_a8_neon_perm_2") |
| 479 | 479 |
| 480 ;; Instructions using this reservation read their source operands at N1, and | 480 ;; Instructions using this reservation read their source operands at N1, and |
| 481 ;; produce a result at N2 on cycle 3. | 481 ;; produce a result at N2 on cycle 3. |
| 482 (define_insn_reservation "neon_bp_3cycle" 4 | 482 (define_insn_reservation "cortex_a8_neon_bp_3cycle" 4 |
| 483 (and (eq_attr "tune" "cortexa8") | 483 (and (eq_attr "tune" "cortexa8") |
| 484 (eq_attr "neon_type" "neon_bp_3cycle")) | 484 (eq_attr "neon_type" "neon_bp_3cycle")) |
| 485 "cortex_a8_neon_perm_3") | 485 "cortex_a8_neon_perm_3") |
| 486 | 486 |
| 487 ;; Instructions using this reservation produce a result at N1. | 487 ;; Instructions using this reservation produce a result at N1. |
| 488 (define_insn_reservation "neon_ldr" 1 | 488 (define_insn_reservation "cortex_a8_neon_ldr" 1 |
| 489 (and (eq_attr "tune" "cortexa8") | 489 (and (eq_attr "tune" "cortexa8") |
| 490 (eq_attr "neon_type" "neon_ldr")) | 490 (eq_attr "neon_type" "neon_ldr")) |
| 491 "cortex_a8_neon_ls") | 491 "cortex_a8_neon_ls") |
| 492 | 492 |
| 493 ;; Instructions using this reservation read their source operands at N1. | 493 ;; Instructions using this reservation read their source operands at N1. |
| 494 (define_insn_reservation "neon_str" 0 | 494 (define_insn_reservation "cortex_a8_neon_str" 0 |
| 495 (and (eq_attr "tune" "cortexa8") | 495 (and (eq_attr "tune" "cortexa8") |
| 496 (eq_attr "neon_type" "neon_str")) | 496 (eq_attr "neon_type" "neon_str")) |
| 497 "cortex_a8_neon_ls") | 497 "cortex_a8_neon_ls") |
| 498 | 498 |
| 499 ;; Instructions using this reservation produce a result at N1 on cycle 2. | 499 ;; Instructions using this reservation produce a result at N1 on cycle 2. |
| 500 (define_insn_reservation "neon_vld1_1_2_regs" 2 | 500 (define_insn_reservation "cortex_a8_neon_vld1_1_2_regs" 2 |
| 501 (and (eq_attr "tune" "cortexa8") | 501 (and (eq_attr "tune" "cortexa8") |
| 502 (eq_attr "neon_type" "neon_vld1_1_2_regs")) | 502 (eq_attr "neon_type" "neon_vld1_1_2_regs")) |
| 503 "cortex_a8_neon_ls_2") | 503 "cortex_a8_neon_ls_2") |
| 504 | 504 |
| 505 ;; Instructions using this reservation produce a result at N1 on cycle 3. | 505 ;; Instructions using this reservation produce a result at N1 on cycle 3. |
| 506 (define_insn_reservation "neon_vld1_3_4_regs" 3 | 506 (define_insn_reservation "cortex_a8_neon_vld1_3_4_regs" 3 |
| 507 (and (eq_attr "tune" "cortexa8") | 507 (and (eq_attr "tune" "cortexa8") |
| 508 (eq_attr "neon_type" "neon_vld1_3_4_regs")) | 508 (eq_attr "neon_type" "neon_vld1_3_4_regs")) |
| 509 "cortex_a8_neon_ls_3") | 509 "cortex_a8_neon_ls_3") |
| 510 | 510 |
| 511 ;; Instructions using this reservation produce a result at N2 on cycle 2. | 511 ;; Instructions using this reservation produce a result at N2 on cycle 2. |
| 512 (define_insn_reservation "neon_vld2_2_regs_vld1_vld2_all_lanes" 3 | 512 (define_insn_reservation "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" 3 |
| 513 (and (eq_attr "tune" "cortexa8") | 513 (and (eq_attr "tune" "cortexa8") |
| 514 (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) | 514 (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) |
| 515 "cortex_a8_neon_ls_2") | 515 "cortex_a8_neon_ls_2") |
| 516 | 516 |
| 517 ;; Instructions using this reservation produce a result at N2 on cycle 3. | 517 ;; Instructions using this reservation produce a result at N2 on cycle 3. |
| 518 (define_insn_reservation "neon_vld2_4_regs" 4 | 518 (define_insn_reservation "cortex_a8_neon_vld2_4_regs" 4 |
| 519 (and (eq_attr "tune" "cortexa8") | 519 (and (eq_attr "tune" "cortexa8") |
| 520 (eq_attr "neon_type" "neon_vld2_4_regs")) | 520 (eq_attr "neon_type" "neon_vld2_4_regs")) |
| 521 "cortex_a8_neon_ls_3") | 521 "cortex_a8_neon_ls_3") |
| 522 | 522 |
| 523 ;; Instructions using this reservation produce a result at N2 on cycle 4. | 523 ;; Instructions using this reservation produce a result at N2 on cycle 4. |
| 524 (define_insn_reservation "neon_vld3_vld4" 5 | 524 (define_insn_reservation "cortex_a8_neon_vld3_vld4" 5 |
| 525 (and (eq_attr "tune" "cortexa8") | 525 (and (eq_attr "tune" "cortexa8") |
| 526 (eq_attr "neon_type" "neon_vld3_vld4")) | 526 (eq_attr "neon_type" "neon_vld3_vld4")) |
| 527 "cortex_a8_neon_ls_4") | 527 "cortex_a8_neon_ls_4") |
| 528 | 528 |
| 529 ;; Instructions using this reservation read their source operands at N1. | 529 ;; Instructions using this reservation read their source operands at N1. |
| 530 (define_insn_reservation "neon_vst1_1_2_regs_vst2_2_regs" 0 | 530 (define_insn_reservation "cortex_a8_neon_vst1_1_2_regs_vst2_2_regs" 0 |
| 531 (and (eq_attr "tune" "cortexa8") | 531 (and (eq_attr "tune" "cortexa8") |
| 532 (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")) | 532 (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")) |
| 533 "cortex_a8_neon_ls_2") | 533 "cortex_a8_neon_ls_2") |
| 534 | 534 |
| 535 ;; Instructions using this reservation read their source operands at N1. | 535 ;; Instructions using this reservation read their source operands at N1. |
| 536 (define_insn_reservation "neon_vst1_3_4_regs" 0 | 536 (define_insn_reservation "cortex_a8_neon_vst1_3_4_regs" 0 |
| 537 (and (eq_attr "tune" "cortexa8") | 537 (and (eq_attr "tune" "cortexa8") |
| 538 (eq_attr "neon_type" "neon_vst1_3_4_regs")) | 538 (eq_attr "neon_type" "neon_vst1_3_4_regs")) |
| 539 "cortex_a8_neon_ls_3") | 539 "cortex_a8_neon_ls_3") |
| 540 | 540 |
| 541 ;; Instructions using this reservation read their source operands at N1. | 541 ;; Instructions using this reservation read their source operands at N1. |
| 542 (define_insn_reservation "neon_vst2_4_regs_vst3_vst4" 0 | 542 (define_insn_reservation "cortex_a8_neon_vst2_4_regs_vst3_vst4" 0 |
| 543 (and (eq_attr "tune" "cortexa8") | 543 (and (eq_attr "tune" "cortexa8") |
| 544 (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")) | 544 (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")) |
| 545 "cortex_a8_neon_ls_4") | 545 "cortex_a8_neon_ls_4") |
| 546 | 546 |
| 547 ;; Instructions using this reservation read their source operands at N1. | 547 ;; Instructions using this reservation read their source operands at N1. |
| 548 (define_insn_reservation "neon_vst3_vst4" 0 | 548 (define_insn_reservation "cortex_a8_neon_vst3_vst4" 0 |
| 549 (and (eq_attr "tune" "cortexa8") | 549 (and (eq_attr "tune" "cortexa8") |
| 550 (eq_attr "neon_type" "neon_vst3_vst4")) | 550 (eq_attr "neon_type" "neon_vst3_vst4")) |
| 551 "cortex_a8_neon_ls_4") | 551 "cortex_a8_neon_ls_4") |
| 552 | 552 |
| 553 ;; Instructions using this reservation read their source operands at N1, and | 553 ;; Instructions using this reservation read their source operands at N1, and |
| 554 ;; produce a result at N2 on cycle 3. | 554 ;; produce a result at N2 on cycle 3. |
| 555 (define_insn_reservation "neon_vld1_vld2_lane" 4 | 555 (define_insn_reservation "cortex_a8_neon_vld1_vld2_lane" 4 |
| 556 (and (eq_attr "tune" "cortexa8") | 556 (and (eq_attr "tune" "cortexa8") |
| 557 (eq_attr "neon_type" "neon_vld1_vld2_lane")) | 557 (eq_attr "neon_type" "neon_vld1_vld2_lane")) |
| 558 "cortex_a8_neon_ls_3") | 558 "cortex_a8_neon_ls_3") |
| 559 | 559 |
| 560 ;; Instructions using this reservation read their source operands at N1, and | 560 ;; Instructions using this reservation read their source operands at N1, and |
| 561 ;; produce a result at N2 on cycle 5. | 561 ;; produce a result at N2 on cycle 5. |
| 562 (define_insn_reservation "neon_vld3_vld4_lane" 6 | 562 (define_insn_reservation "cortex_a8_neon_vld3_vld4_lane" 6 |
| 563 (and (eq_attr "tune" "cortexa8") | 563 (and (eq_attr "tune" "cortexa8") |
| 564 (eq_attr "neon_type" "neon_vld3_vld4_lane")) | 564 (eq_attr "neon_type" "neon_vld3_vld4_lane")) |
| 565 "cortex_a8_neon_ls_5") | 565 "cortex_a8_neon_ls_5") |
| 566 | 566 |
| 567 ;; Instructions using this reservation read their source operands at N1. | 567 ;; Instructions using this reservation read their source operands at N1. |
| 568 (define_insn_reservation "neon_vst1_vst2_lane" 0 | 568 (define_insn_reservation "cortex_a8_neon_vst1_vst2_lane" 0 |
| 569 (and (eq_attr "tune" "cortexa8") | 569 (and (eq_attr "tune" "cortexa8") |
| 570 (eq_attr "neon_type" "neon_vst1_vst2_lane")) | 570 (eq_attr "neon_type" "neon_vst1_vst2_lane")) |
| 571 "cortex_a8_neon_ls_2") | 571 "cortex_a8_neon_ls_2") |
| 572 | 572 |
| 573 ;; Instructions using this reservation read their source operands at N1. | 573 ;; Instructions using this reservation read their source operands at N1. |
| 574 (define_insn_reservation "neon_vst3_vst4_lane" 0 | 574 (define_insn_reservation "cortex_a8_neon_vst3_vst4_lane" 0 |
| 575 (and (eq_attr "tune" "cortexa8") | 575 (and (eq_attr "tune" "cortexa8") |
| 576 (eq_attr "neon_type" "neon_vst3_vst4_lane")) | 576 (eq_attr "neon_type" "neon_vst3_vst4_lane")) |
| 577 "cortex_a8_neon_ls_3") | 577 "cortex_a8_neon_ls_3") |
| 578 | 578 |
| 579 ;; Instructions using this reservation produce a result at N2 on cycle 2. | 579 ;; Instructions using this reservation produce a result at N2 on cycle 2. |
| 580 (define_insn_reservation "neon_vld3_vld4_all_lanes" 3 | 580 (define_insn_reservation "cortex_a8_neon_vld3_vld4_all_lanes" 3 |
| 581 (and (eq_attr "tune" "cortexa8") | 581 (and (eq_attr "tune" "cortexa8") |
| 582 (eq_attr "neon_type" "neon_vld3_vld4_all_lanes")) | 582 (eq_attr "neon_type" "neon_vld3_vld4_all_lanes")) |
| 583 "cortex_a8_neon_ls_3") | 583 "cortex_a8_neon_ls_3") |
| 584 | 584 |
| 585 ;; Instructions using this reservation produce a result at N2. | 585 ;; Instructions using this reservation produce a result at N2. |
| 586 (define_insn_reservation "neon_mcr" 2 | 586 (define_insn_reservation "cortex_a8_neon_mcr" 2 |
| 587 (and (eq_attr "tune" "cortexa8") | 587 (and (eq_attr "tune" "cortexa8") |
| 588 (eq_attr "neon_type" "neon_mcr")) | 588 (eq_attr "neon_type" "neon_mcr")) |
| 589 "cortex_a8_neon_perm") | 589 "cortex_a8_neon_perm") |
| 590 | 590 |
| 591 ;; Instructions using this reservation produce a result at N2. | 591 ;; Instructions using this reservation produce a result at N2. |
| 592 (define_insn_reservation "neon_mcr_2_mcrr" 2 | 592 (define_insn_reservation "cortex_a8_neon_mcr_2_mcrr" 2 |
| 593 (and (eq_attr "tune" "cortexa8") | 593 (and (eq_attr "tune" "cortexa8") |
| 594 (eq_attr "neon_type" "neon_mcr_2_mcrr")) | 594 (eq_attr "neon_type" "neon_mcr_2_mcrr")) |
| 595 "cortex_a8_neon_perm_2") | 595 "cortex_a8_neon_perm_2") |
| 596 | 596 |
| 597 ;; Exceptions to the default latencies. | 597 ;; Exceptions to the default latencies. |
| 598 | 598 |
| 599 (define_bypass 1 "neon_mcr_2_mcrr" | 599 (define_bypass 1 "cortex_a8_neon_mcr_2_mcrr" |
| 600 "neon_int_1,\ | 600 "cortex_a8_neon_int_1,\ |
| 601 neon_int_4,\ | 601 cortex_a8_neon_int_4,\ |
| 602 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 602 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 603 neon_mul_qqq_8_16_32_ddd_32,\ | 603 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 604 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 604 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 605 neon_mla_qqq_8_16,\ | 605 cortex_a8_neon_mla_qqq_8_16,\ |
| 606 neon_fp_vadd_ddd_vabs_dd,\ | 606 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 607 neon_fp_vadd_qqq_vabs_qq,\ | 607 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 608 neon_fp_vmla_ddd,\ | 608 cortex_a8_neon_fp_vmla_ddd,\ |
| 609 neon_fp_vmla_qqq,\ | 609 cortex_a8_neon_fp_vmla_qqq,\ |
| 610 neon_fp_vrecps_vrsqrts_ddd,\ | 610 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 611 neon_fp_vrecps_vrsqrts_qqq") | 611 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 612 | 612 |
| 613 (define_bypass 1 "neon_mcr" | 613 (define_bypass 1 "cortex_a8_neon_mcr" |
| 614 "neon_int_1,\ | 614 "cortex_a8_neon_int_1,\ |
| 615 neon_int_4,\ | 615 cortex_a8_neon_int_4,\ |
| 616 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 616 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 617 neon_mul_qqq_8_16_32_ddd_32,\ | 617 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 618 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 618 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 619 neon_mla_qqq_8_16,\ | 619 cortex_a8_neon_mla_qqq_8_16,\ |
| 620 neon_fp_vadd_ddd_vabs_dd,\ | 620 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 621 neon_fp_vadd_qqq_vabs_qq,\ | 621 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 622 neon_fp_vmla_ddd,\ | 622 cortex_a8_neon_fp_vmla_ddd,\ |
| 623 neon_fp_vmla_qqq,\ | 623 cortex_a8_neon_fp_vmla_qqq,\ |
| 624 neon_fp_vrecps_vrsqrts_ddd,\ | 624 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 625 neon_fp_vrecps_vrsqrts_qqq") | 625 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 626 | 626 |
| 627 (define_bypass 2 "neon_vld3_vld4_all_lanes" | 627 (define_bypass 2 "cortex_a8_neon_vld3_vld4_all_lanes" |
| 628 "neon_int_1,\ | 628 "cortex_a8_neon_int_1,\ |
| 629 neon_int_4,\ | 629 cortex_a8_neon_int_4,\ |
| 630 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 630 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 631 neon_mul_qqq_8_16_32_ddd_32,\ | 631 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 632 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 632 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 633 neon_mla_qqq_8_16,\ | 633 cortex_a8_neon_mla_qqq_8_16,\ |
| 634 neon_fp_vadd_ddd_vabs_dd,\ | 634 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 635 neon_fp_vadd_qqq_vabs_qq,\ | 635 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 636 neon_fp_vmla_ddd,\ | 636 cortex_a8_neon_fp_vmla_ddd,\ |
| 637 neon_fp_vmla_qqq,\ | 637 cortex_a8_neon_fp_vmla_qqq,\ |
| 638 neon_fp_vrecps_vrsqrts_ddd,\ | 638 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 639 neon_fp_vrecps_vrsqrts_qqq") | 639 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 640 | 640 |
| 641 (define_bypass 5 "neon_vld3_vld4_lane" | 641 (define_bypass 5 "cortex_a8_neon_vld3_vld4_lane" |
| 642 "neon_int_1,\ | 642 "cortex_a8_neon_int_1,\ |
| 643 neon_int_4,\ | 643 cortex_a8_neon_int_4,\ |
| 644 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 644 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 645 neon_mul_qqq_8_16_32_ddd_32,\ | 645 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 646 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 646 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 647 neon_mla_qqq_8_16,\ | 647 cortex_a8_neon_mla_qqq_8_16,\ |
| 648 neon_fp_vadd_ddd_vabs_dd,\ | 648 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 649 neon_fp_vadd_qqq_vabs_qq,\ | 649 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 650 neon_fp_vmla_ddd,\ | 650 cortex_a8_neon_fp_vmla_ddd,\ |
| 651 neon_fp_vmla_qqq,\ | 651 cortex_a8_neon_fp_vmla_qqq,\ |
| 652 neon_fp_vrecps_vrsqrts_ddd,\ | 652 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 653 neon_fp_vrecps_vrsqrts_qqq") | 653 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 654 | 654 |
| 655 (define_bypass 3 "neon_vld1_vld2_lane" | 655 (define_bypass 3 "cortex_a8_neon_vld1_vld2_lane" |
| 656 "neon_int_1,\ | 656 "cortex_a8_neon_int_1,\ |
| 657 neon_int_4,\ | 657 cortex_a8_neon_int_4,\ |
| 658 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 658 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 659 neon_mul_qqq_8_16_32_ddd_32,\ | 659 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 660 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 660 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 661 neon_mla_qqq_8_16,\ | 661 cortex_a8_neon_mla_qqq_8_16,\ |
| 662 neon_fp_vadd_ddd_vabs_dd,\ | 662 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 663 neon_fp_vadd_qqq_vabs_qq,\ | 663 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 664 neon_fp_vmla_ddd,\ | 664 cortex_a8_neon_fp_vmla_ddd,\ |
| 665 neon_fp_vmla_qqq,\ | 665 cortex_a8_neon_fp_vmla_qqq,\ |
| 666 neon_fp_vrecps_vrsqrts_ddd,\ | 666 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 667 neon_fp_vrecps_vrsqrts_qqq") | 667 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 668 | 668 |
| 669 (define_bypass 4 "neon_vld3_vld4" | 669 (define_bypass 4 "cortex_a8_neon_vld3_vld4" |
| 670 "neon_int_1,\ | 670 "cortex_a8_neon_int_1,\ |
| 671 neon_int_4,\ | 671 cortex_a8_neon_int_4,\ |
| 672 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 672 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 673 neon_mul_qqq_8_16_32_ddd_32,\ | 673 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 674 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 674 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 675 neon_mla_qqq_8_16,\ | 675 cortex_a8_neon_mla_qqq_8_16,\ |
| 676 neon_fp_vadd_ddd_vabs_dd,\ | 676 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 677 neon_fp_vadd_qqq_vabs_qq,\ | 677 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 678 neon_fp_vmla_ddd,\ | 678 cortex_a8_neon_fp_vmla_ddd,\ |
| 679 neon_fp_vmla_qqq,\ | 679 cortex_a8_neon_fp_vmla_qqq,\ |
| 680 neon_fp_vrecps_vrsqrts_ddd,\ | 680 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 681 neon_fp_vrecps_vrsqrts_qqq") | 681 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 682 | 682 |
| 683 (define_bypass 3 "neon_vld2_4_regs" | 683 (define_bypass 3 "cortex_a8_neon_vld2_4_regs" |
| 684 "neon_int_1,\ | 684 "cortex_a8_neon_int_1,\ |
| 685 neon_int_4,\ | 685 cortex_a8_neon_int_4,\ |
| 686 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 686 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 687 neon_mul_qqq_8_16_32_ddd_32,\ | 687 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 688 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 688 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 689 neon_mla_qqq_8_16,\ | 689 cortex_a8_neon_mla_qqq_8_16,\ |
| 690 neon_fp_vadd_ddd_vabs_dd,\ | 690 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 691 neon_fp_vadd_qqq_vabs_qq,\ | 691 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 692 neon_fp_vmla_ddd,\ | 692 cortex_a8_neon_fp_vmla_ddd,\ |
| 693 neon_fp_vmla_qqq,\ | 693 cortex_a8_neon_fp_vmla_qqq,\ |
| 694 neon_fp_vrecps_vrsqrts_ddd,\ | 694 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 695 neon_fp_vrecps_vrsqrts_qqq") | 695 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 696 | 696 |
| 697 (define_bypass 2 "neon_vld2_2_regs_vld1_vld2_all_lanes" | 697 (define_bypass 2 "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" |
| 698 "neon_int_1,\ | 698 "cortex_a8_neon_int_1,\ |
| 699 neon_int_4,\ | 699 cortex_a8_neon_int_4,\ |
| 700 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 700 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 701 neon_mul_qqq_8_16_32_ddd_32,\ | 701 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 702 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 702 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 703 neon_mla_qqq_8_16,\ | 703 cortex_a8_neon_mla_qqq_8_16,\ |
| 704 neon_fp_vadd_ddd_vabs_dd,\ | 704 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 705 neon_fp_vadd_qqq_vabs_qq,\ | 705 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 706 neon_fp_vmla_ddd,\ | 706 cortex_a8_neon_fp_vmla_ddd,\ |
| 707 neon_fp_vmla_qqq,\ | 707 cortex_a8_neon_fp_vmla_qqq,\ |
| 708 neon_fp_vrecps_vrsqrts_ddd,\ | 708 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 709 neon_fp_vrecps_vrsqrts_qqq") | 709 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 710 | 710 |
| 711 (define_bypass 2 "neon_vld1_3_4_regs" | 711 (define_bypass 2 "cortex_a8_neon_vld1_3_4_regs" |
| 712 "neon_int_1,\ | 712 "cortex_a8_neon_int_1,\ |
| 713 neon_int_4,\ | 713 cortex_a8_neon_int_4,\ |
| 714 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 714 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 715 neon_mul_qqq_8_16_32_ddd_32,\ | 715 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 716 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 716 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 717 neon_mla_qqq_8_16,\ | 717 cortex_a8_neon_mla_qqq_8_16,\ |
| 718 neon_fp_vadd_ddd_vabs_dd,\ | 718 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 719 neon_fp_vadd_qqq_vabs_qq,\ | 719 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 720 neon_fp_vmla_ddd,\ | 720 cortex_a8_neon_fp_vmla_ddd,\ |
| 721 neon_fp_vmla_qqq,\ | 721 cortex_a8_neon_fp_vmla_qqq,\ |
| 722 neon_fp_vrecps_vrsqrts_ddd,\ | 722 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 723 neon_fp_vrecps_vrsqrts_qqq") | 723 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 724 | 724 |
| 725 (define_bypass 1 "neon_vld1_1_2_regs" | 725 (define_bypass 1 "cortex_a8_neon_vld1_1_2_regs" |
| 726 "neon_int_1,\ | 726 "cortex_a8_neon_int_1,\ |
| 727 neon_int_4,\ | 727 cortex_a8_neon_int_4,\ |
| 728 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 728 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 729 neon_mul_qqq_8_16_32_ddd_32,\ | 729 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 730 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 730 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 731 neon_mla_qqq_8_16,\ | 731 cortex_a8_neon_mla_qqq_8_16,\ |
| 732 neon_fp_vadd_ddd_vabs_dd,\ | 732 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 733 neon_fp_vadd_qqq_vabs_qq,\ | 733 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 734 neon_fp_vmla_ddd,\ | 734 cortex_a8_neon_fp_vmla_ddd,\ |
| 735 neon_fp_vmla_qqq,\ | 735 cortex_a8_neon_fp_vmla_qqq,\ |
| 736 neon_fp_vrecps_vrsqrts_ddd,\ | 736 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 737 neon_fp_vrecps_vrsqrts_qqq") | 737 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 738 | 738 |
| 739 (define_bypass 0 "neon_ldr" | 739 (define_bypass 0 "cortex_a8_neon_ldr" |
| 740 "neon_int_1,\ | 740 "cortex_a8_neon_int_1,\ |
| 741 neon_int_4,\ | 741 cortex_a8_neon_int_4,\ |
| 742 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 742 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 743 neon_mul_qqq_8_16_32_ddd_32,\ | 743 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 744 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 744 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 745 neon_mla_qqq_8_16,\ | 745 cortex_a8_neon_mla_qqq_8_16,\ |
| 746 neon_fp_vadd_ddd_vabs_dd,\ | 746 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 747 neon_fp_vadd_qqq_vabs_qq,\ | 747 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 748 neon_fp_vmla_ddd,\ | 748 cortex_a8_neon_fp_vmla_ddd,\ |
| 749 neon_fp_vmla_qqq,\ | 749 cortex_a8_neon_fp_vmla_qqq,\ |
| 750 neon_fp_vrecps_vrsqrts_ddd,\ | 750 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 751 neon_fp_vrecps_vrsqrts_qqq") | 751 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 752 | 752 |
| 753 (define_bypass 3 "neon_bp_3cycle" | 753 (define_bypass 3 "cortex_a8_neon_bp_3cycle" |
| 754 "neon_int_1,\ | 754 "cortex_a8_neon_int_1,\ |
| 755 neon_int_4,\ | 755 cortex_a8_neon_int_4,\ |
| 756 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 756 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 757 neon_mul_qqq_8_16_32_ddd_32,\ | 757 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 758 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 758 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 759 neon_mla_qqq_8_16,\ | 759 cortex_a8_neon_mla_qqq_8_16,\ |
| 760 neon_fp_vadd_ddd_vabs_dd,\ | 760 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 761 neon_fp_vadd_qqq_vabs_qq,\ | 761 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 762 neon_fp_vmla_ddd,\ | 762 cortex_a8_neon_fp_vmla_ddd,\ |
| 763 neon_fp_vmla_qqq,\ | 763 cortex_a8_neon_fp_vmla_qqq,\ |
| 764 neon_fp_vrecps_vrsqrts_ddd,\ | 764 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 765 neon_fp_vrecps_vrsqrts_qqq") | 765 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 766 | 766 |
| 767 (define_bypass 2 "neon_bp_2cycle" | 767 (define_bypass 2 "cortex_a8_neon_bp_2cycle" |
| 768 "neon_int_1,\ | 768 "cortex_a8_neon_int_1,\ |
| 769 neon_int_4,\ | 769 cortex_a8_neon_int_4,\ |
| 770 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 770 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 771 neon_mul_qqq_8_16_32_ddd_32,\ | 771 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 772 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 772 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 773 neon_mla_qqq_8_16,\ | 773 cortex_a8_neon_mla_qqq_8_16,\ |
| 774 neon_fp_vadd_ddd_vabs_dd,\ | 774 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 775 neon_fp_vadd_qqq_vabs_qq,\ | 775 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 776 neon_fp_vmla_ddd,\ | 776 cortex_a8_neon_fp_vmla_ddd,\ |
| 777 neon_fp_vmla_qqq,\ | 777 cortex_a8_neon_fp_vmla_qqq,\ |
| 778 neon_fp_vrecps_vrsqrts_ddd,\ | 778 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 779 neon_fp_vrecps_vrsqrts_qqq") | 779 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 780 | 780 |
| 781 (define_bypass 1 "neon_bp_simple" | 781 (define_bypass 1 "cortex_a8_neon_bp_simple" |
| 782 "neon_int_1,\ | 782 "cortex_a8_neon_int_1,\ |
| 783 neon_int_4,\ | 783 cortex_a8_neon_int_4,\ |
| 784 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 784 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 785 neon_mul_qqq_8_16_32_ddd_32,\ | 785 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 786 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 786 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 787 neon_mla_qqq_8_16,\ | 787 cortex_a8_neon_mla_qqq_8_16,\ |
| 788 neon_fp_vadd_ddd_vabs_dd,\ | 788 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 789 neon_fp_vadd_qqq_vabs_qq,\ | 789 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 790 neon_fp_vmla_ddd,\ | 790 cortex_a8_neon_fp_vmla_ddd,\ |
| 791 neon_fp_vmla_qqq,\ | 791 cortex_a8_neon_fp_vmla_qqq,\ |
| 792 neon_fp_vrecps_vrsqrts_ddd,\ | 792 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 793 neon_fp_vrecps_vrsqrts_qqq") | 793 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 794 | 794 |
| 795 (define_bypass 9 "neon_fp_vrecps_vrsqrts_qqq" | 795 (define_bypass 9 "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" |
| 796 "neon_int_1,\ | 796 "cortex_a8_neon_int_1,\ |
| 797 neon_int_4,\ | 797 cortex_a8_neon_int_4,\ |
| 798 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 798 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 799 neon_mul_qqq_8_16_32_ddd_32,\ | 799 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 800 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 800 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 801 neon_mla_qqq_8_16,\ | 801 cortex_a8_neon_mla_qqq_8_16,\ |
| 802 neon_fp_vadd_ddd_vabs_dd,\ | 802 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 803 neon_fp_vadd_qqq_vabs_qq,\ | 803 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 804 neon_fp_vmla_ddd,\ | 804 cortex_a8_neon_fp_vmla_ddd,\ |
| 805 neon_fp_vmla_qqq,\ | 805 cortex_a8_neon_fp_vmla_qqq,\ |
| 806 neon_fp_vrecps_vrsqrts_ddd,\ | 806 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 807 neon_fp_vrecps_vrsqrts_qqq") | 807 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 808 | 808 |
| 809 (define_bypass 8 "neon_fp_vrecps_vrsqrts_ddd" | 809 (define_bypass 8 "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" |
| 810 "neon_int_1,\ | 810 "cortex_a8_neon_int_1,\ |
| 811 neon_int_4,\ | 811 cortex_a8_neon_int_4,\ |
| 812 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 812 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 813 neon_mul_qqq_8_16_32_ddd_32,\ | 813 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 814 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 814 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 815 neon_mla_qqq_8_16,\ | 815 cortex_a8_neon_mla_qqq_8_16,\ |
| 816 neon_fp_vadd_ddd_vabs_dd,\ | 816 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 817 neon_fp_vadd_qqq_vabs_qq,\ | 817 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 818 neon_fp_vmla_ddd,\ | 818 cortex_a8_neon_fp_vmla_ddd,\ |
| 819 neon_fp_vmla_qqq,\ | 819 cortex_a8_neon_fp_vmla_qqq,\ |
| 820 neon_fp_vrecps_vrsqrts_ddd,\ | 820 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 821 neon_fp_vrecps_vrsqrts_qqq") | 821 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 822 | 822 |
| 823 (define_bypass 9 "neon_fp_vmla_qqq_scalar" | 823 (define_bypass 9 "cortex_a8_neon_fp_vmla_qqq_scalar" |
| 824 "neon_int_1,\ | 824 "cortex_a8_neon_int_1,\ |
| 825 neon_int_4,\ | 825 cortex_a8_neon_int_4,\ |
| 826 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 826 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 827 neon_mul_qqq_8_16_32_ddd_32,\ | 827 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 828 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 828 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 829 neon_mla_qqq_8_16,\ | 829 cortex_a8_neon_mla_qqq_8_16,\ |
| 830 neon_fp_vadd_ddd_vabs_dd,\ | 830 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 831 neon_fp_vadd_qqq_vabs_qq,\ | 831 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 832 neon_fp_vmla_ddd,\ | 832 cortex_a8_neon_fp_vmla_ddd,\ |
| 833 neon_fp_vmla_qqq,\ | 833 cortex_a8_neon_fp_vmla_qqq,\ |
| 834 neon_fp_vrecps_vrsqrts_ddd,\ | 834 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 835 neon_fp_vrecps_vrsqrts_qqq") | 835 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 836 | 836 |
| 837 (define_bypass 8 "neon_fp_vmla_ddd_scalar" | 837 (define_bypass 8 "cortex_a8_neon_fp_vmla_ddd_scalar" |
| 838 "neon_int_1,\ | 838 "cortex_a8_neon_int_1,\ |
| 839 neon_int_4,\ | 839 cortex_a8_neon_int_4,\ |
| 840 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 840 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 841 neon_mul_qqq_8_16_32_ddd_32,\ | 841 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 842 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 842 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 843 neon_mla_qqq_8_16,\ | 843 cortex_a8_neon_mla_qqq_8_16,\ |
| 844 neon_fp_vadd_ddd_vabs_dd,\ | 844 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 845 neon_fp_vadd_qqq_vabs_qq,\ | 845 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 846 neon_fp_vmla_ddd,\ | 846 cortex_a8_neon_fp_vmla_ddd,\ |
| 847 neon_fp_vmla_qqq,\ | 847 cortex_a8_neon_fp_vmla_qqq,\ |
| 848 neon_fp_vrecps_vrsqrts_ddd,\ | 848 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 849 neon_fp_vrecps_vrsqrts_qqq") | 849 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 850 | 850 |
| 851 (define_bypass 9 "neon_fp_vmla_qqq" | 851 (define_bypass 9 "cortex_a8_neon_fp_vmla_qqq" |
| 852 "neon_int_1,\ | 852 "cortex_a8_neon_int_1,\ |
| 853 neon_int_4,\ | 853 cortex_a8_neon_int_4,\ |
| 854 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 854 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 855 neon_mul_qqq_8_16_32_ddd_32,\ | 855 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 856 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 856 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 857 neon_mla_qqq_8_16,\ | 857 cortex_a8_neon_mla_qqq_8_16,\ |
| 858 neon_fp_vadd_ddd_vabs_dd,\ | 858 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 859 neon_fp_vadd_qqq_vabs_qq,\ | 859 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 860 neon_fp_vmla_ddd,\ | 860 cortex_a8_neon_fp_vmla_ddd,\ |
| 861 neon_fp_vmla_qqq,\ | 861 cortex_a8_neon_fp_vmla_qqq,\ |
| 862 neon_fp_vrecps_vrsqrts_ddd,\ | 862 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 863 neon_fp_vrecps_vrsqrts_qqq") | 863 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 864 | 864 |
| 865 (define_bypass 8 "neon_fp_vmla_ddd" | 865 (define_bypass 8 "cortex_a8_neon_fp_vmla_ddd" |
| 866 "neon_int_1,\ | 866 "cortex_a8_neon_int_1,\ |
| 867 neon_int_4,\ | 867 cortex_a8_neon_int_4,\ |
| 868 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 868 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 869 neon_mul_qqq_8_16_32_ddd_32,\ | 869 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 870 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 870 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 871 neon_mla_qqq_8_16,\ | 871 cortex_a8_neon_mla_qqq_8_16,\ |
| 872 neon_fp_vadd_ddd_vabs_dd,\ | 872 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 873 neon_fp_vadd_qqq_vabs_qq,\ | 873 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 874 neon_fp_vmla_ddd,\ | 874 cortex_a8_neon_fp_vmla_ddd,\ |
| 875 neon_fp_vmla_qqq,\ | 875 cortex_a8_neon_fp_vmla_qqq,\ |
| 876 neon_fp_vrecps_vrsqrts_ddd,\ | 876 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 877 neon_fp_vrecps_vrsqrts_qqq") | 877 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 878 | 878 |
| 879 (define_bypass 5 "neon_fp_vmul_qqd" | 879 (define_bypass 5 "cortex_a8_neon_fp_vmul_qqd" |
| 880 "neon_int_1,\ | 880 "cortex_a8_neon_int_1,\ |
| 881 neon_int_4,\ | 881 cortex_a8_neon_int_4,\ |
| 882 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 882 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 883 neon_mul_qqq_8_16_32_ddd_32,\ | 883 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 884 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 884 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 885 neon_mla_qqq_8_16,\ | 885 cortex_a8_neon_mla_qqq_8_16,\ |
| 886 neon_fp_vadd_ddd_vabs_dd,\ | 886 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 887 neon_fp_vadd_qqq_vabs_qq,\ | 887 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 888 neon_fp_vmla_ddd,\ | 888 cortex_a8_neon_fp_vmla_ddd,\ |
| 889 neon_fp_vmla_qqq,\ | 889 cortex_a8_neon_fp_vmla_qqq,\ |
| 890 neon_fp_vrecps_vrsqrts_ddd,\ | 890 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 891 neon_fp_vrecps_vrsqrts_qqq") | 891 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 892 | 892 |
| 893 (define_bypass 4 "neon_fp_vmul_ddd" | 893 (define_bypass 4 "cortex_a8_neon_fp_vmul_ddd" |
| 894 "neon_int_1,\ | 894 "cortex_a8_neon_int_1,\ |
| 895 neon_int_4,\ | 895 cortex_a8_neon_int_4,\ |
| 896 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 896 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 897 neon_mul_qqq_8_16_32_ddd_32,\ | 897 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 898 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 898 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 899 neon_mla_qqq_8_16,\ | 899 cortex_a8_neon_mla_qqq_8_16,\ |
| 900 neon_fp_vadd_ddd_vabs_dd,\ | 900 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 901 neon_fp_vadd_qqq_vabs_qq,\ | 901 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 902 neon_fp_vmla_ddd,\ | 902 cortex_a8_neon_fp_vmla_ddd,\ |
| 903 neon_fp_vmla_qqq,\ | 903 cortex_a8_neon_fp_vmla_qqq,\ |
| 904 neon_fp_vrecps_vrsqrts_ddd,\ | 904 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 905 neon_fp_vrecps_vrsqrts_qqq") | 905 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 906 | 906 |
| 907 (define_bypass 4 "neon_fp_vsum" | 907 (define_bypass 4 "cortex_a8_neon_fp_vsum" |
| 908 "neon_int_1,\ | 908 "cortex_a8_neon_int_1,\ |
| 909 neon_int_4,\ | 909 cortex_a8_neon_int_4,\ |
| 910 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 910 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 911 neon_mul_qqq_8_16_32_ddd_32,\ | 911 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 912 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 912 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 913 neon_mla_qqq_8_16,\ | 913 cortex_a8_neon_mla_qqq_8_16,\ |
| 914 neon_fp_vadd_ddd_vabs_dd,\ | 914 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 915 neon_fp_vadd_qqq_vabs_qq,\ | 915 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 916 neon_fp_vmla_ddd,\ | 916 cortex_a8_neon_fp_vmla_ddd,\ |
| 917 neon_fp_vmla_qqq,\ | 917 cortex_a8_neon_fp_vmla_qqq,\ |
| 918 neon_fp_vrecps_vrsqrts_ddd,\ | 918 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 919 neon_fp_vrecps_vrsqrts_qqq") | 919 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 920 | 920 |
| 921 (define_bypass 5 "neon_fp_vadd_qqq_vabs_qq" | 921 (define_bypass 5 "cortex_a8_neon_fp_vadd_qqq_vabs_qq" |
| 922 "neon_int_1,\ | 922 "cortex_a8_neon_int_1,\ |
| 923 neon_int_4,\ | 923 cortex_a8_neon_int_4,\ |
| 924 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 924 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 925 neon_mul_qqq_8_16_32_ddd_32,\ | 925 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 926 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 926 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 927 neon_mla_qqq_8_16,\ | 927 cortex_a8_neon_mla_qqq_8_16,\ |
| 928 neon_fp_vadd_ddd_vabs_dd,\ | 928 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 929 neon_fp_vadd_qqq_vabs_qq,\ | 929 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 930 neon_fp_vmla_ddd,\ | 930 cortex_a8_neon_fp_vmla_ddd,\ |
| 931 neon_fp_vmla_qqq,\ | 931 cortex_a8_neon_fp_vmla_qqq,\ |
| 932 neon_fp_vrecps_vrsqrts_ddd,\ | 932 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 933 neon_fp_vrecps_vrsqrts_qqq") | 933 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 934 | 934 |
| 935 (define_bypass 4 "neon_fp_vadd_ddd_vabs_dd" | 935 (define_bypass 4 "cortex_a8_neon_fp_vadd_ddd_vabs_dd" |
| 936 "neon_int_1,\ | 936 "cortex_a8_neon_int_1,\ |
| 937 neon_int_4,\ | 937 cortex_a8_neon_int_4,\ |
| 938 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 938 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 939 neon_mul_qqq_8_16_32_ddd_32,\ | 939 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 940 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 940 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 941 neon_mla_qqq_8_16,\ | 941 cortex_a8_neon_mla_qqq_8_16,\ |
| 942 neon_fp_vadd_ddd_vabs_dd,\ | 942 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 943 neon_fp_vadd_qqq_vabs_qq,\ | 943 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 944 neon_fp_vmla_ddd,\ | 944 cortex_a8_neon_fp_vmla_ddd,\ |
| 945 neon_fp_vmla_qqq,\ | 945 cortex_a8_neon_fp_vmla_qqq,\ |
| 946 neon_fp_vrecps_vrsqrts_ddd,\ | 946 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 947 neon_fp_vrecps_vrsqrts_qqq") | 947 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 948 | 948 |
| 949 (define_bypass 5 "neon_vsra_vrsra" | 949 (define_bypass 5 "cortex_a8_neon_vsra_vrsra" |
| 950 "neon_int_1,\ | 950 "cortex_a8_neon_int_1,\ |
| 951 neon_int_4,\ | 951 cortex_a8_neon_int_4,\ |
| 952 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 952 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 953 neon_mul_qqq_8_16_32_ddd_32,\ | 953 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 954 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 954 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 955 neon_mla_qqq_8_16,\ | 955 cortex_a8_neon_mla_qqq_8_16,\ |
| 956 neon_fp_vadd_ddd_vabs_dd,\ | 956 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 957 neon_fp_vadd_qqq_vabs_qq,\ | 957 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 958 neon_fp_vmla_ddd,\ | 958 cortex_a8_neon_fp_vmla_ddd,\ |
| 959 neon_fp_vmla_qqq,\ | 959 cortex_a8_neon_fp_vmla_qqq,\ |
| 960 neon_fp_vrecps_vrsqrts_ddd,\ | 960 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 961 neon_fp_vrecps_vrsqrts_qqq") | 961 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 962 | 962 |
| 963 (define_bypass 4 "neon_vqshl_vrshl_vqrshl_qqq" | 963 (define_bypass 4 "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" |
| 964 "neon_int_1,\ | 964 "cortex_a8_neon_int_1,\ |
| 965 neon_int_4,\ | 965 cortex_a8_neon_int_4,\ |
| 966 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 966 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 967 neon_mul_qqq_8_16_32_ddd_32,\ | 967 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 968 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 968 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 969 neon_mla_qqq_8_16,\ | 969 cortex_a8_neon_mla_qqq_8_16,\ |
| 970 neon_fp_vadd_ddd_vabs_dd,\ | 970 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 971 neon_fp_vadd_qqq_vabs_qq,\ | 971 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 972 neon_fp_vmla_ddd,\ | 972 cortex_a8_neon_fp_vmla_ddd,\ |
| 973 neon_fp_vmla_qqq,\ | 973 cortex_a8_neon_fp_vmla_qqq,\ |
| 974 neon_fp_vrecps_vrsqrts_ddd,\ | 974 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 975 neon_fp_vrecps_vrsqrts_qqq") | 975 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 976 | 976 |
| 977 (define_bypass 0 "neon_vshl_ddd" | 977 (define_bypass 0 "cortex_a8_neon_vshl_ddd" |
| 978 "neon_int_1,\ | 978 "cortex_a8_neon_int_1,\ |
| 979 neon_int_4,\ | 979 cortex_a8_neon_int_4,\ |
| 980 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 980 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 981 neon_mul_qqq_8_16_32_ddd_32,\ | 981 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 982 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 982 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 983 neon_mla_qqq_8_16,\ | 983 cortex_a8_neon_mla_qqq_8_16,\ |
| 984 neon_fp_vadd_ddd_vabs_dd,\ | 984 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 985 neon_fp_vadd_qqq_vabs_qq,\ | 985 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 986 neon_fp_vmla_ddd,\ | 986 cortex_a8_neon_fp_vmla_ddd,\ |
| 987 neon_fp_vmla_qqq,\ | 987 cortex_a8_neon_fp_vmla_qqq,\ |
| 988 neon_fp_vrecps_vrsqrts_ddd,\ | 988 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 989 neon_fp_vrecps_vrsqrts_qqq") | 989 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 990 | 990 |
| 991 (define_bypass 3 "neon_shift_3" | 991 (define_bypass 3 "cortex_a8_neon_shift_3" |
| 992 "neon_int_1,\ | 992 "cortex_a8_neon_int_1,\ |
| 993 neon_int_4,\ | 993 cortex_a8_neon_int_4,\ |
| 994 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 994 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 995 neon_mul_qqq_8_16_32_ddd_32,\ | 995 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 996 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 996 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 997 neon_mla_qqq_8_16,\ | 997 cortex_a8_neon_mla_qqq_8_16,\ |
| 998 neon_fp_vadd_ddd_vabs_dd,\ | 998 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 999 neon_fp_vadd_qqq_vabs_qq,\ | 999 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1000 neon_fp_vmla_ddd,\ | 1000 cortex_a8_neon_fp_vmla_ddd,\ |
| 1001 neon_fp_vmla_qqq,\ | 1001 cortex_a8_neon_fp_vmla_qqq,\ |
| 1002 neon_fp_vrecps_vrsqrts_ddd,\ | 1002 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1003 neon_fp_vrecps_vrsqrts_qqq") | 1003 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1004 | 1004 |
| 1005 (define_bypass 3 "neon_shift_2" | 1005 (define_bypass 3 "cortex_a8_neon_shift_2" |
| 1006 "neon_int_1,\ | 1006 "cortex_a8_neon_int_1,\ |
| 1007 neon_int_4,\ | 1007 cortex_a8_neon_int_4,\ |
| 1008 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1008 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1009 neon_mul_qqq_8_16_32_ddd_32,\ | 1009 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1010 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1010 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1011 neon_mla_qqq_8_16,\ | 1011 cortex_a8_neon_mla_qqq_8_16,\ |
| 1012 neon_fp_vadd_ddd_vabs_dd,\ | 1012 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1013 neon_fp_vadd_qqq_vabs_qq,\ | 1013 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1014 neon_fp_vmla_ddd,\ | 1014 cortex_a8_neon_fp_vmla_ddd,\ |
| 1015 neon_fp_vmla_qqq,\ | 1015 cortex_a8_neon_fp_vmla_qqq,\ |
| 1016 neon_fp_vrecps_vrsqrts_ddd,\ | 1016 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1017 neon_fp_vrecps_vrsqrts_qqq") | 1017 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1018 | 1018 |
| 1019 (define_bypass 2 "neon_shift_1" | 1019 (define_bypass 2 "cortex_a8_neon_shift_1" |
| 1020 "neon_int_1,\ | 1020 "cortex_a8_neon_int_1,\ |
| 1021 neon_int_4,\ | 1021 cortex_a8_neon_int_4,\ |
| 1022 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1022 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1023 neon_mul_qqq_8_16_32_ddd_32,\ | 1023 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1024 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1024 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1025 neon_mla_qqq_8_16,\ | 1025 cortex_a8_neon_mla_qqq_8_16,\ |
| 1026 neon_fp_vadd_ddd_vabs_dd,\ | 1026 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1027 neon_fp_vadd_qqq_vabs_qq,\ | 1027 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1028 neon_fp_vmla_ddd,\ | 1028 cortex_a8_neon_fp_vmla_ddd,\ |
| 1029 neon_fp_vmla_qqq,\ | 1029 cortex_a8_neon_fp_vmla_qqq,\ |
| 1030 neon_fp_vrecps_vrsqrts_ddd,\ | 1030 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1031 neon_fp_vrecps_vrsqrts_qqq") | 1031 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1032 | 1032 |
| 1033 (define_bypass 5 "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" | 1033 (define_bypass 5 "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" |
| 1034 "neon_int_1,\ | 1034 "cortex_a8_neon_int_1,\ |
| 1035 neon_int_4,\ | 1035 cortex_a8_neon_int_4,\ |
| 1036 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1036 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1037 neon_mul_qqq_8_16_32_ddd_32,\ | 1037 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1038 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1038 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1039 neon_mla_qqq_8_16,\ | 1039 cortex_a8_neon_mla_qqq_8_16,\ |
| 1040 neon_fp_vadd_ddd_vabs_dd,\ | 1040 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1041 neon_fp_vadd_qqq_vabs_qq,\ | 1041 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1042 neon_fp_vmla_ddd,\ | 1042 cortex_a8_neon_fp_vmla_ddd,\ |
| 1043 neon_fp_vmla_qqq,\ | 1043 cortex_a8_neon_fp_vmla_qqq,\ |
| 1044 neon_fp_vrecps_vrsqrts_ddd,\ | 1044 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1045 neon_fp_vrecps_vrsqrts_qqq") | 1045 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1046 | 1046 |
| 1047 (define_bypass 8 "neon_mul_qqd_32_scalar" | 1047 (define_bypass 8 "cortex_a8_neon_mul_qqd_32_scalar" |
| 1048 "neon_int_1,\ | 1048 "cortex_a8_neon_int_1,\ |
| 1049 neon_int_4,\ | 1049 cortex_a8_neon_int_4,\ |
| 1050 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1050 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1051 neon_mul_qqq_8_16_32_ddd_32,\ | 1051 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1052 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1052 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1053 neon_mla_qqq_8_16,\ | 1053 cortex_a8_neon_mla_qqq_8_16,\ |
| 1054 neon_fp_vadd_ddd_vabs_dd,\ | 1054 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1055 neon_fp_vadd_qqq_vabs_qq,\ | 1055 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1056 neon_fp_vmla_ddd,\ | 1056 cortex_a8_neon_fp_vmla_ddd,\ |
| 1057 neon_fp_vmla_qqq,\ | 1057 cortex_a8_neon_fp_vmla_qqq,\ |
| 1058 neon_fp_vrecps_vrsqrts_ddd,\ | 1058 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1059 neon_fp_vrecps_vrsqrts_qqq") | 1059 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1060 | 1060 |
| 1061 (define_bypass 5 "neon_mul_ddd_16_scalar_32_16_long_scalar" | 1061 (define_bypass 5 "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" |
| 1062 "neon_int_1,\ | 1062 "cortex_a8_neon_int_1,\ |
| 1063 neon_int_4,\ | 1063 cortex_a8_neon_int_4,\ |
| 1064 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1064 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1065 neon_mul_qqq_8_16_32_ddd_32,\ | 1065 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1066 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1066 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1067 neon_mla_qqq_8_16,\ | 1067 cortex_a8_neon_mla_qqq_8_16,\ |
| 1068 neon_fp_vadd_ddd_vabs_dd,\ | 1068 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1069 neon_fp_vadd_qqq_vabs_qq,\ | 1069 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1070 neon_fp_vmla_ddd,\ | 1070 cortex_a8_neon_fp_vmla_ddd,\ |
| 1071 neon_fp_vmla_qqq,\ | 1071 cortex_a8_neon_fp_vmla_qqq,\ |
| 1072 neon_fp_vrecps_vrsqrts_ddd,\ | 1072 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1073 neon_fp_vrecps_vrsqrts_qqq") | 1073 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1074 | 1074 |
| 1075 (define_bypass 8 "neon_mla_qqq_32_qqd_32_scalar" | 1075 (define_bypass 8 "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" |
| 1076 "neon_int_1,\ | 1076 "cortex_a8_neon_int_1,\ |
| 1077 neon_int_4,\ | 1077 cortex_a8_neon_int_4,\ |
| 1078 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1078 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1079 neon_mul_qqq_8_16_32_ddd_32,\ | 1079 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1080 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1080 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1081 neon_mla_qqq_8_16,\ | 1081 cortex_a8_neon_mla_qqq_8_16,\ |
| 1082 neon_fp_vadd_ddd_vabs_dd,\ | 1082 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1083 neon_fp_vadd_qqq_vabs_qq,\ | 1083 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1084 neon_fp_vmla_ddd,\ | 1084 cortex_a8_neon_fp_vmla_ddd,\ |
| 1085 neon_fp_vmla_qqq,\ | 1085 cortex_a8_neon_fp_vmla_qqq,\ |
| 1086 neon_fp_vrecps_vrsqrts_ddd,\ | 1086 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1087 neon_fp_vrecps_vrsqrts_qqq") | 1087 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1088 | 1088 |
| 1089 (define_bypass 6 "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" | 1089 (define_bypass 6 "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" |
| 1090 "neon_int_1,\ | 1090 "cortex_a8_neon_int_1,\ |
| 1091 neon_int_4,\ | 1091 cortex_a8_neon_int_4,\ |
| 1092 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1092 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1093 neon_mul_qqq_8_16_32_ddd_32,\ | 1093 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1094 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1094 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1095 neon_mla_qqq_8_16,\ | 1095 cortex_a8_neon_mla_qqq_8_16,\ |
| 1096 neon_fp_vadd_ddd_vabs_dd,\ | 1096 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1097 neon_fp_vadd_qqq_vabs_qq,\ | 1097 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1098 neon_fp_vmla_ddd,\ | 1098 cortex_a8_neon_fp_vmla_ddd,\ |
| 1099 neon_fp_vmla_qqq,\ | 1099 cortex_a8_neon_fp_vmla_qqq,\ |
| 1100 neon_fp_vrecps_vrsqrts_ddd,\ | 1100 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1101 neon_fp_vrecps_vrsqrts_qqq") | 1101 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1102 | 1102 |
| 1103 (define_bypass 6 "neon_mla_qqq_8_16" | 1103 (define_bypass 6 "cortex_a8_neon_mla_qqq_8_16" |
| 1104 "neon_int_1,\ | 1104 "cortex_a8_neon_int_1,\ |
| 1105 neon_int_4,\ | 1105 cortex_a8_neon_int_4,\ |
| 1106 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1106 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1107 neon_mul_qqq_8_16_32_ddd_32,\ | 1107 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1108 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1108 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1109 neon_mla_qqq_8_16,\ | 1109 cortex_a8_neon_mla_qqq_8_16,\ |
| 1110 neon_fp_vadd_ddd_vabs_dd,\ | 1110 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1111 neon_fp_vadd_qqq_vabs_qq,\ | 1111 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1112 neon_fp_vmla_ddd,\ | 1112 cortex_a8_neon_fp_vmla_ddd,\ |
| 1113 neon_fp_vmla_qqq,\ | 1113 cortex_a8_neon_fp_vmla_qqq,\ |
| 1114 neon_fp_vrecps_vrsqrts_ddd,\ | 1114 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1115 neon_fp_vrecps_vrsqrts_qqq") | 1115 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1116 | 1116 |
| 1117 (define_bypass 5 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" | 1117 (define_bypass 5 "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" |
| 1118 "neon_int_1,\ | 1118 "cortex_a8_neon_int_1,\ |
| 1119 neon_int_4,\ | 1119 cortex_a8_neon_int_4,\ |
| 1120 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1120 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1121 neon_mul_qqq_8_16_32_ddd_32,\ | 1121 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1122 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1122 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1123 neon_mla_qqq_8_16,\ | 1123 cortex_a8_neon_mla_qqq_8_16,\ |
| 1124 neon_fp_vadd_ddd_vabs_dd,\ | 1124 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1125 neon_fp_vadd_qqq_vabs_qq,\ | 1125 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1126 neon_fp_vmla_ddd,\ | 1126 cortex_a8_neon_fp_vmla_ddd,\ |
| 1127 neon_fp_vmla_qqq,\ | 1127 cortex_a8_neon_fp_vmla_qqq,\ |
| 1128 neon_fp_vrecps_vrsqrts_ddd,\ | 1128 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1129 neon_fp_vrecps_vrsqrts_qqq") | 1129 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1130 | 1130 |
| 1131 (define_bypass 6 "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" | 1131 (define_bypass 6 "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" |
| 1132 "neon_int_1,\ | 1132 "cortex_a8_neon_int_1,\ |
| 1133 neon_int_4,\ | 1133 cortex_a8_neon_int_4,\ |
| 1134 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1134 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1135 neon_mul_qqq_8_16_32_ddd_32,\ | 1135 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1136 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1136 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1137 neon_mla_qqq_8_16,\ | 1137 cortex_a8_neon_mla_qqq_8_16,\ |
| 1138 neon_fp_vadd_ddd_vabs_dd,\ | 1138 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1139 neon_fp_vadd_qqq_vabs_qq,\ | 1139 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1140 neon_fp_vmla_ddd,\ | 1140 cortex_a8_neon_fp_vmla_ddd,\ |
| 1141 neon_fp_vmla_qqq,\ | 1141 cortex_a8_neon_fp_vmla_qqq,\ |
| 1142 neon_fp_vrecps_vrsqrts_ddd,\ | 1142 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1143 neon_fp_vrecps_vrsqrts_qqq") | 1143 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1144 | 1144 |
| 1145 (define_bypass 6 "neon_mul_qqq_8_16_32_ddd_32" | 1145 (define_bypass 6 "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" |
| 1146 "neon_int_1,\ | 1146 "cortex_a8_neon_int_1,\ |
| 1147 neon_int_4,\ | 1147 cortex_a8_neon_int_4,\ |
| 1148 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1148 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1149 neon_mul_qqq_8_16_32_ddd_32,\ | 1149 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1150 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1150 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1151 neon_mla_qqq_8_16,\ | 1151 cortex_a8_neon_mla_qqq_8_16,\ |
| 1152 neon_fp_vadd_ddd_vabs_dd,\ | 1152 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1153 neon_fp_vadd_qqq_vabs_qq,\ | 1153 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1154 neon_fp_vmla_ddd,\ | 1154 cortex_a8_neon_fp_vmla_ddd,\ |
| 1155 neon_fp_vmla_qqq,\ | 1155 cortex_a8_neon_fp_vmla_qqq,\ |
| 1156 neon_fp_vrecps_vrsqrts_ddd,\ | 1156 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1157 neon_fp_vrecps_vrsqrts_qqq") | 1157 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1158 | 1158 |
| 1159 (define_bypass 5 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" | 1159 (define_bypass 5 "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" |
| 1160 "neon_int_1,\ | 1160 "cortex_a8_neon_int_1,\ |
| 1161 neon_int_4,\ | 1161 cortex_a8_neon_int_4,\ |
| 1162 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1162 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1163 neon_mul_qqq_8_16_32_ddd_32,\ | 1163 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1164 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1164 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1165 neon_mla_qqq_8_16,\ | 1165 cortex_a8_neon_mla_qqq_8_16,\ |
| 1166 neon_fp_vadd_ddd_vabs_dd,\ | 1166 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1167 neon_fp_vadd_qqq_vabs_qq,\ | 1167 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1168 neon_fp_vmla_ddd,\ | 1168 cortex_a8_neon_fp_vmla_ddd,\ |
| 1169 neon_fp_vmla_qqq,\ | 1169 cortex_a8_neon_fp_vmla_qqq,\ |
| 1170 neon_fp_vrecps_vrsqrts_ddd,\ | 1170 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1171 neon_fp_vrecps_vrsqrts_qqq") | 1171 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1172 | 1172 |
| 1173 (define_bypass 5 "neon_vsma" | 1173 (define_bypass 5 "cortex_a8_neon_vsma" |
| 1174 "neon_int_1,\ | 1174 "cortex_a8_neon_int_1,\ |
| 1175 neon_int_4,\ | 1175 cortex_a8_neon_int_4,\ |
| 1176 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1176 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1177 neon_mul_qqq_8_16_32_ddd_32,\ | 1177 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1178 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1178 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1179 neon_mla_qqq_8_16,\ | 1179 cortex_a8_neon_mla_qqq_8_16,\ |
| 1180 neon_fp_vadd_ddd_vabs_dd,\ | 1180 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1181 neon_fp_vadd_qqq_vabs_qq,\ | 1181 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1182 neon_fp_vmla_ddd,\ | 1182 cortex_a8_neon_fp_vmla_ddd,\ |
| 1183 neon_fp_vmla_qqq,\ | 1183 cortex_a8_neon_fp_vmla_qqq,\ |
| 1184 neon_fp_vrecps_vrsqrts_ddd,\ | 1184 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1185 neon_fp_vrecps_vrsqrts_qqq") | 1185 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1186 | 1186 |
| 1187 (define_bypass 6 "neon_vaba_qqq" | 1187 (define_bypass 6 "cortex_a8_neon_vaba_qqq" |
| 1188 "neon_int_1,\ | 1188 "cortex_a8_neon_int_1,\ |
| 1189 neon_int_4,\ | 1189 cortex_a8_neon_int_4,\ |
| 1190 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1190 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1191 neon_mul_qqq_8_16_32_ddd_32,\ | 1191 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1192 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1192 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1193 neon_mla_qqq_8_16,\ | 1193 cortex_a8_neon_mla_qqq_8_16,\ |
| 1194 neon_fp_vadd_ddd_vabs_dd,\ | 1194 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1195 neon_fp_vadd_qqq_vabs_qq,\ | 1195 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1196 neon_fp_vmla_ddd,\ | 1196 cortex_a8_neon_fp_vmla_ddd,\ |
| 1197 neon_fp_vmla_qqq,\ | 1197 cortex_a8_neon_fp_vmla_qqq,\ |
| 1198 neon_fp_vrecps_vrsqrts_ddd,\ | 1198 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1199 neon_fp_vrecps_vrsqrts_qqq") | 1199 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1200 | 1200 |
| 1201 (define_bypass 5 "neon_vaba" | 1201 (define_bypass 5 "cortex_a8_neon_vaba" |
| 1202 "neon_int_1,\ | 1202 "cortex_a8_neon_int_1,\ |
| 1203 neon_int_4,\ | 1203 cortex_a8_neon_int_4,\ |
| 1204 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1204 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1205 neon_mul_qqq_8_16_32_ddd_32,\ | 1205 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1206 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1206 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1207 neon_mla_qqq_8_16,\ | 1207 cortex_a8_neon_mla_qqq_8_16,\ |
| 1208 neon_fp_vadd_ddd_vabs_dd,\ | 1208 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1209 neon_fp_vadd_qqq_vabs_qq,\ | 1209 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1210 neon_fp_vmla_ddd,\ | 1210 cortex_a8_neon_fp_vmla_ddd,\ |
| 1211 neon_fp_vmla_qqq,\ | 1211 cortex_a8_neon_fp_vmla_qqq,\ |
| 1212 neon_fp_vrecps_vrsqrts_ddd,\ | 1212 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1213 neon_fp_vrecps_vrsqrts_qqq") | 1213 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1214 | 1214 |
| 1215 (define_bypass 2 "neon_vmov" | 1215 (define_bypass 2 "cortex_a8_neon_vmov" |
| 1216 "neon_int_1,\ | 1216 "cortex_a8_neon_int_1,\ |
| 1217 neon_int_4,\ | 1217 cortex_a8_neon_int_4,\ |
| 1218 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1218 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1219 neon_mul_qqq_8_16_32_ddd_32,\ | 1219 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1220 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1220 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1221 neon_mla_qqq_8_16,\ | 1221 cortex_a8_neon_mla_qqq_8_16,\ |
| 1222 neon_fp_vadd_ddd_vabs_dd,\ | 1222 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1223 neon_fp_vadd_qqq_vabs_qq,\ | 1223 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1224 neon_fp_vmla_ddd,\ | 1224 cortex_a8_neon_fp_vmla_ddd,\ |
| 1225 neon_fp_vmla_qqq,\ | 1225 cortex_a8_neon_fp_vmla_qqq,\ |
| 1226 neon_fp_vrecps_vrsqrts_ddd,\ | 1226 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1227 neon_fp_vrecps_vrsqrts_qqq") | 1227 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1228 | 1228 |
| 1229 (define_bypass 3 "neon_vqneg_vqabs" | 1229 (define_bypass 3 "cortex_a8_neon_vqneg_vqabs" |
| 1230 "neon_int_1,\ | 1230 "cortex_a8_neon_int_1,\ |
| 1231 neon_int_4,\ | 1231 cortex_a8_neon_int_4,\ |
| 1232 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1232 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1233 neon_mul_qqq_8_16_32_ddd_32,\ | 1233 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1234 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1234 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1235 neon_mla_qqq_8_16,\ | 1235 cortex_a8_neon_mla_qqq_8_16,\ |
| 1236 neon_fp_vadd_ddd_vabs_dd,\ | 1236 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1237 neon_fp_vadd_qqq_vabs_qq,\ | 1237 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1238 neon_fp_vmla_ddd,\ | 1238 cortex_a8_neon_fp_vmla_ddd,\ |
| 1239 neon_fp_vmla_qqq,\ | 1239 cortex_a8_neon_fp_vmla_qqq,\ |
| 1240 neon_fp_vrecps_vrsqrts_ddd,\ | 1240 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1241 neon_fp_vrecps_vrsqrts_qqq") | 1241 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1242 | 1242 |
| 1243 (define_bypass 3 "neon_int_5" | 1243 (define_bypass 3 "cortex_a8_neon_int_5" |
| 1244 "neon_int_1,\ | 1244 "cortex_a8_neon_int_1,\ |
| 1245 neon_int_4,\ | 1245 cortex_a8_neon_int_4,\ |
| 1246 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1246 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1247 neon_mul_qqq_8_16_32_ddd_32,\ | 1247 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1248 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1248 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1249 neon_mla_qqq_8_16,\ | 1249 cortex_a8_neon_mla_qqq_8_16,\ |
| 1250 neon_fp_vadd_ddd_vabs_dd,\ | 1250 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1251 neon_fp_vadd_qqq_vabs_qq,\ | 1251 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1252 neon_fp_vmla_ddd,\ | 1252 cortex_a8_neon_fp_vmla_ddd,\ |
| 1253 neon_fp_vmla_qqq,\ | 1253 cortex_a8_neon_fp_vmla_qqq,\ |
| 1254 neon_fp_vrecps_vrsqrts_ddd,\ | 1254 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1255 neon_fp_vrecps_vrsqrts_qqq") | 1255 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1256 | 1256 |
| 1257 (define_bypass 3 "neon_int_4" | 1257 (define_bypass 3 "cortex_a8_neon_int_4" |
| 1258 "neon_int_1,\ | 1258 "cortex_a8_neon_int_1,\ |
| 1259 neon_int_4,\ | 1259 cortex_a8_neon_int_4,\ |
| 1260 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1260 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1261 neon_mul_qqq_8_16_32_ddd_32,\ | 1261 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1262 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1262 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1263 neon_mla_qqq_8_16,\ | 1263 cortex_a8_neon_mla_qqq_8_16,\ |
| 1264 neon_fp_vadd_ddd_vabs_dd,\ | 1264 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1265 neon_fp_vadd_qqq_vabs_qq,\ | 1265 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1266 neon_fp_vmla_ddd,\ | 1266 cortex_a8_neon_fp_vmla_ddd,\ |
| 1267 neon_fp_vmla_qqq,\ | 1267 cortex_a8_neon_fp_vmla_qqq,\ |
| 1268 neon_fp_vrecps_vrsqrts_ddd,\ | 1268 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1269 neon_fp_vrecps_vrsqrts_qqq") | 1269 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1270 | 1270 |
| 1271 (define_bypass 2 "neon_int_3" | 1271 (define_bypass 2 "cortex_a8_neon_int_3" |
| 1272 "neon_int_1,\ | 1272 "cortex_a8_neon_int_1,\ |
| 1273 neon_int_4,\ | 1273 cortex_a8_neon_int_4,\ |
| 1274 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1274 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1275 neon_mul_qqq_8_16_32_ddd_32,\ | 1275 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1276 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1276 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1277 neon_mla_qqq_8_16,\ | 1277 cortex_a8_neon_mla_qqq_8_16,\ |
| 1278 neon_fp_vadd_ddd_vabs_dd,\ | 1278 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1279 neon_fp_vadd_qqq_vabs_qq,\ | 1279 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1280 neon_fp_vmla_ddd,\ | 1280 cortex_a8_neon_fp_vmla_ddd,\ |
| 1281 neon_fp_vmla_qqq,\ | 1281 cortex_a8_neon_fp_vmla_qqq,\ |
| 1282 neon_fp_vrecps_vrsqrts_ddd,\ | 1282 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1283 neon_fp_vrecps_vrsqrts_qqq") | 1283 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1284 | 1284 |
| 1285 (define_bypass 2 "neon_int_2" | 1285 (define_bypass 2 "cortex_a8_neon_int_2" |
| 1286 "neon_int_1,\ | 1286 "cortex_a8_neon_int_1,\ |
| 1287 neon_int_4,\ | 1287 cortex_a8_neon_int_4,\ |
| 1288 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1288 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1289 neon_mul_qqq_8_16_32_ddd_32,\ | 1289 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1290 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1290 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1291 neon_mla_qqq_8_16,\ | 1291 cortex_a8_neon_mla_qqq_8_16,\ |
| 1292 neon_fp_vadd_ddd_vabs_dd,\ | 1292 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1293 neon_fp_vadd_qqq_vabs_qq,\ | 1293 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1294 neon_fp_vmla_ddd,\ | 1294 cortex_a8_neon_fp_vmla_ddd,\ |
| 1295 neon_fp_vmla_qqq,\ | 1295 cortex_a8_neon_fp_vmla_qqq,\ |
| 1296 neon_fp_vrecps_vrsqrts_ddd,\ | 1296 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1297 neon_fp_vrecps_vrsqrts_qqq") | 1297 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1298 | 1298 |
| 1299 (define_bypass 2 "neon_int_1" | 1299 (define_bypass 2 "cortex_a8_neon_int_1" |
| 1300 "neon_int_1,\ | 1300 "cortex_a8_neon_int_1,\ |
| 1301 neon_int_4,\ | 1301 cortex_a8_neon_int_4,\ |
| 1302 neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1302 cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1303 neon_mul_qqq_8_16_32_ddd_32,\ | 1303 cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ |
| 1304 neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | 1304 cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ |
| 1305 neon_mla_qqq_8_16,\ | 1305 cortex_a8_neon_mla_qqq_8_16,\ |
| 1306 neon_fp_vadd_ddd_vabs_dd,\ | 1306 cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ |
| 1307 neon_fp_vadd_qqq_vabs_qq,\ | 1307 cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ |
| 1308 neon_fp_vmla_ddd,\ | 1308 cortex_a8_neon_fp_vmla_ddd,\ |
| 1309 neon_fp_vmla_qqq,\ | 1309 cortex_a8_neon_fp_vmla_qqq,\ |
| 1310 neon_fp_vrecps_vrsqrts_ddd,\ | 1310 cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ |
| 1311 neon_fp_vrecps_vrsqrts_qqq") | 1311 cortex_a8_neon_fp_vrecps_vrsqrts_qqq") |
| 1312 | 1312 |