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comparison gcc/config/arm/cortex-a8.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents a06113de4d67
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 ;; ARM Cortex-A8 scheduling description. 1 ;; ARM Cortex-A8 scheduling description.
2 ;; Copyright (C) 2007 Free Software Foundation, Inc. 2 ;; Copyright (C) 2007, 2010 Free Software Foundation, Inc.
3 ;; Contributed by CodeSourcery. 3 ;; Contributed by CodeSourcery.
4 4
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 6
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
45 ;; the case where that instruction consists of only one micro-op... 45 ;; the case where that instruction consists of only one micro-op...
46 (define_reservation "cortex_a8_load_store_1" 46 (define_reservation "cortex_a8_load_store_1"
47 "(cortex_a8_alu0+cortex_a8_issue_ls)|\ 47 "(cortex_a8_alu0+cortex_a8_issue_ls)|\
48 (cortex_a8_alu1+cortex_a8_issue_ls)") 48 (cortex_a8_alu1+cortex_a8_issue_ls)")
49 49
50 ;; ...and in the case of two micro-ops. We don't need to reserve 50 ;; ...and in the case of two micro-ops. Dual issue is altogether forbidden
51 ;; cortex_a8_issue_ls here because dual issue is altogether forbidden
52 ;; during the issue cycle of the first micro-op. (Instead of modelling 51 ;; during the issue cycle of the first micro-op. (Instead of modelling
53 ;; a separate issue unit, we instead reserve alu0 and alu1 to 52 ;; a separate issue unit, we instead reserve alu0 and alu1 to
54 ;; prevent any other instructions from being issued upon that first cycle.) 53 ;; prevent any other instructions from being issued upon that first cycle.)
55 ;; Even though the load/store pipeline is usually available in either 54 ;; Even though the load/store pipeline is usually available in either
56 ;; ALU pipe, multi-cycle instructions always issue in pipeline 0. This 55 ;; ALU pipe, multi-cycle instructions always issue in pipeline 0.
57 ;; reservation is therefore the same as cortex_a8_multiply_2 below.
58 (define_reservation "cortex_a8_load_store_2" 56 (define_reservation "cortex_a8_load_store_2"
59 "cortex_a8_alu0+cortex_a8_alu1,\ 57 "cortex_a8_alu0+cortex_a8_alu1+cortex_a8_issue_ls,\
60 cortex_a8_alu0") 58 cortex_a8_alu0+cortex_a8_issue_ls")
61 59
62 ;; The flow of a single-cycle multiplication. 60 ;; The flow of a single-cycle multiplication.
63 (define_reservation "cortex_a8_multiply" 61 (define_reservation "cortex_a8_multiply"
64 "cortex_a8_alu0") 62 "cortex_a8_alu0")
65 63
85 83
86 ;; We include CLZ with these since it has the same execution pattern 84 ;; We include CLZ with these since it has the same execution pattern
87 ;; (source read in E2 and destination available at the end of that cycle). 85 ;; (source read in E2 and destination available at the end of that cycle).
88 (define_insn_reservation "cortex_a8_alu" 2 86 (define_insn_reservation "cortex_a8_alu" 2
89 (and (eq_attr "tune" "cortexa8") 87 (and (eq_attr "tune" "cortexa8")
90 (ior (and (eq_attr "type" "alu") 88 (ior (and (and (eq_attr "type" "alu")
91 (not (eq_attr "insn" "mov,mvn"))) 89 (eq_attr "neon_type" "none"))
90 (not (eq_attr "insn" "mov,mvn")))
92 (eq_attr "insn" "clz"))) 91 (eq_attr "insn" "clz")))
93 "cortex_a8_default") 92 "cortex_a8_default")
94 93
95 (define_insn_reservation "cortex_a8_alu_shift" 2 94 (define_insn_reservation "cortex_a8_alu_shift" 2
96 (and (eq_attr "tune" "cortexa8") 95 (and (eq_attr "tune" "cortexa8")