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comparison gcc/config/arm/fpa.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 77e2b8dfacca
children
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
81 (and (eq_attr "fpu" "fpa") 81 (and (eq_attr "fpu" "fpa")
82 (eq_attr "type" "f_2_r")) 82 (eq_attr "type" "f_2_r"))
83 "core+fpa*2") 83 "core+fpa*2")
84 84
85 (define_insn_reservation "f_load" 3 85 (define_insn_reservation "f_load" 3
86 (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_load")) 86 (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_fpa_load"))
87 "fpa_mem+core*3") 87 "fpa_mem+core*3")
88 88
89 (define_insn_reservation "f_store" 4 89 (define_insn_reservation "f_store" 4
90 (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_store")) 90 (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_fpa_store"))
91 "core*4") 91 "core*4")
92 92
93 (define_insn_reservation "r_mem_f" 6 93 (define_insn_reservation "r_mem_f" 6
94 (and (eq_attr "model_wbuf" "no") 94 (and (eq_attr "model_wbuf" "no")
95 (and (eq_attr "fpu" "fpa") (eq_attr "type" "r_mem_f"))) 95 (and (eq_attr "fpu" "fpa") (eq_attr "type" "r_mem_f")))
543 ldr%?\\t%0, %1\\t%@ float 543 ldr%?\\t%0, %1\\t%@ float
544 str%?\\t%1, %0\\t%@ float" 544 str%?\\t%1, %0\\t%@ float"
545 [(set_attr "length" "4,4,4,4,8,8,4,4,4") 545 [(set_attr "length" "4,4,4,4,8,8,4,4,4")
546 (set_attr "predicable" "yes") 546 (set_attr "predicable" "yes")
547 (set_attr "type" 547 (set_attr "type"
548 "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load1,store1") 548 "ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*,load1,store1")
549 (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*") 549 (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
550 (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,4084,*")] 550 (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,4084,*")]
551 ) 551 )
552 552
553 (define_insn "*movdf_fpa" 553 (define_insn "*movdf_fpa"
578 } 578 }
579 " 579 "
580 [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8") 580 [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
581 (set_attr "predicable" "yes") 581 (set_attr "predicable" "yes")
582 (set_attr "type" 582 (set_attr "type"
583 "load1,store2,*,store2,load1,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r") 583 "load1,store2,*,store2,load1,ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r")
584 (set_attr "pool_range" "*,*,*,*,1020,*,*,1024,*,*,*") 584 (set_attr "pool_range" "*,*,*,*,1020,*,*,1024,*,*,*")
585 (set_attr "neg_pool_range" "*,*,*,*,1008,*,*,1008,*,*,*")] 585 (set_attr "neg_pool_range" "*,*,*,*,1008,*,*,1008,*,*,*")]
586 ) 586 )
587 587
588 ;; We treat XFmode as meaning 'internal format'. It's the right size and we 588 ;; We treat XFmode as meaning 'internal format'. It's the right size and we
607 return \"sfm%?\\t%1, 1, %0\"; 607 return \"sfm%?\\t%1, 1, %0\";
608 } 608 }
609 " 609 "
610 [(set_attr "length" "4,4,4") 610 [(set_attr "length" "4,4,4")
611 (set_attr "predicable" "yes") 611 (set_attr "predicable" "yes")
612 (set_attr "type" "ffarith,f_load,f_store")] 612 (set_attr "type" "ffarith,f_fpa_load,f_fpa_store")]
613 ) 613 )
614 614
615 ;; stfs/ldfs always use a conditional infix. This works around the 615 ;; stfs/ldfs always use a conditional infix. This works around the
616 ;; ambiguity between "stf pl s" and "sftp ls". 616 ;; ambiguity between "stf pl s" and "sftp ls".
617 (define_insn "*thumb2_movsf_fpa" 617 (define_insn "*thumb2_movsf_fpa"
633 str%?\\t%1, %0\\t%@ float" 633 str%?\\t%1, %0\\t%@ float"
634 [(set_attr "length" "4,4,4,4,8,8,4,4,4") 634 [(set_attr "length" "4,4,4,4,8,8,4,4,4")
635 (set_attr "ce_count" "1,1,1,1,2,2,1,1,1") 635 (set_attr "ce_count" "1,1,1,1,2,2,1,1,1")
636 (set_attr "predicable" "yes") 636 (set_attr "predicable" "yes")
637 (set_attr "type" 637 (set_attr "type"
638 "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load1,store1") 638 "ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*,load1,store1")
639 (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*") 639 (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
640 (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,0,*")] 640 (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,0,*")]
641 ) 641 )
642 642
643 ;; Not predicable because we don't know the number of instructions. 643 ;; Not predicable because we don't know the number of instructions.
667 } 667 }
668 } 668 }
669 " 669 "
670 [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8") 670 [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
671 (set_attr "type" 671 (set_attr "type"
672 "load1,store2,*,store2,load1,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r") 672 "load1,store2,*,store2,load1,ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r")
673 (set_attr "pool_range" "*,*,*,*,4092,*,*,1024,*,*,*") 673 (set_attr "pool_range" "*,*,*,*,4092,*,*,1024,*,*,*")
674 (set_attr "neg_pool_range" "*,*,*,*,0,*,*,1020,*,*,*")] 674 (set_attr "neg_pool_range" "*,*,*,*,0,*,*,1020,*,*,*")]
675 ) 675 )
676 676
677 ;; Saving and restoring the floating point registers in the prologue should 677 ;; Saving and restoring the floating point registers in the prologue should
696 case 5: return output_mov_long_double_arm_from_fpa (operands); 696 case 5: return output_mov_long_double_arm_from_fpa (operands);
697 case 6: return output_mov_long_double_arm_from_arm (operands); 697 case 6: return output_mov_long_double_arm_from_arm (operands);
698 } 698 }
699 " 699 "
700 [(set_attr "length" "4,4,4,4,8,8,12") 700 [(set_attr "length" "4,4,4,4,8,8,12")
701 (set_attr "type" "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*") 701 (set_attr "type" "ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*")
702 (set_attr "pool_range" "*,*,1024,*,*,*,*") 702 (set_attr "pool_range" "*,*,1024,*,*,*,*")
703 (set_attr "neg_pool_range" "*,*,1004,*,*,*,*")] 703 (set_attr "neg_pool_range" "*,*,1004,*,*,*,*")]
704 ) 704 )
705 705
706 (define_insn "*cmpsf_fpa" 706 (define_insn "*cmpsf_fpa"