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comparison gcc/config/arm/neon.ml @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents b7f97abdc517
children
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
707 let pf_su_8_64 = P8 :: P16 :: F32 :: su_8_64 707 let pf_su_8_64 = P8 :: P16 :: F32 :: su_8_64
708 708
709 let ops = 709 let ops =
710 [ 710 [
711 (* Addition. *) 711 (* Addition. *)
712 Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_64; 712 Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_32;
713 Vadd, [No_op], All (3, Dreg), "vadd", sign_invar_2, [S64; U64];
713 Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64; 714 Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64;
714 Vadd, [], Long, "vaddl", elts_same_2, su_8_32; 715 Vadd, [], Long, "vaddl", elts_same_2, su_8_32;
715 Vadd, [], Wide, "vaddw", elts_same_2, su_8_32; 716 Vadd, [], Wide, "vaddw", elts_same_2, su_8_32;
716 Vadd, [Halving], All (3, Dreg), "vhadd", elts_same_2, su_8_32; 717 Vadd, [Halving], All (3, Dreg), "vhadd", elts_same_2, su_8_32;
717 Vadd, [Halving], All (3, Qreg), "vhaddQ", elts_same_2, su_8_32; 718 Vadd, [Halving], All (3, Qreg), "vhaddQ", elts_same_2, su_8_32;
756 Vmls, [], All (3, Qreg), "vmlsQ", sign_invar_io, F32 :: su_8_32; 757 Vmls, [], All (3, Qreg), "vmlsQ", sign_invar_io, F32 :: su_8_32;
757 Vmls, [], Long, "vmlsl", elts_same_io, su_8_32; 758 Vmls, [], Long, "vmlsl", elts_same_io, su_8_32;
758 Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32]; 759 Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32];
759 760
760 (* Subtraction. *) 761 (* Subtraction. *)
761 Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_64; 762 Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_32;
763 Vsub, [No_op], All (3, Dreg), "vsub", sign_invar_2, [S64; U64];
762 Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64; 764 Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64;
763 Vsub, [], Long, "vsubl", elts_same_2, su_8_32; 765 Vsub, [], Long, "vsubl", elts_same_2, su_8_32;
764 Vsub, [], Wide, "vsubw", elts_same_2, su_8_32; 766 Vsub, [], Wide, "vsubw", elts_same_2, su_8_32;
765 Vsub, [Halving], All (3, Dreg), "vhsub", elts_same_2, su_8_32; 767 Vsub, [Halving], All (3, Dreg), "vhsub", elts_same_2, su_8_32;
766 Vsub, [Halving], All (3, Qreg), "vhsubQ", elts_same_2, su_8_32; 768 Vsub, [Halving], All (3, Qreg), "vhsubQ", elts_same_2, su_8_32;
965 [InfoWord; Disassembles_as [Use_operands [| Corereg; Element_of_dreg |]]; 967 [InfoWord; Disassembles_as [Use_operands [| Corereg; Element_of_dreg |]];
966 Instruction_name ["vmov"]], 968 Instruction_name ["vmov"]],
967 Use_operands [| Corereg; Dreg; Immed |], 969 Use_operands [| Corereg; Dreg; Immed |],
968 "vget_lane", get_lane, pf_su_8_32; 970 "vget_lane", get_lane, pf_su_8_32;
969 Vget_lane, 971 Vget_lane,
970 [InfoWord; 972 [No_op;
973 InfoWord;
971 Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]]; 974 Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]];
972 Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], 975 Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
973 Use_operands [| Corereg; Dreg; Immed |], 976 Use_operands [| Corereg; Dreg; Immed |],
974 "vget_lane", notype_2, [S64; U64]; 977 "vget_lane", notype_2, [S64; U64];
975 Vget_lane, 978 Vget_lane,
987 (* Set lanes in a vector. *) 990 (* Set lanes in a vector. *)
988 Vset_lane, [Disassembles_as [Use_operands [| Element_of_dreg; Corereg |]]; 991 Vset_lane, [Disassembles_as [Use_operands [| Element_of_dreg; Corereg |]];
989 Instruction_name ["vmov"]], 992 Instruction_name ["vmov"]],
990 Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane", 993 Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
991 set_lane, pf_su_8_32; 994 set_lane, pf_su_8_32;
992 Vset_lane, [Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]; 995 Vset_lane, [No_op;
996 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]];
993 Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], 997 Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
994 Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane", 998 Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
995 set_lane_notype, [S64; U64]; 999 set_lane_notype, [S64; U64];
996 Vset_lane, [Disassembles_as [Use_operands [| Element_of_dreg; Corereg |]]; 1000 Vset_lane, [Disassembles_as [Use_operands [| Element_of_dreg; Corereg |]];
997 Instruction_name ["vmov"]], 1001 Instruction_name ["vmov"]],
1015 Alternatives [ Corereg; 1019 Alternatives [ Corereg;
1016 Element_of_dreg ] |]]], 1020 Element_of_dreg ] |]]],
1017 Use_operands [| Dreg; Corereg |], "vdup_n", bits_1, 1021 Use_operands [| Dreg; Corereg |], "vdup_n", bits_1,
1018 pf_su_8_32; 1022 pf_su_8_32;
1019 Vdup_n, 1023 Vdup_n,
1020 [Instruction_name ["vmov"]; 1024 [No_op;
1025 Instruction_name ["vmov"];
1021 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]], 1026 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
1022 Use_operands [| Dreg; Corereg |], "vdup_n", notype_1, 1027 Use_operands [| Dreg; Corereg |], "vdup_n", notype_1,
1023 [S64; U64]; 1028 [S64; U64];
1024 Vdup_n, 1029 Vdup_n,
1025 [Disassembles_as [Use_operands [| Qreg; 1030 [Disassembles_as [Use_operands [| Qreg;
1026 Alternatives [ Corereg; 1031 Alternatives [ Corereg;
1027 Element_of_dreg ] |]]], 1032 Element_of_dreg ] |]]],
1028 Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1, 1033 Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1,
1029 pf_su_8_32; 1034 pf_su_8_32;
1030 Vdup_n, 1035 Vdup_n,
1031 [Instruction_name ["vmov"]; 1036 [No_op;
1037 Instruction_name ["vmov"];
1032 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]; 1038 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
1033 Use_operands [| Dreg; Corereg; Corereg |]]], 1039 Use_operands [| Dreg; Corereg; Corereg |]]],
1034 Use_operands [| Qreg; Corereg |], "vdupQ_n", notype_1, 1040 Use_operands [| Qreg; Corereg |], "vdupQ_n", notype_1,
1035 [S64; U64]; 1041 [S64; U64];
1036 1042
1041 Alternatives [ Corereg; 1047 Alternatives [ Corereg;
1042 Element_of_dreg ] |]]], 1048 Element_of_dreg ] |]]],
1043 Use_operands [| Dreg; Corereg |], 1049 Use_operands [| Dreg; Corereg |],
1044 "vmov_n", bits_1, pf_su_8_32; 1050 "vmov_n", bits_1, pf_su_8_32;
1045 Vmov_n, 1051 Vmov_n,
1046 [Builtin_name "vdup_n"; 1052 [No_op;
1053 Builtin_name "vdup_n";
1047 Instruction_name ["vmov"]; 1054 Instruction_name ["vmov"];
1048 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]], 1055 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
1049 Use_operands [| Dreg; Corereg |], 1056 Use_operands [| Dreg; Corereg |],
1050 "vmov_n", notype_1, [S64; U64]; 1057 "vmov_n", notype_1, [S64; U64];
1051 Vmov_n, 1058 Vmov_n,
1054 Alternatives [ Corereg; 1061 Alternatives [ Corereg;
1055 Element_of_dreg ] |]]], 1062 Element_of_dreg ] |]]],
1056 Use_operands [| Qreg; Corereg |], 1063 Use_operands [| Qreg; Corereg |],
1057 "vmovQ_n", bits_1, pf_su_8_32; 1064 "vmovQ_n", bits_1, pf_su_8_32;
1058 Vmov_n, 1065 Vmov_n,
1059 [Builtin_name "vdupQ_n"; 1066 [No_op;
1067 Builtin_name "vdupQ_n";
1060 Instruction_name ["vmov"]; 1068 Instruction_name ["vmov"];
1061 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]; 1069 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
1062 Use_operands [| Dreg; Corereg; Corereg |]]], 1070 Use_operands [| Dreg; Corereg; Corereg |]]],
1063 Use_operands [| Qreg; Corereg |], 1071 Use_operands [| Qreg; Corereg |],
1064 "vmovQ_n", notype_1, [S64; U64]; 1072 "vmovQ_n", notype_1, [S64; U64];
1611 CstPtrTo Corereg |]]], 1619 CstPtrTo Corereg |]]],
1612 Use_operands [| PtrTo Corereg; VecArray (4, Qreg); Immed |], "vst4Q_lane", 1620 Use_operands [| PtrTo Corereg; VecArray (4, Qreg); Immed |], "vst4Q_lane",
1613 store_3, [P16; F32; U16; U32; S16; S32]; 1621 store_3, [P16; F32; U16; U32; S16; S32];
1614 1622
1615 (* Logical operations. And. *) 1623 (* Logical operations. And. *)
1616 Vand, [], All (3, Dreg), "vand", notype_2, su_8_64; 1624 Vand, [], All (3, Dreg), "vand", notype_2, su_8_32;
1625 Vand, [No_op], All (3, Dreg), "vand", notype_2, [S64; U64];
1617 Vand, [], All (3, Qreg), "vandQ", notype_2, su_8_64; 1626 Vand, [], All (3, Qreg), "vandQ", notype_2, su_8_64;
1618 1627
1619 (* Or. *) 1628 (* Or. *)
1620 Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_64; 1629 Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_32;
1630 Vorr, [No_op], All (3, Dreg), "vorr", notype_2, [S64; U64];
1621 Vorr, [], All (3, Qreg), "vorrQ", notype_2, su_8_64; 1631 Vorr, [], All (3, Qreg), "vorrQ", notype_2, su_8_64;
1622 1632
1623 (* Eor. *) 1633 (* Eor. *)
1624 Veor, [], All (3, Dreg), "veor", notype_2, su_8_64; 1634 Veor, [], All (3, Dreg), "veor", notype_2, su_8_32;
1635 Veor, [No_op], All (3, Dreg), "veor", notype_2, [S64; U64];
1625 Veor, [], All (3, Qreg), "veorQ", notype_2, su_8_64; 1636 Veor, [], All (3, Qreg), "veorQ", notype_2, su_8_64;
1626 1637
1627 (* Bic (And-not). *) 1638 (* Bic (And-not). *)
1628 Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_64; 1639 Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_32;
1640 Vbic, [No_op], All (3, Dreg), "vbic", notype_2, [S64; U64];
1629 Vbic, [], All (3, Qreg), "vbicQ", notype_2, su_8_64; 1641 Vbic, [], All (3, Qreg), "vbicQ", notype_2, su_8_64;
1630 1642
1631 (* Or-not. *) 1643 (* Or-not. *)
1632 Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_64; 1644 Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_32;
1645 Vorn, [No_op], All (3, Dreg), "vorn", notype_2, [S64; U64];
1633 Vorn, [], All (3, Qreg), "vornQ", notype_2, su_8_64; 1646 Vorn, [], All (3, Qreg), "vornQ", notype_2, su_8_64;
1634 ] 1647 ]
1635 1648
1636 let reinterp = 1649 let reinterp =
1637 let elems = P8 :: P16 :: F32 :: su_8_64 in 1650 let elems = P8 :: P16 :: F32 :: su_8_64 in