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comparison gcc/config/i386/ppro.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents a06113de4d67
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 ;; Scheduling for the Intel P6 family of processors 1 ;; Scheduling for the Intel P6 family of processors
2 ;; Copyright (C) 2004, 2005, 2007, 2008 Free Software Foundation, Inc. 2 ;; Copyright (C) 2004, 2005, 2007, 2008, 2010 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify 6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by 7 ;; it under the terms of the GNU General Public License as published by
729 ;; reg-reg instructions produce 1 uop so they can be decoded on any of 729 ;; reg-reg instructions produce 1 uop so they can be decoded on any of
730 ;; the three decoders. 730 ;; the three decoders.
731 (define_insn_reservation "ppro_insn" 1 731 (define_insn_reservation "ppro_insn" 1
732 (and (eq_attr "cpu" "pentiumpro") 732 (and (eq_attr "cpu" "pentiumpro")
733 (and (eq_attr "memory" "none,unknown") 733 (and (eq_attr "memory" "none,unknown")
734 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp"))) 734 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
735 "decodern,(p0|p1)") 735 "decodern,(p0|p1)")
736 736
737 ;; read-modify and register-memory instructions have 2 or three uops, 737 ;; read-modify and register-memory instructions have 2 or three uops,
738 ;; so they have to be decoded on decoder0. 738 ;; so they have to be decoded on decoder0.
739 (define_insn_reservation "ppro_insn_load" 3 739 (define_insn_reservation "ppro_insn_load" 3
740 (and (eq_attr "cpu" "pentiumpro") 740 (and (eq_attr "cpu" "pentiumpro")
741 (and (eq_attr "memory" "load") 741 (and (eq_attr "memory" "load")
742 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp"))) 742 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
743 "decoder0,p2+(p0|p1)") 743 "decoder0,p2+(p0|p1)")
744 744
745 (define_insn_reservation "ppro_insn_store" 1 745 (define_insn_reservation "ppro_insn_store" 1
746 (and (eq_attr "cpu" "pentiumpro") 746 (and (eq_attr "cpu" "pentiumpro")
747 (and (eq_attr "memory" "store") 747 (and (eq_attr "memory" "store")
748 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp"))) 748 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
749 "decoder0,(p0|p1),p4+p3") 749 "decoder0,(p0|p1),p4+p3")
750 750
751 ;; read-modify-store instructions produce 4 uops so they have to be 751 ;; read-modify-store instructions produce 4 uops so they have to be
752 ;; decoded on decoder0 as well. 752 ;; decoded on decoder0 as well.
753 (define_insn_reservation "ppro_insn_both" 4 753 (define_insn_reservation "ppro_insn_both" 4
754 (and (eq_attr "cpu" "pentiumpro") 754 (and (eq_attr "cpu" "pentiumpro")
755 (and (eq_attr "memory" "both") 755 (and (eq_attr "memory" "both")
756 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp"))) 756 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
757 "decoder0,p2+(p0|p1),p4+p3") 757 "decoder0,p2+(p0|p1),p4+p3")
758 758