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comparison gcc/config/ia64/div.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 77e2b8dfacca
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 ;; Copyright (C) 2007, 2008, 2009 Free Software Foundation, Inc. 1 ;; Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
2 ;; 2 ;;
3 ;; This file is part of GCC. 3 ;; This file is part of GCC.
4 ;; 4 ;;
5 ;; GCC is free software; you can redistribute it and/or modify 5 ;; GCC is free software; you can redistribute it and/or modify
6 ;; it under the terms of the GNU General Public License as published by 6 ;; it under the terms of the GNU General Public License as published by
35 35
36 ;; Basic plus/minus/mult operations 36 ;; Basic plus/minus/mult operations
37 37
38 (define_insn "addrf3_cond" 38 (define_insn "addrf3_cond"
39 [(set (match_operand:RF 0 "fr_register_operand" "=f,f") 39 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
40 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c") 40 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
41 (const_int 0)) 41 (const_int 0))
42 (plus:RF 42 (plus:RF
43 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG") 43 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
44 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")) 44 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
45 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H"))) 45 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
50 [(set_attr "itanium_class" "fmac") 50 [(set_attr "itanium_class" "fmac")
51 (set_attr "predicable" "no")]) 51 (set_attr "predicable" "no")])
52 52
53 (define_insn "subrf3_cond" 53 (define_insn "subrf3_cond"
54 [(set (match_operand:RF 0 "fr_register_operand" "=f,f") 54 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
55 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c") 55 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
56 (const_int 0)) 56 (const_int 0))
57 (minus:RF 57 (minus:RF
58 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG") 58 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
59 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")) 59 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
60 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H"))) 60 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
65 [(set_attr "itanium_class" "fmac") 65 [(set_attr "itanium_class" "fmac")
66 (set_attr "predicable" "no")]) 66 (set_attr "predicable" "no")])
67 67
68 (define_insn "mulrf3_cond" 68 (define_insn "mulrf3_cond"
69 [(set (match_operand:RF 0 "fr_register_operand" "=f,f") 69 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
70 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c") 70 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
71 (const_int 0)) 71 (const_int 0))
72 (mult:RF 72 (mult:RF
73 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG") 73 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
74 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")) 74 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
75 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H"))) 75 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
82 82
83 ;; neg-mult operation 83 ;; neg-mult operation
84 84
85 (define_insn "nmulrf3_cond" 85 (define_insn "nmulrf3_cond"
86 [(set (match_operand:RF 0 "fr_register_operand" "=f,f") 86 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
87 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c") 87 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
88 (const_int 0)) 88 (const_int 0))
89 (neg:RF (mult:RF 89 (neg:RF (mult:RF
90 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG") 90 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
91 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))) 91 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")))
92 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H"))) 92 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
99 99
100 ;; add-mult/sub-mult operations (mult as op1) 100 ;; add-mult/sub-mult operations (mult as op1)
101 101
102 (define_insn "m1addrf4_cond" 102 (define_insn "m1addrf4_cond"
103 [(set (match_operand:RF 0 "fr_register_operand" "=f,f") 103 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
104 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c") 104 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
105 (const_int 0)) 105 (const_int 0))
106 (plus:RF 106 (plus:RF
107 (mult:RF 107 (mult:RF
108 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG") 108 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
109 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")) 109 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
116 [(set_attr "itanium_class" "fmac") 116 [(set_attr "itanium_class" "fmac")
117 (set_attr "predicable" "no")]) 117 (set_attr "predicable" "no")])
118 118
119 (define_insn "m1subrf4_cond" 119 (define_insn "m1subrf4_cond"
120 [(set (match_operand:RF 0 "fr_register_operand" "=f,f") 120 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
121 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c") 121 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
122 (const_int 0)) 122 (const_int 0))
123 (minus:RF 123 (minus:RF
124 (mult:RF 124 (mult:RF
125 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG") 125 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
126 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")) 126 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
135 135
136 ;; add-mult/sub-mult operations (mult as op2) 136 ;; add-mult/sub-mult operations (mult as op2)
137 137
138 (define_insn "m2addrf4_cond" 138 (define_insn "m2addrf4_cond"
139 [(set (match_operand:RF 0 "fr_register_operand" "=f,f") 139 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
140 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c") 140 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
141 (const_int 0)) 141 (const_int 0))
142 (plus:RF 142 (plus:RF
143 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG") 143 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
144 (mult:RF 144 (mult:RF
145 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG") 145 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")
152 [(set_attr "itanium_class" "fmac") 152 [(set_attr "itanium_class" "fmac")
153 (set_attr "predicable" "no")]) 153 (set_attr "predicable" "no")])
154 154
155 (define_insn "m2subrf4_cond" 155 (define_insn "m2subrf4_cond"
156 [(set (match_operand:RF 0 "fr_register_operand" "=f,f") 156 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
157 (if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c") 157 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
158 (const_int 0)) 158 (const_int 0))
159 (minus:RF 159 (minus:RF
160 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG") 160 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
161 (mult:RF 161 (mult:RF
162 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG") 162 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")
253 (define_insn "recip_approx_rf" 253 (define_insn "recip_approx_rf"
254 [(set (match_operand:RF 0 "fr_register_operand" "=f") 254 [(set (match_operand:RF 0 "fr_register_operand" "=f")
255 (unspec:RF [(match_operand:RF 1 "fr_reg_or_fp01_operand" "fG") 255 (unspec:RF [(match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")
256 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG")] 256 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG")]
257 UNSPEC_FR_RECIP_APPROX_RES)) 257 UNSPEC_FR_RECIP_APPROX_RES))
258 (set (match_operand:BI 3 "register_operand" "=c") 258 (set (match_operand:CCI 3 "register_operand" "=c")
259 (unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX)) 259 (unspec:CCI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX))
260 (use (match_operand:SI 4 "const_int_operand" ""))] 260 (use (match_operand:SI 4 "const_int_operand" ""))]
261 "" 261 ""
262 "frcpa.s%4 %0, %3 = %F1, %F2" 262 "frcpa.s%4 %0, %3 = %F1, %F2"
263 [(set_attr "itanium_class" "fmisc") 263 [(set_attr "itanium_class" "fmisc")
264 (set_attr "predicable" "no")]) 264 (set_attr "predicable" "no")])
295 rtx y1 = gen_reg_rtx (RFmode); 295 rtx y1 = gen_reg_rtx (RFmode);
296 rtx y2 = gen_reg_rtx (RFmode); 296 rtx y2 = gen_reg_rtx (RFmode);
297 rtx q = gen_reg_rtx (RFmode); 297 rtx q = gen_reg_rtx (RFmode);
298 rtx r = gen_reg_rtx (RFmode); 298 rtx r = gen_reg_rtx (RFmode);
299 rtx q_res = gen_reg_rtx (RFmode); 299 rtx q_res = gen_reg_rtx (RFmode);
300 rtx cond = gen_reg_rtx (BImode); 300 rtx cond = gen_reg_rtx (CCImode);
301 rtx zero = CONST0_RTX (RFmode); 301 rtx zero = CONST0_RTX (RFmode);
302 rtx one = CONST1_RTX (RFmode); 302 rtx one = CONST1_RTX (RFmode);
303 rtx status0 = CONST0_RTX (SImode); 303 rtx status0 = CONST0_RTX (SImode);
304 rtx status1 = CONST1_RTX (SImode); 304 rtx status1 = CONST1_RTX (SImode);
305 rtx trunc_sgl = CONST0_RTX (SImode); 305 rtx trunc_sgl = CONST0_RTX (SImode);
343 rtx e1 = gen_reg_rtx (RFmode); 343 rtx e1 = gen_reg_rtx (RFmode);
344 rtx y1 = gen_reg_rtx (RFmode); 344 rtx y1 = gen_reg_rtx (RFmode);
345 rtx q1 = gen_reg_rtx (RFmode); 345 rtx q1 = gen_reg_rtx (RFmode);
346 rtx r = gen_reg_rtx (RFmode); 346 rtx r = gen_reg_rtx (RFmode);
347 rtx q_res = gen_reg_rtx (RFmode); 347 rtx q_res = gen_reg_rtx (RFmode);
348 rtx cond = gen_reg_rtx (BImode); 348 rtx cond = gen_reg_rtx (CCImode);
349 rtx zero = CONST0_RTX (RFmode); 349 rtx zero = CONST0_RTX (RFmode);
350 rtx one = CONST1_RTX (RFmode); 350 rtx one = CONST1_RTX (RFmode);
351 rtx status0 = CONST0_RTX (SImode); 351 rtx status0 = CONST0_RTX (SImode);
352 rtx status1 = CONST1_RTX (SImode); 352 rtx status1 = CONST1_RTX (SImode);
353 rtx trunc_sgl = CONST0_RTX (SImode); 353 rtx trunc_sgl = CONST0_RTX (SImode);
412 rtx y2 = gen_reg_rtx (RFmode); 412 rtx y2 = gen_reg_rtx (RFmode);
413 rtx e2 = gen_reg_rtx (RFmode); 413 rtx e2 = gen_reg_rtx (RFmode);
414 rtx y3 = gen_reg_rtx (RFmode); 414 rtx y3 = gen_reg_rtx (RFmode);
415 rtx q = gen_reg_rtx (RFmode); 415 rtx q = gen_reg_rtx (RFmode);
416 rtx r = gen_reg_rtx (RFmode); 416 rtx r = gen_reg_rtx (RFmode);
417 rtx cond = gen_reg_rtx (BImode); 417 rtx cond = gen_reg_rtx (CCImode);
418 rtx zero = CONST0_RTX (RFmode); 418 rtx zero = CONST0_RTX (RFmode);
419 rtx one = CONST1_RTX (RFmode); 419 rtx one = CONST1_RTX (RFmode);
420 rtx status0 = CONST0_RTX (SImode); 420 rtx status0 = CONST0_RTX (SImode);
421 rtx status1 = CONST1_RTX (SImode); 421 rtx status1 = CONST1_RTX (SImode);
422 rtx trunc_dbl = CONST1_RTX (SImode); 422 rtx trunc_dbl = CONST1_RTX (SImode);
469 rtx e2 = gen_reg_rtx (RFmode); 469 rtx e2 = gen_reg_rtx (RFmode);
470 rtx q2 = gen_reg_rtx (RFmode); 470 rtx q2 = gen_reg_rtx (RFmode);
471 rtx e3 = gen_reg_rtx (RFmode); 471 rtx e3 = gen_reg_rtx (RFmode);
472 rtx q = gen_reg_rtx (RFmode); 472 rtx q = gen_reg_rtx (RFmode);
473 rtx r1 = gen_reg_rtx (RFmode); 473 rtx r1 = gen_reg_rtx (RFmode);
474 rtx cond = gen_reg_rtx (BImode); 474 rtx cond = gen_reg_rtx (CCImode);
475 rtx zero = CONST0_RTX (RFmode); 475 rtx zero = CONST0_RTX (RFmode);
476 rtx one = CONST1_RTX (RFmode); 476 rtx one = CONST1_RTX (RFmode);
477 rtx status0 = CONST0_RTX (SImode); 477 rtx status0 = CONST0_RTX (SImode);
478 rtx status1 = CONST1_RTX (SImode); 478 rtx status1 = CONST1_RTX (SImode);
479 rtx trunc_dbl = CONST1_RTX (SImode); 479 rtx trunc_dbl = CONST1_RTX (SImode);
533 rtx e3 = gen_reg_rtx (RFmode); 533 rtx e3 = gen_reg_rtx (RFmode);
534 rtx e4 = gen_reg_rtx (RFmode); 534 rtx e4 = gen_reg_rtx (RFmode);
535 rtx q = gen_reg_rtx (RFmode); 535 rtx q = gen_reg_rtx (RFmode);
536 rtx r = gen_reg_rtx (RFmode); 536 rtx r = gen_reg_rtx (RFmode);
537 rtx r1 = gen_reg_rtx (RFmode); 537 rtx r1 = gen_reg_rtx (RFmode);
538 rtx cond = gen_reg_rtx (BImode); 538 rtx cond = gen_reg_rtx (CCImode);
539 rtx zero = CONST0_RTX (RFmode); 539 rtx zero = CONST0_RTX (RFmode);
540 rtx one = CONST1_RTX (RFmode); 540 rtx one = CONST1_RTX (RFmode);
541 rtx status0 = CONST0_RTX (SImode); 541 rtx status0 = CONST0_RTX (SImode);
542 rtx status1 = CONST1_RTX (SImode); 542 rtx status1 = CONST1_RTX (SImode);
543 rtx trunc_off = CONST2_RTX (SImode); 543 rtx trunc_off = CONST2_RTX (SImode);
700 rtx y = gen_reg_rtx (RFmode); 700 rtx y = gen_reg_rtx (RFmode);
701 rtx e = gen_reg_rtx (RFmode); 701 rtx e = gen_reg_rtx (RFmode);
702 rtx e1 = gen_reg_rtx (RFmode); 702 rtx e1 = gen_reg_rtx (RFmode);
703 rtx q = gen_reg_rtx (RFmode); 703 rtx q = gen_reg_rtx (RFmode);
704 rtx q1 = gen_reg_rtx (RFmode); 704 rtx q1 = gen_reg_rtx (RFmode);
705 rtx cond = gen_reg_rtx (BImode); 705 rtx cond = gen_reg_rtx (CCImode);
706 rtx zero = CONST0_RTX (RFmode); 706 rtx zero = CONST0_RTX (RFmode);
707 rtx one = CONST1_RTX (RFmode); 707 rtx one = CONST1_RTX (RFmode);
708 rtx status1 = CONST1_RTX (SImode); 708 rtx status1 = CONST1_RTX (SImode);
709 rtx trunc_off = CONST2_RTX (SImode); 709 rtx trunc_off = CONST2_RTX (SImode);
710 rtx twon34_exp = gen_reg_rtx (DImode); 710 rtx twon34_exp = gen_reg_rtx (DImode);
842 rtx e1 = gen_reg_rtx (RFmode); 842 rtx e1 = gen_reg_rtx (RFmode);
843 rtx q = gen_reg_rtx (RFmode); 843 rtx q = gen_reg_rtx (RFmode);
844 rtx q1 = gen_reg_rtx (RFmode); 844 rtx q1 = gen_reg_rtx (RFmode);
845 rtx q2 = gen_reg_rtx (RFmode); 845 rtx q2 = gen_reg_rtx (RFmode);
846 rtx r = gen_reg_rtx (RFmode); 846 rtx r = gen_reg_rtx (RFmode);
847 rtx cond = gen_reg_rtx (BImode); 847 rtx cond = gen_reg_rtx (CCImode);
848 rtx zero = CONST0_RTX (RFmode); 848 rtx zero = CONST0_RTX (RFmode);
849 rtx one = CONST1_RTX (RFmode); 849 rtx one = CONST1_RTX (RFmode);
850 rtx status1 = CONST1_RTX (SImode); 850 rtx status1 = CONST1_RTX (SImode);
851 rtx trunc_off = CONST2_RTX (SImode); 851 rtx trunc_off = CONST2_RTX (SImode);
852 852
886 rtx y2 = gen_reg_rtx (RFmode); 886 rtx y2 = gen_reg_rtx (RFmode);
887 rtx e = gen_reg_rtx (RFmode); 887 rtx e = gen_reg_rtx (RFmode);
888 rtx e1 = gen_reg_rtx (RFmode); 888 rtx e1 = gen_reg_rtx (RFmode);
889 rtx q2 = gen_reg_rtx (RFmode); 889 rtx q2 = gen_reg_rtx (RFmode);
890 rtx r = gen_reg_rtx (RFmode); 890 rtx r = gen_reg_rtx (RFmode);
891 rtx cond = gen_reg_rtx (BImode); 891 rtx cond = gen_reg_rtx (CCImode);
892 rtx zero = CONST0_RTX (RFmode); 892 rtx zero = CONST0_RTX (RFmode);
893 rtx one = CONST1_RTX (RFmode); 893 rtx one = CONST1_RTX (RFmode);
894 rtx status1 = CONST1_RTX (SImode); 894 rtx status1 = CONST1_RTX (SImode);
895 rtx trunc_off = CONST2_RTX (SImode); 895 rtx trunc_off = CONST2_RTX (SImode);
896 896
918 918
919 (define_insn "sqrt_approx_rf" 919 (define_insn "sqrt_approx_rf"
920 [(set (match_operand:RF 0 "fr_register_operand" "=f") 920 [(set (match_operand:RF 0 "fr_register_operand" "=f")
921 (unspec:RF [(match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")] 921 (unspec:RF [(match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")]
922 UNSPEC_FR_SQRT_RECIP_APPROX_RES)) 922 UNSPEC_FR_SQRT_RECIP_APPROX_RES))
923 (set (match_operand:BI 2 "register_operand" "=c") 923 (set (match_operand:CCI 2 "register_operand" "=c")
924 (unspec:BI [(match_dup 1)] UNSPEC_FR_SQRT_RECIP_APPROX)) 924 (unspec:CCI [(match_dup 1)] UNSPEC_FR_SQRT_RECIP_APPROX))
925 (use (match_operand:SI 3 "const_int_operand" ""))] 925 (use (match_operand:SI 3 "const_int_operand" ""))]
926 "" 926 ""
927 "frsqrta.s%3 %0, %2 = %F1" 927 "frsqrta.s%3 %0, %2 = %F1"
928 [(set_attr "itanium_class" "fmisc") 928 [(set_attr "itanium_class" "fmisc")
929 (set_attr "predicable" "no")]) 929 (set_attr "predicable" "no")])
956 rtx y1 = gen_reg_rtx (RFmode); 956 rtx y1 = gen_reg_rtx (RFmode);
957 rtx g1 = gen_reg_rtx (RFmode); 957 rtx g1 = gen_reg_rtx (RFmode);
958 rtx h = gen_reg_rtx (RFmode); 958 rtx h = gen_reg_rtx (RFmode);
959 rtx d = gen_reg_rtx (RFmode); 959 rtx d = gen_reg_rtx (RFmode);
960 rtx g2 = gen_reg_rtx (RFmode); 960 rtx g2 = gen_reg_rtx (RFmode);
961 rtx cond = gen_reg_rtx (BImode); 961 rtx cond = gen_reg_rtx (CCImode);
962 rtx zero = CONST0_RTX (RFmode); 962 rtx zero = CONST0_RTX (RFmode);
963 rtx one = CONST1_RTX (RFmode); 963 rtx one = CONST1_RTX (RFmode);
964 rtx c1 = ia64_dconst_0_5(); 964 rtx c1 = ia64_dconst_0_5();
965 rtx c2 = ia64_dconst_0_375(); 965 rtx c2 = ia64_dconst_0_375();
966 rtx reg_df_c1 = gen_reg_rtx (DFmode); 966 rtx reg_df_c1 = gen_reg_rtx (DFmode);
1019 rtx f = gen_reg_rtx (RFmode); 1019 rtx f = gen_reg_rtx (RFmode);
1020 rtx f1 = gen_reg_rtx (RFmode); 1020 rtx f1 = gen_reg_rtx (RFmode);
1021 rtx h = gen_reg_rtx (RFmode); 1021 rtx h = gen_reg_rtx (RFmode);
1022 rtx h1 = gen_reg_rtx (RFmode); 1022 rtx h1 = gen_reg_rtx (RFmode);
1023 rtx d = gen_reg_rtx (RFmode); 1023 rtx d = gen_reg_rtx (RFmode);
1024 rtx cond = gen_reg_rtx (BImode); 1024 rtx cond = gen_reg_rtx (CCImode);
1025 rtx zero = CONST0_RTX (RFmode); 1025 rtx zero = CONST0_RTX (RFmode);
1026 rtx one = CONST1_RTX (RFmode); 1026 rtx one = CONST1_RTX (RFmode);
1027 rtx c1 = ia64_dconst_0_5(); 1027 rtx c1 = ia64_dconst_0_5();
1028 rtx c2 = ia64_dconst_0_375(); 1028 rtx c2 = ia64_dconst_0_375();
1029 rtx reg_df_c1 = gen_reg_rtx (DFmode); 1029 rtx reg_df_c1 = gen_reg_rtx (DFmode);
1102 rtx h = gen_reg_rtx (RFmode); 1102 rtx h = gen_reg_rtx (RFmode);
1103 rtx h1 = gen_reg_rtx (RFmode); 1103 rtx h1 = gen_reg_rtx (RFmode);
1104 rtx h2 = gen_reg_rtx (RFmode); 1104 rtx h2 = gen_reg_rtx (RFmode);
1105 rtx d = gen_reg_rtx (RFmode); 1105 rtx d = gen_reg_rtx (RFmode);
1106 rtx d1 = gen_reg_rtx (RFmode); 1106 rtx d1 = gen_reg_rtx (RFmode);
1107 rtx cond = gen_reg_rtx (BImode); 1107 rtx cond = gen_reg_rtx (CCImode);
1108 rtx zero = CONST0_RTX (RFmode); 1108 rtx zero = CONST0_RTX (RFmode);
1109 rtx c1 = ia64_dconst_0_5(); 1109 rtx c1 = ia64_dconst_0_5();
1110 rtx reg_df_c1 = gen_reg_rtx (DFmode); 1110 rtx reg_df_c1 = gen_reg_rtx (DFmode);
1111 rtx reg_rf_c1 = gen_reg_rtx (RFmode); 1111 rtx reg_rf_c1 = gen_reg_rtx (RFmode);
1112 rtx status0 = CONST0_RTX (SImode); 1112 rtx status0 = CONST0_RTX (SImode);
1169 rtx h1 = gen_reg_rtx (RFmode); 1169 rtx h1 = gen_reg_rtx (RFmode);
1170 rtx h2 = gen_reg_rtx (RFmode); 1170 rtx h2 = gen_reg_rtx (RFmode);
1171 rtx h3 = gen_reg_rtx (RFmode); 1171 rtx h3 = gen_reg_rtx (RFmode);
1172 rtx d = gen_reg_rtx (RFmode); 1172 rtx d = gen_reg_rtx (RFmode);
1173 rtx d1 = gen_reg_rtx (RFmode); 1173 rtx d1 = gen_reg_rtx (RFmode);
1174 rtx cond = gen_reg_rtx (BImode); 1174 rtx cond = gen_reg_rtx (CCImode);
1175 rtx zero = CONST0_RTX (RFmode); 1175 rtx zero = CONST0_RTX (RFmode);
1176 rtx c1 = ia64_dconst_0_5(); 1176 rtx c1 = ia64_dconst_0_5();
1177 rtx reg_df_c1 = gen_reg_rtx (DFmode); 1177 rtx reg_df_c1 = gen_reg_rtx (DFmode);
1178 rtx reg_rf_c1 = gen_reg_rtx (RFmode); 1178 rtx reg_rf_c1 = gen_reg_rtx (RFmode);
1179 rtx status0 = CONST0_RTX (SImode); 1179 rtx status0 = CONST0_RTX (SImode);