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comparison gcc/config/m32c/addsub.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents a06113de4d67
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 ;; Machine Descriptions for R8C/M16C/M32C 1 ;; Machine Descriptions for R8C/M16C/M32C
2 ;; Copyright (C) 2005, 2007 2 ;; Copyright (C) 2005, 2007, 2010
3 ;; Free Software Foundation, Inc. 3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat. 4 ;; Contributed by Red Hat.
5 ;; 5 ;;
6 ;; This file is part of GCC. 6 ;; This file is part of GCC.
7 ;; 7 ;;
91 case 0: 91 case 0:
92 return \"add.w %X2,%h0\;adcf.w %H0\"; 92 return \"add.w %X2,%h0\;adcf.w %H0\";
93 case 1: 93 case 1:
94 return \"add.w %X2,%h0\;adcf.w %H0\"; 94 return \"add.w %X2,%h0\;adcf.w %H0\";
95 case 2: 95 case 2:
96 output_asm_insn (\"add.w %X2,%h0\",operands); 96 if (GET_CODE (operands[2]) == SYMBOL_REF)
97 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16); 97 {
98 return \"adc.w %X2,%H0\"; 98 output_asm_insn (\"add.w #%%lo(%d2),%h0\",operands);
99 return \"adc.w #%%hi(%d2),%H0\";
100 }
101 else
102 {
103 output_asm_insn (\"add.w %X2,%h0\",operands);
104 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
105 return \"adc.w %X2,%H0\";
106 }
99 case 3: 107 case 3:
100 return \"add.w %h2,%h0\;adc.w %H2,%H0\"; 108 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
101 case 4: 109 case 4:
102 output_asm_insn (\"add.w %X2,%h0\",operands); 110 output_asm_insn (\"add.w %X2,%h0\",operands);
103 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16); 111 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
106 return \"add.w %h2,%h0\;adc.w %H2,%H0\"; 114 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
107 case 6: 115 case 6:
108 return \"add.w %h2,%h0\;adc.w %H2,%H0\"; 116 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
109 case 7: 117 case 7:
110 return \"add.w %h2,%h0\;adc.w %H2,%H0\"; 118 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
119 default:
120 gcc_unreachable ();
111 }" 121 }"
112 [(set_attr "flags" "x,x,x,x,x,x,x,x")] 122 [(set_attr "flags" "x,x,x,x,x,x,x,x")]
113 ) 123 )
114 124
115 (define_insn "addsi3_2" 125 (define_insn "addsi3_2"
190 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\"; 200 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
191 case 4: 201 case 4:
192 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\"; 202 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
193 case 5: 203 case 5:
194 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\"; 204 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
205 default:
206 gcc_unreachable ();
195 }" 207 }"
196 [(set_attr "flags" "x,x,x,x,x,x")] 208 [(set_attr "flags" "x,x,x,x,x,x")]
197 ) 209 )
198 210
199 (define_insn "subsi3_2" 211 (define_insn "subsi3_2"