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comparison gcc/config/mips/mips-dsp.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents b7f97abdc517
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
14 ;; 14 ;;
15 ;; You should have received a copy of the GNU General Public License 15 ;; You should have received a copy of the GNU General Public License
16 ;; along with GCC; see the file COPYING3. If not see 16 ;; along with GCC; see the file COPYING3. If not see
17 ;; <http://www.gnu.org/licenses/>. 17 ;; <http://www.gnu.org/licenses/>.
18 18
19 ;; MIPS DSP ASE Revision 0.98 3/24/2005
20 (define_c_enum "unspec" [
21 UNSPEC_ADDQ
22 UNSPEC_ADDQ_S
23 UNSPEC_SUBQ
24 UNSPEC_SUBQ_S
25 UNSPEC_ADDSC
26 UNSPEC_ADDWC
27 UNSPEC_MODSUB
28 UNSPEC_RADDU_W_QB
29 UNSPEC_ABSQ_S
30 UNSPEC_PRECRQ_QB_PH
31 UNSPEC_PRECRQ_PH_W
32 UNSPEC_PRECRQ_RS_PH_W
33 UNSPEC_PRECRQU_S_QB_PH
34 UNSPEC_PRECEQ_W_PHL
35 UNSPEC_PRECEQ_W_PHR
36 UNSPEC_PRECEQU_PH_QBL
37 UNSPEC_PRECEQU_PH_QBR
38 UNSPEC_PRECEQU_PH_QBLA
39 UNSPEC_PRECEQU_PH_QBRA
40 UNSPEC_PRECEU_PH_QBL
41 UNSPEC_PRECEU_PH_QBR
42 UNSPEC_PRECEU_PH_QBLA
43 UNSPEC_PRECEU_PH_QBRA
44 UNSPEC_SHLL
45 UNSPEC_SHLL_S
46 UNSPEC_SHRL_QB
47 UNSPEC_SHRA_PH
48 UNSPEC_SHRA_R
49 UNSPEC_MULEU_S_PH_QBL
50 UNSPEC_MULEU_S_PH_QBR
51 UNSPEC_MULQ_RS_PH
52 UNSPEC_MULEQ_S_W_PHL
53 UNSPEC_MULEQ_S_W_PHR
54 UNSPEC_DPAU_H_QBL
55 UNSPEC_DPAU_H_QBR
56 UNSPEC_DPSU_H_QBL
57 UNSPEC_DPSU_H_QBR
58 UNSPEC_DPAQ_S_W_PH
59 UNSPEC_DPSQ_S_W_PH
60 UNSPEC_MULSAQ_S_W_PH
61 UNSPEC_DPAQ_SA_L_W
62 UNSPEC_DPSQ_SA_L_W
63 UNSPEC_MAQ_S_W_PHL
64 UNSPEC_MAQ_S_W_PHR
65 UNSPEC_MAQ_SA_W_PHL
66 UNSPEC_MAQ_SA_W_PHR
67 UNSPEC_BITREV
68 UNSPEC_INSV
69 UNSPEC_REPL_QB
70 UNSPEC_REPL_PH
71 UNSPEC_CMP_EQ
72 UNSPEC_CMP_LT
73 UNSPEC_CMP_LE
74 UNSPEC_CMPGU_EQ_QB
75 UNSPEC_CMPGU_LT_QB
76 UNSPEC_CMPGU_LE_QB
77 UNSPEC_PICK
78 UNSPEC_PACKRL_PH
79 UNSPEC_EXTR_W
80 UNSPEC_EXTR_R_W
81 UNSPEC_EXTR_RS_W
82 UNSPEC_EXTR_S_H
83 UNSPEC_EXTP
84 UNSPEC_EXTPDP
85 UNSPEC_SHILO
86 UNSPEC_MTHLIP
87 UNSPEC_WRDSP
88 UNSPEC_RDDSP
89 ])
90
19 (define_constants 91 (define_constants
20 [(CCDSP_PO_REGNUM 182) 92 [(CCDSP_PO_REGNUM 182)
21 (CCDSP_SC_REGNUM 183) 93 (CCDSP_SC_REGNUM 183)
22 (CCDSP_CA_REGNUM 184) 94 (CCDSP_CA_REGNUM 184)
23 (CCDSP_OU_REGNUM 185) 95 (CCDSP_OU_REGNUM 185)
1107 (pc)))] 1179 (pc)))]
1108 "ISA_HAS_DSP" 1180 "ISA_HAS_DSP"
1109 "%*bposge%1\t%0%/" 1181 "%*bposge%1\t%0%/"
1110 [(set_attr "type" "branch")]) 1182 [(set_attr "type" "branch")])
1111 1183
1184 (define_expand "mips_madd<u>"
1185 [(set (match_operand:DI 0 "register_operand")
1186 (plus:DI
1187 (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
1188 (any_extend:DI (match_operand:SI 3 "register_operand")))
1189 (match_operand:DI 1 "register_operand")))]
1190 "ISA_HAS_DSP && !TARGET_64BIT")
1191
1192 (define_expand "mips_msub<u>"
1193 [(set (match_operand:DI 0 "register_operand")
1194 (minus:DI
1195 (match_operand:DI 1 "register_operand")
1196 (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
1197 (any_extend:DI (match_operand:SI 3 "register_operand")))))]
1198 "ISA_HAS_DSP && !TARGET_64BIT")