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comparison gcc/config/mips/mips.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents b7f97abdc517
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
21 21
22 ;; You should have received a copy of the GNU General Public License 22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see 23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>. 24 ;; <http://www.gnu.org/licenses/>.
25 25
26 (define_enum "processor" [
27 r3000
28 4kc
29 4kp
30 5kc
31 5kf
32 20kc
33 24kc
34 24kf2_1
35 24kf1_1
36 74kc
37 74kf2_1
38 74kf1_1
39 74kf3_2
40 loongson_2e
41 loongson_2f
42 loongson_3a
43 m4k
44 octeon
45 r3900
46 r6000
47 r4000
48 r4100
49 r4111
50 r4120
51 r4130
52 r4300
53 r4600
54 r4650
55 r5000
56 r5400
57 r5500
58 r7000
59 r8000
60 r9000
61 r10000
62 sb1
63 sb1a
64 sr71000
65 xlr
66 ])
67
68 (define_c_enum "unspec" [
69 ;; Unaligned accesses.
70 UNSPEC_LOAD_LEFT
71 UNSPEC_LOAD_RIGHT
72 UNSPEC_STORE_LEFT
73 UNSPEC_STORE_RIGHT
74
75 ;; Floating-point moves.
76 UNSPEC_LOAD_LOW
77 UNSPEC_LOAD_HIGH
78 UNSPEC_STORE_WORD
79 UNSPEC_MFHC1
80 UNSPEC_MTHC1
81
82 ;; HI/LO moves.
83 UNSPEC_MFHI
84 UNSPEC_MTHI
85 UNSPEC_SET_HILO
86
87 ;; GP manipulation.
88 UNSPEC_LOADGP
89 UNSPEC_COPYGP
90 UNSPEC_MOVE_GP
91 UNSPEC_POTENTIAL_CPRESTORE
92 UNSPEC_CPRESTORE
93 UNSPEC_RESTORE_GP
94 UNSPEC_EH_RETURN
95 UNSPEC_GP
96 UNSPEC_SET_GOT_VERSION
97 UNSPEC_UPDATE_GOT_VERSION
98
99 ;; Symbolic accesses.
100 UNSPEC_LOAD_CALL
101 UNSPEC_LOAD_GOT
102 UNSPEC_TLS_LDM
103 UNSPEC_TLS_GET_TP
104
105 ;; MIPS16 constant pools.
106 UNSPEC_ALIGN
107 UNSPEC_CONSTTABLE_INT
108 UNSPEC_CONSTTABLE_FLOAT
109
110 ;; Blockage and synchronisation.
111 UNSPEC_BLOCKAGE
112 UNSPEC_CLEAR_HAZARD
113 UNSPEC_RDHWR
114 UNSPEC_SYNCI
115 UNSPEC_SYNC
116
117 ;; Cache manipulation.
118 UNSPEC_MIPS_CACHE
119 UNSPEC_R10K_CACHE_BARRIER
120
121 ;; Interrupt handling.
122 UNSPEC_ERET
123 UNSPEC_DERET
124 UNSPEC_DI
125 UNSPEC_EHB
126 UNSPEC_RDPGPR
127 UNSPEC_COP0
128
129 ;; Used in a call expression in place of args_size. It's present for PIC
130 ;; indirect calls where it contains args_size and the function symbol.
131 UNSPEC_CALL_ATTR
132 ])
133
26 (define_constants 134 (define_constants
27 [(UNSPEC_LOAD_LOW 0) 135 [(TLS_GET_TP_REGNUM 3)
28 (UNSPEC_LOAD_HIGH 1)
29 (UNSPEC_STORE_WORD 2)
30 (UNSPEC_GET_FNADDR 3)
31 (UNSPEC_BLOCKAGE 4)
32 (UNSPEC_POTENTIAL_CPRESTORE 5)
33 (UNSPEC_CPRESTORE 6)
34 (UNSPEC_RESTORE_GP 7)
35 (UNSPEC_MOVE_GP 8)
36 (UNSPEC_EH_RETURN 9)
37 (UNSPEC_CONSTTABLE_INT 10)
38 (UNSPEC_CONSTTABLE_FLOAT 11)
39 (UNSPEC_ALIGN 14)
40 (UNSPEC_HIGH 17)
41 (UNSPEC_LOAD_LEFT 18)
42 (UNSPEC_LOAD_RIGHT 19)
43 (UNSPEC_STORE_LEFT 20)
44 (UNSPEC_STORE_RIGHT 21)
45 (UNSPEC_LOADGP 22)
46 (UNSPEC_LOAD_CALL 23)
47 (UNSPEC_LOAD_GOT 24)
48 (UNSPEC_GP 25)
49 (UNSPEC_MFHI 26)
50 (UNSPEC_MTHI 27)
51 (UNSPEC_SET_HILO 28)
52 (UNSPEC_TLS_LDM 29)
53 (UNSPEC_TLS_GET_TP 30)
54 (UNSPEC_MFHC1 31)
55 (UNSPEC_MTHC1 32)
56 (UNSPEC_CLEAR_HAZARD 33)
57 (UNSPEC_RDHWR 34)
58 (UNSPEC_SYNCI 35)
59 (UNSPEC_SYNC 36)
60 (UNSPEC_COMPARE_AND_SWAP 37)
61 (UNSPEC_COMPARE_AND_SWAP_12 38)
62 (UNSPEC_SYNC_OLD_OP 39)
63 (UNSPEC_SYNC_NEW_OP 40)
64 (UNSPEC_SYNC_NEW_OP_12 41)
65 (UNSPEC_SYNC_OLD_OP_12 42)
66 (UNSPEC_SYNC_EXCHANGE 43)
67 (UNSPEC_SYNC_EXCHANGE_12 44)
68 (UNSPEC_MEMORY_BARRIER 45)
69 (UNSPEC_SET_GOT_VERSION 46)
70 (UNSPEC_UPDATE_GOT_VERSION 47)
71 (UNSPEC_COPYGP 48)
72 (UNSPEC_ERET 49)
73 (UNSPEC_DERET 50)
74 (UNSPEC_DI 51)
75 (UNSPEC_EHB 52)
76 (UNSPEC_RDPGPR 53)
77 (UNSPEC_COP0 54)
78 ;; Used in a call expression in place of args_size. It's present for PIC
79 ;; indirect calls where it contains args_size and the function symbol.
80 (UNSPEC_CALL_ATTR 55)
81
82 (UNSPEC_ADDRESS_FIRST 100)
83
84 (TLS_GET_TP_REGNUM 3)
85 (RETURN_ADDR_REGNUM 31) 136 (RETURN_ADDR_REGNUM 31)
86 (CPRESTORE_SLOT_REGNUM 76) 137 (CPRESTORE_SLOT_REGNUM 76)
87 (GOT_VERSION_REGNUM 79) 138 (GOT_VERSION_REGNUM 79)
88
89 ;; For MIPS Paired-Singled Floating Point Instructions.
90
91 (UNSPEC_MOVE_TF_PS 200)
92 (UNSPEC_C 201)
93
94 ;; MIPS64/MIPS32R2 alnv.ps
95 (UNSPEC_ALNV_PS 202)
96
97 ;; MIPS-3D instructions
98 (UNSPEC_CABS 203)
99
100 (UNSPEC_ADDR_PS 204)
101 (UNSPEC_CVT_PW_PS 205)
102 (UNSPEC_CVT_PS_PW 206)
103 (UNSPEC_MULR_PS 207)
104 (UNSPEC_ABS_PS 208)
105
106 (UNSPEC_RSQRT1 209)
107 (UNSPEC_RSQRT2 210)
108 (UNSPEC_RECIP1 211)
109 (UNSPEC_RECIP2 212)
110 (UNSPEC_SINGLE_CC 213)
111 (UNSPEC_SCC 214)
112
113 ;; MIPS DSP ASE Revision 0.98 3/24/2005
114 (UNSPEC_ADDQ 300)
115 (UNSPEC_ADDQ_S 301)
116 (UNSPEC_SUBQ 302)
117 (UNSPEC_SUBQ_S 303)
118 (UNSPEC_ADDSC 304)
119 (UNSPEC_ADDWC 305)
120 (UNSPEC_MODSUB 306)
121 (UNSPEC_RADDU_W_QB 307)
122 (UNSPEC_ABSQ_S 308)
123 (UNSPEC_PRECRQ_QB_PH 309)
124 (UNSPEC_PRECRQ_PH_W 310)
125 (UNSPEC_PRECRQ_RS_PH_W 311)
126 (UNSPEC_PRECRQU_S_QB_PH 312)
127 (UNSPEC_PRECEQ_W_PHL 313)
128 (UNSPEC_PRECEQ_W_PHR 314)
129 (UNSPEC_PRECEQU_PH_QBL 315)
130 (UNSPEC_PRECEQU_PH_QBR 316)
131 (UNSPEC_PRECEQU_PH_QBLA 317)
132 (UNSPEC_PRECEQU_PH_QBRA 318)
133 (UNSPEC_PRECEU_PH_QBL 319)
134 (UNSPEC_PRECEU_PH_QBR 320)
135 (UNSPEC_PRECEU_PH_QBLA 321)
136 (UNSPEC_PRECEU_PH_QBRA 322)
137 (UNSPEC_SHLL 323)
138 (UNSPEC_SHLL_S 324)
139 (UNSPEC_SHRL_QB 325)
140 (UNSPEC_SHRA_PH 326)
141 (UNSPEC_SHRA_R 327)
142 (UNSPEC_MULEU_S_PH_QBL 328)
143 (UNSPEC_MULEU_S_PH_QBR 329)
144 (UNSPEC_MULQ_RS_PH 330)
145 (UNSPEC_MULEQ_S_W_PHL 331)
146 (UNSPEC_MULEQ_S_W_PHR 332)
147 (UNSPEC_DPAU_H_QBL 333)
148 (UNSPEC_DPAU_H_QBR 334)
149 (UNSPEC_DPSU_H_QBL 335)
150 (UNSPEC_DPSU_H_QBR 336)
151 (UNSPEC_DPAQ_S_W_PH 337)
152 (UNSPEC_DPSQ_S_W_PH 338)
153 (UNSPEC_MULSAQ_S_W_PH 339)
154 (UNSPEC_DPAQ_SA_L_W 340)
155 (UNSPEC_DPSQ_SA_L_W 341)
156 (UNSPEC_MAQ_S_W_PHL 342)
157 (UNSPEC_MAQ_S_W_PHR 343)
158 (UNSPEC_MAQ_SA_W_PHL 344)
159 (UNSPEC_MAQ_SA_W_PHR 345)
160 (UNSPEC_BITREV 346)
161 (UNSPEC_INSV 347)
162 (UNSPEC_REPL_QB 348)
163 (UNSPEC_REPL_PH 349)
164 (UNSPEC_CMP_EQ 350)
165 (UNSPEC_CMP_LT 351)
166 (UNSPEC_CMP_LE 352)
167 (UNSPEC_CMPGU_EQ_QB 353)
168 (UNSPEC_CMPGU_LT_QB 354)
169 (UNSPEC_CMPGU_LE_QB 355)
170 (UNSPEC_PICK 356)
171 (UNSPEC_PACKRL_PH 357)
172 (UNSPEC_EXTR_W 358)
173 (UNSPEC_EXTR_R_W 359)
174 (UNSPEC_EXTR_RS_W 360)
175 (UNSPEC_EXTR_S_H 361)
176 (UNSPEC_EXTP 362)
177 (UNSPEC_EXTPDP 363)
178 (UNSPEC_SHILO 364)
179 (UNSPEC_MTHLIP 365)
180 (UNSPEC_WRDSP 366)
181 (UNSPEC_RDDSP 367)
182
183 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
184 (UNSPEC_ABSQ_S_QB 400)
185 (UNSPEC_ADDU_PH 401)
186 (UNSPEC_ADDU_S_PH 402)
187 (UNSPEC_ADDUH_QB 403)
188 (UNSPEC_ADDUH_R_QB 404)
189 (UNSPEC_APPEND 405)
190 (UNSPEC_BALIGN 406)
191 (UNSPEC_CMPGDU_EQ_QB 407)
192 (UNSPEC_CMPGDU_LT_QB 408)
193 (UNSPEC_CMPGDU_LE_QB 409)
194 (UNSPEC_DPA_W_PH 410)
195 (UNSPEC_DPS_W_PH 411)
196 (UNSPEC_MADD 412)
197 (UNSPEC_MADDU 413)
198 (UNSPEC_MSUB 414)
199 (UNSPEC_MSUBU 415)
200 (UNSPEC_MUL_PH 416)
201 (UNSPEC_MUL_S_PH 417)
202 (UNSPEC_MULQ_RS_W 418)
203 (UNSPEC_MULQ_S_PH 419)
204 (UNSPEC_MULQ_S_W 420)
205 (UNSPEC_MULSA_W_PH 421)
206 (UNSPEC_MULT 422)
207 (UNSPEC_MULTU 423)
208 (UNSPEC_PRECR_QB_PH 424)
209 (UNSPEC_PRECR_SRA_PH_W 425)
210 (UNSPEC_PRECR_SRA_R_PH_W 426)
211 (UNSPEC_PREPEND 427)
212 (UNSPEC_SHRA_QB 428)
213 (UNSPEC_SHRA_R_QB 429)
214 (UNSPEC_SHRL_PH 430)
215 (UNSPEC_SUBU_PH 431)
216 (UNSPEC_SUBU_S_PH 432)
217 (UNSPEC_SUBUH_QB 433)
218 (UNSPEC_SUBUH_R_QB 434)
219 (UNSPEC_ADDQH_PH 435)
220 (UNSPEC_ADDQH_R_PH 436)
221 (UNSPEC_ADDQH_W 437)
222 (UNSPEC_ADDQH_R_W 438)
223 (UNSPEC_SUBQH_PH 439)
224 (UNSPEC_SUBQH_R_PH 440)
225 (UNSPEC_SUBQH_W 441)
226 (UNSPEC_SUBQH_R_W 442)
227 (UNSPEC_DPAX_W_PH 443)
228 (UNSPEC_DPSX_W_PH 444)
229 (UNSPEC_DPAQX_S_W_PH 445)
230 (UNSPEC_DPAQX_SA_W_PH 446)
231 (UNSPEC_DPSQX_S_W_PH 447)
232 (UNSPEC_DPSQX_SA_W_PH 448)
233
234 ;; ST Microelectronics Loongson-2E/2F.
235 (UNSPEC_LOONGSON_PAVG 500)
236 (UNSPEC_LOONGSON_PCMPEQ 501)
237 (UNSPEC_LOONGSON_PCMPGT 502)
238 (UNSPEC_LOONGSON_PEXTR 503)
239 (UNSPEC_LOONGSON_PINSR_0 504)
240 (UNSPEC_LOONGSON_PINSR_1 505)
241 (UNSPEC_LOONGSON_PINSR_2 506)
242 (UNSPEC_LOONGSON_PINSR_3 507)
243 (UNSPEC_LOONGSON_PMADD 508)
244 (UNSPEC_LOONGSON_PMOVMSK 509)
245 (UNSPEC_LOONGSON_PMULHU 510)
246 (UNSPEC_LOONGSON_PMULH 511)
247 (UNSPEC_LOONGSON_PMULL 512)
248 (UNSPEC_LOONGSON_PMULU 513)
249 (UNSPEC_LOONGSON_PASUBUB 514)
250 (UNSPEC_LOONGSON_BIADD 515)
251 (UNSPEC_LOONGSON_PSADBH 516)
252 (UNSPEC_LOONGSON_PSHUFH 517)
253 (UNSPEC_LOONGSON_PUNPCKH 518)
254 (UNSPEC_LOONGSON_PUNPCKL 519)
255 (UNSPEC_LOONGSON_PADDD 520)
256 (UNSPEC_LOONGSON_PSUBD 521)
257
258 ;; Used in loongson2ef.md
259 (UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN 530)
260 (UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN 531)
261 (UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN 532)
262 (UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN 533)
263
264 (UNSPEC_MIPS_CACHE 600)
265 (UNSPEC_R10K_CACHE_BARRIER 601)
266 139
267 ;; PIC long branch sequences are never longer than 100 bytes. 140 ;; PIC long branch sequences are never longer than 100 bytes.
268 (MAX_PIC_BRANCH_LENGTH 100) 141 (MAX_PIC_BRANCH_LENGTH 100)
269 ] 142 ]
270 ) 143 )
323 ;; scheduling type to be "multi" instead. 196 ;; scheduling type to be "multi" instead.
324 (define_attr "move_type" 197 (define_attr "move_type"
325 "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove, 198 "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
326 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool, 199 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
327 shift_shift,lui_movf" 200 shift_shift,lui_movf"
201 (const_string "unknown"))
202
203 (define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor"
328 (const_string "unknown")) 204 (const_string "unknown"))
329 205
330 ;; Main data type used by the insn 206 ;; Main data type used by the insn
331 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW" 207 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
332 (const_string "unknown")) 208 (const_string "unknown"))
401 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt, 277 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
402 frsqrt,frsqrt1,frsqrt2,multi,nop,ghost" 278 frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
403 (cond [(eq_attr "jal" "!unset") (const_string "call") 279 (cond [(eq_attr "jal" "!unset") (const_string "call")
404 (eq_attr "got" "load") (const_string "load") 280 (eq_attr "got" "load") (const_string "load")
405 281
282 (eq_attr "alu_type" "add,sub") (const_string "arith")
283
284 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
285
406 ;; If a doubleword move uses these expensive instructions, 286 ;; If a doubleword move uses these expensive instructions,
407 ;; it is usually better to schedule them in the same way 287 ;; it is usually better to schedule them in the same way
408 ;; as the singleword form, rather than as "multi". 288 ;; as the singleword form, rather than as "multi".
409 (eq_attr "move_type" "load") (const_string "load") 289 (eq_attr "move_type" "load") (const_string "load")
410 (eq_attr "move_type" "fpload") (const_string "fpload") 290 (eq_attr "move_type" "fpload") (const_string "fpload")
634 514
635 (not (eq_attr "sync_mem" "none")) 515 (not (eq_attr "sync_mem" "none"))
636 (symbol_ref "mips_sync_loop_insns (insn, operands) * 4") 516 (symbol_ref "mips_sync_loop_insns (insn, operands) * 4")
637 ] (const_int 4))) 517 ] (const_int 4)))
638 518
639 ;; Attribute describing the processor. This attribute must match exactly 519 ;; Attribute describing the processor.
640 ;; with the processor_type enumeration in mips.h. 520 (define_enum_attr "cpu" "processor"
641 (define_attr "cpu" 521 (const (symbol_ref "mips_tune")))
642 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sb1a,sr71000,xlr"
643 (const (symbol_ref "mips_tune_attr")))
644 522
645 ;; The type of hardware hazard associated with this instruction. 523 ;; The type of hardware hazard associated with this instruction.
646 ;; DELAY means that the next instruction cannot read the result 524 ;; DELAY means that the next instruction cannot read the result
647 ;; of this one. HILO means that the next two instructions cannot 525 ;; of this one. HILO means that the next two instructions cannot
648 ;; write to HI or LO. 526 ;; write to HI or LO.
1028 (include "6000.md") 906 (include "6000.md")
1029 (include "7000.md") 907 (include "7000.md")
1030 (include "9000.md") 908 (include "9000.md")
1031 (include "10000.md") 909 (include "10000.md")
1032 (include "loongson2ef.md") 910 (include "loongson2ef.md")
911 (include "loongson3a.md")
1033 (include "octeon.md") 912 (include "octeon.md")
1034 (include "sb1.md") 913 (include "sb1.md")
1035 (include "sr71k.md") 914 (include "sr71k.md")
1036 (include "xlr.md") 915 (include "xlr.md")
1037 (include "generic.md") 916 (include "generic.md")
1106 (match_operand:GPR 2 "arith_operand" "d,Q")))] 985 (match_operand:GPR 2 "arith_operand" "d,Q")))]
1107 "!TARGET_MIPS16" 986 "!TARGET_MIPS16"
1108 "@ 987 "@
1109 <d>addu\t%0,%1,%2 988 <d>addu\t%0,%1,%2
1110 <d>addiu\t%0,%1,%2" 989 <d>addiu\t%0,%1,%2"
1111 [(set_attr "type" "arith") 990 [(set_attr "alu_type" "add")
1112 (set_attr "mode" "<MODE>")]) 991 (set_attr "mode" "<MODE>")])
1113 992
1114 (define_insn "*add<mode>3_mips16" 993 (define_insn "*add<mode>3_mips16"
1115 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d") 994 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
1116 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d") 995 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
1120 <d>addiu\t%0,%2 999 <d>addiu\t%0,%2
1121 <d>addiu\t%0,%1,%2 1000 <d>addiu\t%0,%1,%2
1122 <d>addiu\t%0,%2 1001 <d>addiu\t%0,%2
1123 <d>addiu\t%0,%1,%2 1002 <d>addiu\t%0,%1,%2
1124 <d>addu\t%0,%1,%2" 1003 <d>addu\t%0,%1,%2"
1125 [(set_attr "type" "arith") 1004 [(set_attr "alu_type" "add")
1126 (set_attr "mode" "<MODE>") 1005 (set_attr "mode" "<MODE>")
1127 (set_attr_alternative "length" 1006 (set_attr_alternative "length"
1128 [(if_then_else (match_operand 2 "m16_simm8_8") 1007 [(if_then_else (match_operand 2 "m16_simm8_8")
1129 (const_int 4) 1008 (const_int 4)
1130 (const_int 8)) 1009 (const_int 8))
1258 (match_operand:SI 2 "arith_operand" "d,Q"))))] 1137 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1259 "TARGET_64BIT && !TARGET_MIPS16" 1138 "TARGET_64BIT && !TARGET_MIPS16"
1260 "@ 1139 "@
1261 addu\t%0,%1,%2 1140 addu\t%0,%1,%2
1262 addiu\t%0,%1,%2" 1141 addiu\t%0,%1,%2"
1263 [(set_attr "type" "arith") 1142 [(set_attr "alu_type" "add")
1264 (set_attr "mode" "SI")]) 1143 (set_attr "mode" "SI")])
1265 1144
1266 ;; Split this insn so that the addiu splitters can have a crack at it. 1145 ;; Split this insn so that the addiu splitters can have a crack at it.
1267 ;; Use a conservative length estimate until the split. 1146 ;; Use a conservative length estimate until the split.
1268 (define_insn_and_split "*addsi3_extended_mips16" 1147 (define_insn_and_split "*addsi3_extended_mips16"
1273 "TARGET_64BIT && TARGET_MIPS16" 1152 "TARGET_64BIT && TARGET_MIPS16"
1274 "#" 1153 "#"
1275 "&& reload_completed" 1154 "&& reload_completed"
1276 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))] 1155 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1277 { operands[3] = gen_lowpart (SImode, operands[0]); } 1156 { operands[3] = gen_lowpart (SImode, operands[0]); }
1278 [(set_attr "type" "arith") 1157 [(set_attr "alu_type" "add")
1279 (set_attr "mode" "SI") 1158 (set_attr "mode" "SI")
1280 (set_attr "extended_mips16" "yes")]) 1159 (set_attr "extended_mips16" "yes")])
1281 1160
1282 ;; Combiner patterns for unsigned byte-add. 1161 ;; Combiner patterns for unsigned byte-add.
1283 1162
1287 (subreg:QI 1166 (subreg:QI
1288 (plus:SI (match_operand:SI 1 "register_operand" "d") 1167 (plus:SI (match_operand:SI 1 "register_operand" "d")
1289 (match_operand:SI 2 "register_operand" "d")) 3)))] 1168 (match_operand:SI 2 "register_operand" "d")) 3)))]
1290 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN" 1169 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1291 "baddu\\t%0,%1,%2" 1170 "baddu\\t%0,%1,%2"
1292 [(set_attr "type" "arith")]) 1171 [(set_attr "alu_type" "add")])
1293 1172
1294 (define_insn "*baddu_si_el" 1173 (define_insn "*baddu_si_el"
1295 [(set (match_operand:SI 0 "register_operand" "=d") 1174 [(set (match_operand:SI 0 "register_operand" "=d")
1296 (zero_extend:SI 1175 (zero_extend:SI
1297 (subreg:QI 1176 (subreg:QI
1298 (plus:SI (match_operand:SI 1 "register_operand" "d") 1177 (plus:SI (match_operand:SI 1 "register_operand" "d")
1299 (match_operand:SI 2 "register_operand" "d")) 0)))] 1178 (match_operand:SI 2 "register_operand" "d")) 0)))]
1300 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN" 1179 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1301 "baddu\\t%0,%1,%2" 1180 "baddu\\t%0,%1,%2"
1302 [(set_attr "type" "arith")]) 1181 [(set_attr "alu_type" "add")])
1303 1182
1304 (define_insn "*baddu_di<mode>" 1183 (define_insn "*baddu_di<mode>"
1305 [(set (match_operand:GPR 0 "register_operand" "=d") 1184 [(set (match_operand:GPR 0 "register_operand" "=d")
1306 (zero_extend:GPR 1185 (zero_extend:GPR
1307 (truncate:QI 1186 (truncate:QI
1308 (plus:DI (match_operand:DI 1 "register_operand" "d") 1187 (plus:DI (match_operand:DI 1 "register_operand" "d")
1309 (match_operand:DI 2 "register_operand" "d")))))] 1188 (match_operand:DI 2 "register_operand" "d")))))]
1310 "ISA_HAS_BADDU && TARGET_64BIT" 1189 "ISA_HAS_BADDU && TARGET_64BIT"
1311 "baddu\\t%0,%1,%2" 1190 "baddu\\t%0,%1,%2"
1312 [(set_attr "type" "arith")]) 1191 [(set_attr "alu_type" "add")])
1313 1192
1314 ;; 1193 ;;
1315 ;; .................... 1194 ;; ....................
1316 ;; 1195 ;;
1317 ;; SUBTRACTION 1196 ;; SUBTRACTION
1332 [(set (match_operand:GPR 0 "register_operand" "=d") 1211 [(set (match_operand:GPR 0 "register_operand" "=d")
1333 (minus:GPR (match_operand:GPR 1 "register_operand" "d") 1212 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1334 (match_operand:GPR 2 "register_operand" "d")))] 1213 (match_operand:GPR 2 "register_operand" "d")))]
1335 "" 1214 ""
1336 "<d>subu\t%0,%1,%2" 1215 "<d>subu\t%0,%1,%2"
1337 [(set_attr "type" "arith") 1216 [(set_attr "alu_type" "sub")
1338 (set_attr "mode" "<MODE>")]) 1217 (set_attr "mode" "<MODE>")])
1339 1218
1340 (define_insn "*subsi3_extended" 1219 (define_insn "*subsi3_extended"
1341 [(set (match_operand:DI 0 "register_operand" "=d") 1220 [(set (match_operand:DI 0 "register_operand" "=d")
1342 (sign_extend:DI 1221 (sign_extend:DI
1343 (minus:SI (match_operand:SI 1 "register_operand" "d") 1222 (minus:SI (match_operand:SI 1 "register_operand" "d")
1344 (match_operand:SI 2 "register_operand" "d"))))] 1223 (match_operand:SI 2 "register_operand" "d"))))]
1345 "TARGET_64BIT" 1224 "TARGET_64BIT"
1346 "subu\t%0,%1,%2" 1225 "subu\t%0,%1,%2"
1347 [(set_attr "type" "arith") 1226 [(set_attr "alu_type" "sub")
1348 (set_attr "mode" "DI")]) 1227 (set_attr "mode" "DI")])
1349 1228
1350 ;; 1229 ;;
1351 ;; .................... 1230 ;; ....................
1352 ;; 1231 ;;
1444 [(set (match_operand:GPR 0 "register_operand") 1323 [(set (match_operand:GPR 0 "register_operand")
1445 (mult:GPR (match_operand:GPR 1 "register_operand") 1324 (mult:GPR (match_operand:GPR 1 "register_operand")
1446 (match_operand:GPR 2 "register_operand")))] 1325 (match_operand:GPR 2 "register_operand")))]
1447 "" 1326 ""
1448 { 1327 {
1449 if (TARGET_LOONGSON_2EF) 1328 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
1450 emit_insn (gen_mul<mode>3_mul3_ls2ef (operands[0], operands[1], 1329 emit_insn (gen_mul<mode>3_mul3_loongson (operands[0], operands[1],
1451 operands[2])); 1330 operands[2]));
1452 else if (ISA_HAS_<D>MUL3) 1331 else if (ISA_HAS_<D>MUL3)
1453 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2])); 1332 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1454 else if (TARGET_FIX_R4000) 1333 else if (TARGET_FIX_R4000)
1455 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2])); 1334 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1456 else 1335 else
1457 emit_insn 1336 emit_insn
1458 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2])); 1337 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1459 DONE; 1338 DONE;
1460 }) 1339 })
1461 1340
1462 (define_insn "mul<mode>3_mul3_ls2ef" 1341 (define_insn "mul<mode>3_mul3_loongson"
1463 [(set (match_operand:GPR 0 "register_operand" "=d") 1342 [(set (match_operand:GPR 0 "register_operand" "=d")
1464 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1343 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1465 (match_operand:GPR 2 "register_operand" "d")))] 1344 (match_operand:GPR 2 "register_operand" "d")))]
1466 "TARGET_LOONGSON_2EF" 1345 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A"
1467 "<d>multu.g\t%0,%1,%2" 1346 {
1347 if (TARGET_LOONGSON_2EF)
1348 return "<d>multu.g\t%0,%1,%2";
1349 else
1350 return "gs<d>multu\t%0,%1,%2";
1351 }
1468 [(set_attr "type" "imul3nc") 1352 [(set_attr "type" "imul3nc")
1469 (set_attr "mode" "<MODE>")]) 1353 (set_attr "mode" "<MODE>")])
1470 1354
1471 (define_insn "mul<mode>3_mul3" 1355 (define_insn "mul<mode>3_mul3"
1472 [(set (match_operand:GPR 0 "register_operand" "=d,l") 1356 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1852 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>); 1736 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>);
1853 emit_insn (fn (operands[0], operands[1], operands[2])); 1737 emit_insn (fn (operands[0], operands[1], operands[2]));
1854 DONE; 1738 DONE;
1855 }) 1739 })
1856 1740
1741 ;; As well as being named patterns, these instructions are used by the
1742 ;; __builtin_mips_mult<u>() functions. We must always make those functions
1743 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
1857 (define_insn "<u>mulsidi3_32bit" 1744 (define_insn "<u>mulsidi3_32bit"
1858 [(set (match_operand:DI 0 "register_operand" "=x") 1745 [(set (match_operand:DI 0 "register_operand" "=ka")
1859 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 1746 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1860 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))] 1747 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1861 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2" 1748 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP)"
1862 "mult<u>\t%1,%2" 1749 {
1750 if (ISA_HAS_DSP_MULT)
1751 return "mult<u>\t%q0,%1,%2";
1752 else
1753 return "mult<u>\t%1,%2";
1754 }
1863 [(set_attr "type" "imul") 1755 [(set_attr "type" "imul")
1864 (set_attr "mode" "SI")]) 1756 (set_attr "mode" "SI")])
1865 1757
1866 (define_insn "<u>mulsidi3_32bit_r4000" 1758 (define_insn "<u>mulsidi3_32bit_r4000"
1867 [(set (match_operand:DI 0 "register_operand" "=d") 1759 [(set (match_operand:DI 0 "register_operand" "=d")
1977 "!TARGET_64BIT && ISA_HAS_MULS" 1869 "!TARGET_64BIT && ISA_HAS_MULS"
1978 "muls<u>\t$0,%1,%2" 1870 "muls<u>\t$0,%1,%2"
1979 [(set_attr "type" "imul") 1871 [(set_attr "type" "imul")
1980 (set_attr "mode" "SI")]) 1872 (set_attr "mode" "SI")])
1981 1873
1874 ;; As well as being named patterns, these instructions are used by the
1875 ;; __builtin_mips_msub<u>() functions. We must always make those functions
1876 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
1877 ;;
1878 ;; This leads to a slight inconsistency. We honor any tuning overrides
1879 ;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp,
1880 ;; even if !ISA_HAS_DSP_MULT.
1982 (define_insn "<u>msubsidi4" 1881 (define_insn "<u>msubsidi4"
1983 [(set (match_operand:DI 0 "register_operand" "=ka") 1882 [(set (match_operand:DI 0 "register_operand" "=ka")
1984 (minus:DI 1883 (minus:DI
1985 (match_operand:DI 3 "register_operand" "0") 1884 (match_operand:DI 3 "register_operand" "0")
1986 (mult:DI 1885 (mult:DI
1987 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 1886 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1988 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] 1887 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1989 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)" 1888 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
1990 { 1889 {
1991 if (ISA_HAS_DSPR2) 1890 if (ISA_HAS_DSP_MULT)
1992 return "msub<u>\t%q0,%1,%2"; 1891 return "msub<u>\t%q0,%1,%2";
1993 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB) 1892 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1994 return "msub<u>\t%1,%2"; 1893 return "msub<u>\t%1,%2";
1995 else 1894 else
1996 return "msac<u>\t$0,%1,%2"; 1895 return "msac<u>\t$0,%1,%2";
2157 "TARGET_MAD" 2056 "TARGET_MAD"
2158 "mad\t%1,%2" 2057 "mad\t%1,%2"
2159 [(set_attr "type" "imadd") 2058 [(set_attr "type" "imadd")
2160 (set_attr "mode" "SI")]) 2059 (set_attr "mode" "SI")])
2161 2060
2061 ;; See the comment above <u>msubsidi4 for the relationship between
2062 ;; ISA_HAS_DSP and ISA_HAS_DSP_MULT.
2162 (define_insn "<u>maddsidi4" 2063 (define_insn "<u>maddsidi4"
2163 [(set (match_operand:DI 0 "register_operand" "=ka") 2064 [(set (match_operand:DI 0 "register_operand" "=ka")
2164 (plus:DI 2065 (plus:DI
2165 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2066 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2166 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2067 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2167 (match_operand:DI 3 "register_operand" "0")))] 2068 (match_operand:DI 3 "register_operand" "0")))]
2168 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2) 2069 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
2169 && !TARGET_64BIT" 2070 && !TARGET_64BIT"
2170 { 2071 {
2171 if (TARGET_MAD) 2072 if (TARGET_MAD)
2172 return "mad<u>\t%1,%2"; 2073 return "mad<u>\t%1,%2";
2173 else if (ISA_HAS_DSPR2) 2074 else if (ISA_HAS_DSP_MULT)
2174 return "madd<u>\t%q0,%1,%2"; 2075 return "madd<u>\t%q0,%1,%2";
2175 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500) 2076 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2176 return "madd<u>\t%1,%2"; 2077 return "madd<u>\t%1,%2";
2177 else 2078 else
2178 /* See comment in *macc. */ 2079 /* See comment in *macc. */
2611 if (TARGET_MIPS16) 2512 if (TARGET_MIPS16)
2612 return "neg\t%0,%1"; 2513 return "neg\t%0,%1";
2613 else 2514 else
2614 return "subu\t%0,%.,%1"; 2515 return "subu\t%0,%.,%1";
2615 } 2516 }
2616 [(set_attr "type" "arith") 2517 [(set_attr "alu_type" "sub")
2617 (set_attr "mode" "SI")]) 2518 (set_attr "mode" "SI")])
2618 2519
2619 (define_insn "negdi2" 2520 (define_insn "negdi2"
2620 [(set (match_operand:DI 0 "register_operand" "=d") 2521 [(set (match_operand:DI 0 "register_operand" "=d")
2621 (neg:DI (match_operand:DI 1 "register_operand" "d")))] 2522 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2622 "TARGET_64BIT && !TARGET_MIPS16" 2523 "TARGET_64BIT && !TARGET_MIPS16"
2623 "dsubu\t%0,%.,%1" 2524 "dsubu\t%0,%.,%1"
2624 [(set_attr "type" "arith") 2525 [(set_attr "alu_type" "sub")
2625 (set_attr "mode" "DI")]) 2526 (set_attr "mode" "DI")])
2626 2527
2627 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as 2528 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2628 ;; invalid; it does not flip their sign bit. We therefore can't use 2529 ;; invalid; it does not flip their sign bit. We therefore can't use
2629 ;; neg.fmt if the signs of NaNs matter. 2530 ;; neg.fmt if the signs of NaNs matter.
2644 if (TARGET_MIPS16) 2545 if (TARGET_MIPS16)
2645 return "not\t%0,%1"; 2546 return "not\t%0,%1";
2646 else 2547 else
2647 return "nor\t%0,%.,%1"; 2548 return "nor\t%0,%.,%1";
2648 } 2549 }
2649 [(set_attr "type" "logical") 2550 [(set_attr "alu_type" "not")
2650 (set_attr "mode" "<MODE>")]) 2551 (set_attr "mode" "<MODE>")])
2651 2552
2652 ;; 2553 ;;
2653 ;; .................... 2554 ;; ....................
2654 ;; 2555 ;;
2766 (match_operand:GPR 2 "uns_arith_operand" "d,K")))] 2667 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2767 "!TARGET_MIPS16" 2668 "!TARGET_MIPS16"
2768 "@ 2669 "@
2769 or\t%0,%1,%2 2670 or\t%0,%1,%2
2770 ori\t%0,%1,%x2" 2671 ori\t%0,%1,%x2"
2771 [(set_attr "type" "logical") 2672 [(set_attr "alu_type" "or")
2772 (set_attr "mode" "<MODE>")]) 2673 (set_attr "mode" "<MODE>")])
2773 2674
2774 (define_insn "*ior<mode>3_mips16" 2675 (define_insn "*ior<mode>3_mips16"
2775 [(set (match_operand:GPR 0 "register_operand" "=d") 2676 [(set (match_operand:GPR 0 "register_operand" "=d")
2776 (ior:GPR (match_operand:GPR 1 "register_operand" "%0") 2677 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2777 (match_operand:GPR 2 "register_operand" "d")))] 2678 (match_operand:GPR 2 "register_operand" "d")))]
2778 "TARGET_MIPS16" 2679 "TARGET_MIPS16"
2779 "or\t%0,%2" 2680 "or\t%0,%2"
2780 [(set_attr "type" "logical") 2681 [(set_attr "alu_type" "or")
2781 (set_attr "mode" "<MODE>")]) 2682 (set_attr "mode" "<MODE>")])
2782 2683
2783 (define_expand "xor<mode>3" 2684 (define_expand "xor<mode>3"
2784 [(set (match_operand:GPR 0 "register_operand") 2685 [(set (match_operand:GPR 0 "register_operand")
2785 (xor:GPR (match_operand:GPR 1 "register_operand") 2686 (xor:GPR (match_operand:GPR 1 "register_operand")
2793 (match_operand:GPR 2 "uns_arith_operand" "d,K")))] 2694 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2794 "!TARGET_MIPS16" 2695 "!TARGET_MIPS16"
2795 "@ 2696 "@
2796 xor\t%0,%1,%2 2697 xor\t%0,%1,%2
2797 xori\t%0,%1,%x2" 2698 xori\t%0,%1,%x2"
2798 [(set_attr "type" "logical") 2699 [(set_attr "alu_type" "xor")
2799 (set_attr "mode" "<MODE>")]) 2700 (set_attr "mode" "<MODE>")])
2800 2701
2801 (define_insn "" 2702 (define_insn ""
2802 [(set (match_operand:GPR 0 "register_operand" "=d,t,t") 2703 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2803 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d") 2704 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2805 "TARGET_MIPS16" 2706 "TARGET_MIPS16"
2806 "@ 2707 "@
2807 xor\t%0,%2 2708 xor\t%0,%2
2808 cmpi\t%1,%2 2709 cmpi\t%1,%2
2809 cmp\t%1,%2" 2710 cmp\t%1,%2"
2810 [(set_attr "type" "logical,arith,arith") 2711 [(set_attr "alu_type" "xor")
2811 (set_attr "mode" "<MODE>") 2712 (set_attr "mode" "<MODE>")
2812 (set_attr_alternative "length" 2713 (set_attr_alternative "length"
2813 [(const_int 4) 2714 [(const_int 4)
2814 (if_then_else (match_operand:VOID 2 "m16_uimm8_1") 2715 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2815 (const_int 4) 2716 (const_int 4)
2820 [(set (match_operand:GPR 0 "register_operand" "=d") 2721 [(set (match_operand:GPR 0 "register_operand" "=d")
2821 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) 2722 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2822 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))] 2723 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2823 "!TARGET_MIPS16" 2724 "!TARGET_MIPS16"
2824 "nor\t%0,%1,%2" 2725 "nor\t%0,%1,%2"
2825 [(set_attr "type" "logical") 2726 [(set_attr "alu_type" "nor")
2826 (set_attr "mode" "<MODE>")]) 2727 (set_attr "mode" "<MODE>")])
2827 2728
2828 ;; 2729 ;;
2829 ;; .................... 2730 ;; ....................
2830 ;; 2731 ;;
3038 "TARGET_64BIT && !TARGET_MIPS16" 2939 "TARGET_64BIT && !TARGET_MIPS16"
3039 { 2940 {
3040 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode)); 2941 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
3041 return "andi\t%0,%1,%x2"; 2942 return "andi\t%0,%1,%x2";
3042 } 2943 }
3043 [(set_attr "type" "logical") 2944 [(set_attr "alu_type" "and")
3044 (set_attr "mode" "<GPR:MODE>")]) 2945 (set_attr "mode" "<GPR:MODE>")])
3045 2946
3046 (define_insn "*zero_extendhi_truncqi" 2947 (define_insn "*zero_extendhi_truncqi"
3047 [(set (match_operand:HI 0 "register_operand" "=d") 2948 [(set (match_operand:HI 0 "register_operand" "=d")
3048 (zero_extend:HI 2949 (zero_extend:HI
3049 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] 2950 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3050 "TARGET_64BIT && !TARGET_MIPS16" 2951 "TARGET_64BIT && !TARGET_MIPS16"
3051 "andi\t%0,%1,0xff" 2952 "andi\t%0,%1,0xff"
3052 [(set_attr "type" "logical") 2953 [(set_attr "alu_type" "and")
3053 (set_attr "mode" "HI")]) 2954 (set_attr "mode" "HI")])
3054 2955
3055 ;; 2956 ;;
3056 ;; .................... 2957 ;; ....................
3057 ;; 2958 ;;
3979 [(set (match_operand:P 0 "register_operand" "=d") 3880 [(set (match_operand:P 0 "register_operand" "=d")
3980 (lo_sum:P (match_operand:P 1 "register_operand" "d") 3881 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3981 (match_operand:P 2 "immediate_operand" "")))] 3882 (match_operand:P 2 "immediate_operand" "")))]
3982 "!TARGET_MIPS16" 3883 "!TARGET_MIPS16"
3983 "<d>addiu\t%0,%1,%R2" 3884 "<d>addiu\t%0,%1,%R2"
3984 [(set_attr "type" "arith") 3885 [(set_attr "alu_type" "add")
3985 (set_attr "mode" "<MODE>")]) 3886 (set_attr "mode" "<MODE>")])
3986 3887
3987 (define_insn "*low<mode>_mips16" 3888 (define_insn "*low<mode>_mips16"
3988 [(set (match_operand:P 0 "register_operand" "=d") 3889 [(set (match_operand:P 0 "register_operand" "=d")
3989 (lo_sum:P (match_operand:P 1 "register_operand" "0") 3890 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3990 (match_operand:P 2 "immediate_operand" "")))] 3891 (match_operand:P 2 "immediate_operand" "")))]
3991 "TARGET_MIPS16" 3892 "TARGET_MIPS16"
3992 "<d>addiu\t%0,%R2" 3893 "<d>addiu\t%0,%R2"
3993 [(set_attr "type" "arith") 3894 [(set_attr "alu_type" "add")
3994 (set_attr "mode" "<MODE>") 3895 (set_attr "mode" "<MODE>")
3995 (set_attr "extended_mips16" "yes")]) 3896 (set_attr "extended_mips16" "yes")])
3996 3897
3997 ;; Expose MIPS16 uses of the global pointer after reload if the function 3898 ;; Expose MIPS16 uses of the global pointer after reload if the function
3998 ;; is responsible for setting up the register itself. 3899 ;; is responsible for setting up the register itself.
5746 5647
5747 /* This bit is similar to expand_builtin_longjmp except that it 5648 /* This bit is similar to expand_builtin_longjmp except that it
5748 restores $gp as well. */ 5649 restores $gp as well. */
5749 mips_emit_move (hard_frame_pointer_rtx, fp); 5650 mips_emit_move (hard_frame_pointer_rtx, fp);
5750 mips_emit_move (pv, lab); 5651 mips_emit_move (pv, lab);
5751 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX); 5652 emit_stack_restore (SAVE_NONLOCAL, stack);
5752 mips_emit_move (gp, gpv); 5653 mips_emit_move (gp, gpv);
5753 emit_use (hard_frame_pointer_rtx); 5654 emit_use (hard_frame_pointer_rtx);
5754 emit_use (stack_pointer_rtx); 5655 emit_use (stack_pointer_rtx);
5755 emit_use (gp); 5656 emit_use (gp);
5756 emit_indirect_jump (pv); 5657 emit_indirect_jump (pv);
6154 ;; - The splitter deliberately changes the liveness of $gp. The unsplit 6055 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6155 ;; instruction preserves $gp and so have no effect on its liveness. 6056 ;; instruction preserves $gp and so have no effect on its liveness.
6156 ;; But once we generate the separate insns, it becomes obvious that 6057 ;; But once we generate the separate insns, it becomes obvious that
6157 ;; $gp is not live on entry to the call. 6058 ;; $gp is not live on entry to the call.
6158 ;; 6059 ;;
6159 ;; ??? The operands[2] = insn check is a hack to make the original insn
6160 ;; available to the splitter.
6161 (define_insn_and_split "call_internal" 6060 (define_insn_and_split "call_internal"
6162 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S")) 6061 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6163 (match_operand 1 "" "")) 6062 (match_operand 1 "" ""))
6164 (clobber (reg:SI RETURN_ADDR_REGNUM))] 6063 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6165 "" 6064 ""
6166 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, 1); } 6065 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, 1); }
6167 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)" 6066 "reload_completed && TARGET_SPLIT_CALLS"
6168 [(const_int 0)] 6067 [(const_int 0)]
6169 { 6068 {
6170 mips_split_call (operands[2], gen_call_split (operands[0], operands[1])); 6069 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1]));
6171 DONE; 6070 DONE;
6172 } 6071 }
6173 [(set_attr "jal" "indirect,direct")]) 6072 [(set_attr "jal" "indirect,direct")])
6174 6073
6175 (define_insn "call_split" 6074 (define_insn "call_split"
6190 (match_operand 1)) 6089 (match_operand 1))
6191 (const_int 1) 6090 (const_int 1)
6192 (clobber (reg:SI RETURN_ADDR_REGNUM))] 6091 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6193 "" 6092 ""
6194 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, -1); } 6093 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, -1); }
6195 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)" 6094 "reload_completed && TARGET_SPLIT_CALLS"
6196 [(const_int 0)] 6095 [(const_int 0)]
6197 { 6096 {
6198 mips_split_call (operands[2], 6097 mips_split_call (curr_insn,
6199 gen_call_direct_split (operands[0], operands[1])); 6098 gen_call_direct_split (operands[0], operands[1]));
6200 DONE; 6099 DONE;
6201 } 6100 }
6202 [(set_attr "type" "call")]) 6101 [(set_attr "type" "call")])
6203 6102
6229 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 6128 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6230 (match_operand 2 "" ""))) 6129 (match_operand 2 "" "")))
6231 (clobber (reg:SI RETURN_ADDR_REGNUM))] 6130 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6232 "" 6131 ""
6233 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); } 6132 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6234 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)" 6133 "reload_completed && TARGET_SPLIT_CALLS"
6235 [(const_int 0)] 6134 [(const_int 0)]
6236 { 6135 {
6237 mips_split_call (operands[3], 6136 mips_split_call (curr_insn,
6238 gen_call_value_split (operands[0], operands[1], 6137 gen_call_value_split (operands[0], operands[1],
6239 operands[2])); 6138 operands[2]));
6240 DONE; 6139 DONE;
6241 } 6140 }
6242 [(set_attr "jal" "indirect,direct")]) 6141 [(set_attr "jal" "indirect,direct")])
6258 (match_operand 2))) 6157 (match_operand 2)))
6259 (const_int 1) 6158 (const_int 1)
6260 (clobber (reg:SI RETURN_ADDR_REGNUM))] 6159 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6261 "" 6160 ""
6262 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, -1); } 6161 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, -1); }
6263 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)" 6162 "reload_completed && TARGET_SPLIT_CALLS"
6264 [(const_int 0)] 6163 [(const_int 0)]
6265 { 6164 {
6266 mips_split_call (operands[3], 6165 mips_split_call (curr_insn,
6267 gen_call_value_direct_split (operands[0], operands[1], 6166 gen_call_value_direct_split (operands[0], operands[1],
6268 operands[2])); 6167 operands[2]));
6269 DONE; 6168 DONE;
6270 } 6169 }
6271 [(set_attr "type" "call")]) 6170 [(set_attr "type" "call")])
6290 (call (mem:SI (match_dup 1)) 6189 (call (mem:SI (match_dup 1))
6291 (match_dup 2))) 6190 (match_dup 2)))
6292 (clobber (reg:SI RETURN_ADDR_REGNUM))] 6191 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6293 "" 6192 ""
6294 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); } 6193 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6295 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)" 6194 "reload_completed && TARGET_SPLIT_CALLS"
6296 [(const_int 0)] 6195 [(const_int 0)]
6297 { 6196 {
6298 mips_split_call (operands[4], 6197 mips_split_call (curr_insn,
6299 gen_call_value_multiple_split (operands[0], operands[1], 6198 gen_call_value_multiple_split (operands[0], operands[1],
6300 operands[2], operands[3])); 6199 operands[2], operands[3]));
6301 DONE; 6200 DONE;
6302 } 6201 }
6303 [(set_attr "jal" "indirect,direct")]) 6202 [(set_attr "jal" "indirect,direct")])
6351 [(prefetch (match_operand:QI 0 "address_operand" "p") 6250 [(prefetch (match_operand:QI 0 "address_operand" "p")
6352 (match_operand 1 "const_int_operand" "n") 6251 (match_operand 1 "const_int_operand" "n")
6353 (match_operand 2 "const_int_operand" "n"))] 6252 (match_operand 2 "const_int_operand" "n"))]
6354 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" 6253 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6355 { 6254 {
6356 if (TARGET_LOONGSON_2EF) 6255 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
6357 /* Loongson 2[ef] use load to $0 to perform prefetching. */ 6256 /* Loongson 2[ef] and Loongson 3a use load to $0 to perform prefetching. */
6358 return "ld\t$0,%a0"; 6257 return "ld\t$0,%a0";
6359 operands[1] = mips_prefetch_cookie (operands[1], operands[2]); 6258 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6360 return "pref\t%1,%a0"; 6259 return "pref\t%1,%a0";
6361 } 6260 }
6362 [(set_attr "type" "prefetch")]) 6261 [(set_attr "type" "prefetch")])
6579 ; MIPS fixed-point instructions. 6478 ; MIPS fixed-point instructions.
6580 (include "mips-fixed.md") 6479 (include "mips-fixed.md")
6581 6480
6582 ; ST-Microelectronics Loongson-2E/2F-specific patterns. 6481 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6583 (include "loongson.md") 6482 (include "loongson.md")
6483
6484 (define_c_enum "unspec" [
6485 UNSPEC_ADDRESS_FIRST
6486 ])