Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/pa/predicates.md @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
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date | Tue, 22 Mar 2011 17:18:12 +0900 |
parents | 77e2b8dfacca |
children | 04ced10e8804 |
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65:65488c3d617d | 67:f6334be47118 |
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1 ;; Predicate definitions for HP PA-RISC. | 1 ;; Predicate definitions for HP PA-RISC. |
2 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc. | 2 ;; Copyright (C) 2005, 2007, 2010 Free Software Foundation, Inc. |
3 ;; | 3 ;; |
4 ;; This file is part of GCC. | 4 ;; This file is part of GCC. |
5 ;; | 5 ;; |
6 ;; GCC is free software; you can redistribute it and/or modify | 6 ;; GCC is free software; you can redistribute it and/or modify |
7 ;; it under the terms of the GNU General Public License as published by | 7 ;; it under the terms of the GNU General Public License as published by |
238 return 0; | 238 return 0; |
239 | 239 |
240 return memory_address_p (mode, XEXP (op, 0)); | 240 return memory_address_p (mode, XEXP (op, 0)); |
241 }) | 241 }) |
242 | 242 |
243 ;; Accept anything that can be used as the source operand for a | |
244 ;; prefetch instruction with a cache-control completer. | |
245 | |
246 (define_predicate "prefetch_cc_operand" | |
247 (match_code "mem") | |
248 { | |
249 if (GET_CODE (op) != MEM) | |
250 return 0; | |
251 | |
252 op = XEXP (op, 0); | |
253 | |
254 /* We must reject virtual registers as we don't allow REG+D. */ | |
255 if (op == virtual_incoming_args_rtx | |
256 || op == virtual_stack_vars_rtx | |
257 || op == virtual_stack_dynamic_rtx | |
258 || op == virtual_outgoing_args_rtx | |
259 || op == virtual_cfa_rtx) | |
260 return 0; | |
261 | |
262 if (!REG_P (op) && !IS_INDEX_ADDR_P (op)) | |
263 return 0; | |
264 | |
265 /* Until problems with management of the REG_POINTER flag are resolved, | |
266 we need to delay creating prefetch insns with unscaled indexed addresses | |
267 until CSE is not expected. */ | |
268 if (!TARGET_NO_SPACE_REGS | |
269 && !cse_not_expected | |
270 && GET_CODE (op) == PLUS | |
271 && REG_P (XEXP (op, 0))) | |
272 return 0; | |
273 | |
274 return memory_address_p (mode, op); | |
275 }) | |
276 | |
277 ;; Accept anything that can be used as the source operand for a | |
278 ;; prefetch instruction with no cache-control completer. | |
279 | |
280 (define_predicate "prefetch_nocc_operand" | |
281 (match_code "mem") | |
282 { | |
283 if (GET_CODE (op) != MEM) | |
284 return 0; | |
285 | |
286 op = XEXP (op, 0); | |
287 | |
288 /* Until problems with management of the REG_POINTER flag are resolved, | |
289 we need to delay creating prefetch insns with unscaled indexed addresses | |
290 until CSE is not expected. */ | |
291 if (!TARGET_NO_SPACE_REGS | |
292 && !cse_not_expected | |
293 && GET_CODE (op) == PLUS | |
294 && REG_P (XEXP (op, 0)) | |
295 && REG_P (XEXP (op, 1))) | |
296 return 0; | |
297 | |
298 return memory_address_p (mode, op); | |
299 }) | |
300 | |
301 ;; Accept REG and any CONST_INT that can be moved in one instruction | 243 ;; Accept REG and any CONST_INT that can be moved in one instruction |
302 ;; into a general register. | 244 ;; into a general register. |
303 | 245 |
304 (define_predicate "reg_or_cint_move_operand" | 246 (define_predicate "reg_or_cint_move_operand" |
305 (match_code "subreg,reg,const_int") | 247 (match_code "subreg,reg,const_int") |