CbC/CbC_gcc: gcc/config/rs6000/predicates.md comparison

comparison gcc/config/rs6000/predicates.md @ 67:f6334be47118

update gcc from gcc-4.6-20100522 to gcc-4.6-20110318

author	nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date	Tue, 22 Mar 2011 17:18:12 +0900
parents	77e2b8dfacca
children	04ced10e8804

comparison

equal deleted inserted replaced

-:65488c3d617d
+:f6334be47118
 ;; Predicate definitions for POWER and PowerPC.
-;; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010
+;; Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
 ;; GCC is free software; you can redistribute it and/or modify
 ;; it under the terms of the GNU General Public License as published by
 (and (match_operand 0 "register_operand")
 	(match_test "GET_CODE (op) != REG
 		     || VLOGICAL_REGNO_P (REGNO (op))
 		     || REGNO (op) > LAST_VIRTUAL_REGISTER")))
-;; Return 1 if op is XER register.
+;; Return 1 if op is the carry register.
-(define_predicate "xer_operand"
+(define_predicate "ca_operand"
 (and (match_code "reg")
-(match_test "XER_REGNO_P (REGNO (op))")))
+(match_test "CA_REGNO_P (REGNO (op))")))
 ;; Return 1 if op is a signed 5-bit constant integer.
 (define_predicate "s5bit_cint_operand"
 (and (match_code "const_int")
 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
 ;; Return 1 if op is a register that is not special.
 (define_predicate "gpc_reg_operand"
 (and (match_operand 0 "register_operand")
 	(match_test "(GET_CODE (op) != REG
 		      || (REGNO (op) >= ARG_POINTER_REGNUM
-			  && !XER_REGNO_P (REGNO (op)))
+			  && !CA_REGNO_P (REGNO (op)))
 		      || REGNO (op) < MQ_REGNO)
 		     && !((TARGET_E500_DOUBLE || TARGET_SPE)
 			  && invalid_e500_subreg (op, mode))")))
 ;; Return 1 if op is a register that is a condition register field.
 /* As the paired vectors are actually FPRs it seems that there is
 no easy way to load a CONST_VECTOR without using memory.  */
 if (TARGET_PAIRED_FLOAT)
 return false;
-if ((VSX_VECTOR_MODE (mode) || mode == TImode) && zero_constant (op, mode))
+if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
-return true;
-if (ALTIVEC_VECTOR_MODE (mode))
 {
 if (zero_constant (op, mode))
-return true;
+	return true;
 return easy_altivec_constant (op, mode);
 }
 if (SPE_VECTOR_MODE (mode))
 {
 (define_predicate "easy_vector_constant_add_self"
 (and (match_code "const_vector")
 (and (match_test "TARGET_ALTIVEC")
 	    (match_test "easy_altivec_constant (op, mode)")))
 {
-HOST_WIDE_INT val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
+HOST_WIDE_INT val;
+if (mode == V2DImode || mode == V2DFmode)
+return 0;
+val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
 val = ((val & 0xff) ^ 0x80) - 0x80;
 return EASY_VECTOR_15_ADD_SELF (val);
 })
 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
 (define_predicate "easy_vector_constant_msb"
 (and (match_code "const_vector")
 (and (match_test "TARGET_ALTIVEC")
 	    (match_test "easy_altivec_constant (op, mode)")))
 {
-HOST_WIDE_INT val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
+HOST_WIDE_INT val;
+if (mode == V2DImode || mode == V2DFmode)
+return 0;
+val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
 })
 ;; Return 1 if operand is constant zero (scalars and vectors).
 (define_predicate "zero_constant"
 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
 ;; lwa instruction.
 (define_predicate "lwa_operand"
 (match_code "reg,subreg,mem")
 {
-rtx inner = op;
+rtx inner, addr, offset;
+inner = op;
 if (reload_completed && GET_CODE (inner) == SUBREG)
 inner = SUBREG_REG (inner);
-return gpc_reg_operand (inner, mode)
+if (gpc_reg_operand (inner, mode))
-|| (memory_operand (inner, mode)
+return true;
-	&& GET_CODE (XEXP (inner, 0)) != PRE_INC
+if (!memory_operand (inner, mode))
-	&& GET_CODE (XEXP (inner, 0)) != PRE_DEC
+return false;
-	&& (GET_CODE (XEXP (inner, 0)) != PRE_MODIFY
+addr = XEXP (inner, 0);
-	    || legitimate_indexed_address_p (XEXP (XEXP (inner, 0), 1), 0))
+if (GET_CODE (addr) == PRE_INC
-	&& (GET_CODE (XEXP (inner, 0)) != PLUS
+|| GET_CODE (addr) == PRE_DEC
-	    || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
+|| (GET_CODE (addr) == PRE_MODIFY
-	    || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
+	  && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
+return false;
+if (GET_CODE (addr) == LO_SUM
+&& GET_CODE (XEXP (addr, 0)) == REG
+&& GET_CODE (XEXP (addr, 1)) == CONST)
+addr = XEXP (XEXP (addr, 1), 0);
+if (GET_CODE (addr) != PLUS)
+return true;
+offset = XEXP (addr, 1);
+if (GET_CODE (offset) != CONST_INT)
+return true;
+return INTVAL (offset) % 4 == 0;
 })
 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
 (define_predicate "symbol_ref_operand"
 (and (match_code "symbol_ref")
 register.  */
 if (register_operand (op, mode))
 return 1;
 /* A SYMBOL_REF referring to the TOC is valid.  */
-if (legitimate_constant_pool_address_p (op))
+if (legitimate_constant_pool_address_p (op, mode, false))
 return 1;
 /* A constant pool expression (relative to the TOC) is valid */
 if (toc_relative_expr_p (op))
 return 1;
 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
 ;; it must be a positive comparison.
 (define_predicate "scc_comparison_operator"
 (and (match_operand 0 "branch_comparison_operator")
 (match_code "eq,lt,gt,ltu,gtu,unordered")))
+;; Return 1 if OP is a comparison operation whose inverse would be valid for
+;; an SCC insn.
+(define_predicate "scc_rev_comparison_operator"
+(and (match_operand 0 "branch_comparison_operator")
+(match_code "ne,le,ge,leu,geu,ordered")))
 ;; Return 1 if OP is a comparison operation that is valid for a branch
 ;; insn, which is true if the corresponding bit in the CC register is set.
 (define_predicate "branch_positive_comparison_operator"
 (and (match_operand 0 "branch_comparison_operator")

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comparison gcc/config/rs6000/predicates.md @ 67:f6334be47118