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comparison gcc/config/rs6000/rs6000-c.c @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents b7f97abdc517
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 /* Subroutines for the C front end on the POWER and PowerPC architectures. 1 /* Subroutines for the C front end on the POWER and PowerPC architectures.
2 Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 2 Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc. 3 Free Software Foundation, Inc.
4 4
5 Contributed by Zack Weinberg <zack@codesourcery.com> 5 Contributed by Zack Weinberg <zack@codesourcery.com>
6 and Paolo Bonzini <bonzini@gnu.org> 6 and Paolo Bonzini <bonzini@gnu.org>
7 7
25 #include "system.h" 25 #include "system.h"
26 #include "coretypes.h" 26 #include "coretypes.h"
27 #include "tm.h" 27 #include "tm.h"
28 #include "cpplib.h" 28 #include "cpplib.h"
29 #include "tree.h" 29 #include "tree.h"
30 #include "c-common.h" 30 #include "c-family/c-common.h"
31 #include "c-pragma.h" 31 #include "c-family/c-pragma.h"
32 #include "c-tree.h" 32 #include "diagnostic-core.h"
33 #include "toplev.h"
34 #include "tm_p.h" 33 #include "tm_p.h"
35 #include "target.h" 34 #include "target.h"
36 #include "langhooks.h" 35 #include "langhooks.h"
37 36
38 37
361 builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp"); 360 builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp");
362 builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp"); 361 builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp");
363 builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp"); 362 builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp");
364 builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp"); 363 builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp");
365 } 364 }
365 if (RS6000_RECIP_HAVE_RE_P (DFmode))
366 builtin_define ("__RECIP__");
367 if (RS6000_RECIP_HAVE_RE_P (SFmode))
368 builtin_define ("__RECIPF__");
369 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode))
370 builtin_define ("__RSQRTE__");
371 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode))
372 builtin_define ("__RSQRTEF__");
373 if (TARGET_RECIP_PRECISION)
374 builtin_define ("__RECIP_PRECISION__");
366 375
367 /* Tell users they can use __builtin_bswap{16,64}. */ 376 /* Tell users they can use __builtin_bswap{16,64}. */
368 builtin_define ("__HAVE_BSWAP__"); 377 builtin_define ("__HAVE_BSWAP__");
369 378
370 /* May be overridden by target configuration. */ 379 /* May be overridden by target configuration. */
372 381
373 if (TARGET_LONG_DOUBLE_128) 382 if (TARGET_LONG_DOUBLE_128)
374 { 383 {
375 builtin_define ("__LONG_DOUBLE_128__"); 384 builtin_define ("__LONG_DOUBLE_128__");
376 builtin_define ("__LONGDOUBLE128"); 385 builtin_define ("__LONGDOUBLE128");
386 }
387
388 switch (TARGET_CMODEL)
389 {
390 /* Deliberately omit __CMODEL_SMALL__ since that was the default
391 before --mcmodel support was added. */
392 case CMODEL_MEDIUM:
393 builtin_define ("__CMODEL_MEDIUM__");
394 break;
395 case CMODEL_LARGE:
396 builtin_define ("__CMODEL_LARGE__");
397 break;
398 default:
399 break;
377 } 400 }
378 401
379 switch (rs6000_current_abi) 402 switch (rs6000_current_abi)
380 { 403 {
381 case ABI_V4: 404 case ABI_V4:
478 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 }, 501 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
479 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 502 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
480 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 }, 503 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
481 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP, 504 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
482 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 505 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
506 { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
507 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
483 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN, 508 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
484 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 509 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
510 { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
511 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
512 { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
513 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
514 { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
515 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
516 { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_VEC_RSQRT_V2DF,
517 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
485 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP, 518 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
486 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 519 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
520 { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
521 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
487 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ, 522 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
488 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 523 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
489 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ, 524 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
490 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 525 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
491 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB, 526 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
963 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP, 998 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
964 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 999 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
965 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, 1000 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
966 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1001 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
967 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, 1002 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
1003 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1004 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
1005 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1006 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
1007 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1008 ~RS6000_BTI_unsigned_V2DI, 0 },
1009 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
1010 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1011 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
968 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1012 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
969 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, 1013 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
970 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1014 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
971 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX, 1015 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
972 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1016 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1075 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, 1119 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
1076 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1120 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1077 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, 1121 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
1078 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1122 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1079 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, 1123 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
1080 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1124 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1125 ~RS6000_BTI_unsigned_V16QI, 0 },
1081 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL, 1126 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
1082 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1127 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1128 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
1129 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1130 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
1131 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1132 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
1133 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1134 ~RS6000_BTI_unsigned_V2DI, 0 },
1135 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
1136 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1083 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1137 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1084 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1138 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1085 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1139 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1086 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1140 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1087 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1141 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1096 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1150 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1097 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1151 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1098 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1152 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1099 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1153 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1100 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1154 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1155 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1156 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1157 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1158 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1159 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1160 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1161 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1162 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1163 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1164 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1165 ~RS6000_BTI_unsigned_long_long, 0 },
1101 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1166 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1102 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1167 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1103 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1168 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1104 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1169 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1105 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1170 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1114 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1179 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1115 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1180 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1116 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1181 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1117 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1182 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1118 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1183 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1184 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1185 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1186 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1187 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1188 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1189 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1190 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1191 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1192 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1193 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1194 ~RS6000_BTI_unsigned_long_long, 0 },
1119 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1195 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1120 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1196 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1121 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1197 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1122 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1198 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1123 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1199 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
2607 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 2683 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
2608 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE }, 2684 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
2609 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 2685 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
2610 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE }, 2686 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },
2611 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, 2687 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
2688 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
2689 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
2690 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
2691 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
2692 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2693 ~RS6000_BTI_unsigned_V2DI },
2694 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
2695 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
2696 ~RS6000_BTI_bool_V2DI },
2697 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
2612 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 2698 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
2613 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, 2699 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
2614 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 2700 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
2615 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX, 2701 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
2616 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 2702 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
2772 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 2858 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
2773 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, 2859 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
2774 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 2860 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
2775 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL, 2861 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
2776 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 2862 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
2863 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
2864 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
2865 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
2866 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
2867 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
2868 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
2869 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
2870 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2871 ~RS6000_BTI_unsigned_V2DI },
2872 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
2873 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
2874 ~RS6000_BTI_bool_V2DI },
2777 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 2875 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
2778 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 2876 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
2779 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 2877 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
2780 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 2878 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
2781 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 2879 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
2965 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, 3063 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
2966 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, 3064 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
2967 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3065 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
2968 RS6000_BTI_NOT_OPAQUE }, 3066 RS6000_BTI_NOT_OPAQUE },
2969 3067
3068 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3069 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3070 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3071 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3072 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3073 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3074 ~RS6000_BTI_unsigned_V2DI, 0 },
3075 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3076 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
3077 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3078 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3079 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3080 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3081 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3082 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
3083 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3084 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3085 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3086 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3087 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3088 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
3089 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3090 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3091 ~RS6000_BTI_unsigned_V4SI, 0 },
3092 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3093 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3094 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3095 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3096 ~RS6000_BTI_unsigned_long, 0 },
3097 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3098 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
3099 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3100 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
3101 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3102 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3103 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3104 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3105 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3106 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3107 ~RS6000_BTI_unsigned_V8HI, 0 },
3108 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3109 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3110 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3111 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
3112 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3113 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3114 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3115 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3116 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3117 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3118 ~RS6000_BTI_unsigned_V16QI, 0 },
3119 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3120 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3121
3122 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
3123 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3124 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3125 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3126 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3127 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3128 ~RS6000_BTI_unsigned_V2DI },
3129 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3130 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3131 ~RS6000_BTI_bool_V2DI },
3132 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
3133 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3134 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
3135 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3136 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3137 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3138 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3139 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3140 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3141 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3142 ~RS6000_BTI_unsigned_V4SI },
3143 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3144 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3145 ~RS6000_BTI_UINTSI },
3146 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3147 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3148 ~RS6000_BTI_bool_V4SI },
3149 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3150 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3151 ~RS6000_BTI_UINTSI },
3152 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3153 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3154 ~RS6000_BTI_INTSI },
3155 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3156 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3157 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3158 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3159 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3160 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3161 ~RS6000_BTI_unsigned_V8HI },
3162 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3163 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3164 ~RS6000_BTI_UINTHI },
3165 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3166 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3167 ~RS6000_BTI_bool_V8HI },
3168 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3169 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3170 ~RS6000_BTI_UINTHI },
3171 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3172 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3173 ~RS6000_BTI_INTHI },
3174 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3175 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3176 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3177 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3178 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3179 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3180 ~RS6000_BTI_unsigned_V16QI },
3181 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3182 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3183 ~RS6000_BTI_UINTQI },
3184 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3185 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3186 ~RS6000_BTI_bool_V16QI },
3187 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3188 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3189 ~RS6000_BTI_UINTQI },
3190 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3191 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3192 ~RS6000_BTI_INTQI },
3193 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3194 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
3195 ~RS6000_BTI_pixel_V8HI },
3196
2970 /* Predicates. */ 3197 /* Predicates. */
2971 { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 3198 { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
2972 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3199 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
2973 { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 3200 { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
2974 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 3201 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },