CbC/CbC_gcc: gcc/config/rs6000/rs6000.h comparison

comparison gcc/config/rs6000/rs6000.h @ 67:f6334be47118

update gcc from gcc-4.6-20100522 to gcc-4.6-20110318

author	nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date	Tue, 22 Mar 2011 17:18:12 +0900
parents	77e2b8dfacca
children	04ced10e8804

comparison

equal deleted inserted replaced

-:65488c3d617d
+:f6334be47118
 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
+2010, 2011
 Free Software Foundation, Inc.
 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
 This file is part of GCC.
 <http://www.gnu.org/licenses/>.  */
 /* Note that some other tm.h files include this one and then override
 many of the definitions.  */
+#ifndef RS6000_OPTS_H
+#include "config/rs6000/rs6000-opts.h"
+#endif
 /* Definitions for the object file format.  These are set at
 compile-time.  */
 #define OBJECT_XCOFF 1
 #define OBJECT_ELF 2
 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
 #ifndef TARGET_AIX
 #define TARGET_AIX 0
+#endif
+#ifndef TARGET_AIX_OS
+#define TARGET_AIX_OS 0
 #endif
 /* Control whether function entry points use a "dot" symbol when
 ABI_AIX.  */
 #define DOT_SYMBOLS 1
 %{mcpu=e300c2: -me300} \
 %{mcpu=e300c3: -me300} \
 %{mcpu=e500mc: -me500mc} \
 %{mcpu=e500mc64: -me500mc64} \
 %{maltivec: -maltivec} \
+%{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
 -many"
 #define CPP_DEFAULT_SPEC ""
 #define ASM_DEFAULT_SPEC ""
 #ifndef TARGET_SECURE_PLT
 #define TARGET_SECURE_PLT 0
 #endif
+#ifndef TARGET_CMODEL
+#define TARGET_CMODEL CMODEL_SMALL
+#endif
 #define TARGET_32BIT		(! TARGET_64BIT)
 #ifndef HAVE_AS_TLS
 #define HAVE_AS_TLS 0
 #endif
 /* The option machinery will define this.  */
 #endif
 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
-/* Processor type.  Order must match cpu attribute in MD file.  */
-enum processor_type
-{
-PROCESSOR_RIOS1,
-PROCESSOR_RIOS2,
-PROCESSOR_RS64A,
-PROCESSOR_MPCCORE,
-PROCESSOR_PPC403,
-PROCESSOR_PPC405,
-PROCESSOR_PPC440,
-PROCESSOR_PPC476,
-PROCESSOR_PPC601,
-PROCESSOR_PPC603,
-PROCESSOR_PPC604,
-PROCESSOR_PPC604e,
-PROCESSOR_PPC620,
-PROCESSOR_PPC630,
-PROCESSOR_PPC750,
-PROCESSOR_PPC7400,
-PROCESSOR_PPC7450,
-PROCESSOR_PPC8540,
-PROCESSOR_PPCE300C2,
-PROCESSOR_PPCE300C3,
-PROCESSOR_PPCE500MC,
-PROCESSOR_PPCE500MC64,
-PROCESSOR_POWER4,
-PROCESSOR_POWER5,
-PROCESSOR_POWER6,
-PROCESSOR_POWER7,
-PROCESSOR_CELL,
-PROCESSOR_PPCA2
-};
 /* FPU operations supported.
 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
 also test TARGET_HARD_FLOAT.  */
 #define TARGET_SINGLE_FLOAT 1
 #define TARGET_DOUBLE_FLOAT 1
 #define TARGET_SINGLE_FPU   0
 #define TARGET_SIMPLE_FPU   0
 #define TARGET_XILINX_FPU   0
-extern enum processor_type rs6000_cpu;
 /* Recast the processor type to the cpu attribute.  */
 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
 /* Define generic processor types based upon current deployment.  */
 #define PROCESSOR_COMMON    PROCESSOR_PPC601
 /* Define the default processor.  This is overridden by other tm.h files.  */
 #define PROCESSOR_DEFAULT   PROCESSOR_RIOS1
 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
-/* FP processor type.  */
-enum fpu_type_t
-{
-	FPU_NONE,		/* No FPU */
-	FPU_SF_LITE,		/* Limited Single Precision FPU */
-	FPU_DF_LITE,		/* Limited Double Precision FPU */
-	FPU_SF_FULL,		/* Full Single Precision FPU */
-	FPU_DF_FULL		/* Full Double Single Precision FPU */
-};
 extern enum fpu_type_t fpu_type;
 /* Specify the dialect of assembler to use.  New mnemonics is dialect one
 and the old mnemonics are dialect zero.  */
 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
-/* Types of costly dependences.  */
-enum rs6000_dependence_cost
-{
-max_dep_latency = 1000,
-no_dep_costly,
-all_deps_costly,
-true_store_to_load_dep_costly,
-store_to_load_dep_costly
-};
-/* Types of nop insertion schemes in sched target hook sched_finish.  */
-enum rs6000_nop_insertion
-{
-sched_finish_regroup_exact = 1000,
-sched_finish_pad_groups,
-sched_finish_none
-};
-/* Dispatch group termination caused by an insn.  */
-enum group_termination
-{
-current_group,
-previous_group
-};
 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
 struct rs6000_cpu_select
 {
 const char *string;
 };
 extern struct rs6000_cpu_select rs6000_select[];
 /* Debug support */
-extern const char *rs6000_debug_name;	/* Name for -mdebug-xxxx option */
+#define MASK_DEBUG_STACK	0x01	/* debug stack applications */
-extern int rs6000_debug_stack;		/* debug stack applications */
+#define	MASK_DEBUG_ARG		0x02	/* debug argument handling */
-extern int rs6000_debug_arg;		/* debug argument handling */
+#define MASK_DEBUG_REG		0x04	/* debug register handling */
-extern int rs6000_debug_reg;		/* debug register handling */
+#define MASK_DEBUG_ADDR		0x08	/* debug memory addressing */
-extern int rs6000_debug_addr;		/* debug memory addressing */
+#define MASK_DEBUG_COST		0x10	/* debug rtx codes */
-extern int rs6000_debug_cost;		/* debug rtx_costs */
+#define MASK_DEBUG_TARGET	0x20	/* debug target attribute/pragma */
+#define MASK_DEBUG_ALL		(MASK_DEBUG_STACK \
-#define	TARGET_DEBUG_STACK	rs6000_debug_stack
+				 | MASK_DEBUG_ARG \
-#define	TARGET_DEBUG_ARG	rs6000_debug_arg
+				 | MASK_DEBUG_REG \
-#define TARGET_DEBUG_REG	rs6000_debug_reg
+				 | MASK_DEBUG_ADDR \
-#define TARGET_DEBUG_ADDR	rs6000_debug_addr
+				 | MASK_DEBUG_COST \
-#define TARGET_DEBUG_COST	rs6000_debug_cost
+				 | MASK_DEBUG_TARGET)
-extern const char *rs6000_traceback_name; /* Type of traceback table.  */
+#define	TARGET_DEBUG_STACK	(rs6000_debug & MASK_DEBUG_STACK)
+#define	TARGET_DEBUG_ARG	(rs6000_debug & MASK_DEBUG_ARG)
-/* These are separate from target_flags because we've run out of bits
+#define TARGET_DEBUG_REG	(rs6000_debug & MASK_DEBUG_REG)
-there.  */
+#define TARGET_DEBUG_ADDR	(rs6000_debug & MASK_DEBUG_ADDR)
-extern int rs6000_long_double_type_size;
+#define TARGET_DEBUG_COST	(rs6000_debug & MASK_DEBUG_COST)
-extern int rs6000_ieeequad;
+#define TARGET_DEBUG_TARGET	(rs6000_debug & MASK_DEBUG_TARGET)
-extern int rs6000_altivec_abi;
-extern int rs6000_spe_abi;
-extern int rs6000_spe;
-extern int rs6000_float_gprs;
-extern int rs6000_alignment_flags;
-extern const char *rs6000_sched_insert_nops_str;
-extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
-extern int rs6000_xilinx_fpu;
-/* Describe which vector unit to use for a given machine mode.  */
-enum rs6000_vector {
-VECTOR_NONE,			/* Type is not  a vector or not supported */
-VECTOR_ALTIVEC,		/* Use altivec for vector processing */
-VECTOR_VSX,			/* Use VSX for vector processing */
-VECTOR_PAIRED,		/* Use paired floating point for vectors */
-VECTOR_SPE,			/* Use SPE for vector processing */
-VECTOR_OTHER			/* Some other vector unit */
-};
 extern enum rs6000_vector rs6000_vector_unit[];
 #define VECTOR_UNIT_NONE_P(MODE)			\
 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
 #define TARGET_FPRS 1
 #define TARGET_E500_SINGLE 0
 #define TARGET_E500_DOUBLE 0
 #define CHECK_E500_OPTIONS do { } while (0)
+/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
+Enable 32-bit fcfid's on any of the switches for newer ISA machines or
+XILINX.  */
+#define TARGET_FCFID	(TARGET_POWERPC64 \
+			 || TARGET_POPCNTB	/* ISA 2.02 */ \
+			 || TARGET_CMPB		/* ISA 2.05 */ \
+			 || TARGET_POPCNTD	/* ISA 2.06 */ \
+			 || TARGET_XILINX_FPU)
+#define TARGET_FCTIDZ	TARGET_FCFID
+#define TARGET_STFIWX	TARGET_PPC_GFXOPT
+#define TARGET_LFIWAX	TARGET_CMPB
+#define TARGET_LFIWZX	TARGET_POPCNTD
+#define TARGET_FCFIDS	TARGET_POPCNTD
+#define TARGET_FCFIDU	TARGET_POPCNTD
+#define TARGET_FCFIDUS	TARGET_POPCNTD
+#define TARGET_FCTIDUZ	TARGET_POPCNTD
+#define TARGET_FCTIWUZ	TARGET_POPCNTD
 /* E500 processors only support plain "sync", not lwsync.  */
 #define TARGET_NO_LWSYNC TARGET_E500
-/* Sometimes certain combinations of command options do not make sense
+/* Which machine supports the various reciprocal estimate instructions.  */
-on a particular target machine.  You can define a macro
+#define TARGET_FRES	(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
-`OVERRIDE_OPTIONS' to take account of this.  This macro, if
+			 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
-defined, is executed once just after all the command options have
-been parsed.
+#define TARGET_FRE	(TARGET_HARD_FLOAT && TARGET_FPRS \
+			 && TARGET_DOUBLE_FLOAT \
-Do not use this macro to turn on various extra optimizations for
+			 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
-`-O'.  That is what `OPTIMIZATION_OPTIONS' is for.
+#define TARGET_FRSQRTES	(TARGET_HARD_FLOAT && TARGET_POPCNTB \
-On the RS/6000 this is used to define the target cpu type.  */
+			 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
-#define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
+#define TARGET_FRSQRTE	(TARGET_HARD_FLOAT && TARGET_FPRS \
+			 && TARGET_DOUBLE_FLOAT \
-/* Define this to change the optimizations performed by default.  */
+			 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
+/* Whether the various reciprocal divide/square root estimate instructions
-/* Show we can debug even without a frame pointer.  */
+exist, and whether we should automatically generate code for the instruction
-#define CAN_DEBUG_WITHOUT_FP
+by default.  */
+#define RS6000_RECIP_MASK_HAVE_RE	0x1	/* have RE instruction.  */
+#define RS6000_RECIP_MASK_AUTO_RE	0x2	/* generate RE by default.  */
+#define RS6000_RECIP_MASK_HAVE_RSQRTE	0x4	/* have RSQRTE instruction.  */
+#define RS6000_RECIP_MASK_AUTO_RSQRTE	0x8	/* gen. RSQRTE by default.  */
+extern unsigned char rs6000_recip_bits[];
+#define RS6000_RECIP_HAVE_RE_P(MODE) \
+(rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
+#define RS6000_RECIP_AUTO_RE_P(MODE) \
+(rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
+#define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
+(rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
+#define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
+(rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
+#define RS6000_RECIP_HIGH_PRECISION_P(MODE) \
+((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION)
+/* The default CPU for TARGET_OPTION_OVERRIDE.  */
+#define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
 /* Target pragma.  */
 #define REGISTER_TARGET_PRAGMAS() do {				\
 c_register_pragma (0, "longcall", rs6000_pragma_longcall);	\
+targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
 } while (0)
 /* Target #defines.  */
 #define TARGET_CPU_CPP_BUILTINS() \
 	r31 - r13	(saved; order given to save least number)
 	r12		(not saved; if used for DImode or DFmode would use r13)
 	mq		(not saved; best to use it if we can)
 	ctr		(not saved; when we have the choice ctr is better)
 	lr		(saved)
-	cr5, r1, r2, ap, xer (fixed)
+	cr5, r1, r2, ap, ca (fixed)
 	v0 - v1		(not saved or used for anything)
 	v13 - v3	(not saved; incoming vector arg registers)
 	v2		(not saved; incoming vector arg reg; return value)
 	v19 - v14	(not saved or used for anything)
 	v31 - v20	(saved; order given to save least number)
 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
 /* PAIRED SIMD registers are just the FPRs.  */
 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
-/* True if register is the XER register.  */
+/* True if register is the CA register.  */
-#define XER_REGNO_P(N) ((N) == XER_REGNO)
+#define CA_REGNO_P(N) ((N) == CA_REGNO)
 /* True if register is an AltiVec register.  */
 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
 /* True if register is a VSX register.  */
 /* Return number of consecutive hard regs needed starting at reg REGNO
 to hold something of mode MODE.  */
 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
+/* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
+enough space to account for vectors in FP regs. */
+#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE)	\
+(TARGET_VSX						\
+&& ((MODE) == VOIDmode || VSX_VECTOR_MODE (MODE)	\
+|| ALTIVEC_VECTOR_MODE (MODE))			\
+&& FP_REGNO_P (REGNO)				\
+? V2DFmode						\
+: choose_hard_reg_mode ((REGNO), (NREGS), false))
 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE)			\
 (((TARGET_32BIT && TARGET_POWERPC64					\
 && (GET_MODE_SIZE (MODE) > 4)					\
 && INT_REGNO_P (REGNO)) ? 1 : 0)					\
 || (MODE) == V1DImode          \
 || (MODE) == V2SImode)
 #define PAIRED_VECTOR_MODE(MODE)        \
 ((MODE) == V2SFmode)
-#define UNITS_PER_SIMD_WORD(MODE)					\
-	(TARGET_VSX ? UNITS_PER_VSX_WORD				\
-	 : (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD			\
-	 : (TARGET_SPE ? UNITS_PER_SPE_WORD				\
-	 : (TARGET_PAIRED_FLOAT ? UNITS_PER_PAIRED_WORD			\
-	 : UNITS_PER_WORD))))
 /* Value is TRUE if hard register REGNO can hold a value of
 machine-mode MODE.  */
 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
 emitted the vrsave mask.  */
 #define HARD_REGNO_RENAME_OK(SRC, DST) \
 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
-/* A C expression returning the cost of moving data from a register of class
-CLASS1 to one of CLASS2.  */
-#define REGISTER_MOVE_COST rs6000_register_move_cost
-/* A C expressions returning the cost of moving data of MODE from a register to
-or from memory.  */
-#define MEMORY_MOVE_COST rs6000_memory_move_cost
 /* Specify the cost of a branch insn; roughly the number of extra insns that
 should be added to avoid a branch.
 Set this to 3 on the RS/6000 since that is roughly the average cost of an
 unscheduled conditional branch.  */
 with negative offsets.  The 64-bit load/store instructions on the SPE
 only take positive offsets (and small ones at that), so we need to
 reserve a register for consing up negative offsets.  */
 #define FIXED_SCRATCH 0
-/* Define this macro to change register usage conditional on target
-flags.  */
-#define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
 /* Specify the registers used for certain standard purposes.
 The values of these macros are register numbers.  */
 /* RS/6000 pc isn't overloaded on a register that the compiler knows about.  */
 SPECIAL_REGS,
 SPEC_OR_GEN_REGS,
 CR0_REGS,
 CR_REGS,
 NON_FLOAT_REGS,
-XER_REGS,
+CA_REGS,
 ALL_REGS,
 LIM_REG_CLASSES
 };
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 "SPECIAL_REGS",							\
 "SPEC_OR_GEN_REGS",							\
 "CR0_REGS",								\
 "CR_REGS",								\
 "NON_FLOAT_REGS",							\
-"XER_REGS",								\
+"CA_REGS",								\
 "ALL_REGS"								\
 }
 /* Define which registers fit in which classes.
 This is an initializer for a vector of HARD_REG_SET
 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */     \
 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */	     \
 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */	     \
 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */   \
-{ 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */	     \
+{ 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */	     \
 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff }  /* ALL_REGS */	     \
 }
 /* The following macro defines cover classes for Integrated Register
 Allocator.  Cover classes is a set of non-intersected register
 #define IRA_COVER_CLASSES_PRE_VSX					     \
 {									     \
 GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */	     \
 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS,		     \
 /* MQ_REGS, LINK_REGS, CTR_REGS, */					     \
-CR_REGS, XER_REGS, LIM_REG_CLASSES					     \
+CR_REGS, CA_REGS, LIM_REG_CLASSES					     \
 }
 #define IRA_COVER_CLASSES_VSX						     \
 {									     \
 GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS,	     \
 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS,		     \
 /* MQ_REGS, LINK_REGS, CTR_REGS, */					     \
-CR_REGS, XER_REGS, LIM_REG_CLASSES					     \
+CR_REGS, CA_REGS, LIM_REG_CLASSES					     \
 }
 /* The same information, inverted:
 Return the class number of the smallest class containing
 reg number REGNO.  This could be a conditional expression
 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)			\
 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS)
 /* Stack layout; function entry, exit and calling.  */
-/* Enumeration to give which calling sequence to use.  */
-enum rs6000_abi {
-ABI_NONE,
-ABI_AIX,			/* IBM's AIX */
-ABI_V4,			/* System V.4/eabi */
-ABI_DARWIN			/* Apple's Darwin (OS X kernel) */
-};
-extern enum rs6000_abi rs6000_current_abi;	/* available for use by subtarget */
 /* Define this if pushing a word on the stack
 makes the stack pointer a smaller address.  */
 #define STACK_GROWS_DOWNWARD
 /* Offsets recorded in opcodes are a multiple of this alignment factor.  */
 /* Define this if the maximum size of all the outgoing args is to be
 accumulated and pushed during the prologue.  The amount can be
 found in the variable crtl->outgoing_args_size.  */
 #define ACCUMULATE_OUTGOING_ARGS 1
-/* Value is the number of bytes of arguments automatically
-popped when returning from a subroutine call.
-FUNDECL is the declaration node of the function (as a tree),
-FUNTYPE is the data type of the function (as a tree),
-or for a library call it is an identifier node for the subroutine name.
-SIZE is the number of bytes of arguments passed on the stack.  */
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
 /* Define how to find the value returned by a library function
 assuming the value has mode MODE.  */
 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
 int stdarg;			/* Whether function is a stdarg function.  */
 int call_cookie;		/* Do special things for this call */
 int sysv_gregno;		/* next available GP register */
 int intoffset;		/* running offset in struct (darwin64) */
 int use_stack;		/* any part of struct on stack (darwin64) */
+int floats_in_gpr;		/* count of SFmode floats taking up
+				   GPR space (darwin64) */
 int named;			/* false for varargs params */
+int escapes;			/* if function visible outside tu */
 } CUMULATIVE_ARGS;
 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 for a call to a function whose data type is FNTYPE.
 For a library call, FNTYPE is 0.  */
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
-init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
+init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
+			N_NAMED_ARGS, FNDECL, VOIDmode)
 /* Similar, but when scanning the definition of a procedure.  We always
 set NARGS_PROTOTYPE large so we never return an EXPR_LIST.  */
 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
-init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
+init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
+			1000, current_function_decl, VOIDmode)
 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls.  */
 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
-init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
+init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
+			0, NULL_TREE, MODE)
-/* Update the data in CUM to advance over an argument
-of mode MODE and data type TYPE.
-(TYPE is null for libcalls where that information may not be available.)  */
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
-function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
-/* Determine where to put an argument to a function.
-Value is zero to push the argument on the stack,
-or a hard register in which to store the argument.
-MODE is the argument's machine mode.
-TYPE is the data type of the argument (as a tree).
-This is null for libcalls where that information may
-not be available.
-CUM is a variable of type CUMULATIVE_ARGS which gives info about
-the preceding args and about the function being called.
-NAMED is nonzero if this argument is a named parameter
-(otherwise it is an extra parameter matching an ellipsis).
-On RS/6000 the first eight words of non-FP are normally in registers
-and the rest are pushed.  The first 13 FP args are in registers.
-If this is floating-point and no prototype is specified, we use
-both an FP and integer register (or possibly FP reg and stack).  Library
-functions (when TYPE is zero) always have the proper types for args,
-so we can pass the FP value just in one register.  emit_library_function
-doesn't support EXPR_LIST anyway.  */
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-function_arg (&CUM, MODE, TYPE, NAMED)
 /* If defined, a C expression which determines whether, and in which
 direction, to pad out an argument with extra space.  The value
 should be of type `enum direction': either `upward' to pad above
 the argument, `downward' to pad below, or `none' to inhibit
 padding.  */
 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
-/* If defined, a C expression that gives the alignment boundary, in bits,
-of an argument with the specified mode and type.  If it is not defined,
-PARM_BOUNDARY is used for all arguments.  */
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
-function_arg_boundary (MODE, TYPE)
 #define PAD_VARARGS_DOWN \
 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
 /* Output assembler code to FILE to increment profiler label # LABELNO
 int win;								     \
 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM),	     \
 			(int)(TYPE), (IND_LEVELS), &win);		     \
 if ( win )								     \
 goto WIN;								     \
-} while (0)
-/* Go to LABEL if ADDR (a legitimate address expression)
-has an effect that depends on the machine mode it is used for.  */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)		\
-do {								\
-if (rs6000_mode_dependent_address_ptr (ADDR))			\
-goto LABEL;							\
 } while (0)
 #define FIND_BASE_TERM rs6000_find_base_term
 /* The register number of the register used to address a table of
 &rs6000_reg_names[72][0],	/* cr4  */				\
 &rs6000_reg_names[73][0],	/* cr5  */				\
 &rs6000_reg_names[74][0],	/* cr6  */				\
 &rs6000_reg_names[75][0],	/* cr7  */				\
 									\
-&rs6000_reg_names[76][0],	/* xer  */				\
+&rs6000_reg_names[76][0],	/* ca  */				\
 									\
 &rs6000_reg_names[77][0],	/* v0  */				\
 &rs6000_reg_names[78][0],	/* v1  */				\
 &rs6000_reg_names[79][0],	/* v2  */				\
 &rs6000_reg_names[80][0],	/* v3  */				\
 {"spe_acc", 111}, {"spefscr", 112},				\
 /* no additional names for: mq, lr, ctr, ap */		\
 {"cr0",  68}, {"cr1",  69}, {"cr2",  70}, {"cr3",  71},	\
 {"cr4",  72}, {"cr5",  73}, {"cr6",  74}, {"cr7",  75},	\
 {"cc",   68}, {"sp",    1}, {"toc",   2},			\
+/* CA is only part of XER, but we do not model the other parts (yet).  */ \
+{"xer",  76},							\
 /* VSX registers overlaid on top of FR, Altivec registers */	\
 {"vs0",  32}, {"vs1",  33}, {"vs2",  34}, {"vs3",  35},	\
 {"vs4",  36}, {"vs5",  37}, {"vs6",  38}, {"vs7",  39},	\
 {"vs8",  40}, {"vs9",  41}, {"vs10", 42}, {"vs11", 43},	\
 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47},	\
 #define ASM_OUTPUT_ALIGN(FILE,LOG)	\
 if ((LOG) != 0)			\
 fprintf (FILE, "\t.align %d\n", (LOG))
+/* How to align the given loop. */
+#define LOOP_ALIGN(LABEL)  rs6000_loop_align(LABEL)
 /* Pick up the return address upon entry to a procedure. Used for
 dwarf2 unwind information.  This also enables the table driven
 mechanism.  */
 #define INCOMING_RETURN_ADDR_RTX   gen_rtx_REG (Pmode, LR_REGNO)
 ((CODE) == '.' || (CODE) == '&')
 /* Print a memory address as an operand to reference that memory location.  */
 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL)		\
-do								\
-if (!rs6000_output_addr_const_extra (STREAM, X))		\
-goto FAIL;						\
-while (0)
 /* uncomment for disabling the corresponding default options */
 /* #define  MACHINE_no_sched_interblock */
 /* #define  MACHINE_no_sched_speculative */
 /* #define  MACHINE_no_sched_speculative_load */
 /* General flags.  */
-extern int flag_pic;
-extern int optimize;
-extern int flag_expensive_optimizations;
 extern int frame_pointer_needed;
 /* Classification of the builtin functions to properly set the declaration tree
 flags.  */
 enum rs6000_btc
 RS6000_BTI_bool_V4SI,          /* __vector __bool int */
 RS6000_BTI_bool_V2DI,          /* __vector __bool long */
 RS6000_BTI_pixel_V8HI,         /* __vector __pixel */
 RS6000_BTI_long,	         /* long_integer_type_node */
 RS6000_BTI_unsigned_long,      /* long_unsigned_type_node */
+RS6000_BTI_long_long,	         /* long_long_integer_type_node */
+RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */
 RS6000_BTI_INTQI,	         /* intQI_type_node */
 RS6000_BTI_UINTQI,		 /* unsigned_intQI_type_node */
 RS6000_BTI_INTHI,	         /* intHI_type_node */
 RS6000_BTI_UINTHI,		 /* unsigned_intHI_type_node */
 RS6000_BTI_INTSI,		 /* intSI_type_node */
 #define bool_V8HI_type_node	      (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
 #define bool_V4SI_type_node	      (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
 #define bool_V2DI_type_node	      (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
 #define pixel_V8HI_type_node	      (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
+#define long_long_integer_type_internal_node  (rs6000_builtin_types[RS6000_BTI_long_long])
+#define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
 #define long_integer_type_internal_node  (rs6000_builtin_types[RS6000_BTI_long])
 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
 #define intQI_type_internal_node	 (rs6000_builtin_types[RS6000_BTI_INTQI])
 #define uintQI_type_internal_node	 (rs6000_builtin_types[RS6000_BTI_UINTQI])
 #define intHI_type_internal_node	 (rs6000_builtin_types[RS6000_BTI_INTHI])

Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/rs6000/rs6000.h @ 67:f6334be47118