Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/rs6000/vector.md @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
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date | Tue, 22 Mar 2011 17:18:12 +0900 |
parents | b7f97abdc517 |
children | 04ced10e8804 |
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65:65488c3d617d | 67:f6334be47118 |
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1 ;; Expander definitions for vector support between altivec & vsx. No | 1 ;; Expander definitions for vector support between altivec & vsx. No |
2 ;; instructions are in this file, this file provides the generic vector | 2 ;; instructions are in this file, this file provides the generic vector |
3 ;; expander, and the actual vector instructions will be in altivec.md and | 3 ;; expander, and the actual vector instructions will be in altivec.md and |
4 ;; vsx.md | 4 ;; vsx.md |
5 | 5 |
6 ;; Copyright (C) 2009, 2010 | 6 ;; Copyright (C) 2009, 2010, 2011 |
7 ;; Free Software Foundation, Inc. | 7 ;; Free Software Foundation, Inc. |
8 ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com> | 8 ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com> |
9 | 9 |
10 ;; This file is part of GCC. | 10 ;; This file is part of GCC. |
11 | 11 |
120 [(pc)] | 120 [(pc)] |
121 { | 121 { |
122 rs6000_split_multireg_move (operands[0], operands[1]); | 122 rs6000_split_multireg_move (operands[0], operands[1]); |
123 DONE; | 123 DONE; |
124 }) | 124 }) |
125 | |
126 ;; Vector floating point load/store instructions that uses the Altivec | |
127 ;; instructions even if we are compiling for VSX, since the Altivec | |
128 ;; instructions silently ignore the bottom 3 bits of the address, and VSX does | |
129 ;; not. | |
130 (define_expand "vector_altivec_load_<mode>" | |
131 [(set (match_operand:VEC_M 0 "vfloat_operand" "") | |
132 (match_operand:VEC_M 1 "memory_operand" ""))] | |
133 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" | |
134 " | |
135 { | |
136 gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)); | |
137 | |
138 if (VECTOR_MEM_VSX_P (<MODE>mode)) | |
139 { | |
140 operands[1] = rs6000_address_for_altivec (operands[1]); | |
141 emit_insn (gen_altivec_lvx_<mode> (operands[0], operands[1])); | |
142 DONE; | |
143 } | |
144 }") | |
145 | |
146 (define_expand "vector_altivec_store_<mode>" | |
147 [(set (match_operand:VEC_M 0 "memory_operand" "") | |
148 (match_operand:VEC_M 1 "vfloat_operand" ""))] | |
149 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" | |
150 " | |
151 { | |
152 gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)); | |
153 | |
154 if (VECTOR_MEM_VSX_P (<MODE>mode)) | |
155 { | |
156 operands[0] = rs6000_address_for_altivec (operands[0]); | |
157 emit_insn (gen_altivec_stvx_<mode> (operands[0], operands[1])); | |
158 DONE; | |
159 } | |
160 }") | |
161 | |
125 | 162 |
126 | 163 |
127 ;; Reload patterns for vector operations. We may need an addtional base | 164 ;; Reload patterns for vector operations. We may need an addtional base |
128 ;; register to convert the reg+offset addressing to reg+reg for vector | 165 ;; register to convert the reg+offset addressing to reg+reg for vector |
129 ;; registers and reg+reg or (reg+reg)&(-16) addressing to just an index | 166 ;; registers and reg+reg or (reg+reg)&(-16) addressing to just an index |
200 | 237 |
201 (define_expand "mul<mode>3" | 238 (define_expand "mul<mode>3" |
202 [(set (match_operand:VEC_F 0 "vfloat_operand" "") | 239 [(set (match_operand:VEC_F 0 "vfloat_operand" "") |
203 (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") | 240 (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") |
204 (match_operand:VEC_F 2 "vfloat_operand" "")))] | 241 (match_operand:VEC_F 2 "vfloat_operand" "")))] |
205 "(VECTOR_UNIT_VSX_P (<MODE>mode) | 242 "VECTOR_UNIT_VSX_P (<MODE>mode) || VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" |
206 || (VECTOR_UNIT_ALTIVEC_P (<MODE>mode) && TARGET_FUSED_MADD))" | |
207 " | |
208 { | 243 { |
209 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) | 244 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) |
210 { | 245 { |
211 emit_insn (gen_altivec_mulv4sf3 (operands[0], operands[1], operands[2])); | 246 emit_insn (gen_altivec_mulv4sf3 (operands[0], operands[1], operands[2])); |
212 DONE; | 247 DONE; |
213 } | 248 } |
214 }") | 249 }) |
215 | 250 |
216 (define_expand "div<mode>3" | 251 (define_expand "div<mode>3" |
217 [(set (match_operand:VEC_F 0 "vfloat_operand" "") | 252 [(set (match_operand:VEC_F 0 "vfloat_operand" "") |
218 (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") | 253 (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") |
219 (match_operand:VEC_F 2 "vfloat_operand" "")))] | 254 (match_operand:VEC_F 2 "vfloat_operand" "")))] |
265 [(set (match_operand:VEC_F 0 "vfloat_operand" "") | 300 [(set (match_operand:VEC_F 0 "vfloat_operand" "") |
266 (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] | 301 (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] |
267 "VECTOR_UNIT_VSX_P (<MODE>mode)" | 302 "VECTOR_UNIT_VSX_P (<MODE>mode)" |
268 "") | 303 "") |
269 | 304 |
305 (define_expand "rsqrte<mode>2" | |
306 [(set (match_operand:VEC_F 0 "vfloat_operand" "") | |
307 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")] | |
308 UNSPEC_RSQRT))] | |
309 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" | |
310 "") | |
311 | |
312 (define_expand "re<mode>2" | |
313 [(set (match_operand:VEC_F 0 "vfloat_operand" "") | |
314 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "f")] | |
315 UNSPEC_FRES))] | |
316 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" | |
317 "") | |
318 | |
270 (define_expand "ftrunc<mode>2" | 319 (define_expand "ftrunc<mode>2" |
271 [(set (match_operand:VEC_F 0 "vfloat_operand" "") | 320 [(set (match_operand:VEC_F 0 "vfloat_operand" "") |
272 (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] | 321 (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] |
273 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" | 322 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" |
274 "") | 323 "") |
293 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" | 342 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" |
294 "") | 343 "") |
295 | 344 |
296 (define_expand "vector_copysign<mode>3" | 345 (define_expand "vector_copysign<mode>3" |
297 [(set (match_operand:VEC_F 0 "vfloat_operand" "") | 346 [(set (match_operand:VEC_F 0 "vfloat_operand" "") |
298 (if_then_else:VEC_F | 347 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "") |
299 (ge:VEC_F (match_operand:VEC_F 2 "vfloat_operand" "") | 348 (match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))] |
300 (match_dup 3)) | |
301 (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")) | |
302 (neg:VEC_F (abs:VEC_F (match_dup 1)))))] | |
303 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" | 349 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" |
304 " | 350 " |
305 { | 351 { |
306 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) | 352 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) |
307 { | 353 { |
308 emit_insn (gen_altivec_copysign_v4sf3 (operands[0], operands[1], | 354 emit_insn (gen_altivec_copysign_v4sf3 (operands[0], operands[1], |
309 operands[2])); | 355 operands[2])); |
310 DONE; | 356 DONE; |
311 } | 357 } |
312 | |
313 operands[3] = CONST0_RTX (<MODE>mode); | |
314 }") | 358 }") |
315 | 359 |
316 | 360 |
317 ;; Vector comparisons | 361 ;; Vector comparisons |
318 (define_expand "vcond<mode>" | 362 (define_expand "vcond<mode>" |