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comparison gcc/config/score/predicates.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents a06113de4d67
children
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65:65488c3d617d 67:f6334be47118
1 ;; Predicate definitions for Sunplus S+CORE. 1 ;; Predicate definitions for Sunplus S+CORE.
2 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc. 2 ;; Copyright (C) 2005, 2007, 2010 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify 6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by 7 ;; it under the terms of the GNU General Public License as published by
87 (define_predicate "score_load_multiple_operation" 87 (define_predicate "score_load_multiple_operation"
88 (match_code "parallel") 88 (match_code "parallel")
89 { 89 {
90 int count = XVECLEN (op, 0); 90 int count = XVECLEN (op, 0);
91 int dest_regno; 91 int dest_regno;
92 rtx src_addr;
93 int i; 92 int i;
94 93
95 /* Perform a quick check so we don't blow up below. */ 94 /* Perform a quick check so we don't blow up below. */
96 if (count <= 1 95 if (count <= 1
97 || GET_CODE (XVECEXP (op, 0, 0)) != SET 96 || GET_CODE (XVECEXP (op, 0, 0)) != SET
98 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG 97 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
99 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) 98 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
100 return 0; 99 return 0;
101 100
102 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 101 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
103 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
104 102
105 for (i = 1; i < count; i++) 103 for (i = 1; i < count; i++)
106 { 104 {
107 rtx elt = XVECEXP (op, 0, i); 105 rtx elt = XVECEXP (op, 0, i);
108 106
122 (define_predicate "score_store_multiple_operation" 120 (define_predicate "score_store_multiple_operation"
123 (match_code "parallel") 121 (match_code "parallel")
124 { 122 {
125 int count = XVECLEN (op, 0); 123 int count = XVECLEN (op, 0);
126 int src_regno; 124 int src_regno;
127 rtx dest_addr;
128 int i; 125 int i;
129 126
130 /* Perform a quick check so we don't blow up below. */ 127 /* Perform a quick check so we don't blow up below. */
131 if (count <= 1 128 if (count <= 1
132 || GET_CODE (XVECEXP (op, 0, 0)) != SET 129 || GET_CODE (XVECEXP (op, 0, 0)) != SET
133 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM 130 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
134 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) 131 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
135 return 0; 132 return 0;
136 133
137 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); 134 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
138 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
139 135
140 for (i = 1; i < count; i++) 136 for (i = 1; i < count; i++)
141 { 137 {
142 rtx elt = XVECEXP (op, 0, i); 138 rtx elt = XVECEXP (op, 0, i);
143 139