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comparison gcc/config/sparc/sparc.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents b7f97abdc517
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
73 (UNSPECV_SETJMP 5) 73 (UNSPECV_SETJMP 5)
74 (UNSPECV_SAVEW 6) 74 (UNSPECV_SAVEW 6)
75 (UNSPECV_CAS 8) 75 (UNSPECV_CAS 8)
76 (UNSPECV_SWAP 9) 76 (UNSPECV_SWAP 9)
77 (UNSPECV_LDSTUB 10) 77 (UNSPECV_LDSTUB 10)
78 (UNSPECV_PROBE_STACK_RANGE 11)
78 ]) 79 ])
79 80
80 81
81 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) 82 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
82 (define_mode_iterator I [QI HI SI DI]) 83 (define_mode_iterator I [QI HI SI DI])
101 (define_attr "cpu" 102 (define_attr "cpu"
102 "v7, 103 "v7,
103 cypress, 104 cypress,
104 v8, 105 v8,
105 supersparc, 106 supersparc,
106 sparclite,f930,f934, 107 hypersparc,
107 hypersparc,sparclite86x, 108 leon,
108 sparclet,tsc701, 109 sparclite,
110 f930,
111 f934,
112 sparclite86x,
113 sparclet,
114 tsc701,
109 v9, 115 v9,
110 ultrasparc, 116 ultrasparc,
111 ultrasparc3, 117 ultrasparc3,
112 niagara, 118 niagara,
113 niagara2" 119 niagara2"
336 ;; Include SPARC DFA schedulers 342 ;; Include SPARC DFA schedulers
337 343
338 (include "cypress.md") 344 (include "cypress.md")
339 (include "supersparc.md") 345 (include "supersparc.md")
340 (include "hypersparc.md") 346 (include "hypersparc.md")
347 (include "leon.md")
341 (include "sparclet.md") 348 (include "sparclet.md")
342 (include "ultra1_2.md") 349 (include "ultra1_2.md")
343 (include "ultra3.md") 350 (include "ultra3.md")
344 (include "niagara.md") 351 (include "niagara.md")
345 (include "niagara2.md") 352 (include "niagara2.md")
1104 (set_attr "branch_type" "reg")]) 1111 (set_attr "branch_type" "reg")])
1105 1112
1106 1113
1107 ;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic 1114 ;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
1108 ;; value subject to a PC-relative relocation. Operand 2 is a helper function 1115 ;; value subject to a PC-relative relocation. Operand 2 is a helper function
1109 ;; that adds the PC value at the call point to operand 0. 1116 ;; that adds the PC value at the call point to register #(operand 3).
1110 1117
1111 (define_insn "load_pcrel_sym<P:mode>" 1118 (define_insn "load_pcrel_sym<P:mode>"
1112 [(set (match_operand:P 0 "register_operand" "=r") 1119 [(set (match_operand:P 0 "register_operand" "=r")
1113 (unspec:P [(match_operand:P 1 "symbolic_operand" "") 1120 (unspec:P [(match_operand:P 1 "symbolic_operand" "")
1114 (match_operand:P 2 "call_address_operand" "")] UNSPEC_LOAD_PCREL_SYM)) 1121 (match_operand:P 2 "call_address_operand" "")
1122 (match_operand:P 3 "const_int_operand" "")] UNSPEC_LOAD_PCREL_SYM))
1115 (clobber (reg:P 15))] 1123 (clobber (reg:P 15))]
1116 "" 1124 "REGNO (operands[0]) == INTVAL (operands[3])"
1117 { 1125 {
1118 if (flag_delayed_branch) 1126 if (flag_delayed_branch)
1119 return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0"; 1127 return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
1120 else 1128 else
1121 return "sethi\t%%hi(%a1-8), %0\n\tadd\t%0, %%lo(%a1-4), %0\n\tcall\t%a2\n\t nop"; 1129 return "sethi\t%%hi(%a1-8), %0\n\tadd\t%0, %%lo(%a1-4), %0\n\tcall\t%a2\n\t nop";
3504 gen_rtx_REG (CCmode, SPARC_ICC_REG))))); 3512 gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
3505 DONE; 3513 DONE;
3506 } 3514 }
3507 }) 3515 })
3508 3516
3509 (define_insn_and_split "adddi3_insn_sp32" 3517 (define_insn_and_split "*adddi3_insn_sp32"
3510 [(set (match_operand:DI 0 "register_operand" "=r") 3518 [(set (match_operand:DI 0 "register_operand" "=r")
3511 (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") 3519 (plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
3512 (match_operand:DI 2 "arith_double_operand" "rHI"))) 3520 (match_operand:DI 2 "arith_double_operand" "rHI")))
3513 (clobber (reg:CC 100))] 3521 (clobber (reg:CC 100))]
3514 "! TARGET_ARCH64" 3522 "! TARGET_ARCH64"
3577 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] 3585 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
3578 "TARGET_ARCH64" 3586 "TARGET_ARCH64"
3579 "addx\t%r1, %2, %0" 3587 "addx\t%r1, %2, %0"
3580 [(set_attr "type" "ialuX")]) 3588 [(set_attr "type" "ialuX")])
3581 3589
3582 (define_insn_and_split "" 3590 (define_insn_and_split "*adddi3_extend_sp32"
3583 [(set (match_operand:DI 0 "register_operand" "=r") 3591 [(set (match_operand:DI 0 "register_operand" "=r")
3584 (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) 3592 (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
3585 (match_operand:DI 2 "register_operand" "r"))) 3593 (match_operand:DI 2 "register_operand" "r")))
3586 (clobber (reg:CC 100))] 3594 (clobber (reg:CC 100))]
3587 "! TARGET_ARCH64" 3595 "! TARGET_ARCH64"
3677 gen_rtx_REG (CCmode, SPARC_ICC_REG))))); 3685 gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
3678 DONE; 3686 DONE;
3679 } 3687 }
3680 }) 3688 })
3681 3689
3682 (define_insn_and_split "subdi3_insn_sp32" 3690 (define_insn_and_split "*subdi3_insn_sp32"
3683 [(set (match_operand:DI 0 "register_operand" "=r") 3691 [(set (match_operand:DI 0 "register_operand" "=r")
3684 (minus:DI (match_operand:DI 1 "register_operand" "r") 3692 (minus:DI (match_operand:DI 1 "register_operand" "r")
3685 (match_operand:DI 2 "arith_double_operand" "rHI"))) 3693 (match_operand:DI 2 "arith_double_operand" "rHI")))
3686 (clobber (reg:CC 100))] 3694 (clobber (reg:CC 100))]
3687 "! TARGET_ARCH64" 3695 "! TARGET_ARCH64"
3749 (set (match_dup 4) (const_int 0))] 3757 (set (match_dup 4) (const_int 0))]
3750 "operands[3] = gen_lowpart (SImode, operands[0]); 3758 "operands[3] = gen_lowpart (SImode, operands[0]);
3751 operands[4] = gen_highpart (SImode, operands[0]);" 3759 operands[4] = gen_highpart (SImode, operands[0]);"
3752 [(set_attr "length" "2")]) 3760 [(set_attr "length" "2")])
3753 3761
3754 (define_insn_and_split "" 3762 (define_insn_and_split "*subdi3_extend_sp32"
3755 [(set (match_operand:DI 0 "register_operand" "=r") 3763 [(set (match_operand:DI 0 "register_operand" "=r")
3756 (minus:DI (match_operand:DI 1 "register_operand" "r") 3764 (minus:DI (match_operand:DI 1 "register_operand" "r")
3757 (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))) 3765 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))
3758 (clobber (reg:CC 100))] 3766 (clobber (reg:CC 100))]
3759 "! TARGET_ARCH64" 3767 "! TARGET_ARCH64"
5061 5069
5062 (define_insn_and_split "*negdi2_sp32" 5070 (define_insn_and_split "*negdi2_sp32"
5063 [(set (match_operand:DI 0 "register_operand" "=r") 5071 [(set (match_operand:DI 0 "register_operand" "=r")
5064 (neg:DI (match_operand:DI 1 "register_operand" "r"))) 5072 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5065 (clobber (reg:CC 100))] 5073 (clobber (reg:CC 100))]
5066 "TARGET_ARCH32" 5074 "! TARGET_ARCH64"
5067 "#" 5075 "#"
5068 "&& reload_completed" 5076 "&& reload_completed"
5069 [(parallel [(set (reg:CC_NOOV 100) 5077 [(parallel [(set (reg:CC_NOOV 100)
5070 (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5)) 5078 (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5))
5071 (const_int 0))) 5079 (const_int 0)))
6337 "" 6345 ""
6338 { 6346 {
6339 operands[0] 6347 operands[0]
6340 = adjust_address (operands[0], GET_MODE (operands[0]), SPARC_STACK_BIAS); 6348 = adjust_address (operands[0], GET_MODE (operands[0]), SPARC_STACK_BIAS);
6341 }) 6349 })
6350
6351 (define_insn "probe_stack_range<P:mode>"
6352 [(set (match_operand:P 0 "register_operand" "=r")
6353 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
6354 (match_operand:P 2 "register_operand" "r")]
6355 UNSPECV_PROBE_STACK_RANGE))]
6356 ""
6357 "* return output_probe_stack_range (operands[0], operands[2]);"
6358 [(set_attr "type" "multi")])
6342 6359
6343 ;; Prepare to return any type including a structure value. 6360 ;; Prepare to return any type including a structure value.
6344 6361
6345 (define_expand "untyped_return" 6362 (define_expand "untyped_return"
6346 [(match_operand:BLK 0 "memory_operand" "") 6363 [(match_operand:BLK 0 "memory_operand" "")