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comparison gcc/config/sparc/sync.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents a06113de4d67
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 ;; GCC machine description for SPARC synchronization instructions. 1 ;; GCC machine description for SPARC synchronization instructions.
2 ;; Copyright (C) 2005, 2007, 2009 2 ;; Copyright (C) 2005, 2007, 2009, 2010
3 ;; Free Software Foundation, Inc. 3 ;; Free Software Foundation, Inc.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify 7 ;; GCC is free software; you can redistribute it and/or modify
60 DONE; 60 DONE;
61 }) 61 })
62 62
63 (define_expand "sync_compare_and_swap<mode>" 63 (define_expand "sync_compare_and_swap<mode>"
64 [(parallel 64 [(parallel
65 [(set (match_operand:I48MODE 0 "register_operand" "=r") 65 [(set (match_operand:I48MODE 0 "register_operand" "")
66 (match_operand:I48MODE 1 "memory_operand" "")) 66 (match_operand:I48MODE 1 "memory_operand" ""))
67 (set (match_dup 1) 67 (set (match_dup 1)
68 (unspec_volatile:I48MODE 68 (unspec_volatile:I48MODE
69 [(match_operand:I48MODE 2 "register_operand" "") 69 [(match_operand:I48MODE 2 "register_operand" "")
70 (match_operand:I48MODE 3 "register_operand" "")] 70 (match_operand:I48MODE 3 "register_operand" "")]
71 UNSPECV_CAS))])] 71 UNSPECV_CAS))])]
72 "TARGET_V9" 72 "TARGET_V9"
73 { 73 {
74 if (! REG_P (XEXP (operands[1], 0))) 74 if (!REG_P (XEXP (operands[1], 0)))
75 { 75 {
76 rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); 76 rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
77 operands[1] = replace_equiv_address (operands[1], addr); 77 operands[1] = replace_equiv_address (operands[1], addr);
78 } 78 }
79 emit_insn (gen_memory_barrier ()); 79 emit_insn (gen_memory_barrier ());
80 }) 80 })
81 81
82 (define_insn "*sync_compare_and_swap<mode>" 82 (define_insn "*sync_compare_and_swap<mode>"
83 [(set (match_operand:I48MODE 0 "register_operand" "=r") 83 [(set (match_operand:I48MODE 0 "register_operand" "=r")
84 (match_operand:I48MODE 1 "memory_reg_operand" "+m")) 84 (mem:I48MODE (match_operand 1 "register_operand" "r")))
85 (set (match_dup 1) 85 (set (mem:I48MODE (match_dup 1))
86 (unspec_volatile:I48MODE 86 (unspec_volatile:I48MODE
87 [(match_operand:I48MODE 2 "register_operand" "r") 87 [(match_operand:I48MODE 2 "register_operand" "r")
88 (match_operand:I48MODE 3 "register_operand" "0")] 88 (match_operand:I48MODE 3 "register_operand" "0")]
89 UNSPECV_CAS))] 89 UNSPECV_CAS))]
90 "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)" 90 "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
91 "cas<modesuffix>\t%1, %2, %0" 91 "cas<modesuffix>\t[%1], %2, %0"
92 [(set_attr "type" "multi")]) 92 [(set_attr "type" "multi")])
93 93
94 (define_insn "*sync_compare_and_swapdi_v8plus" 94 (define_insn "*sync_compare_and_swapdi_v8plus"
95 [(set (match_operand:DI 0 "register_operand" "=h") 95 [(set (match_operand:DI 0 "register_operand" "=h")
96 (match_operand:DI 1 "memory_reg_operand" "+m")) 96 (mem:DI (match_operand 1 "register_operand" "r")))
97 (set (match_dup 1) 97 (set (mem:DI (match_dup 1))
98 (unspec_volatile:DI 98 (unspec_volatile:DI
99 [(match_operand:DI 2 "register_operand" "h") 99 [(match_operand:DI 2 "register_operand" "h")
100 (match_operand:DI 3 "register_operand" "0")] 100 (match_operand:DI 3 "register_operand" "0")]
101 UNSPECV_CAS))] 101 UNSPECV_CAS))]
102 "TARGET_V8PLUS" 102 "TARGET_V8PLUS"
107 output_asm_insn ("or\t%L3, %H3, %L3", operands); 107 output_asm_insn ("or\t%L3, %H3, %L3", operands);
108 if (sparc_check_64 (operands[2], insn) <= 0) 108 if (sparc_check_64 (operands[2], insn) <= 0)
109 output_asm_insn ("srl\t%L2, 0, %L2", operands); 109 output_asm_insn ("srl\t%L2, 0, %L2", operands);
110 output_asm_insn ("sllx\t%H2, 32, %H3", operands); 110 output_asm_insn ("sllx\t%H2, 32, %H3", operands);
111 output_asm_insn ("or\t%L2, %H3, %H3", operands); 111 output_asm_insn ("or\t%L2, %H3, %H3", operands);
112 output_asm_insn ("casx\t%1, %H3, %L3", operands); 112 output_asm_insn ("casx\t[%1], %H3, %L3", operands);
113 return "srlx\t%L3, 32, %H3"; 113 return "srlx\t%L3, 32, %H3";
114 } 114 }
115 [(set_attr "type" "multi") 115 [(set_attr "type" "multi")
116 (set_attr "length" "8")]) 116 (set_attr "length" "8")])
117 117