Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/spu/spu.md @ 67:f6334be47118

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 77e2b8dfacca
children 04ced10e8804
comparison
equal deleted inserted replaced
65:65488c3d617d 67:f6334be47118
1 ;; Copyright (C) 2006, 2007, 2008, 2009 Free Software Foundation, Inc. 1 ;; Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
2 2
3 ;; This file is free software; you can redistribute it and/or modify it under 3 ;; This file is free software; you can redistribute it and/or modify it under
4 ;; the terms of the GNU General Public License as published by the Free 4 ;; the terms of the GNU General Public License as published by the Free
5 ;; Software Foundation; either version 3 of the License, or (at your option) 5 ;; Software Foundation; either version 3 of the License, or (at your option)
6 ;; any later version. 6 ;; any later version.
267 267
268 268
269 ;; mov 269 ;; mov
270 270
271 (define_expand "mov<mode>" 271 (define_expand "mov<mode>"
272 [(set (match_operand:ALL 0 "spu_nonimm_operand" "=r,r,r,m") 272 [(set (match_operand:ALL 0 "nonimmediate_operand" "")
273 (match_operand:ALL 1 "general_operand" "r,i,m,r"))] 273 (match_operand:ALL 1 "general_operand" ""))]
274 "" 274 ""
275 { 275 {
276 if (spu_expand_mov(operands, <MODE>mode)) 276 if (spu_expand_mov(operands, <MODE>mode))
277 DONE; 277 DONE;
278 }) 278 })
746 emit_insn (gen_floatunsv4siv4sf2 (op2_v4sf, op1_v4si)); 746 emit_insn (gen_floatunsv4siv4sf2 (op2_v4sf, op1_v4si));
747 emit_insn (gen_shlqby_ti (op3_ti, op2_ti, GEN_INT (4))); 747 emit_insn (gen_shlqby_ti (op3_ti, op2_ti, GEN_INT (4)));
748 748
749 emit_move_insn (operands[4], 749 emit_move_insn (operands[4],
750 CONST_DOUBLE_FROM_REAL_VALUE (scale, SFmode)); 750 CONST_DOUBLE_FROM_REAL_VALUE (scale, SFmode));
751 emit_insn (gen_fma_sf (operands[0], 751 emit_insn (gen_fmasf4 (operands[0],
752 operands[2], operands[4], operands[3]));
753 DONE;
754 })
755
756 (define_expand "floattisf2"
757 [(set (match_operand:SF 0 "register_operand" "")
758 (float:SF (match_operand:TI 1 "register_operand" "")))]
759 ""
760 {
761 rtx c0 = gen_reg_rtx (SImode);
762 rtx r0 = gen_reg_rtx (TImode);
763 rtx r1 = gen_reg_rtx (SFmode);
764 rtx r2 = gen_reg_rtx (SImode);
765 rtx setneg = gen_reg_rtx (SImode);
766 rtx isneg = gen_reg_rtx (SImode);
767 rtx neg = gen_reg_rtx (TImode);
768 rtx mask = gen_reg_rtx (TImode);
769
770 emit_move_insn (c0, GEN_INT (-0x80000000ll));
771
772 emit_insn (gen_negti2 (neg, operands[1]));
773 emit_insn (gen_cgt_ti_m1 (isneg, operands[1]));
774 emit_insn (gen_extend_compare (mask, isneg));
775 emit_insn (gen_selb (r0, neg, operands[1], mask));
776 emit_insn (gen_andc_si (setneg, c0, isneg));
777
778 emit_insn (gen_floatunstisf2 (r1, r0));
779
780 emit_insn (gen_iorsi3 (r2, gen_rtx_SUBREG (SImode, r1, 0), setneg));
781 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, r2, 0));
782 DONE;
783 })
784
785 (define_insn_and_split "floatunstisf2"
786 [(set (match_operand:SF 0 "register_operand" "=r")
787 (unsigned_float:SF (match_operand:TI 1 "register_operand" "r")))
788 (clobber (match_scratch:SF 2 "=r"))
789 (clobber (match_scratch:SF 3 "=r"))
790 (clobber (match_scratch:SF 4 "=r"))]
791 ""
792 "#"
793 "reload_completed"
794 [(set (match_dup:SF 0)
795 (unsigned_float:SF (match_dup:TI 1)))]
796 {
797 rtx op1_v4si = gen_rtx_REG (V4SImode, REGNO (operands[1]));
798 rtx op2_v4sf = gen_rtx_REG (V4SFmode, REGNO (operands[2]));
799 rtx op2_ti = gen_rtx_REG (TImode, REGNO (operands[2]));
800 rtx op3_ti = gen_rtx_REG (TImode, REGNO (operands[3]));
801
802 REAL_VALUE_TYPE scale;
803 real_2expN (&scale, 32, SFmode);
804
805 emit_insn (gen_floatunsv4siv4sf2 (op2_v4sf, op1_v4si));
806 emit_insn (gen_shlqby_ti (op3_ti, op2_ti, GEN_INT (4)));
807
808 emit_move_insn (operands[4],
809 CONST_DOUBLE_FROM_REAL_VALUE (scale, SFmode));
810 emit_insn (gen_fmasf4 (operands[2],
811 operands[2], operands[4], operands[3]));
812
813 emit_insn (gen_shlqby_ti (op3_ti, op3_ti, GEN_INT (4)));
814 emit_insn (gen_fmasf4 (operands[2],
815 operands[2], operands[4], operands[3]));
816
817 emit_insn (gen_shlqby_ti (op3_ti, op3_ti, GEN_INT (4)));
818 emit_insn (gen_fmasf4 (operands[0],
752 operands[2], operands[4], operands[3])); 819 operands[2], operands[4], operands[3]));
753 DONE; 820 DONE;
754 }) 821 })
755 822
756 ;; Do (double)(operands[1]+0x80000000u)-(double)0x80000000 823 ;; Do (double)(operands[1]+0x80000000u)-(double)0x80000000
1531 (match_operand:VSDF 2 "spu_reg_operand" "r")))] 1598 (match_operand:VSDF 2 "spu_reg_operand" "r")))]
1532 "" 1599 ""
1533 "<d>fm\t%0,%1,%2" 1600 "<d>fm\t%0,%1,%2"
1534 [(set_attr "type" "fp<d6>")]) 1601 [(set_attr "type" "fp<d6>")])
1535 1602
1536 (define_insn "fma_<mode>" 1603 (define_insn "fma<mode>4"
1537 [(set (match_operand:VSF 0 "spu_reg_operand" "=r") 1604 [(set (match_operand:VSF 0 "spu_reg_operand" "=r")
1538 (plus:VSF (mult:VSF (match_operand:VSF 1 "spu_reg_operand" "r") 1605 (fma:VSF (match_operand:VSF 1 "spu_reg_operand" "r")
1539 (match_operand:VSF 2 "spu_reg_operand" "r")) 1606 (match_operand:VSF 2 "spu_reg_operand" "r")
1540 (match_operand:VSF 3 "spu_reg_operand" "r")))] 1607 (match_operand:VSF 3 "spu_reg_operand" "r")))]
1541 "" 1608 ""
1542 "fma\t%0,%1,%2,%3" 1609 "fma\t%0,%1,%2,%3"
1543 [(set_attr "type" "fp6")]) 1610 [(set_attr "type" "fp6")])
1544 1611
1545 (define_insn "fnms_<mode>" 1612 ;; ??? The official description is (c - a*b), which is exactly (-a*b + c).
1613 ;; Note that this doesn't match the dfnms description. Incorrect?
1614 (define_insn "fnma<mode>4"
1546 [(set (match_operand:VSF 0 "spu_reg_operand" "=r") 1615 [(set (match_operand:VSF 0 "spu_reg_operand" "=r")
1547 (minus:VSF (match_operand:VSF 3 "spu_reg_operand" "r") 1616 (fma:VSF
1548 (mult:VSF (match_operand:VSF 1 "spu_reg_operand" "r") 1617 (neg:VSF (match_operand:VSF 1 "spu_reg_operand" "r"))
1549 (match_operand:VSF 2 "spu_reg_operand" "r"))))] 1618 (match_operand:VSF 2 "spu_reg_operand" "r")
1619 (match_operand:VSF 3 "spu_reg_operand" "r")))]
1550 "" 1620 ""
1551 "fnms\t%0,%1,%2,%3" 1621 "fnms\t%0,%1,%2,%3"
1552 [(set_attr "type" "fp6")]) 1622 [(set_attr "type" "fp6")])
1553 1623
1554 (define_insn "fms_<mode>" 1624 (define_insn "fms<mode>4"
1555 [(set (match_operand:VSF 0 "spu_reg_operand" "=r") 1625 [(set (match_operand:VSF 0 "spu_reg_operand" "=r")
1556 (minus:VSF (mult:VSF (match_operand:VSF 1 "spu_reg_operand" "r") 1626 (fma:VSF
1557 (match_operand:VSF 2 "spu_reg_operand" "r")) 1627 (match_operand:VSF 1 "spu_reg_operand" "r")
1558 (match_operand:VSF 3 "spu_reg_operand" "r")))] 1628 (match_operand:VSF 2 "spu_reg_operand" "r")
1629 (neg:VSF (match_operand:VSF 3 "spu_reg_operand" "r"))))]
1559 "" 1630 ""
1560 "fms\t%0,%1,%2,%3" 1631 "fms\t%0,%1,%2,%3"
1561 [(set_attr "type" "fp6")]) 1632 [(set_attr "type" "fp6")])
1562 1633
1563 (define_insn "fma_<mode>" 1634 (define_insn "fma<mode>4"
1564 [(set (match_operand:VDF 0 "spu_reg_operand" "=r") 1635 [(set (match_operand:VDF 0 "spu_reg_operand" "=r")
1565 (plus:VDF (mult:VDF (match_operand:VDF 1 "spu_reg_operand" "r") 1636 (fma:VDF (match_operand:VDF 1 "spu_reg_operand" "r")
1566 (match_operand:VDF 2 "spu_reg_operand" "r")) 1637 (match_operand:VDF 2 "spu_reg_operand" "r")
1567 (match_operand:VDF 3 "spu_reg_operand" "0")))] 1638 (match_operand:VDF 3 "spu_reg_operand" "0")))]
1568 "" 1639 ""
1569 "dfma\t%0,%1,%2" 1640 "dfma\t%0,%1,%2"
1570 [(set_attr "type" "fpd")]) 1641 [(set_attr "type" "fpd")])
1571 1642
1572 (define_insn "fnma_<mode>" 1643 (define_insn "fms<mode>4"
1573 [(set (match_operand:VDF 0 "spu_reg_operand" "=r") 1644 [(set (match_operand:VDF 0 "spu_reg_operand" "=r")
1574 (neg:VDF (plus:VDF (mult:VDF (match_operand:VDF 1 "spu_reg_operand" "r") 1645 (fma:VDF
1575 (match_operand:VDF 2 "spu_reg_operand" "r")) 1646 (match_operand:VDF 1 "spu_reg_operand" "r")
1576 (match_operand:VDF 3 "spu_reg_operand" "0"))))] 1647 (match_operand:VDF 2 "spu_reg_operand" "r")
1648 (neg:VDF (match_operand:VDF 3 "spu_reg_operand" "0"))))]
1649 ""
1650 "dfms\t%0,%1,%2"
1651 [(set_attr "type" "fpd")])
1652
1653 (define_insn "nfma<mode>4"
1654 [(set (match_operand:VDF 0 "spu_reg_operand" "=r")
1655 (neg:VDF
1656 (fma:VDF (match_operand:VDF 1 "spu_reg_operand" "r")
1657 (match_operand:VDF 2 "spu_reg_operand" "r")
1658 (match_operand:VDF 3 "spu_reg_operand" "0"))))]
1577 "" 1659 ""
1578 "dfnma\t%0,%1,%2" 1660 "dfnma\t%0,%1,%2"
1579 [(set_attr "type" "fpd")]) 1661 [(set_attr "type" "fpd")])
1580 1662
1581 (define_insn "fnms_<mode>" 1663 (define_insn "nfms<mode>4"
1582 [(set (match_operand:VDF 0 "spu_reg_operand" "=r") 1664 [(set (match_operand:VDF 0 "spu_reg_operand" "=r")
1583 (minus:VDF (match_operand:VDF 3 "spu_reg_operand" "0") 1665 (neg:VDF
1584 (mult:VDF (match_operand:VDF 1 "spu_reg_operand" "r") 1666 (fma:VDF
1585 (match_operand:VDF 2 "spu_reg_operand" "r"))))] 1667 (match_operand:VDF 1 "spu_reg_operand" "r")
1668 (match_operand:VDF 2 "spu_reg_operand" "r")
1669 (neg:VDF (match_operand:VDF 3 "spu_reg_operand" "0")))))]
1586 "" 1670 ""
1587 "dfnms\t%0,%1,%2" 1671 "dfnms\t%0,%1,%2"
1588 [(set_attr "type" "fpd")]) 1672 [(set_attr "type" "fpd")])
1589 1673
1590 (define_insn "fms_<mode>" 1674 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
1591 [(set (match_operand:VDF 0 "spu_reg_operand" "=r") 1675 (define_expand "fnma<mode>4"
1592 (minus:VDF (mult:VDF (match_operand:VDF 1 "spu_reg_operand" "r") 1676 [(set (match_operand:VDF 0 "spu_reg_operand" "")
1593 (match_operand:VDF 2 "spu_reg_operand" "r")) 1677 (neg:VDF
1594 (match_operand:VDF 3 "spu_reg_operand" "0")))] 1678 (fma:VDF
1595 "" 1679 (match_operand:VDF 1 "spu_reg_operand" "")
1596 "dfms\t%0,%1,%2" 1680 (match_operand:VDF 2 "spu_reg_operand" "")
1597 [(set_attr "type" "fpd")]) 1681 (neg:VDF (match_operand:VDF 3 "spu_reg_operand" "")))))]
1598 1682 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
1683 "")
1684
1685 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
1686 (define_expand "fnms<mode>4"
1687 [(set (match_operand:VDF 0 "register_operand" "")
1688 (neg:VDF
1689 (fma:VDF
1690 (match_operand:VDF 1 "register_operand" "")
1691 (match_operand:VDF 2 "register_operand" "")
1692 (match_operand:VDF 3 "register_operand" ""))))]
1693 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
1694 "")
1599 1695
1600 ;; mul highpart, used for divide by constant optimizations. 1696 ;; mul highpart, used for divide by constant optimizations.
1601 1697
1602 (define_expand "smulsi3_highpart" 1698 (define_expand "smulsi3_highpart"
1603 [(set (match_operand:SI 0 "register_operand" "") 1699 [(set (match_operand:SI 0 "register_operand" "")
1843 (clobber (scratch:VSF))] 1939 (clobber (scratch:VSF))]
1844 { 1940 {
1845 emit_insn (gen_frest_<mode>(operands[3], operands[2])); 1941 emit_insn (gen_frest_<mode>(operands[3], operands[2]));
1846 emit_insn (gen_fi_<mode>(operands[3], operands[2], operands[3])); 1942 emit_insn (gen_fi_<mode>(operands[3], operands[2], operands[3]));
1847 emit_insn (gen_mul<mode>3(operands[4], operands[1], operands[3])); 1943 emit_insn (gen_mul<mode>3(operands[4], operands[1], operands[3]));
1848 emit_insn (gen_fnms_<mode>(operands[0], operands[4], operands[2], operands[1])); 1944 emit_insn (gen_fnma<mode>4(operands[0], operands[4], operands[2], operands[1]));
1849 emit_insn (gen_fma_<mode>(operands[0], operands[0], operands[3], operands[4])); 1945 emit_insn (gen_fma<mode>4(operands[0], operands[0], operands[3], operands[4]));
1850 DONE; 1946 DONE;
1851 }) 1947 })
1852 1948
1853 (define_insn_and_split "*div<mode>3_adjusted" 1949 (define_insn_and_split "*div<mode>3_adjusted"
1854 [(set (match_operand:VSF 0 "spu_reg_operand" "=r") 1950 [(set (match_operand:VSF 0 "spu_reg_operand" "=r")
1868 (clobber (match_dup:VSF 5))] 1964 (clobber (match_dup:VSF 5))]
1869 { 1965 {
1870 emit_insn (gen_frest_<mode> (operands[3], operands[2])); 1966 emit_insn (gen_frest_<mode> (operands[3], operands[2]));
1871 emit_insn (gen_fi_<mode> (operands[3], operands[2], operands[3])); 1967 emit_insn (gen_fi_<mode> (operands[3], operands[2], operands[3]));
1872 emit_insn (gen_mul<mode>3 (operands[4], operands[1], operands[3])); 1968 emit_insn (gen_mul<mode>3 (operands[4], operands[1], operands[3]));
1873 emit_insn (gen_fnms_<mode> (operands[5], operands[4], operands[2], operands[1])); 1969 emit_insn (gen_fnma<mode>4 (operands[5], operands[4], operands[2], operands[1]));
1874 emit_insn (gen_fma_<mode> (operands[3], operands[5], operands[3], operands[4])); 1970 emit_insn (gen_fma<mode>4 (operands[3], operands[5], operands[3], operands[4]));
1875 1971
1876 /* Due to truncation error, the quotient result may be low by 1 ulp. 1972 /* Due to truncation error, the quotient result may be low by 1 ulp.
1877 Conditionally add one if the estimate is too small in magnitude. */ 1973 Conditionally add one if the estimate is too small in magnitude. */
1878 1974
1879 emit_move_insn (gen_lowpart (<F2I>mode, operands[4]), 1975 emit_move_insn (gen_lowpart (<F2I>mode, operands[4]),
1883 emit_insn (gen_selb (operands[5], operands[5], operands[1], operands[4])); 1979 emit_insn (gen_selb (operands[5], operands[5], operands[1], operands[4]));
1884 1980
1885 emit_insn (gen_add<f2i>3 (gen_lowpart (<F2I>mode, operands[4]), 1981 emit_insn (gen_add<f2i>3 (gen_lowpart (<F2I>mode, operands[4]),
1886 gen_lowpart (<F2I>mode, operands[3]), 1982 gen_lowpart (<F2I>mode, operands[3]),
1887 spu_const (<F2I>mode, 1))); 1983 spu_const (<F2I>mode, 1)));
1888 emit_insn (gen_fnms_<mode> (operands[0], operands[2], operands[4], operands[1])); 1984 emit_insn (gen_fnma<mode>4 (operands[0], operands[2], operands[4], operands[1]));
1889 emit_insn (gen_mul<mode>3 (operands[0], operands[0], operands[5])); 1985 emit_insn (gen_mul<mode>3 (operands[0], operands[0], operands[5]));
1890 emit_insn (gen_cgt_<f2i> (gen_lowpart (<F2I>mode, operands[0]), 1986 emit_insn (gen_cgt_<f2i> (gen_lowpart (<F2I>mode, operands[0]),
1891 gen_lowpart (<F2I>mode, operands[0]), 1987 gen_lowpart (<F2I>mode, operands[0]),
1892 spu_const (<F2I>mode, -1))); 1988 spu_const (<F2I>mode, -1)));
1893 emit_insn (gen_selb (operands[0], operands[3], operands[4], operands[0])); 1989 emit_insn (gen_selb (operands[0], operands[3], operands[4], operands[0]));
1918 emit_move_insn (operands[4],spu_float_const(\"1.00000011920928955078125\",SFmode)); 2014 emit_move_insn (operands[4],spu_float_const(\"1.00000011920928955078125\",SFmode));
1919 emit_insn (gen_frsqest_sf(operands[2],operands[1])); 2015 emit_insn (gen_frsqest_sf(operands[2],operands[1]));
1920 emit_insn (gen_fi_sf(operands[2],operands[1],operands[2])); 2016 emit_insn (gen_fi_sf(operands[2],operands[1],operands[2]));
1921 emit_insn (gen_mulsf3(operands[5],operands[2],operands[1])); 2017 emit_insn (gen_mulsf3(operands[5],operands[2],operands[1]));
1922 emit_insn (gen_mulsf3(operands[3],operands[5],operands[3])); 2018 emit_insn (gen_mulsf3(operands[3],operands[5],operands[3]));
1923 emit_insn (gen_fnms_sf(operands[4],operands[2],operands[5],operands[4])); 2019 emit_insn (gen_fnmasf4(operands[4],operands[2],operands[5],operands[4]));
1924 emit_insn (gen_fma_sf(operands[0],operands[4],operands[3],operands[5])); 2020 emit_insn (gen_fmasf4(operands[0],operands[4],operands[3],operands[5]));
1925 DONE; 2021 DONE;
1926 }) 2022 })
1927 2023
1928 (define_insn "frest_<mode>" 2024 (define_insn "frest_<mode>"
1929 [(set (match_operand:VSF 0 "spu_reg_operand" "=r") 2025 [(set (match_operand:VSF 0 "spu_reg_operand" "=r")
3186 emit_insn (gen_cgt_v4si (op5, op1, op2)); 3282 emit_insn (gen_cgt_v4si (op5, op1, op2));
3187 emit_insn (gen_spu_xswd (op3d, op3)); 3283 emit_insn (gen_spu_xswd (op3d, op3));
3188 emit_insn (gen_selb (op0, op5, op3, op4)); 3284 emit_insn (gen_selb (op0, op5, op3, op4));
3189 DONE; 3285 DONE;
3190 }) 3286 })
3287
3288 (define_insn "cgt_ti_m1"
3289 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
3290 (gt:SI (match_operand:TI 1 "spu_reg_operand" "r")
3291 (const_int -1)))]
3292 ""
3293 "cgti\t%0,%1,-1")
3191 3294
3192 (define_insn "cgt_ti" 3295 (define_insn "cgt_ti"
3193 [(set (match_operand:SI 0 "spu_reg_operand" "=r") 3296 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
3194 (gt:SI (match_operand:TI 1 "spu_reg_operand" "r") 3297 (gt:SI (match_operand:TI 1 "spu_reg_operand" "r")
3195 (match_operand:TI 2 "spu_reg_operand" "r"))) 3298 (match_operand:TI 2 "spu_reg_operand" "r")))