CbC/CbC_gcc: gcc/config/v850/predicates.md comparison

comparison gcc/config/v850/predicates.md @ 67:f6334be47118

update gcc from gcc-4.6-20100522 to gcc-4.6-20110318

author	nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date	Tue, 22 Mar 2011 17:18:12 +0900
parents	a06113de4d67
children	04ced10e8804

comparison

equal deleted inserted replaced

-:65488c3d617d
+:f6334be47118
 ;; Predicate definitions for NEC V850.
-;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
+;; Copyright (C) 2005, 2007, 2010 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
 ;; GCC is free software; you can redistribute it and/or modify
 ;; it under the terms of the GNU General Public License as published by
 {
 if (GET_CODE (op) == CONST_INT)
 return INTVAL (op) == 0;
 else if (GET_CODE (op) == CONST_DOUBLE)
-return CONST_DOUBLE_OK_FOR_G (op);
+return satisfies_constraint_G (op);
 else
 return register_operand (op, mode);
 })
 {
 if (GET_CODE (op) == CONST_INT)
 return TRUE;
 return register_operand (op, mode);
+})
+;; Return true if OP is a even number register.
+(define_predicate "even_reg_operand"
+(match_code "reg")
+{
+return (GET_CODE (op) == REG
+	  && (REGNO (op) >= FIRST_PSEUDO_REGISTER
+	      || ((REGNO (op) > 0) && (REGNO (op) < 32)
+		   && ((REGNO (op) & 1)==0))));
 })
 ;; Return true if OP is a valid call operand.
 (define_predicate "call_address_operand"
 if (TARGET_LONG_CALLS)
 return GET_CODE (op) == REG;
 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
 })
-;; TODO: Add a comment here.
+;; Return true if OP is a valid source operand for SImode move.
 (define_predicate "movsi_source_operand"
 (match_code "label_ref,symbol_ref,const_int,const_double,const,high,mem,reg,subreg")
 {
 /* Some constants, as well as symbolic operands
 return special_symbolref_operand (op, mode);
 else
 return general_operand (op, mode);
 })
-;; TODO: Add a comment here.
+;; Return true if OP is a valid operand for 23 bit displacement
+;; operations.
+(define_predicate "disp23_operand"
+(match_code "const_int")
+{
+if (GET_CODE (op) == CONST_INT
+&& ((unsigned)(INTVAL (op)) >= 0x8000)
+&& ((unsigned)(INTVAL (op)) < 0x400000))
+return 1;
+else
+return 0;
+})
+;; Return true if OP is a symbol ref with 16-bit signed value.
 (define_predicate "special_symbolref_operand"
 (match_code "symbol_ref")
 {
 if (GET_CODE (op) == CONST
 && GET_CODE (XEXP (op, 0)) == PLUS
-&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
+&& satisfies_constraint_K (XEXP (XEXP (op, 0), 1)))
-&& CONST_OK_FOR_K (INTVAL (XEXP (XEXP (op, 0), 1))))
 op = XEXP (XEXP (op, 0), 0);
 if (GET_CODE (op) == SYMBOL_REF)
 return (SYMBOL_REF_FLAGS (op)
 	    & (SYMBOL_FLAG_ZDA | SYMBOL_FLAG_TDA | SYMBOL_FLAG_SDA)) != 0;
 return FALSE;
 })
-;; TODO: Add a comment here.
+;; Return true if OP is a valid operand for bit related operations
+;; containing only single 1 in its binary representation.
 (define_predicate "power_of_two_operand"
 (match_code "const_int")
 {
 if (GET_CODE (op) != CONST_INT)
 int i;
 rtx vector_element;
 /* If there are no registers to save then the function prologue
 is not suitable.  */
-if (count <= 2)
+if (count <= (TARGET_LONG_CALLS ? 3 : 2))
 return 0;
 /* The pattern matching has already established that we are adjusting the
 stack and pushing at least one register.  We must now check that the
 remaining entries in the vector to make sure that they are also register
 	  return 0;
 	}
 }
 /* Make sure that the last entries in the vector are clobbers.  */
-for (; i < count; i++)
+vector_element = XVECEXP (op, 0, i++);
+if (GET_CODE (vector_element) != CLOBBER
+|| GET_CODE (XEXP (vector_element, 0)) != REG
+|| REGNO (XEXP (vector_element, 0)) != 10)
+return 0;
+if (TARGET_LONG_CALLS)
 {
-vector_element = XVECEXP (op, 0, i);
+vector_element = XVECEXP (op, 0, i++);
 if (GET_CODE (vector_element) != CLOBBER
 	  || GET_CODE (XEXP (vector_element, 0)) != REG
-	  || !(REGNO (XEXP (vector_element, 0)) == 10
+	  || REGNO (XEXP (vector_element, 0)) != 11)
-	       || (TARGET_LONG_CALLS ? (REGNO (XEXP (vector_element, 0)) == 11) : 0 )))
 	return 0;
 }
-return 1;
+return i == count;
 })
 ;; Return nonzero if the given RTX is suitable for collapsing into
 ;; jump to a function epilogue.
 The test below performs the C equivalent of this machine description
 pattern match:
 (set (match_operand:SI n "register_is_ok_for_epilogue" "r")
 	  (mem:SI (plus:SI (reg:SI 3) (match_operand:SI n "immediate_operand" "i"))))
+*/
+for (i = 2; i < count; i++)
+{
+rtx vector_element = XVECEXP (op, 0, i);
+rtx dest;
+rtx src;
+rtx plus;
+if (GET_CODE (vector_element) != SET)
+	return 0;
+dest = SET_DEST (vector_element);
+src = SET_SRC (vector_element);
+if (GET_CODE (dest) != REG
+	  || GET_MODE (dest) != SImode
+	  || ! register_is_ok_for_epilogue (dest, SImode)
+	  || GET_CODE (src) != MEM
+	  || GET_MODE (src) != SImode)
+	return 0;
+plus = XEXP (src, 0);
+if (GET_CODE (plus) != PLUS
+	  || GET_CODE (XEXP (plus, 0)) != REG
+	  || GET_MODE (XEXP (plus, 0)) != SImode
+	  || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
+	  || GET_CODE (XEXP (plus, 1)) != CONST_INT)
+	return 0;
+}
+return 1;
+})
+;; Return true if the given RTX is a register which can be restored by
+;; a function epilogue.
+(define_predicate "register_is_ok_for_epilogue"
+(match_code "reg")
+{
+/* The save/restore routines can only cope with registers 20 - 31.  */
+return ((GET_CODE (op) == REG)
+&& (((REGNO (op) >= 20) && REGNO (op) <= 31)));
+})
+;; Return nonzero if the given RTX is suitable for collapsing into a
+;; DISPOSE instruction.
+(define_predicate "pattern_is_ok_for_dispose"
+(match_code "parallel")
+{
+int count = XVECLEN (op, 0);
+int i;
+/* If there are no registers to restore then
+the dispose instruction is not suitable.  */
+if (count <= 2)
+return 0;
+/* The pattern matching has already established that we are performing a
+function epilogue and that we are popping at least one register.  We must
+now check the remaining entries in the vector to make sure that they are
+also register pops.  There is no good reason why there should ever be
+anything else in this vector, but being paranoid always helps...
+The test below performs the C equivalent of this machine description
+pattern match:
+(set (match_operand:SI n "register_is_ok_for_epilogue" "r")
+	  (mem:SI (plus:SI (reg:SI 3)
+	    (match_operand:SI n "immediate_operand" "i"))))
 */
 for (i = 3; i < count; i++)
 {
 rtx vector_element = XVECEXP (op, 0, i);
 if (GET_CODE (vector_element) != SET)
 	return 0;
 dest = SET_DEST (vector_element);
-src = SET_SRC (vector_element);
+src  = SET_SRC (vector_element);
-if (GET_CODE (dest) != REG
+if (   GET_CODE (dest) != REG
 	  || GET_MODE (dest) != SImode
 	  || ! register_is_ok_for_epilogue (dest, SImode)
 	  || GET_CODE (src) != MEM
 	  || GET_MODE (src) != SImode)
 	return 0;
 plus = XEXP (src, 0);
-if (GET_CODE (plus) != PLUS
+if (   GET_CODE (plus) != PLUS
 	  || GET_CODE (XEXP (plus, 0)) != REG
 	  || GET_MODE (XEXP (plus, 0)) != SImode
-	  || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
+	  || REGNO    (XEXP (plus, 0)) != STACK_POINTER_REGNUM
 	  || GET_CODE (XEXP (plus, 1)) != CONST_INT)
 	return 0;
 }
 return 1;
 })
-;; Return true if the given RTX is a register which can be restored by
-;; a function epilogue.
-(define_predicate "register_is_ok_for_epilogue"
-(match_code "reg")
-{
-/* The save/restore routines can only cope with registers 20 - 31.  */
-return ((GET_CODE (op) == REG)
-&& (((REGNO (op) >= 20) && REGNO (op) <= 31)));
-})
 ;; Return nonzero if the given RTX is suitable for collapsing into a
-;; DISPOSE instruction.
+;; PREPARE instruction.
-(define_predicate "pattern_is_ok_for_dispose"
+(define_predicate "pattern_is_ok_for_prepare"
 (match_code "parallel")
 {
 int count = XVECLEN (op, 0);
 int i;
-/* If there are no registers to restore then
+/* If there are no registers to restore then the prepare instruction
-the dispose instruction is not suitable.  */
+is not suitable.  */
-if (count <= 2)
+if (count <= 1)
 return 0;
-/* The pattern matching has already established that we are performing a
+/* The pattern matching has already established that we are adjusting the
-function epilogue and that we are popping at least one register.  We must
+stack and pushing at least one register.  We must now check that the
-now check the remaining entries in the vector to make sure that they are
+remaining entries in the vector to make sure that they are also register
-also register pops.  There is no good reason why there should ever be
+pushes.
-anything else in this vector, but being paranoid always helps...
 The test below performs the C equivalent of this machine description
 pattern match:
-(set (match_operand:SI n "register_is_ok_for_epilogue" "r")
+(set (mem:SI (plus:SI (reg:SI 3)
-	  (mem:SI (plus:SI (reg:SI 3)
+(match_operand:SI 2 "immediate_operand" "i")))
-	    (match_operand:SI n "immediate_operand" "i"))))
+(match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
 */
-for (i = 3; i < count; i++)
+for (i = 1; i < count; i++)
 {
 rtx vector_element = XVECEXP (op, 0, i);
 rtx dest;
 rtx src;
 rtx plus;
-if (GET_CODE (vector_element) != SET)
+if (GET_CODE (vector_element) == CLOBBER)
-	return 0;
+	continue;
-dest = SET_DEST (vector_element);
-src  = SET_SRC (vector_element);
-if (   GET_CODE (dest) != REG
-	  || GET_MODE (dest) != SImode
-	  || ! register_is_ok_for_epilogue (dest, SImode)
-	  || GET_CODE (src) != MEM
-	  || GET_MODE (src) != SImode)
-	return 0;
-plus = XEXP (src, 0);
-if (   GET_CODE (plus) != PLUS
-	  || GET_CODE (XEXP (plus, 0)) != REG
-	  || GET_MODE (XEXP (plus, 0)) != SImode
-	  || REGNO    (XEXP (plus, 0)) != STACK_POINTER_REGNUM
-	  || GET_CODE (XEXP (plus, 1)) != CONST_INT)
-	return 0;
-}
-return 1;
-})
-;; Return nonzero if the given RTX is suitable for collapsing into a
-;; PREPARE instruction.
-(define_predicate "pattern_is_ok_for_prepare"
-(match_code "parallel")
-{
-int count = XVECLEN (op, 0);
-int i;
-/* If there are no registers to restore then the prepare instruction
-is not suitable.  */
-if (count <= 1)
-return 0;
-/* The pattern matching has already established that we are adjusting the
-stack and pushing at least one register.  We must now check that the
-remaining entries in the vector to make sure that they are also register
-pushes.
-The test below performs the C equivalent of this machine description
-pattern match:
-(set (mem:SI (plus:SI (reg:SI 3)
-(match_operand:SI 2 "immediate_operand" "i")))
-(match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
-*/
-for (i = 2; i < count; i++)
-{
-rtx vector_element = XVECEXP (op, 0, i);
-rtx dest;
-rtx src;
-rtx plus;
 if (GET_CODE (vector_element) != SET)
 	return 0;
 dest = SET_DEST (vector_element);
 /* If the register is being pushed somewhere other than the stack
 	 space just acquired by the first operand then abandon this quest.
 	 Note: the test is <= because both values are negative.	 */
 if (INTVAL (XEXP (plus, 1))
-	  <= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
+	  < INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
 	return 0;
 }
 return 1;
 })
-;; TODO: Add a comment here.
+;; Return true if OP is a valid operand for bit related operations
+;; containing only single 0 in its binary representation.
 (define_predicate "not_power_of_two_operand"
 (match_code "const_int")
 {
 unsigned int mask;
 if (exact_log2 (~INTVAL (op) & mask) == -1)
 return 0;
 return 1;
 })
+;; Return true if OP is a float value operand with value as 1.
+(define_predicate "const_float_1_operand"
+(match_code "const_int")
+{
+if (GET_CODE (op) != CONST_DOUBLE
+|| mode != GET_MODE (op)
+|| (mode != DFmode && mode != SFmode))
+return 0;
+return op == CONST1_RTX(mode);
+})
+;; Return true if OP is a float value operand with value as 0.
+(define_predicate "const_float_0_operand"
+(match_code "const_int")
+{
+if (GET_CODE (op) != CONST_DOUBLE
+|| mode != GET_MODE (op)
+|| (mode != DFmode && mode != SFmode))
+return 0;
+return op == CONST0_RTX(mode);
+})

Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/v850/predicates.md @ 67:f6334be47118