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comparison gcc/config/v850/v850.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 77e2b8dfacca
children 04ced10e8804
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65:65488c3d617d 67:f6334be47118
1 ;; GCC machine description for NEC V850 1 ;; GCC machine description for NEC V850
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2002, 2004, 2005, 2007, 2008 2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2002, 2004, 2005, 2007, 2008, 2010
3 ;; Free Software Foundation, Inc. 3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Jeff Law (law@cygnus.com). 4 ;; Contributed by Jeff Law (law@cygnus.com).
5 5
6 ;; This file is part of GCC. 6 ;; This file is part of GCC.
7 7
29 ;; 29 ;;
30 ;; One day we'll probably need to handle calls to targets more than 4M 30 ;; One day we'll probably need to handle calls to targets more than 4M
31 ;; away. 31 ;; away.
32 32
33 ;; The size of instructions in bytes. 33 ;; The size of instructions in bytes.
34
35 ;;---------------------------------------------------------------------------
36 ;; Constants
37
38 ;;
39 (define_constants
40 [(ZERO_REGNUM 0) ; constant zero
41 (SP_REGNUM 3) ; Stack Pointer
42 (GP_REGNUM 4) ; GP Pointer
43 (EP_REGNUM 30) ; EP pointer
44 (LP_REGNUM 31) ; Return address register
45 (CC_REGNUM 32) ; Condition code pseudo register
46 (FCC_REGNUM 33) ; Floating Condition code pseudo register
47 ]
48 )
34 49
35 (define_attr "length" "" 50 (define_attr "length" ""
36 (const_int 4)) 51 (const_int 4))
37 52
38 (define_attr "long_calls" "yes,no" 53 (define_attr "long_calls" "yes,no"
40 (const_string "yes") 55 (const_string "yes")
41 (const_string "no")))) 56 (const_string "no"))))
42 57
43 ;; Types of instructions (for scheduling purposes). 58 ;; Types of instructions (for scheduling purposes).
44 59
45 (define_attr "type" "load,mult,other" 60 (define_attr "type" "load,store,bit1,mult,macc,div,fpu,single,other"
46 (const_string "other")) 61 (const_string "other"))
62
63 (define_attr "cpu" "none,v850,v850e,v850e1,v850e2,v850e2v3"
64 (cond [(ne (symbol_ref "TARGET_V850") (const_int 0))
65 (const_string "v850")
66 (ne (symbol_ref "TARGET_V850E") (const_int 0))
67 (const_string "v850e")
68 (ne (symbol_ref "TARGET_V850E1") (const_int 0))
69 (const_string "v850e1")
70 (ne (symbol_ref "TARGET_V850E2") (const_int 0))
71 (const_string "v850e2")
72 (ne (symbol_ref "TARGET_V850E2") (const_int 0))
73 (const_string "v850e2v3")]
74 (const_string "none")))
47 75
48 ;; Condition code settings. 76 ;; Condition code settings.
49 ;; none - insn does not affect cc 77 ;; none - insn does not affect cc
50 ;; none_0hit - insn does not affect cc but it does modify operand 0 78 ;; none_0hit - insn does not affect cc but it does modify operand 0
51 ;; This attribute is used to keep track of when operand 0 changes. 79 ;; This attribute is used to keep track of when operand 0 changes.
52 ;; See the description of NOTICE_UPDATE_CC for more info. 80 ;; See the description of NOTICE_UPDATE_CC for more info.
53 ;; set_znv - sets z,n,v to usable values; c is unknown. 81 ;; set_znv - sets z,n,v to usable values; c is unknown.
54 ;; set_zn - sets z,n to usable values; v,c is unknown. 82 ;; set_zn - sets z,n to usable values; v,c is unknown.
55 ;; compare - compare instruction 83 ;; compare - compare instruction
56 ;; clobber - value of cc is unknown 84 ;; clobber - value of cc is unknown
57 (define_attr "cc" "none,none_0hit,set_zn,set_znv,compare,clobber" 85 (define_attr "cc" "none,none_0hit,set_z,set_zn,set_znv,compare,clobber"
58 (const_string "clobber")) 86 (const_string "clobber"))
59 87
60 ;; Function units for the V850. As best as I can tell, there's 88 ;; Function units for the V850. As best as I can tell, there's
61 ;; a traditional memory load/use stall as well as a stall if 89 ;; a traditional memory load/use stall as well as a stall if
62 ;; the result of a multiply is used too early. 90 ;; the result of a multiply is used too early.
70 (define_insn_reservation "v850_memory" 2 98 (define_insn_reservation "v850_memory" 2
71 (eq_attr "type" "load") 99 (eq_attr "type" "load")
72 "nothing") 100 "nothing")
73 101
74 (include "predicates.md") 102 (include "predicates.md")
103 (include "constraints.md")
75 104
76 ;; ---------------------------------------------------------------------- 105 ;; ----------------------------------------------------------------------
77 ;; MOVE INSTRUCTIONS 106 ;; MOVE INSTRUCTIONS
78 ;; ---------------------------------------------------------------------- 107 ;; ----------------------------------------------------------------------
79 108 (define_insn "sign23byte_load"
109 [(set (match_operand:SI 0 "register_operand" "=r")
110 (sign_extend:SI
111 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
112 (match_operand 2 "disp23_operand" "W")))))]
113 "TARGET_V850E2V3"
114 "ld.b %2[%1],%0"
115 [(set_attr "length" "4")
116 (set_attr "cc" "none_0hit")])
117
118 (define_insn "unsign23byte_load"
119 [(set (match_operand:SI 0 "register_operand" "=r")
120 (zero_extend:SI
121 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
122 (match_operand 2 "disp23_operand" "W")))))]
123 "TARGET_V850E2V3"
124 "ld.bu %2[%1],%0"
125 [(set_attr "length" "4")
126 (set_attr "cc" "none_0hit")])
127
128 (define_insn "sign23hword_load"
129 [(set (match_operand:SI 0 "register_operand" "=r")
130 (sign_extend:SI
131 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
132 (match_operand 2 "disp23_operand" "W")))))]
133 "TARGET_V850E2V3"
134 "ld.h %2[%1],%0"
135 [(set_attr "length" "4")
136 (set_attr "cc" "none_0hit")])
137
138 (define_insn "unsign23hword_load"
139 [(set (match_operand:SI 0 "register_operand" "=r")
140 (zero_extend:SI
141 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
142 (match_operand 2 "disp23_operand" "W")))))]
143 "TARGET_V850E2V3"
144 "ld.hu %2[%1],%0"
145 [(set_attr "length" "4")
146 (set_attr "cc" "none_0hit")])
147
148 (define_insn "23word_load"
149 [(set (match_operand:SI 0 "register_operand" "=r")
150 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
151 (match_operand 2 "disp23_operand" "W"))))]
152 "TARGET_V850E2V3"
153 "ld.w %2[%1],%0"
154 [(set_attr "length" "4")
155 (set_attr "cc" "none_0hit")])
156
157 (define_insn "23byte_store"
158 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "r")
159 (match_operand 1 "disp23_operand" "W")))
160 (match_operand:QI 2 "register_operand" "r"))]
161 "TARGET_V850E2V3"
162 "st.b %2,%1[%0]"
163 [(set_attr "length" "4")
164 (set_attr "cc" "none_0hit")])
165
166 (define_insn "23hword_store"
167 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "r")
168 (match_operand 1 "disp23_operand" "W")))
169 (match_operand:HI 2 "register_operand" "r"))]
170 "TARGET_V850E2V3"
171 "st.h %2,%1[%0]"
172 [(set_attr "length" "4")
173 (set_attr "cc" "none_0hit")])
174
175 (define_insn "23word_store"
176 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
177 (match_operand 1 "disp23_operand" "W")))
178 (match_operand:SI 2 "register_operand" "r"))]
179 "TARGET_V850E2V3"
180 "st.w %2,%1[%0]"
181 [(set_attr "length" "4")
182 (set_attr "cc" "none_0hit")])
80 ;; movqi 183 ;; movqi
81 184
82 (define_expand "movqi" 185 (define_expand "movqi"
83 [(set (match_operand:QI 0 "general_operand" "") 186 [(set (match_operand:QI 0 "general_operand" "")
84 (match_operand:QI 1 "general_operand" ""))] 187 (match_operand:QI 1 "general_operand" ""))]
97 "register_operand (operands[0], QImode) 200 "register_operand (operands[0], QImode)
98 || reg_or_0_operand (operands[1], QImode)" 201 || reg_or_0_operand (operands[1], QImode)"
99 "* return output_move_single (operands);" 202 "* return output_move_single (operands);"
100 [(set_attr "length" "2,4,2,2,4,4,4") 203 [(set_attr "length" "2,4,2,2,4,4,4")
101 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") 204 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
102 (set_attr "type" "other,other,load,other,load,other,other")]) 205 (set_attr "type" "other,other,load,other,load,store,store")])
103 206
104 ;; movhi 207 ;; movhi
105 208
106 (define_expand "movhi" 209 (define_expand "movhi"
107 [(set (match_operand:HI 0 "general_operand" "") 210 [(set (match_operand:HI 0 "general_operand" "")
121 "register_operand (operands[0], HImode) 224 "register_operand (operands[0], HImode)
122 || reg_or_0_operand (operands[1], HImode)" 225 || reg_or_0_operand (operands[1], HImode)"
123 "* return output_move_single (operands);" 226 "* return output_move_single (operands);"
124 [(set_attr "length" "2,4,2,2,4,4,4") 227 [(set_attr "length" "2,4,2,2,4,4,4")
125 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") 228 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
126 (set_attr "type" "other,other,load,other,load,other,other")]) 229 (set_attr "type" "other,other,load,other,load,store,store")])
127 230
128 ;; movsi and helpers 231 ;; movsi and helpers
129 232
130 (define_insn "*movsi_high" 233 (define_insn "*movsi_high"
131 [(set (match_operand:SI 0 "register_operand" "=r") 234 [(set (match_operand:SI 0 "register_operand" "=r")
159 262
160 /* Some constants, as well as symbolic operands 263 /* Some constants, as well as symbolic operands
161 must be done with HIGH & LO_SUM patterns. */ 264 must be done with HIGH & LO_SUM patterns. */
162 if (CONSTANT_P (operands[1]) 265 if (CONSTANT_P (operands[1])
163 && GET_CODE (operands[1]) != HIGH 266 && GET_CODE (operands[1]) != HIGH
164 && ! TARGET_V850E 267 && ! (TARGET_V850E || TARGET_V850E2_ALL)
165 && !special_symbolref_operand (operands[1], VOIDmode) 268 && !special_symbolref_operand (operands[1], VOIDmode)
166 && !(GET_CODE (operands[1]) == CONST_INT 269 && !(GET_CODE (operands[1]) == CONST_INT
167 && (CONST_OK_FOR_J (INTVAL (operands[1])) 270 && (CONST_OK_FOR_J (INTVAL (operands[1]))
168 || CONST_OK_FOR_K (INTVAL (operands[1])) 271 || CONST_OK_FOR_K (INTVAL (operands[1]))
169 || CONST_OK_FOR_L (INTVAL (operands[1]))))) 272 || CONST_OK_FOR_L (INTVAL (operands[1])))))
191 ;; upper part with hi, and then put the lower part in the load/store insn. 294 ;; upper part with hi, and then put the lower part in the load/store insn.
192 295
193 (define_insn "*movsi_internal_v850e" 296 (define_insn "*movsi_internal_v850e"
194 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m,r") 297 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m,r")
195 (match_operand:SI 1 "general_operand" "Jr,K,L,Q,Ir,m,R,r,I,i"))] 298 (match_operand:SI 1 "general_operand" "Jr,K,L,Q,Ir,m,R,r,I,i"))]
196 "TARGET_V850E 299 "(TARGET_V850E || TARGET_V850E2_ALL)
197 && (register_operand (operands[0], SImode) 300 && (register_operand (operands[0], SImode)
198 || reg_or_0_operand (operands[1], SImode))" 301 || reg_or_0_operand (operands[1], SImode))"
199 "* return output_move_single (operands);" 302 "* return output_move_single (operands);"
200 [(set_attr "length" "2,4,4,2,2,4,4,4,4,6") 303 [(set_attr "length" "2,4,4,2,2,4,4,4,4,6")
201 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") 304 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
202 (set_attr "type" "other,other,other,load,other,load,other,other,other,other")]) 305 (set_attr "type" "other,other,other,load,other,load,other,store,store,other")])
203 306
204 (define_insn "*movsi_internal" 307 (define_insn "*movsi_internal"
205 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m") 308 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m")
206 (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))] 309 (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))]
207 "register_operand (operands[0], SImode) 310 "register_operand (operands[0], SImode)
208 || reg_or_0_operand (operands[1], SImode)" 311 || reg_or_0_operand (operands[1], SImode)"
209 "* return output_move_single (operands);" 312 "* return output_move_single (operands);"
210 [(set_attr "length" "2,4,4,2,2,4,4,4,4") 313 [(set_attr "length" "2,4,4,2,2,4,4,4,4")
211 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") 314 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
212 (set_attr "type" "other,other,other,load,other,load,other,other,other")]) 315 (set_attr "type" "other,other,other,load,other,load,store,store,other")])
213 316
214 (define_insn "*movsf_internal" 317 (define_insn "*movsf_internal"
215 [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r") 318 [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r")
216 (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))] 319 (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))]
217 "register_operand (operands[0], SFmode) 320 "register_operand (operands[0], SFmode)
218 || reg_or_0_operand (operands[1], SFmode)" 321 || reg_or_0_operand (operands[1], SFmode)"
219 "* return output_move_single (operands);" 322 "* return output_move_single (operands);"
220 [(set_attr "length" "2,4,4,8,2,2,4,4,4,8") 323 [(set_attr "length" "2,4,4,8,2,2,4,4,4,8")
221 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") 324 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
222 (set_attr "type" "other,other,other,other,load,other,load,other,other,other")]) 325 (set_attr "type" "other,other,other,other,load,other,load,store,store,other")])
223 326
224
225 ;; ---------------------------------------------------------------------- 327 ;; ----------------------------------------------------------------------
226 ;; TEST INSTRUCTIONS 328 ;; TEST INSTRUCTIONS
227 ;; ---------------------------------------------------------------------- 329 ;; ----------------------------------------------------------------------
228 330
229 (define_insn "*v850_tst1" 331 (define_insn "*v850_tst1"
271 (set (match_operand:SI 0 "register_operand") 373 (set (match_operand:SI 0 "register_operand")
272 (match_operator:SI 1 "ordered_comparison_operator" [(cc0) 374 (match_operator:SI 1 "ordered_comparison_operator" [(cc0)
273 (const_int 0)]))] 375 (const_int 0)]))]
274 "") 376 "")
275 377
276 (define_insn "*cmpsi" 378 (define_expand "cmpsi"
277 [(set (cc0) 379 [(set (cc0)
278 (compare (match_operand:SI 0 "register_operand" "r,r,r") 380 (compare (match_operand:SI 0 "register_operand" "r,r")
279 (match_operand:SI 1 "reg_or_int5_operand" "r,I,J")))] 381 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
382 ""
383 "
384 {
385 v850_compare_op0 = operands[0];
386 v850_compare_op1 = operands[1];
387 DONE;
388 }")
389
390 (define_insn "cmpsi_insn"
391 [(set (cc0)
392 (compare (match_operand:SI 0 "register_operand" "r,r")
393 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
280 "" 394 ""
281 "@ 395 "@
282 cmp %1,%0 396 cmp %1,%0
283 cmp %.,%0
284 cmp %1,%0" 397 cmp %1,%0"
285 [(set_attr "length" "2,2,2") 398 [(set_attr "length" "2,2")
286 (set_attr "cc" "compare,set_znv,compare")]) 399 (set_attr "cc" "compare")])
287 400
288 401 (define_expand "cmpsf"
402 [(set (reg:CC CC_REGNUM)
403 (compare (match_operand:SF 0 "register_operand" "r")
404 (match_operand:SF 1 "register_operand" "r")))]
405 "TARGET_V850E2V3"
406 "
407 {
408 v850_compare_op0 = operands[0];
409 v850_compare_op1 = operands[1];
410 DONE;
411 }")
412
413 (define_expand "cmpdf"
414 [(set (reg:CC CC_REGNUM)
415 (compare (match_operand:DF 0 "even_reg_operand" "r")
416 (match_operand:DF 1 "even_reg_operand" "r")))]
417 "TARGET_V850E2V3"
418 "
419 {
420 v850_compare_op0 = operands[0];
421 v850_compare_op1 = operands[1];
422 DONE;
423 }")
424
289 ;; ---------------------------------------------------------------------- 425 ;; ----------------------------------------------------------------------
290 ;; ADD INSTRUCTIONS 426 ;; ADD INSTRUCTIONS
291 ;; ---------------------------------------------------------------------- 427 ;; ----------------------------------------------------------------------
292 428
293 (define_insn "addsi3" 429 (define_insn "addsi3"
294 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 430 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
295 (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r") 431 (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
296 (match_operand:SI 2 "nonmemory_operand" "rJ,K,U")))] 432 (match_operand:SI 2 "nonmemory_operand" "rJ,K,U")))
433 (clobber (reg:CC CC_REGNUM))]
434
297 "" 435 ""
298 "@ 436 "@
299 add %2,%0 437 add %2,%0
300 addi %2,%1,%0 438 addi %2,%1,%0
301 addi %O2(%P2),%1,%0" 439 addi %O2(%P2),%1,%0"
307 ;; ---------------------------------------------------------------------- 445 ;; ----------------------------------------------------------------------
308 446
309 (define_insn "subsi3" 447 (define_insn "subsi3"
310 [(set (match_operand:SI 0 "register_operand" "=r,r") 448 [(set (match_operand:SI 0 "register_operand" "=r,r")
311 (minus:SI (match_operand:SI 1 "register_operand" "0,r") 449 (minus:SI (match_operand:SI 1 "register_operand" "0,r")
312 (match_operand:SI 2 "register_operand" "r,0")))] 450 (match_operand:SI 2 "register_operand" "r,0")))
451 (clobber (reg:CC CC_REGNUM))]
313 "" 452 ""
314 "@ 453 "@
315 sub %2,%0 454 sub %2,%0
316 subr %1,%0" 455 subr %1,%0"
317 [(set_attr "length" "2,2") 456 [(set_attr "length" "2,2")
318 (set_attr "cc" "set_zn")]) 457 (set_attr "cc" "set_zn,set_zn")])
319 458
320 (define_insn "negsi2" 459 (define_insn "negsi2"
321 [(set (match_operand:SI 0 "register_operand" "=r") 460 [(set (match_operand:SI 0 "register_operand" "=r")
322 (neg:SI (match_operand:SI 1 "register_operand" "0")))] 461 (neg:SI (match_operand:SI 1 "register_operand" "0")))
462 (clobber (reg:CC CC_REGNUM))]
323 "" 463 ""
324 "subr %.,%0" 464 "subr %.,%0"
325 [(set_attr "length" "2") 465 [(set_attr "length" "2")
326 (set_attr "cc" "set_zn")]) 466 (set_attr "cc" "set_zn")])
327 467
377 517
378 (define_insn "mulsi3" 518 (define_insn "mulsi3"
379 [(set (match_operand:SI 0 "register_operand" "=r") 519 [(set (match_operand:SI 0 "register_operand" "=r")
380 (mult:SI (match_operand:SI 1 "register_operand" "%0") 520 (mult:SI (match_operand:SI 1 "register_operand" "%0")
381 (match_operand:SI 2 "reg_or_int9_operand" "rO")))] 521 (match_operand:SI 2 "reg_or_int9_operand" "rO")))]
382 "TARGET_V850E" 522 "(TARGET_V850E || TARGET_V850E2_ALL)"
383 "mul %2,%1,%." 523 "mul %2,%1,%."
384 [(set_attr "length" "4") 524 [(set_attr "length" "4")
385 (set_attr "cc" "none_0hit") 525 (set_attr "cc" "none_0hit")
386 (set_attr "type" "mult")]) 526 (set_attr "type" "mult")])
387 527
399 [(set (match_operand:SI 0 "register_operand" "=r") 539 [(set (match_operand:SI 0 "register_operand" "=r")
400 (div:SI (match_operand:SI 1 "register_operand" "0") 540 (div:SI (match_operand:SI 1 "register_operand" "0")
401 (match_operand:SI 2 "register_operand" "r"))) 541 (match_operand:SI 2 "register_operand" "r")))
402 (set (match_operand:SI 3 "register_operand" "=r") 542 (set (match_operand:SI 3 "register_operand" "=r")
403 (mod:SI (match_dup 1) 543 (mod:SI (match_dup 1)
404 (match_dup 2)))] 544 (match_dup 2)))
545 (clobber (reg:CC CC_REGNUM))]
405 "TARGET_V850E" 546 "TARGET_V850E"
406 "div %2,%0,%3" 547 "div %2,%0,%3"
407 [(set_attr "length" "4") 548 [(set_attr "length" "4")
408 (set_attr "cc" "clobber") 549 (set_attr "cc" "clobber")
409 (set_attr "type" "other")]) 550 (set_attr "type" "div")])
410 551
411 (define_insn "udivmodsi4" 552 (define_insn "udivmodsi4"
412 [(set (match_operand:SI 0 "register_operand" "=r") 553 [(set (match_operand:SI 0 "register_operand" "=r")
413 (udiv:SI (match_operand:SI 1 "register_operand" "0") 554 (udiv:SI (match_operand:SI 1 "register_operand" "0")
414 (match_operand:SI 2 "register_operand" "r"))) 555 (match_operand:SI 2 "register_operand" "r")))
415 (set (match_operand:SI 3 "register_operand" "=r") 556 (set (match_operand:SI 3 "register_operand" "=r")
416 (umod:SI (match_dup 1) 557 (umod:SI (match_dup 1)
417 (match_dup 2)))] 558 (match_dup 2)))
559 (clobber (reg:CC CC_REGNUM))]
418 "TARGET_V850E" 560 "TARGET_V850E"
419 "divu %2,%0,%3" 561 "divu %2,%0,%3"
420 [(set_attr "length" "4") 562 [(set_attr "length" "4")
421 (set_attr "cc" "clobber") 563 (set_attr "cc" "clobber")
422 (set_attr "type" "other")]) 564 (set_attr "type" "div")])
423 565
424 ;; ??? There is a 2 byte instruction for generating only the quotient. 566 ;; ??? There is a 2 byte instruction for generating only the quotient.
425 ;; However, it isn't clear how to compute the length field correctly. 567 ;; However, it isn't clear how to compute the length field correctly.
426 568
427 (define_insn "divmodhi4" 569 (define_insn "divmodhi4"
428 [(set (match_operand:HI 0 "register_operand" "=r") 570 [(set (match_operand:HI 0 "register_operand" "=r")
429 (div:HI (match_operand:HI 1 "register_operand" "0") 571 (div:HI (match_operand:HI 1 "register_operand" "0")
430 (match_operand:HI 2 "register_operand" "r"))) 572 (match_operand:HI 2 "register_operand" "r")))
431 (set (match_operand:HI 3 "register_operand" "=r") 573 (set (match_operand:HI 3 "register_operand" "=r")
432 (mod:HI (match_dup 1) 574 (mod:HI (match_dup 1)
433 (match_dup 2)))] 575 (match_dup 2)))
576 (clobber (reg:CC CC_REGNUM))]
434 "TARGET_V850E" 577 "TARGET_V850E"
435 "divh %2,%0,%3" 578 "divh %2,%0,%3"
436 [(set_attr "length" "4") 579 [(set_attr "length" "4")
437 (set_attr "cc" "clobber") 580 (set_attr "cc" "clobber")
438 (set_attr "type" "other")]) 581 (set_attr "type" "div")])
439 582
440 ;; Half-words are sign-extended by default, so we must zero extend to a word 583 ;; Half-words are sign-extended by default, so we must zero extend to a word
441 ;; here before doing the divide. 584 ;; here before doing the divide.
442 585
443 (define_insn "udivmodhi4" 586 (define_insn "udivmodhi4"
444 [(set (match_operand:HI 0 "register_operand" "=r") 587 [(set (match_operand:HI 0 "register_operand" "=r")
445 (udiv:HI (match_operand:HI 1 "register_operand" "0") 588 (udiv:HI (match_operand:HI 1 "register_operand" "0")
446 (match_operand:HI 2 "register_operand" "r"))) 589 (match_operand:HI 2 "register_operand" "r")))
447 (set (match_operand:HI 3 "register_operand" "=r") 590 (set (match_operand:HI 3 "register_operand" "=r")
448 (umod:HI (match_dup 1) 591 (umod:HI (match_dup 1)
449 (match_dup 2)))] 592 (match_dup 2)))
593 (clobber (reg:CC CC_REGNUM))]
450 "TARGET_V850E" 594 "TARGET_V850E"
451 "zxh %0 ; divhu %2,%0,%3" 595 "zxh %0 ; divhu %2,%0,%3"
452 [(set_attr "length" "4") 596 [(set_attr "length" "4")
453 (set_attr "cc" "clobber") 597 (set_attr "cc" "clobber")
454 (set_attr "type" "other")]) 598 (set_attr "type" "div")])
455 599
456 ;; ---------------------------------------------------------------------- 600 ;; ----------------------------------------------------------------------
457 ;; AND INSTRUCTIONS 601 ;; AND INSTRUCTIONS
458 ;; ---------------------------------------------------------------------- 602 ;; ----------------------------------------------------------------------
459 603
460 (define_insn "*v850_clr1_1" 604 (define_insn "*v850_clr1_1"
461 [(set (match_operand:QI 0 "memory_operand" "=m") 605 [(set (match_operand:QI 0 "memory_operand" "=m")
462 (subreg:QI 606 (subreg:QI
463 (and:SI (subreg:SI (match_dup 0) 0) 607 (and:SI (subreg:SI (match_dup 0) 0)
464 (match_operand:QI 1 "not_power_of_two_operand" "")) 0))] 608 (match_operand:QI 1 "not_power_of_two_operand" "")) 0))
609 (clobber (reg:CC CC_REGNUM))]
465 "" 610 ""
466 "* 611 "*
467 { 612 {
468 rtx xoperands[2]; 613 rtx xoperands[2];
469 xoperands[0] = operands[0]; 614 xoperands[0] = operands[0];
470 xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff); 615 xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff);
471 output_asm_insn (\"clr1 %M1,%0\", xoperands); 616 output_asm_insn (\"clr1 %M1,%0\", xoperands);
472 return \"\"; 617 return \"\";
473 }" 618 }"
474 [(set_attr "length" "4") 619 [(set_attr "length" "4")
475 (set_attr "cc" "clobber")]) 620 (set_attr "cc" "clobber")
621 (set_attr "type" "bit1")])
476 622
477 (define_insn "*v850_clr1_2" 623 (define_insn "*v850_clr1_2"
478 [(set (match_operand:HI 0 "indirect_operand" "=m") 624 [(set (match_operand:HI 0 "indirect_operand" "=m")
479 (subreg:HI 625 (subreg:HI
480 (and:SI (subreg:SI (match_dup 0) 0) 626 (and:SI (subreg:SI (match_dup 0) 0)
481 (match_operand:HI 1 "not_power_of_two_operand" "")) 0))] 627 (match_operand:HI 1 "not_power_of_two_operand" "")) 0))
628 (clobber (reg:CC CC_REGNUM))]
482 "" 629 ""
483 "* 630 "*
484 { 631 {
485 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff); 632 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff);
486 633
490 xoperands[1] = GEN_INT (log2 % 8); 637 xoperands[1] = GEN_INT (log2 % 8);
491 output_asm_insn (\"clr1 %1,%0\", xoperands); 638 output_asm_insn (\"clr1 %1,%0\", xoperands);
492 return \"\"; 639 return \"\";
493 }" 640 }"
494 [(set_attr "length" "4") 641 [(set_attr "length" "4")
495 (set_attr "cc" "clobber")]) 642 (set_attr "cc" "clobber")
643 (set_attr "type" "bit1")])
496 644
497 (define_insn "*v850_clr1_3" 645 (define_insn "*v850_clr1_3"
498 [(set (match_operand:SI 0 "indirect_operand" "=m") 646 [(set (match_operand:SI 0 "indirect_operand" "=m")
499 (and:SI (match_dup 0) 647 (and:SI (match_dup 0)
500 (match_operand:SI 1 "not_power_of_two_operand" "")))] 648 (match_operand:SI 1 "not_power_of_two_operand" "")))
649 (clobber (reg:CC CC_REGNUM))]
501 "" 650 ""
502 "* 651 "*
503 { 652 {
504 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff); 653 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff);
505 654
509 xoperands[1] = GEN_INT (log2 % 8); 658 xoperands[1] = GEN_INT (log2 % 8);
510 output_asm_insn (\"clr1 %1,%0\", xoperands); 659 output_asm_insn (\"clr1 %1,%0\", xoperands);
511 return \"\"; 660 return \"\";
512 }" 661 }"
513 [(set_attr "length" "4") 662 [(set_attr "length" "4")
514 (set_attr "cc" "clobber")]) 663 (set_attr "cc" "clobber")
664 (set_attr "type" "bit1")])
515 665
516 (define_insn "andsi3" 666 (define_insn "andsi3"
517 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 667 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
518 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r") 668 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
519 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))] 669 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))
670 (clobber (reg:CC CC_REGNUM))]
520 "" 671 ""
521 "@ 672 "@
522 and %2,%0 673 and %2,%0
523 and %.,%0 674 and %.,%0
524 andi %2,%1,%0" 675 andi %2,%1,%0"
525 [(set_attr "length" "2,2,4") 676 [(set_attr "length" "2,2,4")
526 (set_attr "cc" "set_znv")]) 677 (set_attr "cc" "set_zn")])
527 678
528 ;; ---------------------------------------------------------------------- 679 ;; ----------------------------------------------------------------------
529 ;; OR INSTRUCTIONS 680 ;; OR INSTRUCTIONS
530 ;; ---------------------------------------------------------------------- 681 ;; ----------------------------------------------------------------------
531 682
532 (define_insn "*v850_set1_1" 683 (define_insn "*v850_set1_1"
533 [(set (match_operand:QI 0 "memory_operand" "=m") 684 [(set (match_operand:QI 0 "memory_operand" "=m")
534 (subreg:QI (ior:SI (subreg:SI (match_dup 0) 0) 685 (subreg:QI (ior:SI (subreg:SI (match_dup 0) 0)
535 (match_operand 1 "power_of_two_operand" "")) 0))] 686 (match_operand 1 "power_of_two_operand" "")) 0))
687 (clobber (reg:CC CC_REGNUM))]
536 "" 688 ""
537 "set1 %M1,%0" 689 "set1 %M1,%0"
538 [(set_attr "length" "4") 690 [(set_attr "length" "4")
539 (set_attr "cc" "clobber")]) 691 (set_attr "cc" "clobber")
692 (set_attr "type" "bit1")])
540 693
541 (define_insn "*v850_set1_2" 694 (define_insn "*v850_set1_2"
542 [(set (match_operand:HI 0 "indirect_operand" "=m") 695 [(set (match_operand:HI 0 "indirect_operand" "=m")
543 (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0) 696 (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0)
544 (match_operand 1 "power_of_two_operand" "")) 0))] 697 (match_operand 1 "power_of_two_operand" "")) 0))]
559 output_asm_insn (\"set1 %1,%0\", xoperands); 712 output_asm_insn (\"set1 %1,%0\", xoperands);
560 } 713 }
561 return \"\"; 714 return \"\";
562 }" 715 }"
563 [(set_attr "length" "4") 716 [(set_attr "length" "4")
564 (set_attr "cc" "clobber")]) 717 (set_attr "cc" "clobber")
718 (set_attr "type" "bit1")])
565 719
566 (define_insn "*v850_set1_3" 720 (define_insn "*v850_set1_3"
567 [(set (match_operand:SI 0 "indirect_operand" "=m") 721 [(set (match_operand:SI 0 "indirect_operand" "=m")
568 (ior:SI (match_dup 0) 722 (ior:SI (match_dup 0)
569 (match_operand 1 "power_of_two_operand" "")))] 723 (match_operand 1 "power_of_two_operand" "")))
724 (clobber (reg:CC CC_REGNUM))]
570 "" 725 ""
571 "* 726 "*
572 { 727 {
573 int log2 = exact_log2 (INTVAL (operands[1])); 728 int log2 = exact_log2 (INTVAL (operands[1]));
574 729
584 output_asm_insn (\"set1 %1,%0\", xoperands); 739 output_asm_insn (\"set1 %1,%0\", xoperands);
585 } 740 }
586 return \"\"; 741 return \"\";
587 }" 742 }"
588 [(set_attr "length" "4") 743 [(set_attr "length" "4")
589 (set_attr "cc" "clobber")]) 744 (set_attr "cc" "clobber")
745 (set_attr "type" "bit1")])
590 746
591 (define_insn "iorsi3" 747 (define_insn "iorsi3"
592 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 748 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
593 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r") 749 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
594 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))] 750 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))
751 (clobber (reg:CC CC_REGNUM))]
595 "" 752 ""
596 "@ 753 "@
597 or %2,%0 754 or %2,%0
598 or %.,%0 755 or %.,%0
599 ori %2,%1,%0" 756 ori %2,%1,%0"
600 [(set_attr "length" "2,2,4") 757 [(set_attr "length" "2,2,4")
601 (set_attr "cc" "set_znv")]) 758 (set_attr "cc" "set_zn")])
602 759
603 ;; ---------------------------------------------------------------------- 760 ;; ----------------------------------------------------------------------
604 ;; XOR INSTRUCTIONS 761 ;; XOR INSTRUCTIONS
605 ;; ---------------------------------------------------------------------- 762 ;; ----------------------------------------------------------------------
606 763
607 (define_insn "*v850_not1_1" 764 (define_insn "*v850_not1_1"
608 [(set (match_operand:QI 0 "memory_operand" "=m") 765 [(set (match_operand:QI 0 "memory_operand" "=m")
609 (subreg:QI (xor:SI (subreg:SI (match_dup 0) 0) 766 (subreg:QI (xor:SI (subreg:SI (match_dup 0) 0)
610 (match_operand 1 "power_of_two_operand" "")) 0))] 767 (match_operand 1 "power_of_two_operand" "")) 0))
768 (clobber (reg:CC CC_REGNUM))]
611 "" 769 ""
612 "not1 %M1,%0" 770 "not1 %M1,%0"
613 [(set_attr "length" "4") 771 [(set_attr "length" "4")
614 (set_attr "cc" "clobber")]) 772 (set_attr "cc" "clobber")
773 (set_attr "type" "bit1")])
615 774
616 (define_insn "*v850_not1_2" 775 (define_insn "*v850_not1_2"
617 [(set (match_operand:HI 0 "indirect_operand" "=m") 776 [(set (match_operand:HI 0 "indirect_operand" "=m")
618 (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0) 777 (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0)
619 (match_operand 1 "power_of_two_operand" "")) 0))] 778 (match_operand 1 "power_of_two_operand" "")) 0))]
634 output_asm_insn (\"not1 %1,%0\", xoperands); 793 output_asm_insn (\"not1 %1,%0\", xoperands);
635 } 794 }
636 return \"\"; 795 return \"\";
637 }" 796 }"
638 [(set_attr "length" "4") 797 [(set_attr "length" "4")
639 (set_attr "cc" "clobber")]) 798 (set_attr "cc" "clobber")
799 (set_attr "type" "bit1")])
640 800
641 (define_insn "*v850_not1_3" 801 (define_insn "*v850_not1_3"
642 [(set (match_operand:SI 0 "indirect_operand" "=m") 802 [(set (match_operand:SI 0 "indirect_operand" "=m")
643 (xor:SI (match_dup 0) 803 (xor:SI (match_dup 0)
644 (match_operand 1 "power_of_two_operand" "")))] 804 (match_operand 1 "power_of_two_operand" "")))
805 (clobber (reg:CC CC_REGNUM))]
645 "" 806 ""
646 "* 807 "*
647 { 808 {
648 int log2 = exact_log2 (INTVAL (operands[1])); 809 int log2 = exact_log2 (INTVAL (operands[1]));
649 810
659 output_asm_insn (\"not1 %1,%0\", xoperands); 820 output_asm_insn (\"not1 %1,%0\", xoperands);
660 } 821 }
661 return \"\"; 822 return \"\";
662 }" 823 }"
663 [(set_attr "length" "4") 824 [(set_attr "length" "4")
664 (set_attr "cc" "clobber")]) 825 (set_attr "cc" "clobber")
826 (set_attr "type" "bit1")])
665 827
666 (define_insn "xorsi3" 828 (define_insn "xorsi3"
667 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 829 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
668 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r") 830 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
669 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))] 831 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))
832 (clobber (reg:CC CC_REGNUM))]
670 "" 833 ""
671 "@ 834 "@
672 xor %2,%0 835 xor %2,%0
673 xor %.,%0 836 xor %.,%0
674 xori %2,%1,%0" 837 xori %2,%1,%0"
675 [(set_attr "length" "2,2,4") 838 [(set_attr "length" "2,2,4")
676 (set_attr "cc" "set_znv")]) 839 (set_attr "cc" "set_zn")])
677 840
678 ;; ---------------------------------------------------------------------- 841 ;; ----------------------------------------------------------------------
679 ;; NOT INSTRUCTIONS 842 ;; NOT INSTRUCTIONS
680 ;; ---------------------------------------------------------------------- 843 ;; ----------------------------------------------------------------------
681 844
682 (define_insn "one_cmplsi2" 845 (define_insn "one_cmplsi2"
683 [(set (match_operand:SI 0 "register_operand" "=r") 846 [(set (match_operand:SI 0 "register_operand" "=r")
684 (not:SI (match_operand:SI 1 "register_operand" "r")))] 847 (not:SI (match_operand:SI 1 "register_operand" "r")))
848 (clobber (reg:CC CC_REGNUM))]
685 "" 849 ""
686 "not %1,%0" 850 "not %1,%0"
687 [(set_attr "length" "2") 851 [(set_attr "length" "2")
688 (set_attr "cc" "set_znv")]) 852 (set_attr "cc" "set_zn")])
689 853
690 ;; ----------------------------------------------------------------- 854 ;; -----------------------------------------------------------------
691 ;; BIT FIELDS 855 ;; BIT FIELDS
692 ;; ----------------------------------------------------------------- 856 ;; -----------------------------------------------------------------
693 857
694 ;; ??? Is it worth defining insv and extv for the V850 series?!? 858 ;; ??? Is it worth defining insv and extv for the V850 series?!?
722 return \"setf %c1,%0\"; 886 return \"setf %c1,%0\";
723 }" 887 }"
724 [(set_attr "length" "4") 888 [(set_attr "length" "4")
725 (set_attr "cc" "none_0hit")]) 889 (set_attr "cc" "none_0hit")])
726 890
891 (define_insn "setf_insn"
892 [(set (match_operand:SI 0 "register_operand" "=r")
893 (match_operator:SI 1 "comparison_operator"
894 [(reg:CC CC_REGNUM) (const_int 0)]))]
895 ""
896 "setf %b1,%0"
897 [(set_attr "length" "4")
898 (set_attr "cc" "none_0hit")])
899
900 (define_insn "set_z_insn"
901 [(set (match_operand:SI 0 "register_operand" "=r")
902 (match_operand 1 "v850_float_z_comparison_operator" ""))]
903 "TARGET_V850E2V3"
904 "setf z,%0"
905 [(set_attr "length" "4")
906 (set_attr "cc" "none_0hit")])
907
908 (define_insn "set_nz_insn"
909 [(set (match_operand:SI 0 "register_operand" "=r")
910 (match_operand 1 "v850_float_nz_comparison_operator" ""))]
911 "TARGET_V850E2V3"
912 "setf nz,%0"
913 [(set_attr "length" "4")
914 (set_attr "cc" "none_0hit")])
915
727 ;; ---------------------------------------------------------------------- 916 ;; ----------------------------------------------------------------------
728 ;; CONDITIONAL MOVE INSTRUCTIONS 917 ;; CONDITIONAL MOVE INSTRUCTIONS
729 ;; ---------------------------------------------------------------------- 918 ;; ----------------------------------------------------------------------
730 919
731 ;; Instructions using cc0 aren't allowed to have input reloads, so we must 920 ;; Instructions using cc0 aren't allowed to have input reloads, so we must
736 [(set (match_operand:SI 0 "register_operand" "=r") 925 [(set (match_operand:SI 0 "register_operand" "=r")
737 (if_then_else:SI 926 (if_then_else:SI
738 (match_operand 1 "comparison_operator") 927 (match_operand 1 "comparison_operator")
739 (match_operand:SI 2 "reg_or_const_operand" "rJ") 928 (match_operand:SI 2 "reg_or_const_operand" "rJ")
740 (match_operand:SI 3 "reg_or_const_operand" "rI")))] 929 (match_operand:SI 3 "reg_or_const_operand" "rI")))]
741 "TARGET_V850E" 930 "(TARGET_V850E || TARGET_V850E2_ALL)"
742 " 931 "
743 { 932 {
744 if ( (GET_CODE (operands[2]) == CONST_INT 933 if ( (GET_CODE (operands[2]) == CONST_INT
745 && GET_CODE (operands[3]) == CONST_INT)) 934 && GET_CODE (operands[3]) == CONST_INT))
746 { 935 {
773 962
774 ;; ??? We sometimes emit an unnecessary compare instruction because the 963 ;; ??? We sometimes emit an unnecessary compare instruction because the
775 ;; condition codes may have already been set by an earlier instruction, 964 ;; condition codes may have already been set by an earlier instruction,
776 ;; but we have no code here to avoid the compare if it is unnecessary. 965 ;; but we have no code here to avoid the compare if it is unnecessary.
777 966
967 (define_insn "movsicc_normal_cc"
968 [(set (match_operand:SI 0 "register_operand" "=r")
969 (if_then_else:SI
970 (match_operator 1 "comparison_operator"
971 [(reg:CC CC_REGNUM) (const_int 0)])
972 (match_operand:SI 2 "reg_or_int5_operand" "rJ")
973 (match_operand:SI 3 "reg_or_0_operand" "rI")))]
974 "(TARGET_V850E || TARGET_V850E2_ALL)"
975 "cmov %c1,%2,%z3,%0";
976 [(set_attr "length" "6")
977 (set_attr "cc" "compare")])
978
979 (define_insn "movsicc_reversed_cc"
980 [(set (match_operand:SI 0 "register_operand" "=r")
981 (if_then_else:SI
982 (match_operator 1 "comparison_operator"
983 [(reg:CC CC_REGNUM) (const_int 0)])
984 (match_operand:SI 2 "reg_or_0_operand" "rI")
985 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))]
986 "(TARGET_V850E || TARGET_V850E2_ALL)"
987 "cmov %C1,%3,%z2,%0"
988 [(set_attr "length" "6")
989 (set_attr "cc" "compare")])
990
778 (define_insn "*movsicc_normal" 991 (define_insn "*movsicc_normal"
779 [(set (match_operand:SI 0 "register_operand" "=r") 992 [(set (match_operand:SI 0 "register_operand" "=r")
780 (if_then_else:SI 993 (if_then_else:SI
781 (match_operator 1 "comparison_operator" 994 (match_operator 1 "comparison_operator"
782 [(match_operand:SI 4 "register_operand" "r") 995 [(match_operand:SI 4 "register_operand" "r")
783 (match_operand:SI 5 "reg_or_int5_operand" "rJ")]) 996 (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
784 (match_operand:SI 2 "reg_or_int5_operand" "rJ") 997 (match_operand:SI 2 "reg_or_int5_operand" "rJ")
785 (match_operand:SI 3 "reg_or_0_operand" "rI")))] 998 (match_operand:SI 3 "reg_or_0_operand" "rI")))]
786 "TARGET_V850E" 999 "(TARGET_V850E || TARGET_V850E2_ALL)"
787 "cmp %5,%4 ; cmov %c1,%2,%z3,%0" 1000 "cmp %5,%4 ; cmov %c1,%2,%z3,%0"
788 [(set_attr "length" "6") 1001 [(set_attr "length" "6")
789 (set_attr "cc" "clobber")]) 1002 (set_attr "cc" "clobber")])
790 1003
791 (define_insn "*movsicc_reversed" 1004 (define_insn "*movsicc_reversed"
794 (match_operator 1 "comparison_operator" 1007 (match_operator 1 "comparison_operator"
795 [(match_operand:SI 4 "register_operand" "r") 1008 [(match_operand:SI 4 "register_operand" "r")
796 (match_operand:SI 5 "reg_or_int5_operand" "rJ")]) 1009 (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
797 (match_operand:SI 2 "reg_or_0_operand" "rI") 1010 (match_operand:SI 2 "reg_or_0_operand" "rI")
798 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))] 1011 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))]
799 "TARGET_V850E" 1012 "(TARGET_V850E || TARGET_V850E2_ALL)"
800 "cmp %5,%4 ; cmov %C1,%3,%z2,%0" 1013 "cmp %5,%4 ; cmov %C1,%3,%z2,%0"
801 [(set_attr "length" "6") 1014 [(set_attr "length" "6")
802 (set_attr "cc" "clobber")]) 1015 (set_attr "cc" "clobber")])
803 1016
804 (define_insn "*movsicc_tst1" 1017 (define_insn "*movsicc_tst1"
810 (const_int 1) 1023 (const_int 1)
811 (match_operand 3 "const_int_operand" "n")) 1024 (match_operand 3 "const_int_operand" "n"))
812 (const_int 0)]) 1025 (const_int 0)])
813 (match_operand:SI 4 "reg_or_int5_operand" "rJ") 1026 (match_operand:SI 4 "reg_or_int5_operand" "rJ")
814 (match_operand:SI 5 "reg_or_0_operand" "rI")))] 1027 (match_operand:SI 5 "reg_or_0_operand" "rI")))]
815 "TARGET_V850E" 1028 "(TARGET_V850E || TARGET_V850E2_ALL)"
816 "tst1 %3,%2 ; cmov %c1,%4,%z5,%0" 1029 "tst1 %3,%2 ; cmov %c1,%4,%z5,%0"
817 [(set_attr "length" "8") 1030 [(set_attr "length" "8")
818 (set_attr "cc" "clobber")]) 1031 (set_attr "cc" "clobber")])
819 1032
820 (define_insn "*movsicc_tst1_reversed" 1033 (define_insn "*movsicc_tst1_reversed"
826 (const_int 1) 1039 (const_int 1)
827 (match_operand 3 "const_int_operand" "n")) 1040 (match_operand 3 "const_int_operand" "n"))
828 (const_int 0)]) 1041 (const_int 0)])
829 (match_operand:SI 4 "reg_or_0_operand" "rI") 1042 (match_operand:SI 4 "reg_or_0_operand" "rI")
830 (match_operand:SI 5 "reg_or_int5_operand" "rJ")))] 1043 (match_operand:SI 5 "reg_or_int5_operand" "rJ")))]
831 "TARGET_V850E" 1044 "(TARGET_V850E || TARGET_V850E2_ALL)"
832 "tst1 %3,%2 ; cmov %C1,%5,%z4,%0" 1045 "tst1 %3,%2 ; cmov %C1,%5,%z4,%0"
833 [(set_attr "length" "8") 1046 [(set_attr "length" "8")
834 (set_attr "cc" "clobber")]) 1047 (set_attr "cc" "clobber")])
835 1048
836 ;; Matching for sasf requires combining 4 instructions, so we provide a 1049 ;; Matching for sasf requires combining 4 instructions, so we provide a
837 ;; dummy pattern to match the first 3, which will always be turned into the 1050 ;; dummy pattern to match the first 3, which will always be turned into the
838 ;; second pattern by subsequent combining. As above, we must include the 1051 ;; second pattern by subsequent combining. As above, we must include the
839 ;; comparison to avoid input reloads in an insn using cc0. 1052 ;; comparison to avoid input reloads in an insn using cc0.
840 1053
841 (define_insn "*sasf_1" 1054 (define_insn "*sasf"
842 [(set (match_operand:SI 0 "register_operand" "")
843 (ior:SI (match_operator 1 "comparison_operator" [(cc0) (const_int 0)])
844 (ashift:SI (match_operand:SI 2 "register_operand" "")
845 (const_int 1))))]
846 "TARGET_V850E"
847 "* gcc_unreachable ();")
848
849 (define_insn "*sasf_2"
850 [(set (match_operand:SI 0 "register_operand" "=r") 1055 [(set (match_operand:SI 0 "register_operand" "=r")
851 (ior:SI 1056 (ior:SI
852 (match_operator 1 "comparison_operator" 1057 (match_operator 1 "comparison_operator"
853 [(match_operand:SI 3 "register_operand" "r") 1058 [(match_operand:SI 3 "register_operand" "r")
854 (match_operand:SI 4 "reg_or_int5_operand" "rJ")]) 1059 (match_operand:SI 4 "reg_or_int5_operand" "rJ")])
855 (ashift:SI (match_operand:SI 2 "register_operand" "0") 1060 (ashift:SI (match_operand:SI 2 "register_operand" "0")
856 (const_int 1))))] 1061 (const_int 1))))
857 "TARGET_V850E" 1062 (clobber (reg:CC CC_REGNUM))]
1063 "(TARGET_V850E || TARGET_V850E2_ALL)"
858 "cmp %4,%3 ; sasf %c1,%0" 1064 "cmp %4,%3 ; sasf %c1,%0"
859 [(set_attr "length" "6") 1065 [(set_attr "length" "6")
860 (set_attr "cc" "clobber")]) 1066 (set_attr "cc" "clobber")])
861 1067
862 (define_split 1068 (define_split
864 (if_then_else:SI 1070 (if_then_else:SI
865 (match_operator 1 "comparison_operator" 1071 (match_operator 1 "comparison_operator"
866 [(match_operand:SI 4 "register_operand" "") 1072 [(match_operand:SI 4 "register_operand" "")
867 (match_operand:SI 5 "reg_or_int5_operand" "")]) 1073 (match_operand:SI 5 "reg_or_int5_operand" "")])
868 (match_operand:SI 2 "const_int_operand" "") 1074 (match_operand:SI 2 "const_int_operand" "")
869 (match_operand:SI 3 "const_int_operand" "")))] 1075 (match_operand:SI 3 "const_int_operand" "")))
870 "TARGET_V850E 1076 (clobber (reg:CC CC_REGNUM))]
1077 "(TARGET_V850E || TARGET_V850E2_ALL)
871 && ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1) 1078 && ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1)
872 && ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1) 1079 && ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1)
873 && (GET_CODE (operands[5]) == CONST_INT 1080 && (GET_CODE (operands[5]) == CONST_INT
874 || REGNO (operands[0]) != REGNO (operands[5])) 1081 || REGNO (operands[0]) != REGNO (operands[5]))
875 && REGNO (operands[0]) != REGNO (operands[4])" 1082 && REGNO (operands[0]) != REGNO (operands[4])"
876 [(set (match_dup 0) (match_dup 6)) 1083 [(set (match_dup 0) (match_dup 6))
877 (set (match_dup 0) 1084 (parallel [(set (match_dup 0)
878 (ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)]) 1085 (ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)])
879 (ashift:SI (match_dup 0) (const_int 1))))] 1086 (ashift:SI (match_dup 0) (const_int 1))))
1087 (clobber (reg:CC CC_REGNUM))])]
880 " 1088 "
881 { 1089 {
882 operands[6] = GEN_INT (INTVAL (operands[2]) >> 1); 1090 operands[6] = GEN_INT (INTVAL (operands[2]) >> 1);
883 if (INTVAL (operands[2]) & 0x1) 1091 if (INTVAL (operands[2]) & 0x1)
884 operands[7] = operands[1]; 1092 operands[7] = operands[1];
885 else 1093 else
886 operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), 1094 operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])),
887 GET_MODE (operands[1]), 1095 GET_MODE (operands[1]),
888 XEXP (operands[1], 0), XEXP (operands[1], 1)); 1096 XEXP (operands[1], 0), XEXP (operands[1], 1));
889 }") 1097 }")
1098
890 ;; --------------------------------------------------------------------- 1099 ;; ---------------------------------------------------------------------
891 ;; BYTE SWAP INSTRUCTIONS 1100 ;; BYTE SWAP INSTRUCTIONS
892 ;; --------------------------------------------------------------------- 1101 ;; ---------------------------------------------------------------------
893
894 (define_expand "rotlhi3" 1102 (define_expand "rotlhi3"
895 [(set (match_operand:HI 0 "register_operand" "") 1103 [(parallel [(set (match_operand:HI 0 "register_operand" "")
896 (rotate:HI (match_operand:HI 1 "register_operand" "") 1104 (rotate:HI (match_operand:HI 1 "register_operand" "")
897 (match_operand:HI 2 "const_int_operand" "")))] 1105 (match_operand:HI 2 "const_int_operand" "")))
898 "TARGET_V850E" 1106 (clobber (reg:CC CC_REGNUM))])]
1107 "(TARGET_V850E || TARGET_V850E2_ALL)"
899 " 1108 "
900 { 1109 {
901 if (INTVAL (operands[2]) != 8) 1110 if (INTVAL (operands[2]) != 8)
902 FAIL; 1111 FAIL;
903 }") 1112 }")
904 1113
905 (define_insn "*rotlhi3_8" 1114 (define_insn "*rotlhi3_8"
906 [(set (match_operand:HI 0 "register_operand" "=r") 1115 [(set (match_operand:HI 0 "register_operand" "=r")
907 (rotate:HI (match_operand:HI 1 "register_operand" "r") 1116 (rotate:HI (match_operand:HI 1 "register_operand" "r")
908 (const_int 8)))] 1117 (const_int 8)))
909 "TARGET_V850E" 1118 (clobber (reg:CC CC_REGNUM))]
1119 "(TARGET_V850E || TARGET_V850E2_ALL)"
910 "bsh %1,%0" 1120 "bsh %1,%0"
911 [(set_attr "length" "4") 1121 [(set_attr "length" "4")
912 (set_attr "cc" "clobber")]) 1122 (set_attr "cc" "clobber")])
913 1123
914 (define_expand "rotlsi3" 1124 (define_expand "rotlsi3"
915 [(set (match_operand:SI 0 "register_operand" "") 1125 [(parallel [(set (match_operand:SI 0 "register_operand" "")
916 (rotate:SI (match_operand:SI 1 "register_operand" "") 1126 (rotate:SI (match_operand:SI 1 "register_operand" "")
917 (match_operand:SI 2 "const_int_operand" "")))] 1127 (match_operand:SI 2 "const_int_operand" "")))
918 "TARGET_V850E" 1128 (clobber (reg:CC CC_REGNUM))])]
1129 "(TARGET_V850E || TARGET_V850E2_ALL)"
919 " 1130 "
920 { 1131 {
921 if (INTVAL (operands[2]) != 16) 1132 if (INTVAL (operands[2]) != 16)
922 FAIL; 1133 FAIL;
923 }") 1134 }")
924 1135
925 (define_insn "*rotlsi3_16" 1136 (define_insn "*rotlsi3_16"
926 [(set (match_operand:SI 0 "register_operand" "=r") 1137 [(set (match_operand:SI 0 "register_operand" "=r")
927 (rotate:SI (match_operand:SI 1 "register_operand" "r") 1138 (rotate:SI (match_operand:SI 1 "register_operand" "r")
928 (const_int 16)))] 1139 (const_int 16)))
929 "TARGET_V850E" 1140 (clobber (reg:CC CC_REGNUM))]
1141 "(TARGET_V850E || TARGET_V850E2_ALL)"
930 "hsw %1,%0" 1142 "hsw %1,%0"
931 [(set_attr "length" "4") 1143 [(set_attr "length" "4")
932 (set_attr "cc" "clobber")]) 1144 (set_attr "cc" "clobber")])
933 1145
934 ;; ---------------------------------------------------------------------- 1146 ;; ----------------------------------------------------------------------
935 ;; JUMP INSTRUCTIONS 1147 ;; JUMP INSTRUCTIONS
936 ;; ---------------------------------------------------------------------- 1148 ;; ----------------------------------------------------------------------
937 1149
938 ;; Conditional jump instructions 1150 ;; Conditional jump instructions
990 (const_int 256)) 1202 (const_int 256))
991 (const_int 2) 1203 (const_int 2)
992 (const_int 6))) 1204 (const_int 6)))
993 (set_attr "cc" "none")]) 1205 (set_attr "cc" "none")])
994 1206
1207 (define_insn "branch_z_normal"
1208 [(set (pc)
1209 (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "")
1210 (label_ref (match_operand 0 "" ""))
1211 (pc)))]
1212 "TARGET_V850E2V3"
1213 "*
1214 {
1215 if (get_attr_length (insn) == 2)
1216 return \"bz %l0\";
1217 else
1218 return \"bnz 1f ; jr %l0 ; 1:\";
1219 }"
1220 [(set (attr "length")
1221 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1222 (const_int 256))
1223 (const_int 2)
1224 (const_int 6)))
1225 (set_attr "cc" "none")])
1226
1227 (define_insn "*branch_z_invert"
1228 [(set (pc)
1229 (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "")
1230 (pc)
1231 (label_ref (match_operand 0 "" ""))))]
1232 "TARGET_V850E2V3"
1233 "*
1234 {
1235 if (get_attr_length (insn) == 2)
1236 return \"bnz %l0\";
1237 else
1238 return \"bz 1f ; jr %l0 ; 1:\";
1239 }"
1240 [(set (attr "length")
1241 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1242 (const_int 256))
1243 (const_int 2)
1244 (const_int 6)))
1245 (set_attr "cc" "none")])
1246
1247 (define_insn "branch_nz_normal"
1248 [(set (pc)
1249 (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "")
1250 (label_ref (match_operand 0 "" ""))
1251 (pc)))]
1252 "TARGET_V850E2V3"
1253 "*
1254 {
1255 if (get_attr_length (insn) == 2)
1256 return \"bnz %l0\";
1257 else
1258 return \"bz 1f ; jr %l0 ; 1:\";
1259 }"
1260 [(set (attr "length")
1261 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1262 (const_int 256))
1263 (const_int 2)
1264 (const_int 6)))
1265 (set_attr "cc" "none")])
1266
1267 (define_insn "*branch_nz_invert"
1268 [(set (pc)
1269 (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "")
1270 (pc)
1271 (label_ref (match_operand 0 "" ""))))]
1272 "TARGET_V850E2V3"
1273 "*
1274 {
1275 if (get_attr_length (insn) == 2)
1276 return \"bz %l0\";
1277 else
1278 return \"bnz 1f ; jr %l0 ; 1:\";
1279 }"
1280 [(set (attr "length")
1281 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1282 (const_int 256))
1283 (const_int 2)
1284 (const_int 6)))
1285 (set_attr "cc" "none")])
1286
995 ;; Unconditional and other jump instructions. 1287 ;; Unconditional and other jump instructions.
996 1288
997 (define_insn "jump" 1289 (define_insn "jump"
998 [(set (pc) 1290 [(set (pc)
999 (label_ref (match_operand 0 "" "")))] 1291 (label_ref (match_operand 0 "" "")))]
1000 "" 1292 ""
1001 "* 1293 "*
1002 { 1294 {
1003 if (get_attr_length (insn) == 2) 1295 if (get_attr_length (insn) == 2)
1004 return \"br %0\"; 1296 return \"br %0\";
1005 else 1297 else
1006 return \"jr %0\"; 1298 return \"jr %0\";
1007 }" 1299 }"
1008 [(set (attr "length") 1300 [(set (attr "length")
1029 1321
1030 (define_insn "switch" 1322 (define_insn "switch"
1031 [(set (pc) 1323 [(set (pc)
1032 (plus:SI 1324 (plus:SI
1033 (sign_extend:SI 1325 (sign_extend:SI
1034 (mem:HI 1326 (mem:HI
1035 (plus:SI (ashift:SI (match_operand:SI 0 "register_operand" "r") 1327 (plus:SI (ashift:SI (match_operand:SI 0 "register_operand" "r")
1036 (const_int 1)) 1328 (const_int 1))
1037 (label_ref (match_operand 1 "" ""))))) 1329 (label_ref (match_operand 1 "" "")))))
1038 (label_ref (match_dup 1))))] 1330 (label_ref (match_dup 1))))]
1039 "TARGET_V850E" 1331 "(TARGET_V850E || TARGET_V850E2_ALL)"
1040 "switch %0" 1332 "switch %0"
1041 [(set_attr "length" "2") 1333 [(set_attr "length" "2")
1042 (set_attr "cc" "none")]) 1334 (set_attr "cc" "none")])
1043 1335
1044 (define_expand "casesi" 1336 (define_expand "casesi"
1111 (clobber (reg:SI 31))] 1403 (clobber (reg:SI 31))]
1112 "! TARGET_LONG_CALLS" 1404 "! TARGET_LONG_CALLS"
1113 "@ 1405 "@
1114 jarl %0,r31 1406 jarl %0,r31
1115 jarl .+4,r31 ; add 4,r31 ; jmp %0" 1407 jarl .+4,r31 ; add 4,r31 ; jmp %0"
1116 [(set_attr "length" "4,8")] 1408 [(set_attr "length" "4,8")
1409 (set_attr "cc" "clobber,clobber")]
1117 ) 1410 )
1118 1411
1119 (define_insn "call_internal_long" 1412 (define_insn "call_internal_long"
1120 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r")) 1413 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
1121 (match_operand:SI 1 "general_operand" "g,g")) 1414 (match_operand:SI 1 "general_operand" "g,g"))
1131 return \"movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11\"; 1424 return \"movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11\";
1132 } 1425 }
1133 else 1426 else
1134 return \"jarl .+4,r31 ; add 4,r31 ; jmp %0\"; 1427 return \"jarl .+4,r31 ; add 4,r31 ; jmp %0\";
1135 }" 1428 }"
1136 [(set_attr "length" "16,8")] 1429 [(set_attr "length" "16,8")
1430 (set_attr "cc" "clobber,clobber")]
1137 ) 1431 )
1138 1432
1139 ;; Call subroutine, returning value in operand 0 1433 ;; Call subroutine, returning value in operand 0
1140 ;; (which must be a hard register). 1434 ;; (which must be a hard register).
1141 1435
1167 (clobber (reg:SI 31))] 1461 (clobber (reg:SI 31))]
1168 "! TARGET_LONG_CALLS" 1462 "! TARGET_LONG_CALLS"
1169 "@ 1463 "@
1170 jarl %1,r31 1464 jarl %1,r31
1171 jarl .+4,r31 ; add 4,r31 ; jmp %1" 1465 jarl .+4,r31 ; add 4,r31 ; jmp %1"
1172 [(set_attr "length" "4,8")] 1466 [(set_attr "length" "4,8")
1467 (set_attr "cc" "clobber,clobber")]
1173 ) 1468 )
1174 1469
1175 (define_insn "call_value_internal_long" 1470 (define_insn "call_value_internal_long"
1176 [(set (match_operand 0 "" "=r,r") 1471 [(set (match_operand 0 "" "=r,r")
1177 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r")) 1472 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1189 return \"movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11\"; 1484 return \"movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11\";
1190 } 1485 }
1191 else 1486 else
1192 return \"jarl .+4, r31 ; add 4, r31 ; jmp %1\"; 1487 return \"jarl .+4, r31 ; add 4, r31 ; jmp %1\";
1193 }" 1488 }"
1194 [(set_attr "length" "16,8")] 1489 [(set_attr "length" "16,8")
1490 (set_attr "cc" "clobber,clobber")]
1195 ) 1491 )
1196 1492
1197 (define_insn "nop" 1493 (define_insn "nop"
1198 [(const_int 0)] 1494 [(const_int 0)]
1199 "" 1495 ""
1206 ;; ---------------------------------------------------------------------- 1502 ;; ----------------------------------------------------------------------
1207 1503
1208 (define_insn "" 1504 (define_insn ""
1209 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 1505 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1210 (zero_extend:SI 1506 (zero_extend:SI
1211 (match_operand:HI 1 "nonimmediate_operand" "0,r,T,m")))] 1507 (match_operand:HI 1 "nonimmediate_operand" "0,r,T,m")))
1212 "TARGET_V850E" 1508 (clobber (reg:CC CC_REGNUM))]
1509 "(TARGET_V850E || TARGET_V850E2_ALL)"
1213 "@ 1510 "@
1214 zxh %0 1511 zxh %0
1215 andi 65535,%1,%0 1512 andi 65535,%1,%0
1216 sld.hu %1,%0 1513 sld.hu %1,%0
1217 ld.hu %1,%0" 1514 ld.hu %1,%0"
1218 [(set_attr "length" "2,4,2,4") 1515 [(set_attr "length" "2,4,2,4")
1219 (set_attr "cc" "none_0hit,set_znv,none_0hit,none_0hit")]) 1516 (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")])
1220 1517
1221 (define_insn "zero_extendhisi2" 1518 (define_insn "zero_extendhisi2"
1222 [(set (match_operand:SI 0 "register_operand" "=r") 1519 [(set (match_operand:SI 0 "register_operand" "=r")
1223 (zero_extend:SI 1520 (zero_extend:SI
1224 (match_operand:HI 1 "register_operand" "r")))] 1521 (match_operand:HI 1 "register_operand" "r")))
1522 (clobber (reg:CC CC_REGNUM))]
1225 "" 1523 ""
1226 "andi 65535,%1,%0" 1524 "andi 65535,%1,%0"
1227 [(set_attr "length" "4") 1525 [(set_attr "length" "4")
1228 (set_attr "cc" "set_znv")]) 1526 (set_attr "cc" "set_zn")])
1229 1527
1230 (define_insn "" 1528 (define_insn ""
1231 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 1529 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1232 (zero_extend:SI 1530 (zero_extend:SI
1233 (match_operand:QI 1 "nonimmediate_operand" "0,r,T,m")))] 1531 (match_operand:QI 1 "nonimmediate_operand" "0,r,T,m")))
1234 "TARGET_V850E" 1532 (clobber (reg:CC CC_REGNUM))]
1533 "(TARGET_V850E || TARGET_V850E2_ALL)"
1235 "@ 1534 "@
1236 zxb %0 1535 zxb %0
1237 andi 255,%1,%0 1536 andi 255,%1,%0
1238 sld.bu %1,%0 1537 sld.bu %1,%0
1239 ld.bu %1,%0" 1538 ld.bu %1,%0"
1240 [(set_attr "length" "2,4,2,4") 1539 [(set_attr "length" "2,4,2,4")
1241 (set_attr "cc" "none_0hit,set_znv,none_0hit,none_0hit")]) 1540 (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")])
1242 1541
1243 (define_insn "zero_extendqisi2" 1542 (define_insn "zero_extendqisi2"
1244 [(set (match_operand:SI 0 "register_operand" "=r") 1543 [(set (match_operand:SI 0 "register_operand" "=r")
1245 (zero_extend:SI 1544 (zero_extend:SI
1246 (match_operand:QI 1 "register_operand" "r")))] 1545 (match_operand:QI 1 "register_operand" "r")))
1546 (clobber (reg:CC CC_REGNUM))]
1247 "" 1547 ""
1248 "andi 255,%1,%0" 1548 "andi 255,%1,%0"
1249 [(set_attr "length" "4") 1549 [(set_attr "length" "4")
1250 (set_attr "cc" "set_znv")]) 1550 (set_attr "cc" "set_zn")])
1251 1551
1252 ;;- sign extension instructions 1552 ;;- sign extension instructions
1253 1553
1254 ;; ??? The extendhisi2 pattern should not emit shifts for v850e? 1554 ;; ??? The extendhisi2 pattern should not emit shifts for v850e?
1255 1555
1256 (define_insn "*extendhisi_insn" 1556 (define_insn "*extendhisi_insn"
1257 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1557 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1258 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m")))] 1558 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m")))
1259 "TARGET_V850E" 1559 (clobber (reg:CC CC_REGNUM))]
1560 "(TARGET_V850E || TARGET_V850E2_ALL)"
1260 "@ 1561 "@
1261 sxh %0 1562 sxh %0
1262 sld.h %1,%0 1563 sld.h %1,%0
1263 ld.h %1,%0" 1564 ld.h %1,%0"
1264 [(set_attr "length" "2,2,4") 1565 [(set_attr "length" "2,2,4")
1266 1567
1267 ;; ??? This is missing a sign extend from memory pattern to match the ld.h 1568 ;; ??? This is missing a sign extend from memory pattern to match the ld.h
1268 ;; instruction. 1569 ;; instruction.
1269 1570
1270 (define_expand "extendhisi2" 1571 (define_expand "extendhisi2"
1271 [(set (match_dup 2) 1572 [(parallel [(set (match_dup 2)
1272 (ashift:SI (match_operand:HI 1 "register_operand" "") 1573 (ashift:SI (match_operand:HI 1 "register_operand" "")
1273 (const_int 16))) 1574 (const_int 16)))
1274 (set (match_operand:SI 0 "register_operand" "") 1575 (clobber (reg:CC CC_REGNUM))])
1275 (ashiftrt:SI (match_dup 2) 1576 (parallel [(set (match_operand:SI 0 "register_operand" "")
1276 (const_int 16)))] 1577 (ashiftrt:SI (match_dup 2)
1578 (const_int 16)))
1579 (clobber (reg:CC CC_REGNUM))])]
1277 "" 1580 ""
1278 " 1581 "
1279 { 1582 {
1280 operands[1] = gen_lowpart (SImode, operands[1]); 1583 operands[1] = gen_lowpart (SImode, operands[1]);
1281 operands[2] = gen_reg_rtx (SImode); 1584 operands[2] = gen_reg_rtx (SImode);
1283 1586
1284 ;; ??? The extendqisi2 pattern should not emit shifts for v850e? 1587 ;; ??? The extendqisi2 pattern should not emit shifts for v850e?
1285 1588
1286 (define_insn "*extendqisi_insn" 1589 (define_insn "*extendqisi_insn"
1287 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1590 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1288 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m")))] 1591 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m")))
1289 "TARGET_V850E" 1592 (clobber (reg:CC CC_REGNUM))]
1593 "(TARGET_V850E || TARGET_V850E2_ALL)"
1290 "@ 1594 "@
1291 sxb %0 1595 sxb %0
1292 sld.b %1,%0 1596 sld.b %1,%0
1293 ld.b %1,%0" 1597 ld.b %1,%0"
1294 [(set_attr "length" "2,2,4") 1598 [(set_attr "length" "2,2,4")
1296 1600
1297 ;; ??? This is missing a sign extend from memory pattern to match the ld.b 1601 ;; ??? This is missing a sign extend from memory pattern to match the ld.b
1298 ;; instruction. 1602 ;; instruction.
1299 1603
1300 (define_expand "extendqisi2" 1604 (define_expand "extendqisi2"
1301 [(set (match_dup 2) 1605 [(parallel [(set (match_dup 2)
1302 (ashift:SI (match_operand:QI 1 "register_operand" "") 1606 (ashift:SI (match_operand:QI 1 "register_operand" "")
1303 (const_int 24))) 1607 (const_int 24)))
1304 (set (match_operand:SI 0 "register_operand" "") 1608 (clobber (reg:CC CC_REGNUM))])
1305 (ashiftrt:SI (match_dup 2) 1609 (parallel [(set (match_operand:SI 0 "register_operand" "")
1306 (const_int 24)))] 1610 (ashiftrt:SI (match_dup 2)
1611 (const_int 24)))
1612 (clobber (reg:CC CC_REGNUM))])]
1307 "" 1613 ""
1308 " 1614 "
1309 { 1615 {
1310 operands[1] = gen_lowpart (SImode, operands[1]); 1616 operands[1] = gen_lowpart (SImode, operands[1]);
1311 operands[2] = gen_reg_rtx (SImode); 1617 operands[2] = gen_reg_rtx (SImode);
1315 ;; SHIFTS 1621 ;; SHIFTS
1316 ;; ---------------------------------------------------------------------- 1622 ;; ----------------------------------------------------------------------
1317 1623
1318 (define_insn "ashlsi3" 1624 (define_insn "ashlsi3"
1319 [(set (match_operand:SI 0 "register_operand" "=r,r") 1625 [(set (match_operand:SI 0 "register_operand" "=r,r")
1320 (ashift:SI 1626 (ashift:SI
1321 (match_operand:SI 1 "register_operand" "0,0") 1627 (match_operand:SI 1 "register_operand" "0,0")
1322 (match_operand:SI 2 "nonmemory_operand" "r,N")))] 1628 (match_operand:SI 2 "nonmemory_operand" "r,N")))
1629 (clobber (reg:CC CC_REGNUM))]
1323 "" 1630 ""
1324 "@ 1631 "@
1325 shl %2,%0 1632 shl %2,%0
1326 shl %2,%0" 1633 shl %2,%0"
1327 [(set_attr "length" "4,2") 1634 [(set_attr "length" "4,2")
1635 (set_attr "cc" "set_zn")])
1636
1637 (define_insn "ashlsi3_v850e2"
1638 [(set (match_operand:SI 0 "register_operand" "=r")
1639 (ashift:SI
1640 (match_operand:SI 1 "register_operand" "r")
1641 (match_operand:SI 2 "nonmemory_operand" "r")))
1642 (clobber (reg:CC CC_REGNUM))]
1643 "TARGET_V850E2_ALL"
1644 "shl %2,%1,%0"
1645 [(set_attr "length" "4")
1328 (set_attr "cc" "set_znv")]) 1646 (set_attr "cc" "set_znv")])
1329 1647
1330 (define_insn "lshrsi3" 1648 (define_insn "lshrsi3"
1331 [(set (match_operand:SI 0 "register_operand" "=r,r") 1649 [(set (match_operand:SI 0 "register_operand" "=r,r")
1332 (lshiftrt:SI 1650 (lshiftrt:SI
1333 (match_operand:SI 1 "register_operand" "0,0") 1651 (match_operand:SI 1 "register_operand" "0,0")
1334 (match_operand:SI 2 "nonmemory_operand" "r,N")))] 1652 (match_operand:SI 2 "nonmemory_operand" "r,N")))
1653 (clobber (reg:CC CC_REGNUM))]
1335 "" 1654 ""
1336 "@ 1655 "@
1337 shr %2,%0 1656 shr %2,%0
1338 shr %2,%0" 1657 shr %2,%0"
1339 [(set_attr "length" "4,2") 1658 [(set_attr "length" "4,2")
1340 (set_attr "cc" "set_znv")]) 1659 (set_attr "cc" "set_zn")])
1660
1661 (define_insn "lshrsi3_v850e2"
1662 [(set (match_operand:SI 0 "register_operand" "=r")
1663 (lshiftrt:SI
1664 (match_operand:SI 1 "register_operand" "r")
1665 (match_operand:SI 2 "nonmemory_operand" "r")))
1666 (clobber (reg:CC CC_REGNUM))]
1667 "TARGET_V850E2_ALL"
1668 "shr %2,%1,%0"
1669 [(set_attr "length" "4")
1670 (set_attr "cc" "set_zn")])
1341 1671
1342 (define_insn "ashrsi3" 1672 (define_insn "ashrsi3"
1343 [(set (match_operand:SI 0 "register_operand" "=r,r") 1673 [(set (match_operand:SI 0 "register_operand" "=r,r")
1344 (ashiftrt:SI 1674 (ashiftrt:SI
1345 (match_operand:SI 1 "register_operand" "0,0") 1675 (match_operand:SI 1 "register_operand" "0,0")
1346 (match_operand:SI 2 "nonmemory_operand" "r,N")))] 1676 (match_operand:SI 2 "nonmemory_operand" "r,N")))
1677 (clobber (reg:CC CC_REGNUM))]
1347 "" 1678 ""
1348 "@ 1679 "@
1349 sar %2,%0 1680 sar %2,%0
1350 sar %2,%0" 1681 sar %2,%0"
1351 [(set_attr "length" "4,2") 1682 [(set_attr "length" "4,2")
1352 (set_attr "cc" "set_znv")]) 1683 (set_attr "cc" "set_zn, set_zn")])
1684
1685 (define_insn "ashrsi3_v850e2"
1686 [(set (match_operand:SI 0 "register_operand" "=r")
1687 (ashiftrt:SI
1688 (match_operand:SI 1 "register_operand" "r")
1689 (match_operand:SI 2 "nonmemory_operand" "r")))
1690 (clobber (reg:CC CC_REGNUM))]
1691 "TARGET_V850E2_ALL"
1692 "sar %2,%1,%0"
1693 [(set_attr "length" "4")
1694 (set_attr "cc" "set_zn")])
1695
1696 ;; ----------------------------------------------------------------------
1697 ;; FIND FIRST BIT INSTRUCTION
1698 ;; ----------------------------------------------------------------------
1699
1700 (define_insn "ffssi2"
1701 [(set (match_operand:SI 0 "register_operand" "=r")
1702 (ffs:SI (match_operand:SI 1 "register_operand" "r")))
1703 (clobber (reg:CC CC_REGNUM))]
1704 "TARGET_V850E2_ALL"
1705 "sch1r %1,%0"
1706 [(set_attr "length" "4")
1707 (set_attr "cc" "clobber")])
1353 1708
1354 ;; ---------------------------------------------------------------------- 1709 ;; ----------------------------------------------------------------------
1355 ;; PROLOGUE/EPILOGUE 1710 ;; PROLOGUE/EPILOGUE
1356 ;; ---------------------------------------------------------------------- 1711 ;; ----------------------------------------------------------------------
1357 (define_expand "prologue" 1712 (define_expand "prologue"
1381 "" 1736 ""
1382 "jmp [r31]" 1737 "jmp [r31]"
1383 [(set_attr "length" "2") 1738 [(set_attr "length" "2")
1384 (set_attr "cc" "none")]) 1739 (set_attr "cc" "none")])
1385 1740
1386 1741 ;; ----------------------------------------------------------------------
1387 1742 ;; v850e2V3 floating-point hardware support
1743 ;; ----------------------------------------------------------------------
1744
1745
1746 (define_insn "addsf3"
1747 [(set (match_operand:SF 0 "register_operand" "=r")
1748 (plus:SF (match_operand:SF 1 "register_operand" "r")
1749 (match_operand:SF 2 "register_operand" "r")))]
1750 "TARGET_V850E2V3"
1751 "addf.s %1,%2,%0"
1752 [(set_attr "length" "4")
1753 (set_attr "cc" "none_0hit")
1754 (set_attr "type" "fpu")])
1755
1756 (define_insn "adddf3"
1757 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1758 (plus:DF (match_operand:DF 1 "even_reg_operand" "r")
1759 (match_operand:DF 2 "even_reg_operand" "r")))]
1760 "TARGET_V850E2V3"
1761 "addf.d %1,%2,%0"
1762 [(set_attr "length" "4")
1763 (set_attr "cc" "none_0hit")
1764 (set_attr "type" "fpu")])
1765
1766 (define_insn "subsf3"
1767 [(set (match_operand:SF 0 "register_operand" "=r")
1768 (minus:SF (match_operand:SF 1 "register_operand" "r")
1769 (match_operand:SF 2 "register_operand" "r")))]
1770 "TARGET_V850E2V3"
1771 "subf.s %2,%1,%0"
1772 [(set_attr "length" "4")
1773 (set_attr "cc" "none_0hit")
1774 (set_attr "type" "fpu")])
1775
1776 (define_insn "subdf3"
1777 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1778 (minus:DF (match_operand:DF 1 "even_reg_operand" "r")
1779 (match_operand:DF 2 "even_reg_operand" "r")))]
1780 "TARGET_V850E2V3"
1781 "subf.d %2,%1,%0"
1782 [(set_attr "length" "4")
1783 (set_attr "cc" "none_0hit")
1784 (set_attr "type" "fpu")])
1785
1786 (define_insn "mulsf3"
1787 [(set (match_operand:SF 0 "register_operand" "=r")
1788 (mult:SF (match_operand:SF 1 "register_operand" "r")
1789 (match_operand:SF 2 "register_operand" "r")))]
1790 "TARGET_V850E2V3"
1791 "mulf.s %1,%2,%0"
1792 [(set_attr "length" "4")
1793 (set_attr "cc" "none_0hit")
1794 (set_attr "type" "fpu")])
1795
1796 (define_insn "muldf3"
1797 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1798 (mult:DF (match_operand:DF 1 "even_reg_operand" "r")
1799 (match_operand:DF 2 "even_reg_operand" "r")))]
1800 "TARGET_V850E2V3"
1801 "mulf.d %1,%2,%0"
1802 [(set_attr "length" "4")
1803 (set_attr "cc" "none_0hit")
1804 (set_attr "type" "fpu")])
1805
1806 (define_insn "divsf3"
1807 [(set (match_operand:SF 0 "register_operand" "=r")
1808 (div:SF (match_operand:SF 1 "register_operand" "r")
1809 (match_operand:SF 2 "register_operand" "r")))]
1810 "TARGET_V850E2V3"
1811 "divf.s %2,%1,%0"
1812 [(set_attr "length" "4")
1813 (set_attr "cc" "none_0hit")
1814 (set_attr "type" "fpu")])
1815
1816 (define_insn "divdf3"
1817 [(set (match_operand:DF 0 "register_operand" "=r")
1818 (div:DF (match_operand:DF 1 "even_reg_operand" "r")
1819 (match_operand:DF 2 "even_reg_operand" "r")))]
1820 "TARGET_V850E2V3"
1821 "divf.d %2,%1,%0"
1822 [(set_attr "length" "4")
1823 (set_attr "cc" "none_0hit")
1824 (set_attr "type" "fpu")])
1825
1826 (define_insn "minsf3"
1827 [(set (match_operand:SF 0 "register_operand" "=r")
1828 (smin:SF (match_operand:SF 1 "reg_or_0_operand" "r")
1829 (match_operand:SF 2 "reg_or_0_operand" "r")))]
1830 "TARGET_V850E2V3"
1831 "minf.s %z1,%z2,%0"
1832 [(set_attr "length" "4")
1833 (set_attr "cc" "none_0hit")
1834 (set_attr "type" "fpu")])
1835
1836 (define_insn "mindf3"
1837 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1838 (smin:DF (match_operand:DF 1 "even_reg_operand" "r")
1839 (match_operand:DF 2 "even_reg_operand" "r")))]
1840 "TARGET_V850E2V3"
1841 "minf.d %1,%2,%0"
1842 [(set_attr "length" "4")
1843 (set_attr "cc" "none_0hit")
1844 (set_attr "type" "fpu")])
1845
1846 (define_insn "maxsf3"
1847 [(set (match_operand:SF 0 "register_operand" "=r")
1848 (smax:SF (match_operand:SF 1 "reg_or_0_operand" "r")
1849 (match_operand:SF 2 "reg_or_0_operand" "r")))]
1850 "TARGET_V850E2V3"
1851 "maxf.s %z1,%z2,%0"
1852 [(set_attr "length" "4")
1853 (set_attr "cc" "none_0hit")
1854 (set_attr "type" "fpu")])
1855
1856 (define_insn "maxdf3"
1857 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1858 (smax:DF (match_operand:DF 1 "even_reg_operand" "r")
1859 (match_operand:DF 2 "even_reg_operand" "r")))]
1860 "TARGET_V850E2V3"
1861 "maxf.d %1,%2,%0"
1862 [(set_attr "length" "4")
1863 (set_attr "cc" "none_0hit")
1864 (set_attr "type" "fpu")])
1865
1866 (define_insn "abssf2"
1867 [(set (match_operand:SF 0 "register_operand" "=r")
1868 (abs:SF (match_operand:SF 1 "register_operand" "r")))]
1869 "TARGET_V850E2V3"
1870 "absf.s %1,%0"
1871 [(set_attr "length" "4")
1872 (set_attr "cc" "none_0hit")
1873 (set_attr "type" "fpu")])
1874
1875 (define_insn "absdf2"
1876 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1877 (abs:DF (match_operand:DF 1 "even_reg_operand" "r")))]
1878 "TARGET_V850E2V3"
1879 "absf.d %1,%0"
1880 [(set_attr "length" "4")
1881 (set_attr "cc" "none_0hit")
1882 (set_attr "type" "fpu")])
1883
1884 (define_insn "negsf2"
1885 [(set (match_operand:SF 0 "register_operand" "=r")
1886 (neg:SF (match_operand:SF 1 "register_operand" "r")))]
1887 "TARGET_V850E2V3"
1888 "negf.s %1,%0"
1889 [(set_attr "length" "4")
1890 (set_attr "cc" "none_0hit")
1891 (set_attr "type" "fpu")])
1892
1893 (define_insn "negdf2"
1894 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1895 (neg:DF (match_operand:DF 1 "even_reg_operand" "r")))]
1896 "TARGET_V850E2V3"
1897 "negf.d %1,%0"
1898 [(set_attr "length" "4")
1899 (set_attr "cc" "none_0hit")
1900 (set_attr "type" "fpu")])
1901
1902 ;; square-root
1903 (define_insn "sqrtsf2"
1904 [(set (match_operand:SF 0 "register_operand" "=r")
1905 (sqrt:SF (match_operand:SF 1 "register_operand" "r")))]
1906 "TARGET_V850E2V3"
1907 "sqrtf.s %1,%0"
1908 [(set_attr "length" "4")
1909 (set_attr "cc" "none_0hit")
1910 (set_attr "type" "fpu")])
1911
1912 (define_insn "sqrtdf2"
1913 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1914 (sqrt:DF (match_operand:DF 1 "even_reg_operand" "r")))]
1915 "TARGET_V850E2V3"
1916 "sqrtf.d %1,%0"
1917 [(set_attr "length" "4")
1918 (set_attr "cc" "none_0hit")
1919 (set_attr "type" "fpu")])
1920
1921 ;; float -> int
1922 (define_insn "fix_truncsfsi2"
1923 [(set (match_operand:SI 0 "register_operand" "=r")
1924 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "r"))))]
1925 "TARGET_V850E2V3"
1926 "trncf.sw %1,%0"
1927 [(set_attr "length" "4")
1928 (set_attr "cc" "none_0hit")
1929 (set_attr "type" "fpu")])
1930
1931 (define_insn "fix_truncdfsi2"
1932 [(set (match_operand:SI 0 "register_operand" "=r")
1933 (fix:SI (fix:DF (match_operand:DF 1 "even_reg_operand" "r"))))]
1934 "TARGET_V850E2V3"
1935 "trncf.dw %1,%0"
1936 [(set_attr "length" "4")
1937 (set_attr "cc" "none_0hit")
1938 (set_attr "type" "fpu")])
1939
1940 ;; int -> float
1941 (define_insn "floatsisf2"
1942 [(set (match_operand:SF 0 "register_operand" "=r")
1943 (float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
1944 "TARGET_V850E2V3"
1945 "cvtf.ws %z1, %0"
1946 [(set_attr "length" "4")
1947 (set_attr "cc" "none_0hit")
1948 (set_attr "type" "fpu")])
1949
1950 (define_insn "floatsidf2"
1951 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1952 (float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
1953 "TARGET_V850E2V3"
1954 "cvtf.wd %z1,%0"
1955 [(set_attr "length" "4")
1956 (set_attr "cc" "none_0hit")
1957 (set_attr "type" "fpu")])
1958
1959 ;; single-float -> double-float
1960 (define_insn "extendsfdf2"
1961 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1962 (float_extend:DF
1963 (match_operand:SF 1 "reg_or_0_operand" "rI")))]
1964 "TARGET_V850E2V3"
1965 "cvtf.sd %z1,%0"
1966 [(set_attr "length" "4")
1967 (set_attr "cc" "none_0hit")
1968 (set_attr "type" "fpu")])
1969
1970 ;; double-float -> single-float
1971 (define_insn "truncdfsf2"
1972 [(set (match_operand:SF 0 "register_operand" "=r")
1973 (float_truncate:SF
1974 (match_operand:DF 1 "even_reg_operand" "r")))]
1975 "TARGET_V850E2V3"
1976 "cvtf.ds %1,%0"
1977 [(set_attr "length" "4")
1978 (set_attr "cc" "none_0hit")
1979 (set_attr "type" "fpu")])
1980
1981 ;;
1982 ;; ---------------- special insns
1983 ;;
1984
1985 ;;; reciprocal
1986 (define_insn "recipsf2"
1987 [(set (match_operand:SF 0 "register_operand" "=r")
1988 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
1989 (match_operand:SF 2 "register_operand" "r")))]
1990 "TARGET_V850E2V3"
1991 "recipf.s %2,%0"
1992 [(set_attr "length" "4")
1993 (set_attr "cc" "none_0hit")
1994 (set_attr "type" "fpu")])
1995
1996 (define_insn "recipdf2"
1997 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1998 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
1999 (match_operand:DF 2 "even_reg_operand" "r")))]
2000 "TARGET_V850E2V3"
2001 "recipf.d %2,%0"
2002 [(set_attr "length" "4")
2003 (set_attr "cc" "none_0hit")
2004 (set_attr "type" "fpu")])
2005
2006 ;;; reciprocal of square-root
2007 (define_insn "rsqrtsf2"
2008 [(set (match_operand:SF 0 "register_operand" "=r")
2009 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
2010 (sqrt:SF (match_operand:SF 2 "register_operand" "r"))))]
2011 "TARGET_V850E2V3"
2012 "rsqrtf.s %2,%0"
2013 [(set_attr "length" "4")
2014 (set_attr "cc" "none_0hit")
2015 (set_attr "type" "fpu")])
2016
2017 (define_insn "rsqrtdf2"
2018 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2019 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
2020 (sqrt:DF (match_operand:DF 2 "even_reg_operand" "r"))))]
2021 "TARGET_V850E2V3"
2022 "rsqrtf.d %2,%0"
2023 [(set_attr "length" "4")
2024 (set_attr "cc" "none_0hit")
2025 (set_attr "type" "fpu")])
2026
2027 ;;; multiply-add
2028 (define_insn "fmasf4"
2029 [(set (match_operand:SF 0 "register_operand" "=r")
2030 (fma:SF (match_operand:SF 1 "register_operand" "r")
2031 (match_operand:SF 2 "register_operand" "r")
2032 (match_operand:SF 3 "register_operand" "r")))]
2033 "TARGET_V850E2V3"
2034 "maddf.s %2,%1,%3,%0"
2035 [(set_attr "length" "4")
2036 (set_attr "cc" "none_0hit")
2037 (set_attr "type" "fpu")])
2038
2039 ;;; multiply-subtract
2040 (define_insn "fmssf4"
2041 [(set (match_operand:SF 0 "register_operand" "=r")
2042 (fma:SF (match_operand:SF 1 "register_operand" "r")
2043 (match_operand:SF 2 "register_operand" "r")
2044 (neg:SF (match_operand:SF 3 "register_operand" "r"))))]
2045 "TARGET_V850E2V3"
2046 "msubf.s %2,%1,%3,%0"
2047 [(set_attr "length" "4")
2048 (set_attr "cc" "none_0hit")
2049 (set_attr "type" "fpu")])
2050
2051 ;;; negative-multiply-add
2052 (define_insn "fnmasf4"
2053 [(set (match_operand:SF 0 "register_operand" "=r")
2054 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
2055 (match_operand:SF 2 "register_operand" "r")
2056 (match_operand:SF 3 "register_operand" "r")))]
2057 "TARGET_V850E2V3"
2058 "nmaddf.s %2,%1,%3,%0"
2059 [(set_attr "length" "4")
2060 (set_attr "cc" "none_0hit")
2061 (set_attr "type" "fpu")])
2062
2063 ;; negative-multiply-subtract
2064 (define_insn "fnmssf4"
2065 [(set (match_operand:SF 0 "register_operand" "=r")
2066 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
2067 (match_operand:SF 2 "register_operand" "r")
2068 (neg:SF (match_operand:SF 3 "register_operand" "r"))))]
2069 "TARGET_V850E2V3"
2070 "nmsubf.s %2,%1,%3,%0"
2071 [(set_attr "length" "4")
2072 (set_attr "cc" "none_0hit")
2073 (set_attr "type" "fpu")])
2074 ;
2075 ; ---------------- comparison/conditionals
2076 ;
2077 ; SF
2078
2079 (define_insn "cmpsf_le_insn"
2080 [(set (reg:CC_FPU_LE FCC_REGNUM)
2081 (compare:CC_FPU_LE (match_operand:SF 0 "register_operand" "r")
2082 (match_operand:SF 1 "register_operand" "r")))]
2083 "TARGET_V850E2V3"
2084 "cmpf.s le,%z0,%z1"
2085 [(set_attr "length" "4")
2086 (set_attr "cc" "none_0hit")
2087 (set_attr "type" "fpu")])
2088
2089 (define_insn "cmpsf_lt_insn"
2090 [(set (reg:CC_FPU_LT FCC_REGNUM)
2091 (compare:CC_FPU_LT (match_operand:SF 0 "register_operand" "r")
2092 (match_operand:SF 1 "register_operand" "r")))]
2093 "TARGET_V850E2V3"
2094 "cmpf.s lt,%z0,%z1"
2095 [(set_attr "length" "4")
2096 (set_attr "cc" "none_0hit")
2097 (set_attr "type" "fpu")])
2098
2099 (define_insn "cmpsf_ge_insn"
2100 [(set (reg:CC_FPU_GE FCC_REGNUM)
2101 (compare:CC_FPU_GE (match_operand:SF 0 "register_operand" "r")
2102 (match_operand:SF 1 "register_operand" "r")))]
2103 "TARGET_V850E2V3"
2104 "cmpf.s ge,%z0,%z1"
2105 [(set_attr "length" "4")
2106 (set_attr "cc" "none_0hit")
2107 (set_attr "type" "fpu")])
2108
2109 (define_insn "cmpsf_gt_insn"
2110 [(set (reg:CC_FPU_GT FCC_REGNUM)
2111 (compare:CC_FPU_GT (match_operand:SF 0 "register_operand" "r")
2112 (match_operand:SF 1 "register_operand" "r")))]
2113 "TARGET_V850E2V3"
2114 "cmpf.s gt,%z0,%z1"
2115 [(set_attr "length" "4")
2116 (set_attr "cc" "none_0hit")
2117 (set_attr "type" "fpu")])
2118
2119 (define_insn "cmpsf_eq_insn"
2120 [(set (reg:CC_FPU_EQ FCC_REGNUM)
2121 (compare:CC_FPU_EQ (match_operand:SF 0 "register_operand" "r")
2122 (match_operand:SF 1 "register_operand" "r")))]
2123 "TARGET_V850E2V3"
2124 "cmpf.s eq,%z0,%z1"
2125 [(set_attr "length" "4")
2126 (set_attr "cc" "none_0hit")
2127 (set_attr "type" "fpu")])
2128
2129 (define_insn "cmpsf_ne_insn"
2130 [(set (reg:CC_FPU_NE FCC_REGNUM)
2131 (compare:CC_FPU_NE (match_operand:SF 0 "register_operand" "r")
2132 (match_operand:SF 1 "register_operand" "r")))]
2133 "TARGET_V850E2V3"
2134 "cmpf.s neq,%z0,%z1"
2135 [(set_attr "length" "4")
2136 (set_attr "cc" "none_0hit")
2137 (set_attr "type" "fpu")])
2138
2139 ; DF
2140
2141 (define_insn "cmpdf_le_insn"
2142 [(set (reg:CC_FPU_LE FCC_REGNUM)
2143 (compare:CC_FPU_LE (match_operand:DF 0 "even_reg_operand" "r")
2144 (match_operand:DF 1 "even_reg_operand" "r")))]
2145 "TARGET_V850E2V3"
2146 "cmpf.d le,%z0,%z1"
2147 [(set_attr "length" "4")
2148 (set_attr "cc" "none_0hit")
2149 (set_attr "type" "fpu")])
2150
2151 (define_insn "cmpdf_lt_insn"
2152 [(set (reg:CC_FPU_LT FCC_REGNUM)
2153 (compare:CC_FPU_LT (match_operand:DF 0 "even_reg_operand" "r")
2154 (match_operand:DF 1 "even_reg_operand" "r")))]
2155 "TARGET_V850E2V3"
2156 "cmpf.d lt,%z0,%z1"
2157 [(set_attr "length" "4")
2158 (set_attr "cc" "none_0hit")
2159 (set_attr "type" "fpu")])
2160
2161 (define_insn "cmpdf_ge_insn"
2162 [(set (reg:CC_FPU_GE FCC_REGNUM)
2163 (compare:CC_FPU_GE (match_operand:DF 0 "even_reg_operand" "r")
2164 (match_operand:DF 1 "even_reg_operand" "r")))]
2165 "TARGET_V850E2V3"
2166 "cmpf.d ge,%z0,%z1"
2167 [(set_attr "length" "4")
2168 (set_attr "cc" "none_0hit")
2169 (set_attr "type" "fpu")])
2170
2171 (define_insn "cmpdf_gt_insn"
2172 [(set (reg:CC_FPU_GT FCC_REGNUM)
2173 (compare:CC_FPU_GT (match_operand:DF 0 "even_reg_operand" "r")
2174 (match_operand:DF 1 "even_reg_operand" "r")))]
2175 "TARGET_V850E2V3"
2176 "cmpf.d gt,%z0,%z1"
2177 [(set_attr "length" "4")
2178 (set_attr "cc" "none_0hit")
2179 (set_attr "type" "fpu")])
2180
2181 (define_insn "cmpdf_eq_insn"
2182 [(set (reg:CC_FPU_EQ FCC_REGNUM)
2183 (compare:CC_FPU_EQ (match_operand:DF 0 "even_reg_operand" "r")
2184 (match_operand:DF 1 "even_reg_operand" "r")))]
2185 "TARGET_V850E2V3"
2186 "cmpf.d eq,%z0,%z1"
2187 [(set_attr "length" "4")
2188 (set_attr "cc" "none_0hit")
2189 (set_attr "type" "fpu")])
2190
2191 (define_insn "cmpdf_ne_insn"
2192 [(set (reg:CC_FPU_NE FCC_REGNUM)
2193 (compare:CC_FPU_NE (match_operand:DF 0 "even_reg_operand" "r")
2194 (match_operand:DF 1 "even_reg_operand" "r")))]
2195 "TARGET_V850E2V3"
2196 "cmpf.d neq,%z0,%z1"
2197 [(set_attr "length" "4")
2198 (set_attr "cc" "none_0hit")
2199 (set_attr "type" "fpu")])
2200
2201
2202 ;;
2203 ;; Transfer a v850e2v3 fcc to the Z bit of CC0 (this is necessary to do a
2204 ;; conditional branch based on a floating-point compare)
2205 ;;
2206
2207 (define_insn "trfsr"
2208 [(set (match_operand 0 "" "") (match_operand 1 "" ""))]
2209 "TARGET_V850E2V3
2210 && GET_MODE(operands[0]) == GET_MODE(operands[1])
2211 && GET_CODE(operands[0]) == REG && REGNO (operands[0]) == CC_REGNUM
2212 && GET_CODE(operands[1]) == REG && REGNO (operands[1]) == FCC_REGNUM
2213 && (GET_MODE(operands[0]) == CC_FPU_LEmode
2214 || GET_MODE(operands[0]) == CC_FPU_GEmode
2215 || GET_MODE(operands[0]) == CC_FPU_LTmode
2216 || GET_MODE(operands[0]) == CC_FPU_GTmode
2217 || GET_MODE(operands[0]) == CC_FPU_EQmode
2218 || GET_MODE(operands[0]) == CC_FPU_NEmode)"
2219 "trfsr"
2220 [(set_attr "length" "4")
2221 (set_attr "cc" "set_z")
2222 (set_attr "type" "fpu")])
2223
2224 ;;
2225 ;; Floating-point conditional moves for the v850e2v3.
2226 ;;
2227
2228 ;; The actual v850e2v3 conditional move instructions
2229 ;;
2230 (define_insn "movsfcc_z_insn"
2231 [(set (match_operand:SF 0 "register_operand" "=r")
2232 (if_then_else:SF
2233 (match_operand 3 "v850_float_z_comparison_operator" "")
2234 (match_operand:SF 1 "reg_or_0_operand" "rIG")
2235 (match_operand:SF 2 "reg_or_0_operand" "rIG")))]
2236 "TARGET_V850E2V3"
2237 "cmovf.s 0,%z1,%z2,%0"
2238 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2239
2240 (define_insn "movsfcc_nz_insn"
2241 [(set (match_operand:SF 0 "register_operand" "=r")
2242 (if_then_else:SF
2243 (match_operand 3 "v850_float_nz_comparison_operator" "")
2244 (match_operand:SF 1 "reg_or_0_operand" "rIG")
2245 (match_operand:SF 2 "reg_or_0_operand" "rIG")))]
2246 "TARGET_V850E2V3"
2247 "cmovf.s 0,%z2,%z1,%0"
2248 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2249
2250 (define_insn "movdfcc_z_insn"
2251 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2252 (if_then_else:DF
2253 (match_operand 3 "v850_float_z_comparison_operator" "")
2254 (match_operand:DF 1 "even_reg_operand" "r")
2255 (match_operand:DF 2 "even_reg_operand" "r")))]
2256 "TARGET_V850E2V3"
2257 "cmovf.d 0,%z1,%z2,%0"
2258 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2259
2260 (define_insn "movdfcc_nz_insn"
2261 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2262 (if_then_else:DF
2263 (match_operand 3 "v850_float_nz_comparison_operator" "")
2264 (match_operand:DF 1 "even_reg_operand" "r")
2265 (match_operand:DF 2 "even_reg_operand" "r")))]
2266 "TARGET_V850E2V3"
2267 "cmovf.d 0,%z2,%z1,%0"
2268 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2269
2270 (define_insn "movedfcc_z_zero"
2271 [(set (match_operand:DF 0 "register_operand" "=r")
2272 (if_then_else:DF
2273 (match_operand 3 "v850_float_z_comparison_operator" "")
2274 (match_operand:DF 1 "reg_or_0_operand" "rIG")
2275 (match_operand:DF 2 "reg_or_0_operand" "rIG")))]
2276 "TARGET_V850E2V3"
2277 "cmovf.s 0,%z1,%z2,%0 ; cmovf.s 0,%Z1,%Z2,%R0"
2278 [(set_attr "length" "8")
2279 (set_attr "cc" "clobber")]) ;; ??? or none_0hit
2280
2281 (define_insn "movedfcc_nz_zero"
2282 [(set (match_operand:DF 0 "register_operand" "=r")
2283 (if_then_else:DF
2284 (match_operand 3 "v850_float_nz_comparison_operator" "")
2285 (match_operand:DF 1 "reg_or_0_operand" "rIG")
2286 (match_operand:DF 2 "reg_or_0_operand" "rIG")))]
2287 "TARGET_V850E2V3"
2288 "cmovf.s 0,%z2,%z1,%0 ; cmovf.s 0,%Z2,%Z1,%R0"
2289 [(set_attr "length" "8")
2290 (set_attr "cc" "clobber")]) ;; ??? or none_0hit
2291
2292
1388 ;; ---------------------------------------------------------------------- 2293 ;; ----------------------------------------------------------------------
1389 ;; HELPER INSTRUCTIONS for saving the prologue and epilogue registers 2294 ;; HELPER INSTRUCTIONS for saving the prologue and epilogue registers
1390 ;; ---------------------------------------------------------------------- 2295 ;; ----------------------------------------------------------------------
1391 2296
1392 ;; This pattern will match a stack adjust RTX followed by any number of push 2297 ;; This pattern will match a stack adjust RTX followed by any number of push
1394 ;; function. 2299 ;; function.
1395 2300
1396 ;; 2301 ;;
1397 ;; Actually, convert the RTXs into a PREPARE instruction. 2302 ;; Actually, convert the RTXs into a PREPARE instruction.
1398 ;; 2303 ;;
2304
1399 (define_insn "" 2305 (define_insn ""
1400 [(match_parallel 0 "pattern_is_ok_for_prepare" 2306 [(match_parallel 0 "pattern_is_ok_for_prepare"
1401 [(set (reg:SI 3) 2307 [(set (reg:SI 3)
1402 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) 2308 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1403 (set (mem:SI (plus:SI (reg:SI 3) 2309 (set (mem:SI (plus:SI (reg:SI 3)
1404 (match_operand:SI 2 "immediate_operand" "i"))) 2310 (match_operand:SI 2 "immediate_operand" "i")))
1405 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])] 2311 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
1406 "TARGET_PROLOG_FUNCTION && TARGET_V850E" 2312 "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)"
1407 "* return construct_prepare_instruction (operands[0]); 2313 "* return construct_prepare_instruction (operands[0]);
1408 " 2314 "
1409 [(set_attr "length" "4") 2315 [(set_attr "length" "4")
1410 (set_attr "cc" "none")]) 2316 (set_attr "cc" "clobber")])
1411 2317
1412 (define_insn "" 2318 (define_insn ""
1413 [(match_parallel 0 "pattern_is_ok_for_prologue" 2319 [(match_parallel 0 "pattern_is_ok_for_prologue"
1414 [(set (reg:SI 3) 2320 [(set (reg:SI 3)
1415 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) 2321 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1416 (set (mem:SI (plus:SI (reg:SI 3) 2322 (set (mem:SI (plus:SI (reg:SI 3)
1417 (match_operand:SI 2 "immediate_operand" "i"))) 2323 (match_operand:SI 2 "immediate_operand" "i")))
1418 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])] 2324 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
1419 "TARGET_PROLOG_FUNCTION && TARGET_V850" 2325 "TARGET_PROLOG_FUNCTION"
1420 "* return construct_save_jarl (operands[0]); 2326 "* return construct_save_jarl (operands[0]);
1421 " 2327 "
1422 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") 2328 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
1423 (const_string "16") 2329 (const_string "16")
1424 (const_string "4"))) 2330 (const_string "4")))
1433 (set (reg:SI 3) 2339 (set (reg:SI 3)
1434 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) 2340 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1435 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r") 2341 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
1436 (mem:SI (plus:SI (reg:SI 3) 2342 (mem:SI (plus:SI (reg:SI 3)
1437 (match_operand:SI 3 "immediate_operand" "i"))))])] 2343 (match_operand:SI 3 "immediate_operand" "i"))))])]
1438 "TARGET_PROLOG_FUNCTION && TARGET_V850E" 2344 "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)"
1439 "* return construct_dispose_instruction (operands[0]); 2345 "* return construct_dispose_instruction (operands[0]);
1440 " 2346 "
1441 [(set_attr "length" "4") 2347 [(set_attr "length" "4")
1442 (set_attr "cc" "none")]) 2348 (set_attr "cc" "clobber")])
1443 2349
1444 ;; This pattern will match a return RTX followed by any number of pop RTXs 2350 ;; This pattern will match a return RTX followed by any number of pop RTXs
1445 ;; and possible a stack adjustment as well. These RTXs will be turned into 2351 ;; and possible a stack adjustment as well. These RTXs will be turned into
1446 ;; a suitable call to a worker function. 2352 ;; a suitable call to a worker function.
1447 2353
1451 (set (reg:SI 3) 2357 (set (reg:SI 3)
1452 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) 2358 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1453 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r") 2359 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
1454 (mem:SI (plus:SI (reg:SI 3) 2360 (mem:SI (plus:SI (reg:SI 3)
1455 (match_operand:SI 3 "immediate_operand" "i"))))])] 2361 (match_operand:SI 3 "immediate_operand" "i"))))])]
1456 "TARGET_PROLOG_FUNCTION && TARGET_V850" 2362 "TARGET_PROLOG_FUNCTION"
1457 "* return construct_restore_jr (operands[0]); 2363 "* return construct_restore_jr (operands[0]);
1458 " 2364 "
1459 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") 2365 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
1460 (const_string "12") 2366 (const_string "12")
1461 (const_string "4"))) 2367 (const_string "4")))
1462 (set_attr "cc" "clobber")]) 2368 (set_attr "cc" "clobber")])
1463 2369
1464 ;; Initialize an interrupt function. Do not depend on TARGET_PROLOG_FUNCTION. 2370 ;; Initialize an interrupt function. Do not depend on TARGET_PROLOG_FUNCTION.
1465 (define_insn "callt_save_interrupt" 2371 (define_insn "callt_save_interrupt"
1466 [(unspec_volatile [(const_int 0)] 2)] 2372 [(unspec_volatile [(const_int 0)] 2)]
1467 "TARGET_V850E && !TARGET_DISABLE_CALLT" 2373 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
1468 ;; The CALLT instruction stores the next address of CALLT to CTPC register 2374 ;; The CALLT instruction stores the next address of CALLT to CTPC register
1469 ;; without saving its previous value. So if the interrupt handler 2375 ;; without saving its previous value. So if the interrupt handler
1470 ;; or its caller could possibly execute the CALLT insn, save_interrupt 2376 ;; or its caller could possibly execute the CALLT insn, save_interrupt
1471 ;; MUST NOT be called via CALLT. 2377 ;; MUST NOT be called via CALLT.
1472 "* 2378 "*
1473 { 2379 {
1474 output_asm_insn (\"addi -24, sp, sp\", operands); 2380 output_asm_insn (\"addi -28, sp, sp\", operands);
2381 output_asm_insn (\"st.w r1, 24[sp]\", operands);
1475 output_asm_insn (\"st.w r10, 12[sp]\", operands); 2382 output_asm_insn (\"st.w r10, 12[sp]\", operands);
2383 output_asm_insn (\"st.w r11, 16[sp]\", operands);
1476 output_asm_insn (\"stsr ctpc, r10\", operands); 2384 output_asm_insn (\"stsr ctpc, r10\", operands);
1477 output_asm_insn (\"st.w r10, 16[sp]\", operands); 2385 output_asm_insn (\"st.w r10, 20[sp]\", operands);
1478 output_asm_insn (\"stsr ctpsw, r10\", operands); 2386 output_asm_insn (\"stsr ctpsw, r10\", operands);
1479 output_asm_insn (\"st.w r10, 20[sp]\", operands); 2387 output_asm_insn (\"st.w r10, 24[sp]\", operands);
1480 output_asm_insn (\"callt ctoff(__callt_save_interrupt)\", operands); 2388 output_asm_insn (\"callt ctoff(__callt_save_interrupt)\", operands);
1481 return \"\"; 2389 return \"\";
1482 }" 2390 }"
1483 [(set_attr "length" "26") 2391 [(set_attr "length" "26")
1484 (set_attr "cc" "none")]) 2392 (set_attr "cc" "clobber")])
1485 2393
1486 (define_insn "callt_return_interrupt" 2394 (define_insn "callt_return_interrupt"
1487 [(unspec_volatile [(const_int 0)] 3)] 2395 [(unspec_volatile [(const_int 0)] 3)]
1488 "TARGET_V850E && !TARGET_DISABLE_CALLT" 2396 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
1489 "callt ctoff(__callt_return_interrupt)" 2397 "callt ctoff(__callt_return_interrupt)"
1490 [(set_attr "length" "2") 2398 [(set_attr "length" "2")
1491 (set_attr "cc" "clobber")]) 2399 (set_attr "cc" "clobber")])
1492 2400
1493 (define_insn "save_interrupt" 2401 (define_insn "save_interrupt"
1494 [(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -16))) 2402 [(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -20)))
1495 (set (mem:SI (plus:SI (reg:SI 3) (const_int -16))) (reg:SI 30)) 2403 (set (mem:SI (plus:SI (reg:SI 3) (const_int -20))) (reg:SI 30))
1496 (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 4)) 2404 (set (mem:SI (plus:SI (reg:SI 3) (const_int -16))) (reg:SI 4))
1497 (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 1)) 2405 (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 1))
1498 (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 10))] 2406 (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 10))
2407 (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 11))]
1499 "" 2408 ""
1500 "* 2409 "*
1501 { 2410 {
1502 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) 2411 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
1503 return \"add -16,sp\;st.w r10,12[sp]\;jarl __save_interrupt,r10\"; 2412 return \"addi -20,sp,sp \; st.w r11,16[sp] \; st.w r10,12[sp] \; jarl __save_interrupt,r10\";
1504 else 2413 else
1505 { 2414 {
1506 output_asm_insn (\"add -16, sp\", operands); 2415 output_asm_insn (\"addi -20, sp, sp\", operands);
2416 output_asm_insn (\"st.w r11, 16[sp]\", operands);
1507 output_asm_insn (\"st.w r10, 12[sp]\", operands); 2417 output_asm_insn (\"st.w r10, 12[sp]\", operands);
1508 output_asm_insn (\"st.w ep, 0[sp]\", operands); 2418 output_asm_insn (\"st.w ep, 0[sp]\", operands);
1509 output_asm_insn (\"st.w gp, 4[sp]\", operands); 2419 output_asm_insn (\"st.w gp, 4[sp]\", operands);
1510 output_asm_insn (\"st.w r1, 8[sp]\", operands); 2420 output_asm_insn (\"st.w r1, 8[sp]\", operands);
1511 output_asm_insn (\"movhi hi(__ep), r0, ep\", operands); 2421 output_asm_insn (\"movhi hi(__ep), r0, ep\", operands);
1522 (set_attr "cc" "clobber")]) 2432 (set_attr "cc" "clobber")])
1523 2433
1524 ;; Restore r1, r4, r10, and return from the interrupt 2434 ;; Restore r1, r4, r10, and return from the interrupt
1525 (define_insn "return_interrupt" 2435 (define_insn "return_interrupt"
1526 [(return) 2436 [(return)
1527 (set (reg:SI 3) (plus:SI (reg:SI 3) (const_int 16))) 2437 (set (reg:SI 3) (plus:SI (reg:SI 3) (const_int 20)))
2438 (set (reg:SI 11) (mem:SI (plus:SI (reg:SI 3) (const_int 16))))
1528 (set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 12)))) 2439 (set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 12))))
1529 (set (reg:SI 1) (mem:SI (plus:SI (reg:SI 3) (const_int 8)))) 2440 (set (reg:SI 1) (mem:SI (plus:SI (reg:SI 3) (const_int 8))))
1530 (set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4)))) 2441 (set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4))))
1531 (set (reg:SI 30) (mem:SI (reg:SI 3)))] 2442 (set (reg:SI 30) (mem:SI (reg:SI 3)))]
1532 "" 2443 ""
1538 { 2449 {
1539 output_asm_insn (\"ld.w 0[sp], ep\", operands); 2450 output_asm_insn (\"ld.w 0[sp], ep\", operands);
1540 output_asm_insn (\"ld.w 4[sp], gp\", operands); 2451 output_asm_insn (\"ld.w 4[sp], gp\", operands);
1541 output_asm_insn (\"ld.w 8[sp], r1\", operands); 2452 output_asm_insn (\"ld.w 8[sp], r1\", operands);
1542 output_asm_insn (\"ld.w 12[sp], r10\", operands); 2453 output_asm_insn (\"ld.w 12[sp], r10\", operands);
1543 output_asm_insn (\"addi 16, sp, sp\", operands); 2454 output_asm_insn (\"ld.w 16[sp], r11\", operands);
2455 output_asm_insn (\"addi 20, sp, sp\", operands);
1544 output_asm_insn (\"reti\", operands); 2456 output_asm_insn (\"reti\", operands);
1545 return \"\"; 2457 return \"\";
1546 } 2458 }
1547 }" 2459 }"
1548 [(set (attr "length") 2460 [(set (attr "length")
1558 ;; This is needed because the rest of the compiler is not ready to handle 2470 ;; This is needed because the rest of the compiler is not ready to handle
1559 ;; insns this complicated. 2471 ;; insns this complicated.
1560 2472
1561 (define_insn "callt_save_all_interrupt" 2473 (define_insn "callt_save_all_interrupt"
1562 [(unspec_volatile [(const_int 0)] 0)] 2474 [(unspec_volatile [(const_int 0)] 0)]
1563 "TARGET_V850E && !TARGET_DISABLE_CALLT" 2475 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
1564 "callt ctoff(__callt_save_all_interrupt)" 2476 "callt ctoff(__callt_save_all_interrupt)"
1565 [(set_attr "length" "2") 2477 [(set_attr "length" "2")
1566 (set_attr "cc" "none")]) 2478 (set_attr "cc" "none")])
1567 2479
1568 (define_insn "save_all_interrupt" 2480 (define_insn "save_all_interrupt"
1659 ;; This is needed because the rest of the compiler is not ready to handle 2571 ;; This is needed because the rest of the compiler is not ready to handle
1660 ;; insns this complicated. 2572 ;; insns this complicated.
1661 2573
1662 (define_insn "callt_restore_all_interrupt" 2574 (define_insn "callt_restore_all_interrupt"
1663 [(unspec_volatile [(const_int 0)] 1)] 2575 [(unspec_volatile [(const_int 0)] 1)]
1664 "TARGET_V850E && !TARGET_DISABLE_CALLT" 2576 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
1665 "callt ctoff(__callt_restore_all_interrupt)" 2577 "callt ctoff(__callt_restore_all_interrupt)"
1666 [(set_attr "length" "2") 2578 [(set_attr "length" "2")
1667 (set_attr "cc" "none")]) 2579 (set_attr "cc" "none")])
1668 2580
1669 (define_insn "restore_all_interrupt" 2581 (define_insn "restore_all_interrupt"
1750 "TARGET_V850 && ! TARGET_LONG_CALLS" 2662 "TARGET_V850 && ! TARGET_LONG_CALLS"
1751 "jarl __restore_all_interrupt,r10" 2663 "jarl __restore_all_interrupt,r10"
1752 [(set_attr "length" "4") 2664 [(set_attr "length" "4")
1753 (set_attr "cc" "clobber")]) 2665 (set_attr "cc" "clobber")])
1754 2666
1755 ;; Save r6-r9 for a variable argument function 2667
1756 (define_insn "save_r6_r9_v850e"
1757 [(set (mem:SI (reg:SI 3)) (reg:SI 6))
1758 (set (mem:SI (plus:SI (reg:SI 3) (const_int 4))) (reg:SI 7))
1759 (set (mem:SI (plus:SI (reg:SI 3) (const_int 8))) (reg:SI 8))
1760 (set (mem:SI (plus:SI (reg:SI 3) (const_int 12))) (reg:SI 9))
1761 ]
1762 "TARGET_PROLOG_FUNCTION && TARGET_V850E && !TARGET_DISABLE_CALLT"
1763 "callt ctoff(__callt_save_r6_r9)"
1764 [(set_attr "length" "2")
1765 (set_attr "cc" "none")])
1766
1767 (define_insn "save_r6_r9"
1768 [(set (mem:SI (reg:SI 3)) (reg:SI 6))
1769 (set (mem:SI (plus:SI (reg:SI 3) (const_int 4))) (reg:SI 7))
1770 (set (mem:SI (plus:SI (reg:SI 3) (const_int 8))) (reg:SI 8))
1771 (set (mem:SI (plus:SI (reg:SI 3) (const_int 12))) (reg:SI 9))
1772 (clobber (reg:SI 10))]
1773 "TARGET_PROLOG_FUNCTION && ! TARGET_LONG_CALLS"
1774 "jarl __save_r6_r9,r10"
1775 [(set_attr "length" "4")
1776 (set_attr "cc" "clobber")])
1777