CbC/CbC_gcc: gcc/reload1.c comparison

comparison gcc/reload1.c @ 67:f6334be47118

update gcc from gcc-4.6-20100522 to gcc-4.6-20110318

author	nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date	Tue, 22 Mar 2011 17:18:12 +0900
parents	b7f97abdc517
children	04ced10e8804

comparison

equal deleted inserted replaced

-:65488c3d617d
+:f6334be47118
 /* Reload pseudo regs into hard regs for insns that require hard regs.
 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
+1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
-Free Software Foundation, Inc.
+2011 Free Software Foundation, Inc.
 This file is part of GCC.
 GCC is free software; you can redistribute it and/or modify it under
 the terms of the GNU General Public License as published by the Free
 #include "coretypes.h"
 #include "tm.h"
 #include "machmode.h"
 #include "hard-reg-set.h"
-#include "rtl.h"
+#include "rtl-error.h"
 #include "tm_p.h"
 #include "obstack.h"
 #include "insn-config.h"
 #include "flags.h"
 #include "function.h"
 #include "basic-block.h"
 #include "df.h"
 #include "reload.h"
 #include "recog.h"
 #include "output.h"
-#include "toplev.h"
 #include "except.h"
 #include "tree.h"
 #include "ira.h"
 #include "target.h"
 #include "emit-rtl.h"
 is in charge of scanning the entire rtl code, accumulating the
 reload needs, spilling, assigning reload registers to use for
 fixing up each insn, and generating the new insns to copy values
 into the reload registers.  */
+struct target_reload default_target_reload;
+#if SWITCHABLE_TARGET
+struct target_reload *this_target_reload = &default_target_reload;
+#endif
+#define spill_indirect_levels			\
+(this_target_reload->x_spill_indirect_levels)
 /* During reload_as_needed, element N contains a REG rtx for the hard reg
 into which reg N has been reloaded (perhaps for a previous insn).  */
 static rtx *reg_last_reload_reg;
 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
 /* Index of last register assigned as a spill register.  We allocate in
 a round-robin fashion.  */
 static int last_spill_reg;
-/* Nonzero if indirect addressing is supported on the machine; this means
-that spilling (REG n) does not require reloading it into a register in
-order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))).  The
-value indicates the level of indirect addressing supported, e.g., two
-means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
-a hard register.  */
-static char spill_indirect_levels;
-/* Nonzero if indirect addressing is supported when the innermost MEM is
-of the form (MEM (SYMBOL_REF sym)).  It is assumed that the level to
-which these are valid is the same as spill_indirect_levels, above.  */
-char indirect_symref_ok;
-/* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid.  */
-char double_reg_address_ok;
 /* Record the stack slot for each spilled hard register.  */
 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
 /* Width allocated so far for that stack slot.  */
 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
 int caller_save_needed;
 /* Set to 1 while reload_as_needed is operating.
 Required by some machines to handle any generated moves differently.  */
 int reload_in_progress = 0;
-/* These arrays record the insn_code of insns that may be needed to
-perform input and output reloads of special objects.  They provide a
-place to pass a scratch register.  */
-enum insn_code reload_in_optab[NUM_MACHINE_MODES];
-enum insn_code reload_out_optab[NUM_MACHINE_MODES];
 /* This obstack is used for allocation of rtl during register elimination.
 The allocated storage can be freed once find_reloads has processed the
 insn.  */
 static struct obstack reload_obstack;
 static void delete_dead_insn (rtx);
 static void alter_reg (int, int, bool);
 static void set_label_offsets (rtx, rtx, int);
 static void check_eliminable_occurrences (rtx);
 static void elimination_effects (rtx, enum machine_mode);
+static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
 static int eliminate_regs_in_insn (rtx, int);
 static void update_eliminable_offsets (void);
 static void mark_not_eliminable (rtx, const_rtx, void *);
 static void set_initial_elim_offsets (void);
 static bool verify_initial_elim_offsets (void);
 static void set_initial_label_offsets (void);
 static void set_offsets_for_label (rtx);
+static void init_eliminable_invariants (rtx, bool);
 static void init_elim_table (void);
+static void free_reg_equiv (void);
 static void update_eliminables (HARD_REG_SET *);
+static void elimination_costs_in_insn (rtx);
 static void spill_hard_reg (unsigned int, int);
 static int finish_spills (int);
 static void scan_paradoxical_subregs (rtx);
 static void count_pseudo (int);
 static void order_regs_for_reload (struct insn_chain *);
 static int conflicts_with_override (rtx);
 static void failed_reload (rtx, int);
 static int set_reload_reg (int, int);
 static void choose_reload_regs_init (struct insn_chain *, rtx *);
 static void choose_reload_regs (struct insn_chain *);
-static void merge_assigned_reloads (rtx);
 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
 				     rtx, int);
 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
 				      int);
 static void do_input_reload (struct insn_chain *, struct reload *, int);
 unsigned int regno = REGNO (x);
 if (regno < FIRST_PSEUDO_REGISTER)
 	return;
-x = eliminate_regs (x, mem_mode, usage);
+x = eliminate_regs_1 (x, mem_mode, usage, true, false);
 if (x != *loc)
 	{
 	  *loc = x;
 	  replace_pseudos_in (loc, mem_mode, usage);
 	  return;
 	}
 if (reg_equiv_constant[regno])
 	*loc = reg_equiv_constant[regno];
+else if (reg_equiv_invariant[regno])
+	*loc = reg_equiv_invariant[regno];
 else if (reg_equiv_mem[regno])
 	*loc = reg_equiv_mem[regno];
 else if (reg_equiv_address[regno])
 	*loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
 else
 free (worklist);
 /* Now see if there's a reachable block with an exceptional incoming
 edge.  */
 FOR_EACH_BB (bb)
-if (bb->flags & BB_REACHABLE)
+if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
-FOR_EACH_EDGE (e, ei, bb->preds)
+return true;
-	if (e->flags & EDGE_ABNORMAL)
-	  return true;
 /* No exceptional block reached exit unexceptionally.  */
 return false;
 }
 /* Global variables used by reload and its subroutines.  */
+/* The current basic block while in calculate_elim_costs_all_insns.  */
+static basic_block elim_bb;
 /* Set during calculate_needs if an insn needs register elimination.  */
 static int something_needs_elimination;
 /* Set during calculate_needs if an insn needs an operand changed.  */
 static int something_needs_operands_changed;
 if (crtl->saves_all_registers)
 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
 	df_set_regs_ever_live (i, true);
-/* Find all the pseudo registers that didn't get hard regs
+reg_old_renumber = XCNEWVEC (short, max_regno);
-but do have known equivalent constants or memory slots.
+memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
-These include parameters (known equivalent to parameter slots)
+pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
-and cse'd or loop-moved constant memory addresses.
+pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
-Record constant equivalents in reg_equiv_constant
+CLEAR_HARD_REG_SET (bad_spill_regs_global);
-so they will be substituted by find_reloads.
-Record memory equivalents in reg_mem_equiv so they can
+init_eliminable_invariants (first, true);
-be substituted eventually by altering the REG-rtx's.  */
+init_elim_table ();
+/* Alter each pseudo-reg rtx to contain its hard reg number.  Assign
+stack slots to the pseudos that lack hard regs or equivalents.
+Do not touch virtual registers.  */
+temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
+for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
+temp_pseudo_reg_arr[n++] = i;
+if (ira_conflicts_p)
+/* Ask IRA to order pseudo-registers for better stack slot
+sharing.  */
+ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
+for (i = 0; i < n; i++)
+alter_reg (temp_pseudo_reg_arr[i], -1, false);
+/* If we have some registers we think can be eliminated, scan all insns to
+see if there is an insn that sets one of these registers to something
+other than itself plus a constant.  If so, the register cannot be
+eliminated.  Doing this scan here eliminates an extra pass through the
+main reload loop in the most common case where register elimination
+cannot be done.  */
+for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
+if (INSN_P (insn))
+note_stores (PATTERN (insn), mark_not_eliminable, NULL);
+maybe_fix_stack_asms ();
+insns_need_reload = 0;
+something_needs_elimination = 0;
+/* Initialize to -1, which means take the first spill register.  */
+last_spill_reg = -1;
+/* Spill any hard regs that we know we can't eliminate.  */
+CLEAR_HARD_REG_SET (used_spill_regs);
+/* There can be multiple ways to eliminate a register;
+they should be listed adjacently.
+Elimination for any register fails only if all possible ways fail.  */
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; )
+{
+int from = ep->from;
+int can_eliminate = 0;
+do
+	{
+can_eliminate |= ep->can_eliminate;
+ep++;
+	}
+while (ep < &reg_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
+if (! can_eliminate)
+	spill_hard_reg (from, 1);
+}
+#if !HARD_FRAME_POINTER_IS_FRAME_POINTER
+if (frame_pointer_needed)
+spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
+#endif
+finish_spills (global);
+/* From now on, we may need to generate moves differently.  We may also
+allow modifications of insns which cause them to not be recognized.
+Any such modifications will be cleaned up during reload itself.  */
+reload_in_progress = 1;
+/* This loop scans the entire function each go-round
+and repeats until one repetition spills no additional hard regs.  */
+for (;;)
+{
+int something_changed;
+int did_spill;
+HOST_WIDE_INT starting_frame_size;
+starting_frame_size = get_frame_size ();
+something_was_spilled = false;
+set_initial_elim_offsets ();
+set_initial_label_offsets ();
+/* For each pseudo register that has an equivalent location defined,
+	 try to eliminate any eliminable registers (such as the frame pointer)
+	 assuming initial offsets for the replacement register, which
+	 is the normal case.
+	 If the resulting location is directly addressable, substitute
+	 the MEM we just got directly for the old REG.
+	 If it is not addressable but is a constant or the sum of a hard reg
+	 and constant, it is probably not addressable because the constant is
+	 out of range, in that case record the address; we will generate
+	 hairy code to compute the address in a register each time it is
+	 needed.  Similarly if it is a hard register, but one that is not
+	 valid as an address register.
+	 If the location is not addressable, but does not have one of the
+	 above forms, assign a stack slot.  We have to do this to avoid the
+	 potential of producing lots of reloads if, e.g., a location involves
+	 a pseudo that didn't get a hard register and has an equivalent memory
+	 location that also involves a pseudo that didn't get a hard register.
+	 Perhaps at some point we will improve reload_when_needed handling
+	 so this problem goes away.  But that's very hairy.  */
+for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
+	if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
+	  {
+	    rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
+				    NULL_RTX);
+	    if (strict_memory_address_addr_space_p
+		  (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
+		   MEM_ADDR_SPACE (x)))
+	      reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
+	    else if (CONSTANT_P (XEXP (x, 0))
+		     || (REG_P (XEXP (x, 0))
+			 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
+		     || (GET_CODE (XEXP (x, 0)) == PLUS
+			 && REG_P (XEXP (XEXP (x, 0), 0))
+			 && (REGNO (XEXP (XEXP (x, 0), 0))
+			     < FIRST_PSEUDO_REGISTER)
+			 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
+	      reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
+	    else
+	      {
+		/* Make a new stack slot.  Then indicate that something
+		   changed so we go back and recompute offsets for
+		   eliminable registers because the allocation of memory
+		   below might change some offset.  reg_equiv_{mem,address}
+		   will be set up for this pseudo on the next pass around
+		   the loop.  */
+		reg_equiv_memory_loc[i] = 0;
+		reg_equiv_init[i] = 0;
+		alter_reg (i, -1, true);
+	      }
+	  }
+if (caller_save_needed)
+	setup_save_areas ();
+/* If we allocated another stack slot, redo elimination bookkeeping.  */
+if (something_was_spilled || starting_frame_size != get_frame_size ())
+	continue;
+if (starting_frame_size && crtl->stack_alignment_needed)
+	{
+	  /* If we have a stack frame, we must align it now.  The
+	     stack size may be a part of the offset computation for
+	     register elimination.  So if this changes the stack size,
+	     then repeat the elimination bookkeeping.  We don't
+	     realign when there is no stack, as that will cause a
+	     stack frame when none is needed should
+	     STARTING_FRAME_OFFSET not be already aligned to
+	     STACK_BOUNDARY.  */
+	  assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
+	  if (starting_frame_size != get_frame_size ())
+	    continue;
+	}
+if (caller_save_needed)
+	{
+	  save_call_clobbered_regs ();
+	  /* That might have allocated new insn_chain structures.  */
+	  reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
+	}
+calculate_needs_all_insns (global);
+if (! ira_conflicts_p)
+	/* Don't do it for IRA.  We need this info because we don't
+	   change live_throughout and dead_or_set for chains when IRA
+	   is used.  */
+	CLEAR_REG_SET (&spilled_pseudos);
+did_spill = 0;
+something_changed = 0;
+/* If we allocated any new memory locations, make another pass
+	 since it might have changed elimination offsets.  */
+if (something_was_spilled || starting_frame_size != get_frame_size ())
+	something_changed = 1;
+/* Even if the frame size remained the same, we might still have
+	 changed elimination offsets, e.g. if find_reloads called
+	 force_const_mem requiring the back end to allocate a constant
+	 pool base register that needs to be saved on the stack.  */
+else if (!verify_initial_elim_offsets ())
+	something_changed = 1;
+{
+	HARD_REG_SET to_spill;
+	CLEAR_HARD_REG_SET (to_spill);
+	update_eliminables (&to_spill);
+	AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
+	for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+	  if (TEST_HARD_REG_BIT (to_spill, i))
+	    {
+	      spill_hard_reg (i, 1);
+	      did_spill = 1;
+	      /* Regardless of the state of spills, if we previously had
+		 a register that we thought we could eliminate, but now can
+		 not eliminate, we must run another pass.
+		 Consider pseudos which have an entry in reg_equiv_* which
+		 reference an eliminable register.  We must make another pass
+		 to update reg_equiv_* so that we do not substitute in the
+		 old value from when we thought the elimination could be
+		 performed.  */
+	      something_changed = 1;
+	    }
+}
+select_reload_regs ();
+if (failure)
+	goto failed;
+if (insns_need_reload != 0 || did_spill)
+	something_changed |= finish_spills (global);
+if (! something_changed)
+	break;
+if (caller_save_needed)
+	delete_caller_save_insns ();
+obstack_free (&reload_obstack, reload_firstobj);
+}
+/* If global-alloc was run, notify it of any register eliminations we have
+done.  */
+if (global)
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+if (ep->can_eliminate)
+	mark_elimination (ep->from, ep->to);
+/* If a pseudo has no hard reg, delete the insns that made the equivalence.
+If that insn didn't set the register (i.e., it copied the register to
+memory), just delete that insn instead of the equivalencing insn plus
+anything now dead.  If we call delete_dead_insn on that insn, we may
+delete the insn that actually sets the register if the register dies
+there and that is incorrect.  */
+for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
+{
+if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
+	{
+	  rtx list;
+	  for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
+	    {
+	      rtx equiv_insn = XEXP (list, 0);
+	      /* If we already deleted the insn or if it may trap, we can't
+		 delete it.  The latter case shouldn't happen, but can
+		 if an insn has a variable address, gets a REG_EH_REGION
+		 note added to it, and then gets converted into a load
+		 from a constant address.  */
+	      if (NOTE_P (equiv_insn)
+		  || can_throw_internal (equiv_insn))
+		;
+	      else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
+		delete_dead_insn (equiv_insn);
+	      else
+		SET_INSN_DELETED (equiv_insn);
+	    }
+	}
+}
+/* Use the reload registers where necessary
+by generating move instructions to move the must-be-register
+values into or out of the reload registers.  */
+if (insns_need_reload != 0 || something_needs_elimination
+|| something_needs_operands_changed)
+{
+HOST_WIDE_INT old_frame_size = get_frame_size ();
+reload_as_needed (global);
+gcc_assert (old_frame_size == get_frame_size ());
+gcc_assert (verify_initial_elim_offsets ());
+}
+/* If we were able to eliminate the frame pointer, show that it is no
+longer live at the start of any basic block.  If it ls live by
+virtue of being in a pseudo, that pseudo will be marked live
+and hence the frame pointer will be known to be live via that
+pseudo.  */
+if (! frame_pointer_needed)
+FOR_EACH_BB (bb)
+bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
+/* Come here (with failure set nonzero) if we can't get enough spill
+regs.  */
+failed:
+CLEAR_REG_SET (&changed_allocation_pseudos);
+CLEAR_REG_SET (&spilled_pseudos);
+reload_in_progress = 0;
+/* Now eliminate all pseudo regs by modifying them into
+their equivalent memory references.
+The REG-rtx's for the pseudos are modified in place,
+so all insns that used to refer to them now refer to memory.
+For a reg that has a reg_equiv_address, all those insns
+were changed by reloading so that no insns refer to it any longer;
+but the DECL_RTL of a variable decl may refer to it,
+and if so this causes the debugging info to mention the variable.  */
+for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
+{
+rtx addr = 0;
+if (reg_equiv_mem[i])
+	addr = XEXP (reg_equiv_mem[i], 0);
+if (reg_equiv_address[i])
+	addr = reg_equiv_address[i];
+if (addr)
+	{
+	  if (reg_renumber[i] < 0)
+	    {
+	      rtx reg = regno_reg_rtx[i];
+	      REG_USERVAR_P (reg) = 0;
+	      PUT_CODE (reg, MEM);
+	      XEXP (reg, 0) = addr;
+	      if (reg_equiv_memory_loc[i])
+		MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
+	      else
+		{
+		  MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
+		  MEM_ATTRS (reg) = 0;
+		}
+	      MEM_NOTRAP_P (reg) = 1;
+	    }
+	  else if (reg_equiv_mem[i])
+	    XEXP (reg_equiv_mem[i], 0) = addr;
+	}
+/* We don't want complex addressing modes in debug insns
+	 if simpler ones will do, so delegitimize equivalences
+	 in debug insns.  */
+if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
+	{
+	  rtx reg = regno_reg_rtx[i];
+	  rtx equiv = 0;
+	  df_ref use, next;
+	  if (reg_equiv_constant[i])
+	    equiv = reg_equiv_constant[i];
+	  else if (reg_equiv_invariant[i])
+	    equiv = reg_equiv_invariant[i];
+	  else if (reg && MEM_P (reg))
+	    equiv = targetm.delegitimize_address (reg);
+	  else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
+	    equiv = reg;
+	  if (equiv == reg)
+	    continue;
+	  for (use = DF_REG_USE_CHAIN (i); use; use = next)
+	    {
+	      insn = DF_REF_INSN (use);
+	      /* Make sure the next ref is for a different instruction,
+		 so that we're not affected by the rescan.  */
+	      next = DF_REF_NEXT_REG (use);
+	      while (next && DF_REF_INSN (next) == insn)
+		next = DF_REF_NEXT_REG (next);
+	      if (DEBUG_INSN_P (insn))
+		{
+		  if (!equiv)
+		    {
+		      INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
+		      df_insn_rescan_debug_internal (insn);
+		    }
+		  else
+		    INSN_VAR_LOCATION_LOC (insn)
+		      = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
+					      reg, equiv);
+		}
+	    }
+	}
+}
+/* We must set reload_completed now since the cleanup_subreg_operands call
+below will re-recognize each insn and reload may have generated insns
+which are only valid during and after reload.  */
+reload_completed = 1;
+/* Make a pass over all the insns and delete all USEs which we inserted
+only to tag a REG_EQUAL note on them.  Remove all REG_DEAD and REG_UNUSED
+notes.  Delete all CLOBBER insns, except those that refer to the return
+value and the special mem:BLK CLOBBERs added to prevent the scheduler
+from misarranging variable-array code, and simplify (subreg (reg))
+operands.  Strip and regenerate REG_INC notes that may have been moved
+around.  */
+for (insn = first; insn; insn = NEXT_INSN (insn))
+if (INSN_P (insn))
+{
+	rtx *pnote;
+	if (CALL_P (insn))
+	  replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
+			      VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
+	if ((GET_CODE (PATTERN (insn)) == USE
+	     /* We mark with QImode USEs introduced by reload itself.  */
+	     && (GET_MODE (insn) == QImode
+		 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
+	    || (GET_CODE (PATTERN (insn)) == CLOBBER
+		&& (!MEM_P (XEXP (PATTERN (insn), 0))
+		    || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
+		    || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
+			&& XEXP (XEXP (PATTERN (insn), 0), 0)
+				!= stack_pointer_rtx))
+		&& (!REG_P (XEXP (PATTERN (insn), 0))
+		    || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
+	  {
+	    delete_insn (insn);
+	    continue;
+	  }
+	/* Some CLOBBERs may survive until here and still reference unassigned
+	   pseudos with const equivalent, which may in turn cause ICE in later
+	   passes if the reference remains in place.  */
+	if (GET_CODE (PATTERN (insn)) == CLOBBER)
+	  replace_pseudos_in (& XEXP (PATTERN (insn), 0),
+			      VOIDmode, PATTERN (insn));
+	/* Discard obvious no-ops, even without -O.  This optimization
+	   is fast and doesn't interfere with debugging.  */
+	if (NONJUMP_INSN_P (insn)
+	    && GET_CODE (PATTERN (insn)) == SET
+	    && REG_P (SET_SRC (PATTERN (insn)))
+	    && REG_P (SET_DEST (PATTERN (insn)))
+	    && (REGNO (SET_SRC (PATTERN (insn)))
+		== REGNO (SET_DEST (PATTERN (insn)))))
+	  {
+	    delete_insn (insn);
+	    continue;
+	  }
+	pnote = &REG_NOTES (insn);
+	while (*pnote != 0)
+	  {
+	    if (REG_NOTE_KIND (*pnote) == REG_DEAD
+		|| REG_NOTE_KIND (*pnote) == REG_UNUSED
+		|| REG_NOTE_KIND (*pnote) == REG_INC)
+	      *pnote = XEXP (*pnote, 1);
+	    else
+	      pnote = &XEXP (*pnote, 1);
+	  }
+#ifdef AUTO_INC_DEC
+	add_auto_inc_notes (insn, PATTERN (insn));
+#endif
+	/* Simplify (subreg (reg)) if it appears as an operand.  */
+	cleanup_subreg_operands (insn);
+	/* Clean up invalid ASMs so that they don't confuse later passes.
+	   See PR 21299.  */
+	if (asm_noperands (PATTERN (insn)) >= 0)
+	  {
+	    extract_insn (insn);
+	    if (!constrain_operands (1))
+	      {
+		error_for_asm (insn,
+			       "%<asm%> operand has impossible constraints");
+		delete_insn (insn);
+		continue;
+	      }
+	  }
+}
+/* If we are doing generic stack checking, give a warning if this
+function's frame size is larger than we expect.  */
+if (flag_stack_check == GENERIC_STACK_CHECK)
+{
+HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
+static int verbose_warned = 0;
+for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+	if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
+	  size += UNITS_PER_WORD;
+if (size > STACK_CHECK_MAX_FRAME_SIZE)
+	{
+	  warning (0, "frame size too large for reliable stack checking");
+	  if (! verbose_warned)
+	    {
+	      warning (0, "try reducing the number of local variables");
+	      verbose_warned = 1;
+	    }
+	}
+}
+free (temp_pseudo_reg_arr);
+/* Indicate that we no longer have known memory locations or constants.  */
+free_reg_equiv ();
+reg_equiv_init = 0;
+free (reg_max_ref_width);
+free (reg_old_renumber);
+free (pseudo_previous_regs);
+free (pseudo_forbidden_regs);
+CLEAR_HARD_REG_SET (used_spill_regs);
+for (i = 0; i < n_spills; i++)
+SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
+/* Free all the insn_chain structures at once.  */
+obstack_free (&reload_obstack, reload_startobj);
+unused_insn_chains = 0;
+fixup_abnormal_edges ();
+/* Replacing pseudos with their memory equivalents might have
+created shared rtx.  Subsequent passes would get confused
+by this, so unshare everything here.  */
+unshare_all_rtl_again (first);
+#ifdef STACK_BOUNDARY
+/* init_emit has set the alignment of the hard frame pointer
+to STACK_BOUNDARY.  It is very likely no longer valid if
+the hard frame pointer was used for register allocation.  */
+if (!frame_pointer_needed)
+REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
+#endif
+VEC_free (rtx_p, heap, substitute_stack);
+gcc_assert (bitmap_empty_p (&spilled_pseudos));
+return failure;
+}
+/* Yet another special case.  Unfortunately, reg-stack forces people to
+write incorrect clobbers in asm statements.  These clobbers must not
+cause the register to appear in bad_spill_regs, otherwise we'll call
+fatal_insn later.  We clear the corresponding regnos in the live
+register sets to avoid this.
+The whole thing is rather sick, I'm afraid.  */
+static void
+maybe_fix_stack_asms (void)
+{
+#ifdef STACK_REGS
+const char *constraints[MAX_RECOG_OPERANDS];
+enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
+struct insn_chain *chain;
+for (chain = reload_insn_chain; chain != 0; chain = chain->next)
+{
+int i, noperands;
+HARD_REG_SET clobbered, allowed;
+rtx pat;
+if (! INSN_P (chain->insn)
+	  || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
+	continue;
+pat = PATTERN (chain->insn);
+if (GET_CODE (pat) != PARALLEL)
+	continue;
+CLEAR_HARD_REG_SET (clobbered);
+CLEAR_HARD_REG_SET (allowed);
+/* First, make a mask of all stack regs that are clobbered.  */
+for (i = 0; i < XVECLEN (pat, 0); i++)
+	{
+	  rtx t = XVECEXP (pat, 0, i);
+	  if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
+	    SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
+	}
+/* Get the operand values and constraints out of the insn.  */
+decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
+			   constraints, operand_mode, NULL);
+/* For every operand, see what registers are allowed.  */
+for (i = 0; i < noperands; i++)
+	{
+	  const char *p = constraints[i];
+	  /* For every alternative, we compute the class of registers allowed
+	     for reloading in CLS, and merge its contents into the reg set
+	     ALLOWED.  */
+	  int cls = (int) NO_REGS;
+	  for (;;)
+	    {
+	      char c = *p;
+	      if (c == '\0' || c == ',' || c == '#')
+		{
+		  /* End of one alternative - mark the regs in the current
+		     class, and reset the class.  */
+		  IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
+		  cls = NO_REGS;
+		  p++;
+		  if (c == '#')
+		    do {
+		      c = *p++;
+		    } while (c != '\0' && c != ',');
+		  if (c == '\0')
+		    break;
+		  continue;
+		}
+	      switch (c)
+		{
+		case '=': case '+': case '*': case '%': case '?': case '!':
+		case '0': case '1': case '2': case '3': case '4': case '<':
+		case '>': case 'V': case 'o': case '&': case 'E': case 'F':
+		case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
+		case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
+		case TARGET_MEM_CONSTRAINT:
+		  break;
+		case 'p':
+		  cls = (int) reg_class_subunion[cls]
+		      [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
+		  break;
+		case 'g':
+		case 'r':
+		  cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
+		  break;
+		default:
+		  if (EXTRA_ADDRESS_CONSTRAINT (c, p))
+		    cls = (int) reg_class_subunion[cls]
+		      [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
+		  else
+		    cls = (int) reg_class_subunion[cls]
+		      [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
+		}
+	      p += CONSTRAINT_LEN (c, p);
+	    }
+	}
+/* Those of the registers which are clobbered, but allowed by the
+	 constraints, must be usable as reload registers.  So clear them
+	 out of the life information.  */
+AND_HARD_REG_SET (allowed, clobbered);
+for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+	if (TEST_HARD_REG_BIT (allowed, i))
+	  {
+	    CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
+	    CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
+	  }
+}
+#endif
+}
+/* Copy the global variables n_reloads and rld into the corresponding elts
+of CHAIN.  */
+static void
+copy_reloads (struct insn_chain *chain)
+{
+chain->n_reloads = n_reloads;
+chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
+memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
+reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
+}
+/* Walk the chain of insns, and determine for each whether it needs reloads
+and/or eliminations.  Build the corresponding insns_need_reload list, and
+set something_needs_elimination as appropriate.  */
+static void
+calculate_needs_all_insns (int global)
+{
+struct insn_chain **pprev_reload = &insns_need_reload;
+struct insn_chain *chain, *next = 0;
+something_needs_elimination = 0;
+reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
+for (chain = reload_insn_chain; chain != 0; chain = next)
+{
+rtx insn = chain->insn;
+next = chain->next;
+/* Clear out the shortcuts.  */
+chain->n_reloads = 0;
+chain->need_elim = 0;
+chain->need_reload = 0;
+chain->need_operand_change = 0;
+/* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
+	 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
+	 what effects this has on the known offsets at labels.  */
+if (LABEL_P (insn) || JUMP_P (insn)
+	  || (INSN_P (insn) && REG_NOTES (insn) != 0))
+	set_label_offsets (insn, insn, 0);
+if (INSN_P (insn))
+	{
+	  rtx old_body = PATTERN (insn);
+	  int old_code = INSN_CODE (insn);
+	  rtx old_notes = REG_NOTES (insn);
+	  int did_elimination = 0;
+	  int operands_changed = 0;
+	  rtx set = single_set (insn);
+	  /* Skip insns that only set an equivalence.  */
+	  if (set && REG_P (SET_DEST (set))
+	      && reg_renumber[REGNO (SET_DEST (set))] < 0
+	      && (reg_equiv_constant[REGNO (SET_DEST (set))]
+		  || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
+		      && reg_equiv_init[REGNO (SET_DEST (set))])
+	    continue;
+	  /* If needed, eliminate any eliminable registers.  */
+	  if (num_eliminable || num_eliminable_invariants)
+	    did_elimination = eliminate_regs_in_insn (insn, 0);
+	  /* Analyze the instruction.  */
+	  operands_changed = find_reloads (insn, 0, spill_indirect_levels,
+					   global, spill_reg_order);
+	  /* If a no-op set needs more than one reload, this is likely
+	     to be something that needs input address reloads.  We
+	     can't get rid of this cleanly later, and it is of no use
+	     anyway, so discard it now.
+	     We only do this when expensive_optimizations is enabled,
+	     since this complements reload inheritance / output
+	     reload deletion, and it can make debugging harder.  */
+	  if (flag_expensive_optimizations && n_reloads > 1)
+	    {
+	      rtx set = single_set (insn);
+	      if (set
+		  &&
+		  ((SET_SRC (set) == SET_DEST (set)
+		    && REG_P (SET_SRC (set))
+		    && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
+		   || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
+		       && reg_renumber[REGNO (SET_SRC (set))] < 0
+		       && reg_renumber[REGNO (SET_DEST (set))] < 0
+		       && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
+		       && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
+		       && rtx_equal_p (reg_equiv_memory_loc
+				       [REGNO (SET_SRC (set))],
+				       reg_equiv_memory_loc
+				       [REGNO (SET_DEST (set))]))))
+		{
+		  if (ira_conflicts_p)
+		    /* Inform IRA about the insn deletion.  */
+		    ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
+						   REGNO (SET_SRC (set)));
+		  delete_insn (insn);
+		  /* Delete it from the reload chain.  */
+		  if (chain->prev)
+		    chain->prev->next = next;
+		  else
+		    reload_insn_chain = next;
+		  if (next)
+		    next->prev = chain->prev;
+		  chain->next = unused_insn_chains;
+		  unused_insn_chains = chain;
+		  continue;
+		}
+	    }
+	  if (num_eliminable)
+	    update_eliminable_offsets ();
+	  /* Remember for later shortcuts which insns had any reloads or
+	     register eliminations.  */
+	  chain->need_elim = did_elimination;
+	  chain->need_reload = n_reloads > 0;
+	  chain->need_operand_change = operands_changed;
+	  /* Discard any register replacements done.  */
+	  if (did_elimination)
+	    {
+	      obstack_free (&reload_obstack, reload_insn_firstobj);
+	      PATTERN (insn) = old_body;
+	      INSN_CODE (insn) = old_code;
+	      REG_NOTES (insn) = old_notes;
+	      something_needs_elimination = 1;
+	    }
+	  something_needs_operands_changed |= operands_changed;
+	  if (n_reloads != 0)
+	    {
+	      copy_reloads (chain);
+	      *pprev_reload = chain;
+	      pprev_reload = &chain->next_need_reload;
+	    }
+	}
+}
+*pprev_reload = 0;
+}
+/* This function is called from the register allocator to set up estimates
+for the cost of eliminating pseudos which have REG_EQUIV equivalences to
+an invariant.  The structure is similar to calculate_needs_all_insns.  */
+void
+calculate_elim_costs_all_insns (void)
+{
+int *reg_equiv_init_cost;
+basic_block bb;
+int i;
+reg_equiv_init_cost = XCNEWVEC (int, max_regno);
+init_elim_table ();
+init_eliminable_invariants (get_insns (), false);
+set_initial_elim_offsets ();
+set_initial_label_offsets ();
+FOR_EACH_BB (bb)
+{
+rtx insn;
+elim_bb = bb;
+FOR_BB_INSNS (bb, insn)
+	{
+	  /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
+	     include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
+	     what effects this has on the known offsets at labels.  */
+	  if (LABEL_P (insn) || JUMP_P (insn)
+	      || (INSN_P (insn) && REG_NOTES (insn) != 0))
+	    set_label_offsets (insn, insn, 0);
+	  if (INSN_P (insn))
+	    {
+	      rtx set = single_set (insn);
+	      /* Skip insns that only set an equivalence.  */
+	      if (set && REG_P (SET_DEST (set))
+		  && reg_renumber[REGNO (SET_DEST (set))] < 0
+		  && (reg_equiv_constant[REGNO (SET_DEST (set))]
+		      || (reg_equiv_invariant[REGNO (SET_DEST (set))])))
+		{
+		  unsigned regno = REGNO (SET_DEST (set));
+		  rtx init = reg_equiv_init[regno];
+		  if (init)
+		    {
+		      rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
+						false, true);
+		      int cost = rtx_cost (t, SET,
+					   optimize_bb_for_speed_p (bb));
+		      int freq = REG_FREQ_FROM_BB (bb);
+		      reg_equiv_init_cost[regno] = cost * freq;
+		      continue;
+		    }
+		}
+	      /* If needed, eliminate any eliminable registers.  */
+	      if (num_eliminable || num_eliminable_invariants)
+		elimination_costs_in_insn (insn);
+	      if (num_eliminable)
+		update_eliminable_offsets ();
+	    }
+	}
+}
+for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
+{
+if (reg_equiv_invariant[i])
+	{
+	  if (reg_equiv_init[i])
+	    {
+	      int cost = reg_equiv_init_cost[i];
+	      if (dump_file)
+		fprintf (dump_file,
+			 "Reg %d has equivalence, initial gains %d\n", i, cost);
+	      if (cost != 0)
+		ira_adjust_equiv_reg_cost (i, cost);
+	    }
+	  else
+	    {
+	      if (dump_file)
+		fprintf (dump_file,
+			 "Reg %d had equivalence, but can't be eliminated\n",
+			 i);
+	      ira_adjust_equiv_reg_cost (i, 0);
+	    }
+	}
+}
+free_reg_equiv ();
+free (reg_equiv_init_cost);
+}
+/* Comparison function for qsort to decide which of two reloads
+should be handled first.  *P1 and *P2 are the reload numbers.  */
+static int
+reload_reg_class_lower (const void *r1p, const void *r2p)
+{
+int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
+int t;
+/* Consider required reloads before optional ones.  */
+t = rld[r1].optional - rld[r2].optional;
+if (t != 0)
+return t;
+/* Count all solitary classes before non-solitary ones.  */
+t = ((reg_class_size[(int) rld[r2].rclass] == 1)
+- (reg_class_size[(int) rld[r1].rclass] == 1));
+if (t != 0)
+return t;
+/* Aside from solitaires, consider all multi-reg groups first.  */
+t = rld[r2].nregs - rld[r1].nregs;
+if (t != 0)
+return t;
+/* Consider reloads in order of increasing reg-class number.  */
+t = (int) rld[r1].rclass - (int) rld[r2].rclass;
+if (t != 0)
+return t;
+/* If reloads are equally urgent, sort by reload number,
+so that the results of qsort leave nothing to chance.  */
+return r1 - r2;
+}
+/* The cost of spilling each hard reg.  */
+static int spill_cost[FIRST_PSEUDO_REGISTER];
+/* When spilling multiple hard registers, we use SPILL_COST for the first
+spilled hard reg and SPILL_ADD_COST for subsequent regs.  SPILL_ADD_COST
+only the first hard reg for a multi-reg pseudo.  */
+static int spill_add_cost[FIRST_PSEUDO_REGISTER];
+/* Map of hard regno to pseudo regno currently occupying the hard
+reg.  */
+static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
+/* Update the spill cost arrays, considering that pseudo REG is live.  */
+static void
+count_pseudo (int reg)
+{
+int freq = REG_FREQ (reg);
+int r = reg_renumber[reg];
+int nregs;
+if (REGNO_REG_SET_P (&pseudos_counted, reg)
+|| REGNO_REG_SET_P (&spilled_pseudos, reg)
+/* Ignore spilled pseudo-registers which can be here only if IRA
+	 is used.  */
+|| (ira_conflicts_p && r < 0))
+return;
+SET_REGNO_REG_SET (&pseudos_counted, reg);
+gcc_assert (r >= 0);
+spill_add_cost[r] += freq;
+nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
+while (nregs-- > 0)
+{
+hard_regno_to_pseudo_regno[r + nregs] = reg;
+spill_cost[r + nregs] += freq;
+}
+}
+/* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
+contents of BAD_SPILL_REGS for the insn described by CHAIN.  */
+static void
+order_regs_for_reload (struct insn_chain *chain)
+{
+unsigned i;
+HARD_REG_SET used_by_pseudos;
+HARD_REG_SET used_by_pseudos2;
+reg_set_iterator rsi;
+COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
+memset (spill_cost, 0, sizeof spill_cost);
+memset (spill_add_cost, 0, sizeof spill_add_cost);
+for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+hard_regno_to_pseudo_regno[i] = -1;
+/* Count number of uses of each hard reg by pseudo regs allocated to it
+and then order them by decreasing use.  First exclude hard registers
+that are live in or across this insn.  */
+REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
+REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
+IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
+IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
+/* Now find out which pseudos are allocated to it, and update
+hard_reg_n_uses.  */
+CLEAR_REG_SET (&pseudos_counted);
+EXECUTE_IF_SET_IN_REG_SET
+(&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
+{
+count_pseudo (i);
+}
+EXECUTE_IF_SET_IN_REG_SET
+(&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
+{
+count_pseudo (i);
+}
+CLEAR_REG_SET (&pseudos_counted);
+}
+/* Vector of reload-numbers showing the order in which the reloads should
+be processed.  */
+static short reload_order[MAX_RELOADS];
+/* This is used to keep track of the spill regs used in one insn.  */
+static HARD_REG_SET used_spill_regs_local;
+/* We decided to spill hard register SPILLED, which has a size of
+SPILLED_NREGS.  Determine how pseudo REG, which is live during the insn,
+is affected.  We will add it to SPILLED_PSEUDOS if necessary, and we will
+update SPILL_COST/SPILL_ADD_COST.  */
+static void
+count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
+{
+int freq = REG_FREQ (reg);
+int r = reg_renumber[reg];
+int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
+/* Ignore spilled pseudo-registers which can be here only if IRA is
+used.  */
+if ((ira_conflicts_p && r < 0)
+|| REGNO_REG_SET_P (&spilled_pseudos, reg)
+|| spilled + spilled_nregs <= r || r + nregs <= spilled)
+return;
+SET_REGNO_REG_SET (&spilled_pseudos, reg);
+spill_add_cost[r] -= freq;
+while (nregs-- > 0)
+{
+hard_regno_to_pseudo_regno[r + nregs] = -1;
+spill_cost[r + nregs] -= freq;
+}
+}
+/* Find reload register to use for reload number ORDER.  */
+static int
+find_reg (struct insn_chain *chain, int order)
+{
+int rnum = reload_order[order];
+struct reload *rl = rld + rnum;
+int best_cost = INT_MAX;
+int best_reg = -1;
+unsigned int i, j, n;
+int k;
+HARD_REG_SET not_usable;
+HARD_REG_SET used_by_other_reload;
+reg_set_iterator rsi;
+static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
+static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
+COPY_HARD_REG_SET (not_usable, bad_spill_regs);
+IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
+IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
+CLEAR_HARD_REG_SET (used_by_other_reload);
+for (k = 0; k < order; k++)
+{
+int other = reload_order[k];
+if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
+	for (j = 0; j < rld[other].nregs; j++)
+	  SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
+}
+for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+{
+#ifdef REG_ALLOC_ORDER
+unsigned int regno = reg_alloc_order[i];
+#else
+unsigned int regno = i;
+#endif
+if (! TEST_HARD_REG_BIT (not_usable, regno)
+	  && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
+	  && HARD_REGNO_MODE_OK (regno, rl->mode))
+	{
+	  int this_cost = spill_cost[regno];
+	  int ok = 1;
+	  unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
+	  for (j = 1; j < this_nregs; j++)
+	    {
+	      this_cost += spill_add_cost[regno + j];
+	      if ((TEST_HARD_REG_BIT (not_usable, regno + j))
+		  || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
+		ok = 0;
+	    }
+	  if (! ok)
+	    continue;
+	  if (ira_conflicts_p)
+	    {
+	      /* Ask IRA to find a better pseudo-register for
+		 spilling.  */
+	      for (n = j = 0; j < this_nregs; j++)
+		{
+		  int r = hard_regno_to_pseudo_regno[regno + j];
+		  if (r < 0)
+		    continue;
+		  if (n == 0 || regno_pseudo_regs[n - 1] != r)
+		    regno_pseudo_regs[n++] = r;
+		}
+	      regno_pseudo_regs[n++] = -1;
+	      if (best_reg < 0
+		  || ira_better_spill_reload_regno_p (regno_pseudo_regs,
+						      best_regno_pseudo_regs,
+						      rl->in, rl->out,
+						      chain->insn))
+		{
+		  best_reg = regno;
+		  for (j = 0;; j++)
+		    {
+		      best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
+		      if (regno_pseudo_regs[j] < 0)
+			break;
+		    }
+		}
+	      continue;
+	    }
+	  if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
+	    this_cost--;
+	  if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
+	    this_cost--;
+	  if (this_cost < best_cost
+	      /* Among registers with equal cost, prefer caller-saved ones, or
+		 use REG_ALLOC_ORDER if it is defined.  */
+	      || (this_cost == best_cost
+#ifdef REG_ALLOC_ORDER
+		  && (inv_reg_alloc_order[regno]
+		      < inv_reg_alloc_order[best_reg])
+#else
+		  && call_used_regs[regno]
+		  && ! call_used_regs[best_reg]
+#endif
+		  ))
+	    {
+	      best_reg = regno;
+	      best_cost = this_cost;
+	    }
+	}
+}
+if (best_reg == -1)
+return 0;
+if (dump_file)
+fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
+rl->nregs = hard_regno_nregs[best_reg][rl->mode];
+rl->regno = best_reg;
+EXECUTE_IF_SET_IN_REG_SET
+(&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
+{
+count_spilled_pseudo (best_reg, rl->nregs, j);
+}
+EXECUTE_IF_SET_IN_REG_SET
+(&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
+{
+count_spilled_pseudo (best_reg, rl->nregs, j);
+}
+for (i = 0; i < rl->nregs; i++)
+{
+gcc_assert (spill_cost[best_reg + i] == 0);
+gcc_assert (spill_add_cost[best_reg + i] == 0);
+gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
+SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
+}
+return 1;
+}
+/* Find more reload regs to satisfy the remaining need of an insn, which
+is given by CHAIN.
+Do it by ascending class number, since otherwise a reg
+might be spilled for a big class and might fail to count
+for a smaller class even though it belongs to that class.  */
+static void
+find_reload_regs (struct insn_chain *chain)
+{
+int i;
+/* In order to be certain of getting the registers we need,
+we must sort the reloads into order of increasing register class.
+Then our grabbing of reload registers will parallel the process
+that provided the reload registers.  */
+for (i = 0; i < chain->n_reloads; i++)
+{
+/* Show whether this reload already has a hard reg.  */
+if (chain->rld[i].reg_rtx)
+	{
+	  int regno = REGNO (chain->rld[i].reg_rtx);
+	  chain->rld[i].regno = regno;
+	  chain->rld[i].nregs
+	    = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
+	}
+else
+	chain->rld[i].regno = -1;
+reload_order[i] = i;
+}
+n_reloads = chain->n_reloads;
+memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
+CLEAR_HARD_REG_SET (used_spill_regs_local);
+if (dump_file)
+fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
+qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
+/* Compute the order of preference for hard registers to spill.  */
+order_regs_for_reload (chain);
+for (i = 0; i < n_reloads; i++)
+{
+int r = reload_order[i];
+/* Ignore reloads that got marked inoperative.  */
+if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
+	  && ! rld[r].optional
+	  && rld[r].regno == -1)
+	if (! find_reg (chain, i))
+	  {
+	    if (dump_file)
+	      fprintf (dump_file, "reload failure for reload %d\n", r);
+	    spill_failure (chain->insn, rld[r].rclass);
+	    failure = 1;
+	    return;
+	  }
+}
+COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
+IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
+memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
+}
+static void
+select_reload_regs (void)
+{
+struct insn_chain *chain;
+/* Try to satisfy the needs for each insn.  */
+for (chain = insns_need_reload; chain != 0;
+chain = chain->next_need_reload)
+find_reload_regs (chain);
+}
+/* Delete all insns that were inserted by emit_caller_save_insns during
+this iteration.  */
+static void
+delete_caller_save_insns (void)
+{
+struct insn_chain *c = reload_insn_chain;
+while (c != 0)
+{
+while (c != 0 && c->is_caller_save_insn)
+	{
+	  struct insn_chain *next = c->next;
+	  rtx insn = c->insn;
+	  if (c == reload_insn_chain)
+	    reload_insn_chain = next;
+	  delete_insn (insn);
+	  if (next)
+	    next->prev = c->prev;
+	  if (c->prev)
+	    c->prev->next = next;
+	  c->next = unused_insn_chains;
+	  unused_insn_chains = c;
+	  c = next;
+	}
+if (c != 0)
+	c = c->next;
+}
+}
+/* Handle the failure to find a register to spill.
+INSN should be one of the insns which needed this particular spill reg.  */
+static void
+spill_failure (rtx insn, enum reg_class rclass)
+{
+if (asm_noperands (PATTERN (insn)) >= 0)
+error_for_asm (insn, "can%'t find a register in class %qs while "
+		   "reloading %<asm%>",
+		   reg_class_names[rclass]);
+else
+{
+error ("unable to find a register to spill in class %qs",
+	     reg_class_names[rclass]);
+if (dump_file)
+	{
+	  fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
+	  debug_reload_to_stream (dump_file);
+	}
+fatal_insn ("this is the insn:", insn);
+}
+}
+/* Delete an unneeded INSN and any previous insns who sole purpose is loading
+data that is dead in INSN.  */
+static void
+delete_dead_insn (rtx insn)
+{
+rtx prev = prev_active_insn (insn);
+rtx prev_dest;
+/* If the previous insn sets a register that dies in our insn, delete it
+too.  */
+if (prev && GET_CODE (PATTERN (prev)) == SET
+&& (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
+&& reg_mentioned_p (prev_dest, PATTERN (insn))
+&& find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
+&& ! side_effects_p (SET_SRC (PATTERN (prev))))
+delete_dead_insn (prev);
+SET_INSN_DELETED (insn);
+}
+/* Modify the home of pseudo-reg I.
+The new home is present in reg_renumber[I].
+FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
+or it may be -1, meaning there is none or it is not relevant.
+This is used so that all pseudos spilled from a given hard reg
+can share one stack slot.  */
+static void
+alter_reg (int i, int from_reg, bool dont_share_p)
+{
+/* When outputting an inline function, this can happen
+for a reg that isn't actually used.  */
+if (regno_reg_rtx[i] == 0)
+return;
+/* If the reg got changed to a MEM at rtl-generation time,
+ignore it.  */
+if (!REG_P (regno_reg_rtx[i]))
+return;
+/* Modify the reg-rtx to contain the new hard reg
+number or else to contain its pseudo reg number.  */
+SET_REGNO (regno_reg_rtx[i],
+	     reg_renumber[i] >= 0 ? reg_renumber[i] : i);
+/* If we have a pseudo that is needed but has no hard reg or equivalent,
+allocate a stack slot for it.  */
+if (reg_renumber[i] < 0
+&& REG_N_REFS (i) > 0
+&& reg_equiv_constant[i] == 0
+&& (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
+&& reg_equiv_memory_loc[i] == 0)
+{
+rtx x = NULL_RTX;
+enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
+unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
+unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
+unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
+unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
+int adjust = 0;
+something_was_spilled = true;
+if (ira_conflicts_p)
+	{
+	  /* Mark the spill for IRA.  */
+	  SET_REGNO_REG_SET (&spilled_pseudos, i);
+	  if (!dont_share_p)
+	    x = ira_reuse_stack_slot (i, inherent_size, total_size);
+	}
+if (x)
+	;
+/* Each pseudo reg has an inherent size which comes from its own mode,
+	 and a total size which provides room for paradoxical subregs
+	 which refer to the pseudo reg in wider modes.
+	 We can use a slot already allocated if it provides both
+	 enough inherent space and enough total space.
+	 Otherwise, we allocate a new slot, making sure that it has no less
+	 inherent space, and no less total space, then the previous slot.  */
+else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
+	{
+	  rtx stack_slot;
+	  /* No known place to spill from => no slot to reuse.  */
+	  x = assign_stack_local (mode, total_size,
+				  min_align > inherent_align
+				  || total_size > inherent_size ? -1 : 0);
+	  stack_slot = x;
+	  /* Cancel the big-endian correction done in assign_stack_local.
+	     Get the address of the beginning of the slot.  This is so we
+	     can do a big-endian correction unconditionally below.  */
+	  if (BYTES_BIG_ENDIAN)
+	    {
+	      adjust = inherent_size - total_size;
+	      if (adjust)
+		stack_slot
+		  = adjust_address_nv (x, mode_for_size (total_size
+						         * BITS_PER_UNIT,
+						         MODE_INT, 1),
+				       adjust);
+	    }
+	  if (! dont_share_p && ira_conflicts_p)
+	    /* Inform IRA about allocation a new stack slot.  */
+	    ira_mark_new_stack_slot (stack_slot, i, total_size);
+	}
+/* Reuse a stack slot if possible.  */
+else if (spill_stack_slot[from_reg] != 0
+	       && spill_stack_slot_width[from_reg] >= total_size
+	       && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
+		   >= inherent_size)
+	       && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
+	x = spill_stack_slot[from_reg];
+/* Allocate a bigger slot.  */
+else
+	{
+	  /* Compute maximum size needed, both for inherent size
+	     and for total size.  */
+	  rtx stack_slot;
+	  if (spill_stack_slot[from_reg])
+	    {
+	      if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
+		  > inherent_size)
+		mode = GET_MODE (spill_stack_slot[from_reg]);
+	      if (spill_stack_slot_width[from_reg] > total_size)
+		total_size = spill_stack_slot_width[from_reg];
+	      if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
+		min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
+	    }
+	  /* Make a slot with that size.  */
+	  x = assign_stack_local (mode, total_size,
+				  min_align > inherent_align
+				  || total_size > inherent_size ? -1 : 0);
+	  stack_slot = x;
+	  /* Cancel the  big-endian correction done in assign_stack_local.
+	     Get the address of the beginning of the slot.  This is so we
+	     can do a big-endian correction unconditionally below.  */
+	  if (BYTES_BIG_ENDIAN)
+	    {
+	      adjust = GET_MODE_SIZE (mode) - total_size;
+	      if (adjust)
+		stack_slot
+		  = adjust_address_nv (x, mode_for_size (total_size
+							 * BITS_PER_UNIT,
+							 MODE_INT, 1),
+				       adjust);
+	    }
+	  spill_stack_slot[from_reg] = stack_slot;
+	  spill_stack_slot_width[from_reg] = total_size;
+	}
+/* On a big endian machine, the "address" of the slot
+	 is the address of the low part that fits its inherent mode.  */
+if (BYTES_BIG_ENDIAN && inherent_size < total_size)
+	adjust += (total_size - inherent_size);
+/* If we have any adjustment to make, or if the stack slot is the
+	 wrong mode, make a new stack slot.  */
+x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
+/* Set all of the memory attributes as appropriate for a spill.  */
+set_mem_attrs_for_spill (x);
+/* Save the stack slot for later.  */
+reg_equiv_memory_loc[i] = x;
+}
+}
+/* Mark the slots in regs_ever_live for the hard regs used by
+pseudo-reg number REGNO, accessed in MODE.  */
+static void
+mark_home_live_1 (int regno, enum machine_mode mode)
+{
+int i, lim;
+i = reg_renumber[regno];
+if (i < 0)
+return;
+lim = end_hard_regno (mode, i);
+while (i < lim)
+df_set_regs_ever_live(i++, true);
+}
+/* Mark the slots in regs_ever_live for the hard regs
+used by pseudo-reg number REGNO.  */
+void
+mark_home_live (int regno)
+{
+if (reg_renumber[regno] >= 0)
+mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
+}
+/* This function handles the tracking of elimination offsets around branches.
+X is a piece of RTL being scanned.
+INSN is the insn that it came from, if any.
+INITIAL_P is nonzero if we are to set the offset to be the initial
+offset and zero if we are setting the offset of the label to be the
+current offset.  */
+static void
+set_label_offsets (rtx x, rtx insn, int initial_p)
+{
+enum rtx_code code = GET_CODE (x);
+rtx tem;
+unsigned int i;
+struct elim_table *p;
+switch (code)
+{
+case LABEL_REF:
+if (LABEL_REF_NONLOCAL_P (x))
+	return;
+x = XEXP (x, 0);
+/* ... fall through ...  */
+case CODE_LABEL:
+/* If we know nothing about this label, set the desired offsets.  Note
+	 that this sets the offset at a label to be the offset before a label
+	 if we don't know anything about the label.  This is not correct for
+	 the label after a BARRIER, but is the best guess we can make.  If
+	 we guessed wrong, we will suppress an elimination that might have
+	 been possible had we been able to guess correctly.  */
+if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
+	{
+	  for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
+	    offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
+	      = (initial_p ? reg_eliminate[i].initial_offset
+		 : reg_eliminate[i].offset);
+	  offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
+	}
+/* Otherwise, if this is the definition of a label and it is
+	 preceded by a BARRIER, set our offsets to the known offset of
+	 that label.  */
+else if (x == insn
+	       && (tem = prev_nonnote_insn (insn)) != 0
+	       && BARRIER_P (tem))
+	set_offsets_for_label (insn);
+else
+	/* If neither of the above cases is true, compare each offset
+	   with those previously recorded and suppress any eliminations
+	   where the offsets disagree.  */
+	for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
+	  if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
+	      != (initial_p ? reg_eliminate[i].initial_offset
+		  : reg_eliminate[i].offset))
+	    reg_eliminate[i].can_eliminate = 0;
+return;
+case JUMP_INSN:
+set_label_offsets (PATTERN (insn), insn, initial_p);
+/* ... fall through ...  */
+case INSN:
+case CALL_INSN:
+/* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
+	 to indirectly and hence must have all eliminations at their
+	 initial offsets.  */
+for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
+	if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
+	  set_label_offsets (XEXP (tem, 0), insn, 1);
+return;
+case PARALLEL:
+case ADDR_VEC:
+case ADDR_DIFF_VEC:
+/* Each of the labels in the parallel or address vector must be
+	 at their initial offsets.  We want the first field for PARALLEL
+	 and ADDR_VEC and the second field for ADDR_DIFF_VEC.  */
+for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
+	set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
+			   insn, initial_p);
+return;
+case SET:
+/* We only care about setting PC.  If the source is not RETURN,
+	 IF_THEN_ELSE, or a label, disable any eliminations not at
+	 their initial offsets.  Similarly if any arm of the IF_THEN_ELSE
+	 isn't one of those possibilities.  For branches to a label,
+	 call ourselves recursively.
+	 Note that this can disable elimination unnecessarily when we have
+	 a non-local goto since it will look like a non-constant jump to
+	 someplace in the current function.  This isn't a significant
+	 problem since such jumps will normally be when all elimination
+	 pairs are back to their initial offsets.  */
+if (SET_DEST (x) != pc_rtx)
+	return;
+switch (GET_CODE (SET_SRC (x)))
+	{
+	case PC:
+	case RETURN:
+	  return;
+	case LABEL_REF:
+	  set_label_offsets (SET_SRC (x), insn, initial_p);
+	  return;
+	case IF_THEN_ELSE:
+	  tem = XEXP (SET_SRC (x), 1);
+	  if (GET_CODE (tem) == LABEL_REF)
+	    set_label_offsets (XEXP (tem, 0), insn, initial_p);
+	  else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
+	    break;
+	  tem = XEXP (SET_SRC (x), 2);
+	  if (GET_CODE (tem) == LABEL_REF)
+	    set_label_offsets (XEXP (tem, 0), insn, initial_p);
+	  else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
+	    break;
+	  return;
+	default:
+	  break;
+	}
+/* If we reach here, all eliminations must be at their initial
+	 offset because we are doing a jump to a variable address.  */
+for (p = reg_eliminate; p < &reg_eliminate[NUM_ELIMINABLE_REGS]; p++)
+	if (p->offset != p->initial_offset)
+	  p->can_eliminate = 0;
+break;
+default:
+break;
+}
+}
+/* Called through for_each_rtx, this function examines every reg that occurs
+in PX and adjusts the costs for its elimination which are gathered by IRA.
+DATA is the insn in which PX occurs.  We do not recurse into MEM
+expressions.  */
+static int
+note_reg_elim_costly (rtx *px, void *data)
+{
+rtx insn = (rtx)data;
+rtx x = *px;
+if (MEM_P (x))
+return -1;
+if (REG_P (x)
+&& REGNO (x) >= FIRST_PSEUDO_REGISTER
+&& reg_equiv_init[REGNO (x)]
+&& reg_equiv_invariant[REGNO (x)])
+{
+rtx t = reg_equiv_invariant[REGNO (x)];
+rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
+int cost = rtx_cost (new_rtx, SET, optimize_bb_for_speed_p (elim_bb));
+int freq = REG_FREQ_FROM_BB (elim_bb);
+if (cost != 0)
+	ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
+}
+return 0;
+}
+/* Scan X and replace any eliminable registers (such as fp) with a
+replacement (such as sp), plus an offset.
+MEM_MODE is the mode of an enclosing MEM.  We need this to know how
+much to adjust a register for, e.g., PRE_DEC.  Also, if we are inside a
+MEM, we are allowed to replace a sum of a register and the constant zero
+with the register, which we cannot do outside a MEM.  In addition, we need
+to record the fact that a register is referenced outside a MEM.
+If INSN is an insn, it is the insn containing X.  If we replace a REG
+in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
+CLOBBER of the pseudo after INSN so find_equiv_regs will know that
+the REG is being modified.
+Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
+That's used when we eliminate in expressions stored in notes.
+This means, do not set ref_outside_mem even if the reference
+is outside of MEMs.
+If FOR_COSTS is true, we are being called before reload in order to
+estimate the costs of keeping registers with an equivalence unallocated.
+REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
+replacements done assuming all offsets are at their initial values.  If
+they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
+encounter, return the actual location so that find_reloads will do
+the proper thing.  */
+static rtx
+eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
+		  bool may_use_invariant, bool for_costs)
+{
+enum rtx_code code = GET_CODE (x);
+struct elim_table *ep;
+int regno;
+rtx new_rtx;
+int i, j;
+const char *fmt;
+int copied = 0;
+if (! current_function_decl)
+return x;
+switch (code)
+{
+case CONST_INT:
+case CONST_DOUBLE:
+case CONST_FIXED:
+case CONST_VECTOR:
+case CONST:
+case SYMBOL_REF:
+case CODE_LABEL:
+case PC:
+case CC0:
+case ASM_INPUT:
+case ADDR_VEC:
+case ADDR_DIFF_VEC:
+case RETURN:
+return x;
+case REG:
+regno = REGNO (x);
+/* First handle the case where we encounter a bare register that
+	 is eliminable.  Replace it with a PLUS.  */
+if (regno < FIRST_PSEUDO_REGISTER)
+	{
+	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
+	       ep++)
+	    if (ep->from_rtx == x && ep->can_eliminate)
+	      return plus_constant (ep->to_rtx, ep->previous_offset);
+	}
+else if (reg_renumber && reg_renumber[regno] < 0
+	       && reg_equiv_invariant && reg_equiv_invariant[regno])
+	{
+	  if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
+	    return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
+			             mem_mode, insn, true, for_costs);
+	  /* There exists at least one use of REGNO that cannot be
+	     eliminated.  Prevent the defining insn from being deleted.  */
+	  reg_equiv_init[regno] = NULL_RTX;
+	  if (!for_costs)
+	    alter_reg (regno, -1, true);
+	}
+return x;
+/* You might think handling MINUS in a manner similar to PLUS is a
+good idea.  It is not.  It has been tried multiple times and every
+time the change has had to have been reverted.
+Other parts of reload know a PLUS is special (gen_reload for example)
+and require special code to handle code a reloaded PLUS operand.
+Also consider backends where the flags register is clobbered by a
+MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
+lea instruction comes to mind).  If we try to reload a MINUS, we
+may kill the flags register that was holding a useful value.
+So, please before trying to handle MINUS, consider reload as a
+whole instead of this little section as well as the backend issues.  */
+case PLUS:
+/* If this is the sum of an eliminable register and a constant, rework
+	 the sum.  */
+if (REG_P (XEXP (x, 0))
+	  && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
+	  && CONSTANT_P (XEXP (x, 1)))
+	{
+	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
+	       ep++)
+	    if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
+	      {
+		/* The only time we want to replace a PLUS with a REG (this
+		   occurs when the constant operand of the PLUS is the negative
+		   of the offset) is when we are inside a MEM.  We won't want
+		   to do so at other times because that would change the
+		   structure of the insn in a way that reload can't handle.
+		   We special-case the commonest situation in
+		   eliminate_regs_in_insn, so just replace a PLUS with a
+		   PLUS here, unless inside a MEM.  */
+		if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
+		    && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
+		  return ep->to_rtx;
+		else
+		  return gen_rtx_PLUS (Pmode, ep->to_rtx,
+				       plus_constant (XEXP (x, 1),
+						      ep->previous_offset));
+	      }
+	  /* If the register is not eliminable, we are done since the other
+	     operand is a constant.  */
+	  return x;
+	}
+/* If this is part of an address, we want to bring any constant to the
+	 outermost PLUS.  We will do this by doing register replacement in
+	 our operands and seeing if a constant shows up in one of them.
+	 Note that there is no risk of modifying the structure of the insn,
+	 since we only get called for its operands, thus we are either
+	 modifying the address inside a MEM, or something like an address
+	 operand of a load-address insn.  */
+{
+	rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
+				     for_costs);
+	rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
+				     for_costs);
+	if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
+	  {
+	    /* If one side is a PLUS and the other side is a pseudo that
+	       didn't get a hard register but has a reg_equiv_constant,
+	       we must replace the constant here since it may no longer
+	       be in the position of any operand.  */
+	    if (GET_CODE (new0) == PLUS && REG_P (new1)
+		&& REGNO (new1) >= FIRST_PSEUDO_REGISTER
+		&& reg_renumber[REGNO (new1)] < 0
+		&& reg_equiv_constant != 0
+		&& reg_equiv_constant[REGNO (new1)] != 0)
+	      new1 = reg_equiv_constant[REGNO (new1)];
+	    else if (GET_CODE (new1) == PLUS && REG_P (new0)
+		     && REGNO (new0) >= FIRST_PSEUDO_REGISTER
+		     && reg_renumber[REGNO (new0)] < 0
+		     && reg_equiv_constant[REGNO (new0)] != 0)
+	      new0 = reg_equiv_constant[REGNO (new0)];
+	    new_rtx = form_sum (GET_MODE (x), new0, new1);
+	    /* As above, if we are not inside a MEM we do not want to
+	       turn a PLUS into something else.  We might try to do so here
+	       for an addition of 0 if we aren't optimizing.  */
+	    if (! mem_mode && GET_CODE (new_rtx) != PLUS)
+	      return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
+	    else
+	      return new_rtx;
+	  }
+}
+return x;
+case MULT:
+/* If this is the product of an eliminable register and a
+	 constant, apply the distribute law and move the constant out
+	 so that we have (plus (mult ..) ..).  This is needed in order
+	 to keep load-address insns valid.   This case is pathological.
+	 We ignore the possibility of overflow here.  */
+if (REG_P (XEXP (x, 0))
+	  && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
+	  && CONST_INT_P (XEXP (x, 1)))
+	for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
+	     ep++)
+	  if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
+	    {
+	      if (! mem_mode
+		  /* Refs inside notes or in DEBUG_INSNs don't count for
+		     this purpose.  */
+		  && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
+				      || GET_CODE (insn) == INSN_LIST
+				      || DEBUG_INSN_P (insn))))
+		ep->ref_outside_mem = 1;
+	      return
+		plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
+			       ep->previous_offset * INTVAL (XEXP (x, 1)));
+	    }
+/* ... fall through ...  */
+case CALL:
+case COMPARE:
+/* See comments before PLUS about handling MINUS.  */
+case MINUS:
+case DIV:      case UDIV:
+case MOD:      case UMOD:
+case AND:      case IOR:      case XOR:
+case ROTATERT: case ROTATE:
+case ASHIFTRT: case LSHIFTRT: case ASHIFT:
+case NE:       case EQ:
+case GE:       case GT:       case GEU:    case GTU:
+case LE:       case LT:       case LEU:    case LTU:
+{
+	rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
+				     for_costs);
+	rtx new1 = XEXP (x, 1)
+	  ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
+			      for_costs) : 0;
+	if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
+	  return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
+}
+return x;
+case EXPR_LIST:
+/* If we have something in XEXP (x, 0), the usual case, eliminate it.  */
+if (XEXP (x, 0))
+	{
+	  new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
+				      for_costs);
+	  if (new_rtx != XEXP (x, 0))
+	    {
+	      /* If this is a REG_DEAD note, it is not valid anymore.
+		 Using the eliminated version could result in creating a
+		 REG_DEAD note for the stack or frame pointer.  */
+	      if (REG_NOTE_KIND (x) == REG_DEAD)
+		return (XEXP (x, 1)
+			? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
+					    for_costs)
+			: NULL_RTX);
+	      x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
+	    }
+	}
+/* ... fall through ...  */
+case INSN_LIST:
+/* Now do eliminations in the rest of the chain.  If this was
+	 an EXPR_LIST, this might result in allocating more memory than is
+	 strictly needed, but it simplifies the code.  */
+if (XEXP (x, 1))
+	{
+	  new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
+				      for_costs);
+	  if (new_rtx != XEXP (x, 1))
+	    return
+	      gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
+	}
+return x;
+case PRE_INC:
+case POST_INC:
+case PRE_DEC:
+case POST_DEC:
+/* We do not support elimination of a register that is modified.
+	 elimination_effects has already make sure that this does not
+	 happen.  */
+return x;
+case PRE_MODIFY:
+case POST_MODIFY:
+/* We do not support elimination of a register that is modified.
+	 elimination_effects has already make sure that this does not
+	 happen.  The only remaining case we need to consider here is
+	 that the increment value may be an eliminable register.  */
+if (GET_CODE (XEXP (x, 1)) == PLUS
+	  && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
+	{
+	  rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
+					  insn, true, for_costs);
+	  if (new_rtx != XEXP (XEXP (x, 1), 1))
+	    return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
+				   gen_rtx_PLUS (GET_MODE (x),
+						 XEXP (x, 0), new_rtx));
+	}
+return x;
+case STRICT_LOW_PART:
+case NEG:          case NOT:
+case SIGN_EXTEND:  case ZERO_EXTEND:
+case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
+case FLOAT:        case FIX:
+case UNSIGNED_FIX: case UNSIGNED_FLOAT:
+case ABS:
+case SQRT:
+case FFS:
+case CLZ:
+case CTZ:
+case POPCOUNT:
+case PARITY:
+case BSWAP:
+new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
+				  for_costs);
+if (new_rtx != XEXP (x, 0))
+	return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
+return x;
+case SUBREG:
+/* Similar to above processing, but preserve SUBREG_BYTE.
+	 Convert (subreg (mem)) to (mem) if not paradoxical.
+	 Also, if we have a non-paradoxical (subreg (pseudo)) and the
+	 pseudo didn't get a hard reg, we must replace this with the
+	 eliminated version of the memory location because push_reload
+	 may do the replacement in certain circumstances.  */
+if (REG_P (SUBREG_REG (x))
+	  && (GET_MODE_SIZE (GET_MODE (x))
+	      <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
+	  && reg_equiv_memory_loc != 0
+	  && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
+	{
+	  new_rtx = SUBREG_REG (x);
+	}
+else
+	new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false,
+				    for_costs);
+if (new_rtx != SUBREG_REG (x))
+	{
+	  int x_size = GET_MODE_SIZE (GET_MODE (x));
+	  int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
+	  if (MEM_P (new_rtx)
+	      && ((x_size < new_size
+#ifdef WORD_REGISTER_OPERATIONS
+		   /* On these machines, combine can create rtl of the form
+		      (set (subreg:m1 (reg:m2 R) 0) ...)
+		      where m1 < m2, and expects something interesting to
+		      happen to the entire word.  Moreover, it will use the
+		      (reg:m2 R) later, expecting all bits to be preserved.
+		      So if the number of words is the same, preserve the
+		      subreg so that push_reload can see it.  */
+		   && ! ((x_size - 1) / UNITS_PER_WORD
+			 == (new_size -1 ) / UNITS_PER_WORD)
+#endif
+		   )
+		  || x_size == new_size)
+	      )
+	    return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
+	  else
+	    return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
+	}
+return x;
+case MEM:
+/* Our only special processing is to pass the mode of the MEM to our
+	 recursive call and copy the flags.  While we are here, handle this
+	 case more efficiently.  */
+new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
+				  for_costs);
+if (for_costs
+	  && memory_address_p (GET_MODE (x), XEXP (x, 0))
+	  && !memory_address_p (GET_MODE (x), new_rtx))
+	for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
+return replace_equiv_address_nv (x, new_rtx);
+case USE:
+/* Handle insn_list USE that a call to a pure function may generate.  */
+new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
+				  for_costs);
+if (new_rtx != XEXP (x, 0))
+	return gen_rtx_USE (GET_MODE (x), new_rtx);
+return x;
+case CLOBBER:
+case ASM_OPERANDS:
+gcc_assert (insn && DEBUG_INSN_P (insn));
+break;
+case SET:
+gcc_unreachable ();
+default:
+break;
+}
+/* Process each of our operands recursively.  If any have changed, make a
+copy of the rtx.  */
+fmt = GET_RTX_FORMAT (code);
+for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
+{
+if (*fmt == 'e')
+	{
+	  new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
+				      for_costs);
+	  if (new_rtx != XEXP (x, i) && ! copied)
+	    {
+	      x = shallow_copy_rtx (x);
+	      copied = 1;
+	    }
+	  XEXP (x, i) = new_rtx;
+	}
+else if (*fmt == 'E')
+	{
+	  int copied_vec = 0;
+	  for (j = 0; j < XVECLEN (x, i); j++)
+	    {
+	      new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
+					  for_costs);
+	      if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
+		{
+		  rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
+					     XVEC (x, i)->elem);
+		  if (! copied)
+		    {
+		      x = shallow_copy_rtx (x);
+		      copied = 1;
+		    }
+		  XVEC (x, i) = new_v;
+		  copied_vec = 1;
+		}
+	      XVECEXP (x, i, j) = new_rtx;
+	    }
+	}
+}
+return x;
+}
+rtx
+eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
+{
+return eliminate_regs_1 (x, mem_mode, insn, false, false);
+}
+/* Scan rtx X for modifications of elimination target registers.  Update
+the table of eliminables to reflect the changed state.  MEM_MODE is
+the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM.  */
+static void
+elimination_effects (rtx x, enum machine_mode mem_mode)
+{
+enum rtx_code code = GET_CODE (x);
+struct elim_table *ep;
+int regno;
+int i, j;
+const char *fmt;
+switch (code)
+{
+case CONST_INT:
+case CONST_DOUBLE:
+case CONST_FIXED:
+case CONST_VECTOR:
+case CONST:
+case SYMBOL_REF:
+case CODE_LABEL:
+case PC:
+case CC0:
+case ASM_INPUT:
+case ADDR_VEC:
+case ADDR_DIFF_VEC:
+case RETURN:
+return;
+case REG:
+regno = REGNO (x);
+/* First handle the case where we encounter a bare register that
+	 is eliminable.  Replace it with a PLUS.  */
+if (regno < FIRST_PSEUDO_REGISTER)
+	{
+	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
+	       ep++)
+	    if (ep->from_rtx == x && ep->can_eliminate)
+	      {
+		if (! mem_mode)
+		  ep->ref_outside_mem = 1;
+		return;
+	      }
+	}
+else if (reg_renumber[regno] < 0 && reg_equiv_constant
+	       && reg_equiv_constant[regno]
+	       && ! function_invariant_p (reg_equiv_constant[regno]))
+	elimination_effects (reg_equiv_constant[regno], mem_mode);
+return;
+case PRE_INC:
+case POST_INC:
+case PRE_DEC:
+case POST_DEC:
+case POST_MODIFY:
+case PRE_MODIFY:
+/* If we modify the source of an elimination rule, disable it.  */
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+	if (ep->from_rtx == XEXP (x, 0))
+	  ep->can_eliminate = 0;
+/* If we modify the target of an elimination rule by adding a constant,
+	 update its offset.  If we modify the target in any other way, we'll
+	 have to disable the rule as well.  */
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+	if (ep->to_rtx == XEXP (x, 0))
+	  {
+	    int size = GET_MODE_SIZE (mem_mode);
+	    /* If more bytes than MEM_MODE are pushed, account for them.  */
+#ifdef PUSH_ROUNDING
+	    if (ep->to_rtx == stack_pointer_rtx)
+	      size = PUSH_ROUNDING (size);
+#endif
+	    if (code == PRE_DEC || code == POST_DEC)
+	      ep->offset += size;
+	    else if (code == PRE_INC || code == POST_INC)
+	      ep->offset -= size;
+	    else if (code == PRE_MODIFY || code == POST_MODIFY)
+	      {
+		if (GET_CODE (XEXP (x, 1)) == PLUS
+		    && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
+		    && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
+		  ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
+		else
+		  ep->can_eliminate = 0;
+	      }
+	  }
+/* These two aren't unary operators.  */
+if (code == POST_MODIFY || code == PRE_MODIFY)
+	break;
+/* Fall through to generic unary operation case.  */
+case STRICT_LOW_PART:
+case NEG:          case NOT:
+case SIGN_EXTEND:  case ZERO_EXTEND:
+case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
+case FLOAT:        case FIX:
+case UNSIGNED_FIX: case UNSIGNED_FLOAT:
+case ABS:
+case SQRT:
+case FFS:
+case CLZ:
+case CTZ:
+case POPCOUNT:
+case PARITY:
+case BSWAP:
+elimination_effects (XEXP (x, 0), mem_mode);
+return;
+case SUBREG:
+if (REG_P (SUBREG_REG (x))
+	  && (GET_MODE_SIZE (GET_MODE (x))
+	      <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
+	  && reg_equiv_memory_loc != 0
+	  && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
+	return;
+elimination_effects (SUBREG_REG (x), mem_mode);
+return;
+case USE:
+/* If using a register that is the source of an eliminate we still
+	 think can be performed, note it cannot be performed since we don't
+	 know how this register is used.  */
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+	if (ep->from_rtx == XEXP (x, 0))
+	  ep->can_eliminate = 0;
+elimination_effects (XEXP (x, 0), mem_mode);
+return;
+case CLOBBER:
+/* If clobbering a register that is the replacement register for an
+	 elimination we still think can be performed, note that it cannot
+	 be performed.  Otherwise, we need not be concerned about it.  */
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+	if (ep->to_rtx == XEXP (x, 0))
+	  ep->can_eliminate = 0;
+elimination_effects (XEXP (x, 0), mem_mode);
+return;
+case SET:
+/* Check for setting a register that we know about.  */
+if (REG_P (SET_DEST (x)))
+	{
+	  /* See if this is setting the replacement register for an
+	     elimination.
+	     If DEST is the hard frame pointer, we do nothing because we
+	     assume that all assignments to the frame pointer are for
+	     non-local gotos and are being done at a time when they are valid
+	     and do not disturb anything else.  Some machines want to
+	     eliminate a fake argument pointer (or even a fake frame pointer)
+	     with either the real frame or the stack pointer.  Assignments to
+	     the hard frame pointer must not prevent this elimination.  */
+	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
+	       ep++)
+	    if (ep->to_rtx == SET_DEST (x)
+		&& SET_DEST (x) != hard_frame_pointer_rtx)
+	      {
+		/* If it is being incremented, adjust the offset.  Otherwise,
+		   this elimination can't be done.  */
+		rtx src = SET_SRC (x);
+		if (GET_CODE (src) == PLUS
+		    && XEXP (src, 0) == SET_DEST (x)
+		    && CONST_INT_P (XEXP (src, 1)))
+		  ep->offset -= INTVAL (XEXP (src, 1));
+		else
+		  ep->can_eliminate = 0;
+	      }
+	}
+elimination_effects (SET_DEST (x), VOIDmode);
+elimination_effects (SET_SRC (x), VOIDmode);
+return;
+case MEM:
+/* Our only special processing is to pass the mode of the MEM to our
+	 recursive call.  */
+elimination_effects (XEXP (x, 0), GET_MODE (x));
+return;
+default:
+break;
+}
+fmt = GET_RTX_FORMAT (code);
+for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
+{
+if (*fmt == 'e')
+	elimination_effects (XEXP (x, i), mem_mode);
+else if (*fmt == 'E')
+	for (j = 0; j < XVECLEN (x, i); j++)
+	  elimination_effects (XVECEXP (x, i, j), mem_mode);
+}
+}
+/* Descend through rtx X and verify that no references to eliminable registers
+remain.  If any do remain, mark the involved register as not
+eliminable.  */
+static void
+check_eliminable_occurrences (rtx x)
+{
+const char *fmt;
+int i;
+enum rtx_code code;
+if (x == 0)
+return;
+code = GET_CODE (x);
+if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
+{
+struct elim_table *ep;
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+	if (ep->from_rtx == x)
+	  ep->can_eliminate = 0;
+return;
+}
+fmt = GET_RTX_FORMAT (code);
+for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
+{
+if (*fmt == 'e')
+	check_eliminable_occurrences (XEXP (x, i));
+else if (*fmt == 'E')
+	{
+	  int j;
+	  for (j = 0; j < XVECLEN (x, i); j++)
+	    check_eliminable_occurrences (XVECEXP (x, i, j));
+	}
+}
+}
+/* Scan INSN and eliminate all eliminable registers in it.
+If REPLACE is nonzero, do the replacement destructively.  Also
+delete the insn as dead it if it is setting an eliminable register.
+If REPLACE is zero, do all our allocations in reload_obstack.
+If no eliminations were done and this insn doesn't require any elimination
+processing (these are not identical conditions: it might be updating sp,
+but not referencing fp; this needs to be seen during reload_as_needed so
+that the offset between fp and sp can be taken into consideration), zero
+is returned.  Otherwise, 1 is returned.  */
+static int
+eliminate_regs_in_insn (rtx insn, int replace)
+{
+int icode = recog_memoized (insn);
+rtx old_body = PATTERN (insn);
+int insn_is_asm = asm_noperands (old_body) >= 0;
+rtx old_set = single_set (insn);
+rtx new_body;
+int val = 0;
+int i;
+rtx substed_operand[MAX_RECOG_OPERANDS];
+rtx orig_operand[MAX_RECOG_OPERANDS];
+struct elim_table *ep;
+rtx plus_src, plus_cst_src;
+if (! insn_is_asm && icode < 0)
+{
+gcc_assert (GET_CODE (PATTERN (insn)) == USE
+		  || GET_CODE (PATTERN (insn)) == CLOBBER
+		  || GET_CODE (PATTERN (insn)) == ADDR_VEC
+		  || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
+		  || GET_CODE (PATTERN (insn)) == ASM_INPUT
+		  || DEBUG_INSN_P (insn));
+if (DEBUG_INSN_P (insn))
+	INSN_VAR_LOCATION_LOC (insn)
+	  = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
+return 0;
+}
+if (old_set != 0 && REG_P (SET_DEST (old_set))
+&& REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
+{
+/* Check for setting an eliminable register.  */
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+	if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
+	  {
+#if !HARD_FRAME_POINTER_IS_FRAME_POINTER
+	    /* If this is setting the frame pointer register to the
+	       hardware frame pointer register and this is an elimination
+	       that will be done (tested above), this insn is really
+	       adjusting the frame pointer downward to compensate for
+	       the adjustment done before a nonlocal goto.  */
+	    if (ep->from == FRAME_POINTER_REGNUM
+		&& ep->to == HARD_FRAME_POINTER_REGNUM)
+	      {
+		rtx base = SET_SRC (old_set);
+		rtx base_insn = insn;
+		HOST_WIDE_INT offset = 0;
+		while (base != ep->to_rtx)
+		  {
+		    rtx prev_insn, prev_set;
+		    if (GET_CODE (base) == PLUS
+		        && CONST_INT_P (XEXP (base, 1)))
+		      {
+		        offset += INTVAL (XEXP (base, 1));
+		        base = XEXP (base, 0);
+		      }
+		    else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
+			     && (prev_set = single_set (prev_insn)) != 0
+			     && rtx_equal_p (SET_DEST (prev_set), base))
+		      {
+		        base = SET_SRC (prev_set);
+		        base_insn = prev_insn;
+		      }
+		    else
+		      break;
+		  }
+		if (base == ep->to_rtx)
+		  {
+		    rtx src
+		      = plus_constant (ep->to_rtx, offset - ep->offset);
+		    new_body = old_body;
+		    if (! replace)
+		      {
+			new_body = copy_insn (old_body);
+			if (REG_NOTES (insn))
+			  REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
+		      }
+		    PATTERN (insn) = new_body;
+		    old_set = single_set (insn);
+		    /* First see if this insn remains valid when we
+		       make the change.  If not, keep the INSN_CODE
+		       the same and let reload fit it up.  */
+		    validate_change (insn, &SET_SRC (old_set), src, 1);
+		    validate_change (insn, &SET_DEST (old_set),
+				     ep->to_rtx, 1);
+		    if (! apply_change_group ())
+		      {
+			SET_SRC (old_set) = src;
+			SET_DEST (old_set) = ep->to_rtx;
+		      }
+		    val = 1;
+		    goto done;
+		  }
+	      }
+#endif
+	    /* In this case this insn isn't serving a useful purpose.  We
+	       will delete it in reload_as_needed once we know that this
+	       elimination is, in fact, being done.
+	       If REPLACE isn't set, we can't delete this insn, but needn't
+	       process it since it won't be used unless something changes.  */
+	    if (replace)
+	      {
+		delete_dead_insn (insn);
+		return 1;
+	      }
+	    val = 1;
+	    goto done;
+	  }
+}
+/* We allow one special case which happens to work on all machines we
+currently support: a single set with the source or a REG_EQUAL
+note being a PLUS of an eliminable register and a constant.  */
+plus_src = plus_cst_src = 0;
+if (old_set && REG_P (SET_DEST (old_set)))
+{
+if (GET_CODE (SET_SRC (old_set)) == PLUS)
+	plus_src = SET_SRC (old_set);
+/* First see if the source is of the form (plus (...) CST).  */
+if (plus_src
+	  && CONST_INT_P (XEXP (plus_src, 1)))
+	plus_cst_src = plus_src;
+else if (REG_P (SET_SRC (old_set))
+	       || plus_src)
+	{
+	  /* Otherwise, see if we have a REG_EQUAL note of the form
+	     (plus (...) CST).  */
+	  rtx links;
+	  for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
+	    {
+	      if ((REG_NOTE_KIND (links) == REG_EQUAL
+		   || REG_NOTE_KIND (links) == REG_EQUIV)
+		  && GET_CODE (XEXP (links, 0)) == PLUS
+		  && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
+		{
+		  plus_cst_src = XEXP (links, 0);
+		  break;
+		}
+	    }
+	}
+/* Check that the first operand of the PLUS is a hard reg or
+	 the lowpart subreg of one.  */
+if (plus_cst_src)
+	{
+	  rtx reg = XEXP (plus_cst_src, 0);
+	  if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
+	    reg = SUBREG_REG (reg);
+	  if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
+	    plus_cst_src = 0;
+	}
+}
+if (plus_cst_src)
+{
+rtx reg = XEXP (plus_cst_src, 0);
+HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
+if (GET_CODE (reg) == SUBREG)
+	reg = SUBREG_REG (reg);
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+	if (ep->from_rtx == reg && ep->can_eliminate)
+	  {
+	    rtx to_rtx = ep->to_rtx;
+	    offset += ep->offset;
+	    offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
+	    if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
+	      to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
+				    to_rtx);
+	    /* If we have a nonzero offset, and the source is already
+	       a simple REG, the following transformation would
+	       increase the cost of the insn by replacing a simple REG
+	       with (plus (reg sp) CST).  So try only when we already
+	       had a PLUS before.  */
+	    if (offset == 0 || plus_src)
+	      {
+		rtx new_src = plus_constant (to_rtx, offset);
+		new_body = old_body;
+		if (! replace)
+		  {
+		    new_body = copy_insn (old_body);
+		    if (REG_NOTES (insn))
+		      REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
+		  }
+		PATTERN (insn) = new_body;
+		old_set = single_set (insn);
+		/* First see if this insn remains valid when we make the
+		   change.  If not, try to replace the whole pattern with
+		   a simple set (this may help if the original insn was a
+		   PARALLEL that was only recognized as single_set due to
+		   REG_UNUSED notes).  If this isn't valid either, keep
+		   the INSN_CODE the same and let reload fix it up.  */
+		if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
+		  {
+		    rtx new_pat = gen_rtx_SET (VOIDmode,
+					       SET_DEST (old_set), new_src);
+		    if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
+		      SET_SRC (old_set) = new_src;
+		  }
+	      }
+	    else
+	      break;
+	    val = 1;
+	    /* This can't have an effect on elimination offsets, so skip right
+	       to the end.  */
+	    goto done;
+	  }
+}
+/* Determine the effects of this insn on elimination offsets.  */
+elimination_effects (old_body, VOIDmode);
+/* Eliminate all eliminable registers occurring in operands that
+can be handled by reload.  */
+extract_insn (insn);
+for (i = 0; i < recog_data.n_operands; i++)
+{
+orig_operand[i] = recog_data.operand[i];
+substed_operand[i] = recog_data.operand[i];
+/* For an asm statement, every operand is eliminable.  */
+if (insn_is_asm || insn_data[icode].operand[i].eliminable)
+	{
+	  bool is_set_src, in_plus;
+	  /* Check for setting a register that we know about.  */
+	  if (recog_data.operand_type[i] != OP_IN
+	      && REG_P (orig_operand[i]))
+	    {
+	      /* If we are assigning to a register that can be eliminated, it
+		 must be as part of a PARALLEL, since the code above handles
+		 single SETs.  We must indicate that we can no longer
+		 eliminate this reg.  */
+	      for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
+		   ep++)
+		if (ep->from_rtx == orig_operand[i])
+		  ep->can_eliminate = 0;
+	    }
+	  /* Companion to the above plus substitution, we can allow
+	     invariants as the source of a plain move.  */
+	  is_set_src = false;
+	  if (old_set
+	      && recog_data.operand_loc[i] == &SET_SRC (old_set))
+	    is_set_src = true;
+	  in_plus = false;
+	  if (plus_src
+	      && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
+		  || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
+	    in_plus = true;
+	  substed_operand[i]
+	    = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
+			        replace ? insn : NULL_RTX,
+				is_set_src || in_plus, false);
+	  if (substed_operand[i] != orig_operand[i])
+	    val = 1;
+	  /* Terminate the search in check_eliminable_occurrences at
+	     this point.  */
+	  *recog_data.operand_loc[i] = 0;
+	  /* If an output operand changed from a REG to a MEM and INSN is an
+	     insn, write a CLOBBER insn.  */
+	  if (recog_data.operand_type[i] != OP_IN
+	      && REG_P (orig_operand[i])
+	      && MEM_P (substed_operand[i])
+	      && replace)
+	    emit_insn_after (gen_clobber (orig_operand[i]), insn);
+	}
+}
+for (i = 0; i < recog_data.n_dups; i++)
+*recog_data.dup_loc[i]
+= *recog_data.operand_loc[(int) recog_data.dup_num[i]];
+/* If any eliminable remain, they aren't eliminable anymore.  */
+check_eliminable_occurrences (old_body);
+/* Substitute the operands; the new values are in the substed_operand
+array.  */
+for (i = 0; i < recog_data.n_operands; i++)
+*recog_data.operand_loc[i] = substed_operand[i];
+for (i = 0; i < recog_data.n_dups; i++)
+*recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
+/* If we are replacing a body that was a (set X (plus Y Z)), try to
+re-recognize the insn.  We do this in case we had a simple addition
+but now can do this as a load-address.  This saves an insn in this
+common case.
+If re-recognition fails, the old insn code number will still be used,
+and some register operands may have changed into PLUS expressions.
+These will be handled by find_reloads by loading them into a register
+again.  */
+if (val)
+{
+/* If we aren't replacing things permanently and we changed something,
+	 make another copy to ensure that all the RTL is new.  Otherwise
+	 things can go wrong if find_reload swaps commutative operands
+	 and one is inside RTL that has been copied while the other is not.  */
+new_body = old_body;
+if (! replace)
+	{
+	  new_body = copy_insn (old_body);
+	  if (REG_NOTES (insn))
+	    REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
+	}
+PATTERN (insn) = new_body;
+/* If we had a move insn but now we don't, rerecognize it.  This will
+	 cause spurious re-recognition if the old move had a PARALLEL since
+	 the new one still will, but we can't call single_set without
+	 having put NEW_BODY into the insn and the re-recognition won't
+	 hurt in this rare case.  */
+/* ??? Why this huge if statement - why don't we just rerecognize the
+	 thing always?  */
+if (! insn_is_asm
+	  && old_set != 0
+	  && ((REG_P (SET_SRC (old_set))
+	       && (GET_CODE (new_body) != SET
+		   || !REG_P (SET_SRC (new_body))))
+	      /* If this was a load from or store to memory, compare
+		 the MEM in recog_data.operand to the one in the insn.
+		 If they are not equal, then rerecognize the insn.  */
+	      || (old_set != 0
+		  && ((MEM_P (SET_SRC (old_set))
+		       && SET_SRC (old_set) != recog_data.operand[1])
+		      || (MEM_P (SET_DEST (old_set))
+			  && SET_DEST (old_set) != recog_data.operand[0])))
+	      /* If this was an add insn before, rerecognize.  */
+	      || GET_CODE (SET_SRC (old_set)) == PLUS))
+	{
+	  int new_icode = recog (PATTERN (insn), insn, 0);
+	  if (new_icode >= 0)
+	    INSN_CODE (insn) = new_icode;
+	}
+}
+/* Restore the old body.  If there were any changes to it, we made a copy
+of it while the changes were still in place, so we'll correctly return
+a modified insn below.  */
+if (! replace)
+{
+/* Restore the old body.  */
+for (i = 0; i < recog_data.n_operands; i++)
+	/* Restoring a top-level match_parallel would clobber the new_body
+	   we installed in the insn.  */
+	if (recog_data.operand_loc[i] != &PATTERN (insn))
+	  *recog_data.operand_loc[i] = orig_operand[i];
+for (i = 0; i < recog_data.n_dups; i++)
+	*recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
+}
+/* Update all elimination pairs to reflect the status after the current
+insn.  The changes we make were determined by the earlier call to
+elimination_effects.
+We also detect cases where register elimination cannot be done,
+namely, if a register would be both changed and referenced outside a MEM
+in the resulting insn since such an insn is often undefined and, even if
+not, we cannot know what meaning will be given to it.  Note that it is
+valid to have a register used in an address in an insn that changes it
+(presumably with a pre- or post-increment or decrement).
+If anything changes, return nonzero.  */
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+{
+if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
+	ep->can_eliminate = 0;
+ep->ref_outside_mem = 0;
+if (ep->previous_offset != ep->offset)
+	val = 1;
+}
+done:
+/* If we changed something, perform elimination in REG_NOTES.  This is
+needed even when REPLACE is zero because a REG_DEAD note might refer
+to a register that we eliminate and could cause a different number
+of spill registers to be needed in the final reload pass than in
+the pre-passes.  */
+if (val && REG_NOTES (insn) != 0)
+REG_NOTES (insn)
+= eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
+			  false);
+return val;
+}
+/* Like eliminate_regs_in_insn, but only estimate costs for the use of the
+register allocator.  INSN is the instruction we need to examine, we perform
+eliminations in its operands and record cases where eliminating a reg with
+an invariant equivalence would add extra cost.  */
+static void
+elimination_costs_in_insn (rtx insn)
+{
+int icode = recog_memoized (insn);
+rtx old_body = PATTERN (insn);
+int insn_is_asm = asm_noperands (old_body) >= 0;
+rtx old_set = single_set (insn);
+int i;
+rtx orig_operand[MAX_RECOG_OPERANDS];
+rtx orig_dup[MAX_RECOG_OPERANDS];
+struct elim_table *ep;
+rtx plus_src, plus_cst_src;
+bool sets_reg_p;
+if (! insn_is_asm && icode < 0)
+{
+gcc_assert (GET_CODE (PATTERN (insn)) == USE
+		  || GET_CODE (PATTERN (insn)) == CLOBBER
+		  || GET_CODE (PATTERN (insn)) == ADDR_VEC
+		  || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
+		  || GET_CODE (PATTERN (insn)) == ASM_INPUT
+		  || DEBUG_INSN_P (insn));
+return;
+}
+if (old_set != 0 && REG_P (SET_DEST (old_set))
+&& REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
+{
+/* Check for setting an eliminable register.  */
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+	if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
+	  return;
+}
+/* We allow one special case which happens to work on all machines we
+currently support: a single set with the source or a REG_EQUAL
+note being a PLUS of an eliminable register and a constant.  */
+plus_src = plus_cst_src = 0;
+sets_reg_p = false;
+if (old_set && REG_P (SET_DEST (old_set)))
+{
+sets_reg_p = true;
+if (GET_CODE (SET_SRC (old_set)) == PLUS)
+	plus_src = SET_SRC (old_set);
+/* First see if the source is of the form (plus (...) CST).  */
+if (plus_src
+	  && CONST_INT_P (XEXP (plus_src, 1)))
+	plus_cst_src = plus_src;
+else if (REG_P (SET_SRC (old_set))
+	       || plus_src)
+	{
+	  /* Otherwise, see if we have a REG_EQUAL note of the form
+	     (plus (...) CST).  */
+	  rtx links;
+	  for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
+	    {
+	      if ((REG_NOTE_KIND (links) == REG_EQUAL
+		   || REG_NOTE_KIND (links) == REG_EQUIV)
+		  && GET_CODE (XEXP (links, 0)) == PLUS
+		  && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
+		{
+		  plus_cst_src = XEXP (links, 0);
+		  break;
+		}
+	    }
+	}
+}
+/* Determine the effects of this insn on elimination offsets.  */
+elimination_effects (old_body, VOIDmode);
+/* Eliminate all eliminable registers occurring in operands that
+can be handled by reload.  */
+extract_insn (insn);
+for (i = 0; i < recog_data.n_dups; i++)
+orig_dup[i] = *recog_data.dup_loc[i];
+for (i = 0; i < recog_data.n_operands; i++)
+{
+orig_operand[i] = recog_data.operand[i];
+/* For an asm statement, every operand is eliminable.  */
+if (insn_is_asm || insn_data[icode].operand[i].eliminable)
+	{
+	  bool is_set_src, in_plus;
+	  /* Check for setting a register that we know about.  */
+	  if (recog_data.operand_type[i] != OP_IN
+	      && REG_P (orig_operand[i]))
+	    {
+	      /* If we are assigning to a register that can be eliminated, it
+		 must be as part of a PARALLEL, since the code above handles
+		 single SETs.  We must indicate that we can no longer
+		 eliminate this reg.  */
+	      for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
+		   ep++)
+		if (ep->from_rtx == orig_operand[i])
+		  ep->can_eliminate = 0;
+	    }
+	  /* Companion to the above plus substitution, we can allow
+	     invariants as the source of a plain move.  */
+	  is_set_src = false;
+	  if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
+	    is_set_src = true;
+	  if (is_set_src && !sets_reg_p)
+	    note_reg_elim_costly (&SET_SRC (old_set), insn);
+	  in_plus = false;
+	  if (plus_src && sets_reg_p
+	      && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
+		  || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
+	    in_plus = true;
+	  eliminate_regs_1 (recog_data.operand[i], VOIDmode,
+			    NULL_RTX,
+			    is_set_src || in_plus, true);
+	  /* Terminate the search in check_eliminable_occurrences at
+	     this point.  */
+	  *recog_data.operand_loc[i] = 0;
+	}
+}
+for (i = 0; i < recog_data.n_dups; i++)
+*recog_data.dup_loc[i]
+= *recog_data.operand_loc[(int) recog_data.dup_num[i]];
+/* If any eliminable remain, they aren't eliminable anymore.  */
+check_eliminable_occurrences (old_body);
+/* Restore the old body.  */
+for (i = 0; i < recog_data.n_operands; i++)
+*recog_data.operand_loc[i] = orig_operand[i];
+for (i = 0; i < recog_data.n_dups; i++)
+*recog_data.dup_loc[i] = orig_dup[i];
+/* Update all elimination pairs to reflect the status after the current
+insn.  The changes we make were determined by the earlier call to
+elimination_effects.  */
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+{
+if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
+	ep->can_eliminate = 0;
+ep->ref_outside_mem = 0;
+}
+return;
+}
+/* Loop through all elimination pairs.
+Recalculate the number not at initial offset.
+Compute the maximum offset (minimum offset if the stack does not
+grow downward) for each elimination pair.  */
+static void
+update_eliminable_offsets (void)
+{
+struct elim_table *ep;
+num_not_at_initial_offset = 0;
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+{
+ep->previous_offset = ep->offset;
+if (ep->can_eliminate && ep->offset != ep->initial_offset)
+	num_not_at_initial_offset++;
+}
+}
+/* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
+replacement we currently believe is valid, mark it as not eliminable if X
+modifies DEST in any way other than by adding a constant integer to it.
+If DEST is the frame pointer, we do nothing because we assume that
+all assignments to the hard frame pointer are nonlocal gotos and are being
+done at a time when they are valid and do not disturb anything else.
+Some machines want to eliminate a fake argument pointer with either the
+frame or stack pointer.  Assignments to the hard frame pointer must not
+prevent this elimination.
+Called via note_stores from reload before starting its passes to scan
+the insns of the function.  */
+static void
+mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
+{
+unsigned int i;
+/* A SUBREG of a hard register here is just changing its mode.  We should
+not see a SUBREG of an eliminable hard register, but check just in
+case.  */
+if (GET_CODE (dest) == SUBREG)
+dest = SUBREG_REG (dest);
+if (dest == hard_frame_pointer_rtx)
+return;
+for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
+if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
+	&& (GET_CODE (x) != SET
+	    || GET_CODE (SET_SRC (x)) != PLUS
+	    || XEXP (SET_SRC (x), 0) != dest
+	    || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
+{
+	reg_eliminate[i].can_eliminate_previous
+	  = reg_eliminate[i].can_eliminate = 0;
+	num_eliminable--;
+}
+}
+/* Verify that the initial elimination offsets did not change since the
+last call to set_initial_elim_offsets.  This is used to catch cases
+where something illegal happened during reload_as_needed that could
+cause incorrect code to be generated if we did not check for it.  */
+static bool
+verify_initial_elim_offsets (void)
+{
+HOST_WIDE_INT t;
+if (!num_eliminable)
+return true;
+#ifdef ELIMINABLE_REGS
+{
+struct elim_table *ep;
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+{
+INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
+if (t != ep->initial_offset)
+	 return false;
+}
+}
+#else
+INITIAL_FRAME_POINTER_OFFSET (t);
+if (t != reg_eliminate[0].initial_offset)
+return false;
+#endif
+return true;
+}
+/* Reset all offsets on eliminable registers to their initial values.  */
+static void
+set_initial_elim_offsets (void)
+{
+struct elim_table *ep = reg_eliminate;
+#ifdef ELIMINABLE_REGS
+for (; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+{
+INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
+ep->previous_offset = ep->offset = ep->initial_offset;
+}
+#else
+INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
+ep->previous_offset = ep->offset = ep->initial_offset;
+#endif
+num_not_at_initial_offset = 0;
+}
+/* Subroutine of set_initial_label_offsets called via for_each_eh_label.  */
+static void
+set_initial_eh_label_offset (rtx label)
+{
+set_label_offsets (label, NULL_RTX, 1);
+}
+/* Initialize the known label offsets.
+Set a known offset for each forced label to be at the initial offset
+of each elimination.  We do this because we assume that all
+computed jumps occur from a location where each elimination is
+at its initial offset.
+For all other labels, show that we don't know the offsets.  */
+static void
+set_initial_label_offsets (void)
+{
+rtx x;
+memset (offsets_known_at, 0, num_labels);
+for (x = forced_labels; x; x = XEXP (x, 1))
+if (XEXP (x, 0))
+set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
+for_each_eh_label (set_initial_eh_label_offset);
+}
+/* Set all elimination offsets to the known values for the code label given
+by INSN.  */
+static void
+set_offsets_for_label (rtx insn)
+{
+unsigned int i;
+int label_nr = CODE_LABEL_NUMBER (insn);
+struct elim_table *ep;
+num_not_at_initial_offset = 0;
+for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
+{
+ep->offset = ep->previous_offset
+		 = offsets_at[label_nr - first_label_num][i];
+if (ep->can_eliminate && ep->offset != ep->initial_offset)
+	num_not_at_initial_offset++;
+}
+}
+/* See if anything that happened changes which eliminations are valid.
+For example, on the SPARC, whether or not the frame pointer can
+be eliminated can depend on what registers have been used.  We need
+not check some conditions again (such as flag_omit_frame_pointer)
+since they can't have changed.  */
+static void
+update_eliminables (HARD_REG_SET *pset)
+{
+int previous_frame_pointer_needed = frame_pointer_needed;
+struct elim_table *ep;
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+if ((ep->from == HARD_FRAME_POINTER_REGNUM
+&& targetm.frame_pointer_required ())
+#ifdef ELIMINABLE_REGS
+	|| ! targetm.can_eliminate (ep->from, ep->to)
+#endif
+	)
+ep->can_eliminate = 0;
+/* Look for the case where we have discovered that we can't replace
+register A with register B and that means that we will now be
+trying to replace register A with register C.  This means we can
+no longer replace register C with register B and we need to disable
+such an elimination, if it exists.  This occurs often with A == ap,
+B == sp, and C == fp.  */
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+{
+struct elim_table *op;
+int new_to = -1;
+if (! ep->can_eliminate && ep->can_eliminate_previous)
+	{
+	  /* Find the current elimination for ep->from, if there is a
+	     new one.  */
+	  for (op = reg_eliminate;
+	       op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
+	    if (op->from == ep->from && op->can_eliminate)
+	      {
+		new_to = op->to;
+		break;
+	      }
+	  /* See if there is an elimination of NEW_TO -> EP->TO.  If so,
+	     disable it.  */
+	  for (op = reg_eliminate;
+	       op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
+	    if (op->from == new_to && op->to == ep->to)
+	      op->can_eliminate = 0;
+	}
+}
+/* See if any registers that we thought we could eliminate the previous
+time are no longer eliminable.  If so, something has changed and we
+must spill the register.  Also, recompute the number of eliminable
+registers and see if the frame pointer is needed; it is if there is
+no elimination of the frame pointer that we can perform.  */
+frame_pointer_needed = 1;
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+{
+if (ep->can_eliminate
+	  && ep->from == FRAME_POINTER_REGNUM
+	  && ep->to != HARD_FRAME_POINTER_REGNUM
+	  && (! SUPPORTS_STACK_ALIGNMENT
+	      || ! crtl->stack_realign_needed))
+	frame_pointer_needed = 0;
+if (! ep->can_eliminate && ep->can_eliminate_previous)
+	{
+	  ep->can_eliminate_previous = 0;
+	  SET_HARD_REG_BIT (*pset, ep->from);
+	  num_eliminable--;
+	}
+}
+/* If we didn't need a frame pointer last time, but we do now, spill
+the hard frame pointer.  */
+if (frame_pointer_needed && ! previous_frame_pointer_needed)
+SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
+}
+/* Return true if X is used as the target register of an elimination.  */
+bool
+elimination_target_reg_p (rtx x)
+{
+struct elim_table *ep;
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+if (ep->to_rtx == x && ep->can_eliminate)
+return true;
+return false;
+}
+/* Initialize the table of registers to eliminate.
+Pre-condition: global flag frame_pointer_needed has been set before
+calling this function.  */
+static void
+init_elim_table (void)
+{
+struct elim_table *ep;
+#ifdef ELIMINABLE_REGS
+const struct elim_table_1 *ep1;
+#endif
+if (!reg_eliminate)
+reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
+num_eliminable = 0;
+#ifdef ELIMINABLE_REGS
+for (ep = reg_eliminate, ep1 = reg_eliminate_1;
+ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
+{
+ep->from = ep1->from;
+ep->to = ep1->to;
+ep->can_eliminate = ep->can_eliminate_previous
+	= (targetm.can_eliminate (ep->from, ep->to)
+	   && ! (ep->to == STACK_POINTER_REGNUM
+		 && frame_pointer_needed
+		 && (! SUPPORTS_STACK_ALIGNMENT
+		     || ! stack_realign_fp)));
+}
+#else
+reg_eliminate[0].from = reg_eliminate_1[0].from;
+reg_eliminate[0].to = reg_eliminate_1[0].to;
+reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
+= ! frame_pointer_needed;
+#endif
+/* Count the number of eliminable registers and build the FROM and TO
+REG rtx's.  Note that code in gen_rtx_REG will cause, e.g.,
+gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
+We depend on this.  */
+for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+{
+num_eliminable += ep->can_eliminate;
+ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
+ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
+}
+}
+/* Find all the pseudo registers that didn't get hard regs
+but do have known equivalent constants or memory slots.
+These include parameters (known equivalent to parameter slots)
+and cse'd or loop-moved constant memory addresses.
+Record constant equivalents in reg_equiv_constant
+so they will be substituted by find_reloads.
+Record memory equivalents in reg_mem_equiv so they can
+be substituted eventually by altering the REG-rtx's.  */
+static void
+init_eliminable_invariants (rtx first, bool do_subregs)
+{
+int i;
+rtx insn;
 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
 reg_equiv_address = XCNEWVEC (rtx, max_regno);
-reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
+if (do_subregs)
-reg_old_renumber = XCNEWVEC (short, max_regno);
+reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
-memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
+else
-pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
+reg_max_ref_width = NULL;
-pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
-CLEAR_HARD_REG_SET (bad_spill_regs_global);
-/* Look for REG_EQUIV notes; record what each pseudo is equivalent
-to.  Also find all paradoxical subregs and find largest such for
-each pseudo.  */
 num_eliminable_invariants = 0;
+first_label_num = get_first_label_num ();
+num_labels = max_label_num () - first_label_num;
+/* Allocate the tables used to store offset information at labels.  */
+offsets_known_at = XNEWVEC (char, num_labels);
+offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
+/* Look for REG_EQUIV notes; record what each pseudo is equivalent
+to.  If DO_SUBREGS is true, also find all paradoxical subregs and
+find largest such for each pseudo.  FIRST is the head of the insn
+list.  */
 for (insn = first; insn; insn = NEXT_INSN (insn))
 {
 rtx set = single_set (insn);
 /* We may introduce USEs that we want to remove at the end, so
 	 previously-marked insns left by say regmove.  */
 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
 	  && GET_MODE (insn) != VOIDmode)
 	PUT_MODE (insn, VOIDmode);
-if (NONDEBUG_INSN_P (insn))
+if (do_subregs && NONDEBUG_INSN_P (insn))
 	scan_paradoxical_subregs (PATTERN (insn));
 if (set != 0 && REG_P (SET_DEST (set)))
 	{
 	  rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
 	  x = XEXP (note, 0);
 	  if (i <= LAST_VIRTUAL_REGISTER)
 	    continue;
-	  if (! function_invariant_p (x)
+	  /* If flag_pic and we have constant, verify it's legitimate.  */
-	      || ! flag_pic
+	  if (!CONSTANT_P (x)
-	      /* A function invariant is often CONSTANT_P but may
+	      || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
-		 include a register.  We promise to only pass
-		 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P.  */
-	      || (CONSTANT_P (x)
-		  && LEGITIMATE_PIC_OPERAND_P (x)))
 	    {
 	      /* It can happen that a REG_EQUIV note contains a MEM
 		 that is not a legitimate memory operand.  As later
 		 stages of reload assume that all addresses found
 		 in the reg_equiv_* arrays were originally legitimate,
 	{
 	  fprintf (dump_file, "init_insns for %u: ", i);
 	  print_inline_rtx (dump_file, reg_equiv_init[i], 20);
 	  fprintf (dump_file, "\n");
 	}
+}
-init_elim_table ();
+/* Indicate that we no longer have known memory locations or constants.
-first_label_num = get_first_label_num ();
+Free all data involved in tracking these.  */
-num_labels = max_label_num () - first_label_num;
+static void
-/* Allocate the tables used to store offset information at labels.  */
+free_reg_equiv (void)
-/* We used to use alloca here, but the size of what it would try to
+{
-allocate would occasionally cause it to exceed the stack limit and
+int i;
-cause a core dump.  */
-offsets_known_at = XNEWVEC (char, num_labels);
-offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
-/* Alter each pseudo-reg rtx to contain its hard reg number.  Assign
-stack slots to the pseudos that lack hard regs or equivalents.
-Do not touch virtual registers.  */
-temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
-for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
-temp_pseudo_reg_arr[n++] = i;
-if (ira_conflicts_p)
-/* Ask IRA to order pseudo-registers for better stack slot
-sharing.  */
-ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
-for (i = 0; i < n; i++)
-alter_reg (temp_pseudo_reg_arr[i], -1, false);
-/* If we have some registers we think can be eliminated, scan all insns to
-see if there is an insn that sets one of these registers to something
-other than itself plus a constant.  If so, the register cannot be
-eliminated.  Doing this scan here eliminates an extra pass through the
-main reload loop in the most common case where register elimination
-cannot be done.  */
-for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
-if (INSN_P (insn))
-note_stores (PATTERN (insn), mark_not_eliminable, NULL);
-maybe_fix_stack_asms ();
-insns_need_reload = 0;
-something_needs_elimination = 0;
-/* Initialize to -1, which means take the first spill register.  */
-last_spill_reg = -1;
-/* Spill any hard regs that we know we can't eliminate.  */
-CLEAR_HARD_REG_SET (used_spill_regs);
-/* There can be multiple ways to eliminate a register;
-they should be listed adjacently.
-Elimination for any register fails only if all possible ways fail.  */
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; )
-{
-int from = ep->from;
-int can_eliminate = 0;
-do
-	{
-can_eliminate |= ep->can_eliminate;
-ep++;
-	}
-while (ep < &reg_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
-if (! can_eliminate)
-	spill_hard_reg (from, 1);
-}
-#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
-if (frame_pointer_needed)
-spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
-#endif
-finish_spills (global);
-/* From now on, we may need to generate moves differently.  We may also
-allow modifications of insns which cause them to not be recognized.
-Any such modifications will be cleaned up during reload itself.  */
-reload_in_progress = 1;
-/* This loop scans the entire function each go-round
-and repeats until one repetition spills no additional hard regs.  */
-for (;;)
-{
-int something_changed;
-int did_spill;
-HOST_WIDE_INT starting_frame_size;
-starting_frame_size = get_frame_size ();
-something_was_spilled = false;
-set_initial_elim_offsets ();
-set_initial_label_offsets ();
-/* For each pseudo register that has an equivalent location defined,
-	 try to eliminate any eliminable registers (such as the frame pointer)
-	 assuming initial offsets for the replacement register, which
-	 is the normal case.
-	 If the resulting location is directly addressable, substitute
-	 the MEM we just got directly for the old REG.
-	 If it is not addressable but is a constant or the sum of a hard reg
-	 and constant, it is probably not addressable because the constant is
-	 out of range, in that case record the address; we will generate
-	 hairy code to compute the address in a register each time it is
-	 needed.  Similarly if it is a hard register, but one that is not
-	 valid as an address register.
-	 If the location is not addressable, but does not have one of the
-	 above forms, assign a stack slot.  We have to do this to avoid the
-	 potential of producing lots of reloads if, e.g., a location involves
-	 a pseudo that didn't get a hard register and has an equivalent memory
-	 location that also involves a pseudo that didn't get a hard register.
-	 Perhaps at some point we will improve reload_when_needed handling
-	 so this problem goes away.  But that's very hairy.  */
-for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
-	if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
-	  {
-	    rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
-				    NULL_RTX);
-	    if (strict_memory_address_addr_space_p
-		  (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
-		   MEM_ADDR_SPACE (x)))
-	      reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
-	    else if (CONSTANT_P (XEXP (x, 0))
-		     || (REG_P (XEXP (x, 0))
-			 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
-		     || (GET_CODE (XEXP (x, 0)) == PLUS
-			 && REG_P (XEXP (XEXP (x, 0), 0))
-			 && (REGNO (XEXP (XEXP (x, 0), 0))
-			     < FIRST_PSEUDO_REGISTER)
-			 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
-	      reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
-	    else
-	      {
-		/* Make a new stack slot.  Then indicate that something
-		   changed so we go back and recompute offsets for
-		   eliminable registers because the allocation of memory
-		   below might change some offset.  reg_equiv_{mem,address}
-		   will be set up for this pseudo on the next pass around
-		   the loop.  */
-		reg_equiv_memory_loc[i] = 0;
-		reg_equiv_init[i] = 0;
-		alter_reg (i, -1, true);
-	      }
-	  }
-if (caller_save_needed)
-	setup_save_areas ();
-/* If we allocated another stack slot, redo elimination bookkeeping.  */
-if (something_was_spilled || starting_frame_size != get_frame_size ())
-	continue;
-if (starting_frame_size && crtl->stack_alignment_needed)
-	{
-	  /* If we have a stack frame, we must align it now.  The
-	     stack size may be a part of the offset computation for
-	     register elimination.  So if this changes the stack size,
-	     then repeat the elimination bookkeeping.  We don't
-	     realign when there is no stack, as that will cause a
-	     stack frame when none is needed should
-	     STARTING_FRAME_OFFSET not be already aligned to
-	     STACK_BOUNDARY.  */
-	  assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
-	  if (starting_frame_size != get_frame_size ())
-	    continue;
-	}
-if (caller_save_needed)
-	{
-	  save_call_clobbered_regs ();
-	  /* That might have allocated new insn_chain structures.  */
-	  reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
-	}
-calculate_needs_all_insns (global);
-if (! ira_conflicts_p)
-	/* Don't do it for IRA.  We need this info because we don't
-	   change live_throughout and dead_or_set for chains when IRA
-	   is used.  */
-	CLEAR_REG_SET (&spilled_pseudos);
-did_spill = 0;
-something_changed = 0;
-/* If we allocated any new memory locations, make another pass
-	 since it might have changed elimination offsets.  */
-if (something_was_spilled || starting_frame_size != get_frame_size ())
-	something_changed = 1;
-/* Even if the frame size remained the same, we might still have
-	 changed elimination offsets, e.g. if find_reloads called
-	 force_const_mem requiring the back end to allocate a constant
-	 pool base register that needs to be saved on the stack.  */
-else if (!verify_initial_elim_offsets ())
-	something_changed = 1;
-{
-	HARD_REG_SET to_spill;
-	CLEAR_HARD_REG_SET (to_spill);
-	update_eliminables (&to_spill);
-	AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
-	for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	  if (TEST_HARD_REG_BIT (to_spill, i))
-	    {
-	      spill_hard_reg (i, 1);
-	      did_spill = 1;
-	      /* Regardless of the state of spills, if we previously had
-		 a register that we thought we could eliminate, but now can
-		 not eliminate, we must run another pass.
-		 Consider pseudos which have an entry in reg_equiv_* which
-		 reference an eliminable register.  We must make another pass
-		 to update reg_equiv_* so that we do not substitute in the
-		 old value from when we thought the elimination could be
-		 performed.  */
-	      something_changed = 1;
-	    }
-}
-select_reload_regs ();
-if (failure)
-	goto failed;
-if (insns_need_reload != 0 || did_spill)
-	something_changed |= finish_spills (global);
-if (! something_changed)
-	break;
-if (caller_save_needed)
-	delete_caller_save_insns ();
-obstack_free (&reload_obstack, reload_firstobj);
-}
-/* If global-alloc was run, notify it of any register eliminations we have
-done.  */
-if (global)
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-if (ep->can_eliminate)
-	mark_elimination (ep->from, ep->to);
-/* If a pseudo has no hard reg, delete the insns that made the equivalence.
-If that insn didn't set the register (i.e., it copied the register to
-memory), just delete that insn instead of the equivalencing insn plus
-anything now dead.  If we call delete_dead_insn on that insn, we may
-delete the insn that actually sets the register if the register dies
-there and that is incorrect.  */
-for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
-{
-if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
-	{
-	  rtx list;
-	  for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
-	    {
-	      rtx equiv_insn = XEXP (list, 0);
-	      /* If we already deleted the insn or if it may trap, we can't
-		 delete it.  The latter case shouldn't happen, but can
-		 if an insn has a variable address, gets a REG_EH_REGION
-		 note added to it, and then gets converted into a load
-		 from a constant address.  */
-	      if (NOTE_P (equiv_insn)
-		  || can_throw_internal (equiv_insn))
-		;
-	      else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
-		delete_dead_insn (equiv_insn);
-	      else
-		SET_INSN_DELETED (equiv_insn);
-	    }
-	}
-}
-/* Use the reload registers where necessary
-by generating move instructions to move the must-be-register
-values into or out of the reload registers.  */
-if (insns_need_reload != 0 || something_needs_elimination
-|| something_needs_operands_changed)
-{
-HOST_WIDE_INT old_frame_size = get_frame_size ();
-reload_as_needed (global);
-gcc_assert (old_frame_size == get_frame_size ());
-gcc_assert (verify_initial_elim_offsets ());
-}
-/* If we were able to eliminate the frame pointer, show that it is no
-longer live at the start of any basic block.  If it ls live by
-virtue of being in a pseudo, that pseudo will be marked live
-and hence the frame pointer will be known to be live via that
-pseudo.  */
-if (! frame_pointer_needed)
-FOR_EACH_BB (bb)
-bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
-/* Come here (with failure set nonzero) if we can't get enough spill
-regs.  */
-failed:
-CLEAR_REG_SET (&changed_allocation_pseudos);
-CLEAR_REG_SET (&spilled_pseudos);
-reload_in_progress = 0;
-/* Now eliminate all pseudo regs by modifying them into
-their equivalent memory references.
-The REG-rtx's for the pseudos are modified in place,
-so all insns that used to refer to them now refer to memory.
-For a reg that has a reg_equiv_address, all those insns
-were changed by reloading so that no insns refer to it any longer;
-but the DECL_RTL of a variable decl may refer to it,
-and if so this causes the debugging info to mention the variable.  */
-for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
-{
-rtx addr = 0;
-if (reg_equiv_mem[i])
-	addr = XEXP (reg_equiv_mem[i], 0);
-if (reg_equiv_address[i])
-	addr = reg_equiv_address[i];
-if (addr)
-	{
-	  if (reg_renumber[i] < 0)
-	    {
-	      rtx reg = regno_reg_rtx[i];
-	      REG_USERVAR_P (reg) = 0;
-	      PUT_CODE (reg, MEM);
-	      XEXP (reg, 0) = addr;
-	      if (reg_equiv_memory_loc[i])
-		MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
-	      else
-		{
-		  MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
-		  MEM_ATTRS (reg) = 0;
-		}
-	      MEM_NOTRAP_P (reg) = 1;
-	    }
-	  else if (reg_equiv_mem[i])
-	    XEXP (reg_equiv_mem[i], 0) = addr;
-	}
-/* We don't want complex addressing modes in debug insns
-	 if simpler ones will do, so delegitimize equivalences
-	 in debug insns.  */
-if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
-	{
-	  rtx reg = regno_reg_rtx[i];
-	  rtx equiv = 0;
-	  df_ref use, next;
-	  if (reg_equiv_constant[i])
-	    equiv = reg_equiv_constant[i];
-	  else if (reg_equiv_invariant[i])
-	    equiv = reg_equiv_invariant[i];
-	  else if (reg && MEM_P (reg))
-	    equiv = targetm.delegitimize_address (reg);
-	  else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
-	    equiv = reg;
-	  if (equiv == reg)
-	    continue;
-	  for (use = DF_REG_USE_CHAIN (i); use; use = next)
-	    {
-	      insn = DF_REF_INSN (use);
-	      /* Make sure the next ref is for a different instruction,
-		 so that we're not affected by the rescan.  */
-	      next = DF_REF_NEXT_REG (use);
-	      while (next && DF_REF_INSN (next) == insn)
-		next = DF_REF_NEXT_REG (next);
-	      if (DEBUG_INSN_P (insn))
-		{
-		  if (!equiv)
-		    {
-		      INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
-		      df_insn_rescan_debug_internal (insn);
-		    }
-		  else
-		    INSN_VAR_LOCATION_LOC (insn)
-		      = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
-					      reg, equiv);
-		}
-	    }
-	}
-}
-/* We must set reload_completed now since the cleanup_subreg_operands call
-below will re-recognize each insn and reload may have generated insns
-which are only valid during and after reload.  */
-reload_completed = 1;
-/* Make a pass over all the insns and delete all USEs which we inserted
-only to tag a REG_EQUAL note on them.  Remove all REG_DEAD and REG_UNUSED
-notes.  Delete all CLOBBER insns, except those that refer to the return
-value and the special mem:BLK CLOBBERs added to prevent the scheduler
-from misarranging variable-array code, and simplify (subreg (reg))
-operands.  Strip and regenerate REG_INC notes that may have been moved
-around.  */
-for (insn = first; insn; insn = NEXT_INSN (insn))
-if (INSN_P (insn))
-{
-	rtx *pnote;
-	if (CALL_P (insn))
-	  replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
-			      VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
-	if ((GET_CODE (PATTERN (insn)) == USE
-	     /* We mark with QImode USEs introduced by reload itself.  */
-	     && (GET_MODE (insn) == QImode
-		 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
-	    || (GET_CODE (PATTERN (insn)) == CLOBBER
-		&& (!MEM_P (XEXP (PATTERN (insn), 0))
-		    || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
-		    || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
-			&& XEXP (XEXP (PATTERN (insn), 0), 0)
-				!= stack_pointer_rtx))
-		&& (!REG_P (XEXP (PATTERN (insn), 0))
-		    || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
-	  {
-	    delete_insn (insn);
-	    continue;
-	  }
-	/* Some CLOBBERs may survive until here and still reference unassigned
-	   pseudos with const equivalent, which may in turn cause ICE in later
-	   passes if the reference remains in place.  */
-	if (GET_CODE (PATTERN (insn)) == CLOBBER)
-	  replace_pseudos_in (& XEXP (PATTERN (insn), 0),
-			      VOIDmode, PATTERN (insn));
-	/* Discard obvious no-ops, even without -O.  This optimization
-	   is fast and doesn't interfere with debugging.  */
-	if (NONJUMP_INSN_P (insn)
-	    && GET_CODE (PATTERN (insn)) == SET
-	    && REG_P (SET_SRC (PATTERN (insn)))
-	    && REG_P (SET_DEST (PATTERN (insn)))
-	    && (REGNO (SET_SRC (PATTERN (insn)))
-		== REGNO (SET_DEST (PATTERN (insn)))))
-	  {
-	    delete_insn (insn);
-	    continue;
-	  }
-	pnote = &REG_NOTES (insn);
-	while (*pnote != 0)
-	  {
-	    if (REG_NOTE_KIND (*pnote) == REG_DEAD
-		|| REG_NOTE_KIND (*pnote) == REG_UNUSED
-		|| REG_NOTE_KIND (*pnote) == REG_INC)
-	      *pnote = XEXP (*pnote, 1);
-	    else
-	      pnote = &XEXP (*pnote, 1);
-	  }
-#ifdef AUTO_INC_DEC
-	add_auto_inc_notes (insn, PATTERN (insn));
-#endif
-	/* Simplify (subreg (reg)) if it appears as an operand.  */
-	cleanup_subreg_operands (insn);
-	/* Clean up invalid ASMs so that they don't confuse later passes.
-	   See PR 21299.  */
-	if (asm_noperands (PATTERN (insn)) >= 0)
-	  {
-	    extract_insn (insn);
-	    if (!constrain_operands (1))
-	      {
-		error_for_asm (insn,
-			       "%<asm%> operand has impossible constraints");
-		delete_insn (insn);
-		continue;
-	      }
-	  }
-}
-/* If we are doing generic stack checking, give a warning if this
-function's frame size is larger than we expect.  */
-if (flag_stack_check == GENERIC_STACK_CHECK)
-{
-HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
-static int verbose_warned = 0;
-for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
-	  size += UNITS_PER_WORD;
-if (size > STACK_CHECK_MAX_FRAME_SIZE)
-	{
-	  warning (0, "frame size too large for reliable stack checking");
-	  if (! verbose_warned)
-	    {
-	      warning (0, "try reducing the number of local variables");
-	      verbose_warned = 1;
-	    }
-	}
-}
-/* Indicate that we no longer have known memory locations or constants.  */
 if (reg_equiv_constant)
 free (reg_equiv_constant);
 if (reg_equiv_invariant)
 free (reg_equiv_invariant);
 reg_equiv_constant = 0;
 reg_equiv_invariant = 0;
 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
 reg_equiv_memory_loc = 0;
-free (temp_pseudo_reg_arr);
 if (offsets_known_at)
 free (offsets_known_at);
 if (offsets_at)
 free (offsets_at);
+offsets_at = 0;
+offsets_known_at = 0;
 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 if (reg_equiv_alt_mem_list[i])
 free_EXPR_LIST_list (&reg_equiv_alt_mem_list[i]);
 free (reg_equiv_alt_mem_list);
 free (reg_equiv_mem);
-reg_equiv_init = 0;
 free (reg_equiv_address);
-free (reg_max_ref_width);
-free (reg_old_renumber);
-free (pseudo_previous_regs);
-free (pseudo_forbidden_regs);
-CLEAR_HARD_REG_SET (used_spill_regs);
-for (i = 0; i < n_spills; i++)
-SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
-/* Free all the insn_chain structures at once.  */
-obstack_free (&reload_obstack, reload_startobj);
-unused_insn_chains = 0;
-fixup_abnormal_edges ();
-/* Replacing pseudos with their memory equivalents might have
-created shared rtx.  Subsequent passes would get confused
-by this, so unshare everything here.  */
-unshare_all_rtl_again (first);
-#ifdef STACK_BOUNDARY
-/* init_emit has set the alignment of the hard frame pointer
-to STACK_BOUNDARY.  It is very likely no longer valid if
-the hard frame pointer was used for register allocation.  */
-if (!frame_pointer_needed)
-REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
-#endif
-VEC_free (rtx_p, heap, substitute_stack);
-return failure;
-}
-/* Yet another special case.  Unfortunately, reg-stack forces people to
-write incorrect clobbers in asm statements.  These clobbers must not
-cause the register to appear in bad_spill_regs, otherwise we'll call
-fatal_insn later.  We clear the corresponding regnos in the live
-register sets to avoid this.
-The whole thing is rather sick, I'm afraid.  */
-static void
-maybe_fix_stack_asms (void)
-{
-#ifdef STACK_REGS
-const char *constraints[MAX_RECOG_OPERANDS];
-enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
-struct insn_chain *chain;
-for (chain = reload_insn_chain; chain != 0; chain = chain->next)
-{
-int i, noperands;
-HARD_REG_SET clobbered, allowed;
-rtx pat;
-if (! INSN_P (chain->insn)
-	  || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
-	continue;
-pat = PATTERN (chain->insn);
-if (GET_CODE (pat) != PARALLEL)
-	continue;
-CLEAR_HARD_REG_SET (clobbered);
-CLEAR_HARD_REG_SET (allowed);
-/* First, make a mask of all stack regs that are clobbered.  */
-for (i = 0; i < XVECLEN (pat, 0); i++)
-	{
-	  rtx t = XVECEXP (pat, 0, i);
-	  if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
-	    SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
-	}
-/* Get the operand values and constraints out of the insn.  */
-decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
-			   constraints, operand_mode, NULL);
-/* For every operand, see what registers are allowed.  */
-for (i = 0; i < noperands; i++)
-	{
-	  const char *p = constraints[i];
-	  /* For every alternative, we compute the class of registers allowed
-	     for reloading in CLS, and merge its contents into the reg set
-	     ALLOWED.  */
-	  int cls = (int) NO_REGS;
-	  for (;;)
-	    {
-	      char c = *p;
-	      if (c == '\0' || c == ',' || c == '#')
-		{
-		  /* End of one alternative - mark the regs in the current
-		     class, and reset the class.  */
-		  IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
-		  cls = NO_REGS;
-		  p++;
-		  if (c == '#')
-		    do {
-		      c = *p++;
-		    } while (c != '\0' && c != ',');
-		  if (c == '\0')
-		    break;
-		  continue;
-		}
-	      switch (c)
-		{
-		case '=': case '+': case '*': case '%': case '?': case '!':
-		case '0': case '1': case '2': case '3': case '4': case '<':
-		case '>': case 'V': case 'o': case '&': case 'E': case 'F':
-		case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
-		case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
-		case TARGET_MEM_CONSTRAINT:
-		  break;
-		case 'p':
-		  cls = (int) reg_class_subunion[cls]
-		      [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
-		  break;
-		case 'g':
-		case 'r':
-		  cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
-		  break;
-		default:
-		  if (EXTRA_ADDRESS_CONSTRAINT (c, p))
-		    cls = (int) reg_class_subunion[cls]
-		      [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
-		  else
-		    cls = (int) reg_class_subunion[cls]
-		      [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
-		}
-	      p += CONSTRAINT_LEN (c, p);
-	    }
-	}
-/* Those of the registers which are clobbered, but allowed by the
-	 constraints, must be usable as reload registers.  So clear them
-	 out of the life information.  */
-AND_HARD_REG_SET (allowed, clobbered);
-for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	if (TEST_HARD_REG_BIT (allowed, i))
-	  {
-	    CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
-	    CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
-	  }
-}
-#endif
-}
-/* Copy the global variables n_reloads and rld into the corresponding elts
-of CHAIN.  */
-static void
-copy_reloads (struct insn_chain *chain)
-{
-chain->n_reloads = n_reloads;
-chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
-memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
-reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
-}
-/* Walk the chain of insns, and determine for each whether it needs reloads
-and/or eliminations.  Build the corresponding insns_need_reload list, and
-set something_needs_elimination as appropriate.  */
-static void
-calculate_needs_all_insns (int global)
-{
-struct insn_chain **pprev_reload = &insns_need_reload;
-struct insn_chain *chain, *next = 0;
-something_needs_elimination = 0;
-reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
-for (chain = reload_insn_chain; chain != 0; chain = next)
-{
-rtx insn = chain->insn;
-next = chain->next;
-/* Clear out the shortcuts.  */
-chain->n_reloads = 0;
-chain->need_elim = 0;
-chain->need_reload = 0;
-chain->need_operand_change = 0;
-/* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
-	 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
-	 what effects this has on the known offsets at labels.  */
-if (LABEL_P (insn) || JUMP_P (insn)
-	  || (INSN_P (insn) && REG_NOTES (insn) != 0))
-	set_label_offsets (insn, insn, 0);
-if (INSN_P (insn))
-	{
-	  rtx old_body = PATTERN (insn);
-	  int old_code = INSN_CODE (insn);
-	  rtx old_notes = REG_NOTES (insn);
-	  int did_elimination = 0;
-	  int operands_changed = 0;
-	  rtx set = single_set (insn);
-	  /* Skip insns that only set an equivalence.  */
-	  if (set && REG_P (SET_DEST (set))
-	      && reg_renumber[REGNO (SET_DEST (set))] < 0
-	      && (reg_equiv_constant[REGNO (SET_DEST (set))]
-		  || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
-		      && reg_equiv_init[REGNO (SET_DEST (set))])
-	    continue;
-	  /* If needed, eliminate any eliminable registers.  */
-	  if (num_eliminable || num_eliminable_invariants)
-	    did_elimination = eliminate_regs_in_insn (insn, 0);
-	  /* Analyze the instruction.  */
-	  operands_changed = find_reloads (insn, 0, spill_indirect_levels,
-					   global, spill_reg_order);
-	  /* If a no-op set needs more than one reload, this is likely
-	     to be something that needs input address reloads.  We
-	     can't get rid of this cleanly later, and it is of no use
-	     anyway, so discard it now.
-	     We only do this when expensive_optimizations is enabled,
-	     since this complements reload inheritance / output
-	     reload deletion, and it can make debugging harder.  */
-	  if (flag_expensive_optimizations && n_reloads > 1)
-	    {
-	      rtx set = single_set (insn);
-	      if (set
-		  &&
-		  ((SET_SRC (set) == SET_DEST (set)
-		    && REG_P (SET_SRC (set))
-		    && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
-		   || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
-		       && reg_renumber[REGNO (SET_SRC (set))] < 0
-		       && reg_renumber[REGNO (SET_DEST (set))] < 0
-		       && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
-		       && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
-		       && rtx_equal_p (reg_equiv_memory_loc
-				       [REGNO (SET_SRC (set))],
-				       reg_equiv_memory_loc
-				       [REGNO (SET_DEST (set))]))))
-		{
-		  if (ira_conflicts_p)
-		    /* Inform IRA about the insn deletion.  */
-		    ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
-						   REGNO (SET_SRC (set)));
-		  delete_insn (insn);
-		  /* Delete it from the reload chain.  */
-		  if (chain->prev)
-		    chain->prev->next = next;
-		  else
-		    reload_insn_chain = next;
-		  if (next)
-		    next->prev = chain->prev;
-		  chain->next = unused_insn_chains;
-		  unused_insn_chains = chain;
-		  continue;
-		}
-	    }
-	  if (num_eliminable)
-	    update_eliminable_offsets ();
-	  /* Remember for later shortcuts which insns had any reloads or
-	     register eliminations.  */
-	  chain->need_elim = did_elimination;
-	  chain->need_reload = n_reloads > 0;
-	  chain->need_operand_change = operands_changed;
-	  /* Discard any register replacements done.  */
-	  if (did_elimination)
-	    {
-	      obstack_free (&reload_obstack, reload_insn_firstobj);
-	      PATTERN (insn) = old_body;
-	      INSN_CODE (insn) = old_code;
-	      REG_NOTES (insn) = old_notes;
-	      something_needs_elimination = 1;
-	    }
-	  something_needs_operands_changed |= operands_changed;
-	  if (n_reloads != 0)
-	    {
-	      copy_reloads (chain);
-	      *pprev_reload = chain;
-	      pprev_reload = &chain->next_need_reload;
-	    }
-	}
-}
-*pprev_reload = 0;
-}
-/* Comparison function for qsort to decide which of two reloads
-should be handled first.  *P1 and *P2 are the reload numbers.  */
-static int
-reload_reg_class_lower (const void *r1p, const void *r2p)
-{
-int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
-int t;
-/* Consider required reloads before optional ones.  */
-t = rld[r1].optional - rld[r2].optional;
-if (t != 0)
-return t;
-/* Count all solitary classes before non-solitary ones.  */
-t = ((reg_class_size[(int) rld[r2].rclass] == 1)
-- (reg_class_size[(int) rld[r1].rclass] == 1));
-if (t != 0)
-return t;
-/* Aside from solitaires, consider all multi-reg groups first.  */
-t = rld[r2].nregs - rld[r1].nregs;
-if (t != 0)
-return t;
-/* Consider reloads in order of increasing reg-class number.  */
-t = (int) rld[r1].rclass - (int) rld[r2].rclass;
-if (t != 0)
-return t;
-/* If reloads are equally urgent, sort by reload number,
-so that the results of qsort leave nothing to chance.  */
-return r1 - r2;
-}
-/* The cost of spilling each hard reg.  */
-static int spill_cost[FIRST_PSEUDO_REGISTER];
-/* When spilling multiple hard registers, we use SPILL_COST for the first
-spilled hard reg and SPILL_ADD_COST for subsequent regs.  SPILL_ADD_COST
-only the first hard reg for a multi-reg pseudo.  */
-static int spill_add_cost[FIRST_PSEUDO_REGISTER];
-/* Map of hard regno to pseudo regno currently occupying the hard
-reg.  */
-static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
-/* Update the spill cost arrays, considering that pseudo REG is live.  */
-static void
-count_pseudo (int reg)
-{
-int freq = REG_FREQ (reg);
-int r = reg_renumber[reg];
-int nregs;
-if (REGNO_REG_SET_P (&pseudos_counted, reg)
-|| REGNO_REG_SET_P (&spilled_pseudos, reg)
-/* Ignore spilled pseudo-registers which can be here only if IRA
-	 is used.  */
-|| (ira_conflicts_p && r < 0))
-return;
-SET_REGNO_REG_SET (&pseudos_counted, reg);
-gcc_assert (r >= 0);
-spill_add_cost[r] += freq;
-nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
-while (nregs-- > 0)
-{
-hard_regno_to_pseudo_regno[r + nregs] = reg;
-spill_cost[r + nregs] += freq;
-}
-}
-/* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
-contents of BAD_SPILL_REGS for the insn described by CHAIN.  */
-static void
-order_regs_for_reload (struct insn_chain *chain)
-{
-unsigned i;
-HARD_REG_SET used_by_pseudos;
-HARD_REG_SET used_by_pseudos2;
-reg_set_iterator rsi;
-COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
-memset (spill_cost, 0, sizeof spill_cost);
-memset (spill_add_cost, 0, sizeof spill_add_cost);
-for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-hard_regno_to_pseudo_regno[i] = -1;
-/* Count number of uses of each hard reg by pseudo regs allocated to it
-and then order them by decreasing use.  First exclude hard registers
-that are live in or across this insn.  */
-REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
-REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
-IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
-IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
-/* Now find out which pseudos are allocated to it, and update
-hard_reg_n_uses.  */
-CLEAR_REG_SET (&pseudos_counted);
-EXECUTE_IF_SET_IN_REG_SET
-(&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
-{
-count_pseudo (i);
-}
-EXECUTE_IF_SET_IN_REG_SET
-(&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
-{
-count_pseudo (i);
-}
-CLEAR_REG_SET (&pseudos_counted);
-}
-/* Vector of reload-numbers showing the order in which the reloads should
-be processed.  */
-static short reload_order[MAX_RELOADS];
-/* This is used to keep track of the spill regs used in one insn.  */
-static HARD_REG_SET used_spill_regs_local;
-/* We decided to spill hard register SPILLED, which has a size of
-SPILLED_NREGS.  Determine how pseudo REG, which is live during the insn,
-is affected.  We will add it to SPILLED_PSEUDOS if necessary, and we will
-update SPILL_COST/SPILL_ADD_COST.  */
-static void
-count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
-{
-int freq = REG_FREQ (reg);
-int r = reg_renumber[reg];
-int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
-/* Ignore spilled pseudo-registers which can be here only if IRA is
-used.  */
-if ((ira_conflicts_p && r < 0)
-|| REGNO_REG_SET_P (&spilled_pseudos, reg)
-|| spilled + spilled_nregs <= r || r + nregs <= spilled)
-return;
-SET_REGNO_REG_SET (&spilled_pseudos, reg);
-spill_add_cost[r] -= freq;
-while (nregs-- > 0)
-{
-hard_regno_to_pseudo_regno[r + nregs] = -1;
-spill_cost[r + nregs] -= freq;
-}
-}
-/* Find reload register to use for reload number ORDER.  */
-static int
-find_reg (struct insn_chain *chain, int order)
-{
-int rnum = reload_order[order];
-struct reload *rl = rld + rnum;
-int best_cost = INT_MAX;
-int best_reg = -1;
-unsigned int i, j, n;
-int k;
-HARD_REG_SET not_usable;
-HARD_REG_SET used_by_other_reload;
-reg_set_iterator rsi;
-static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
-static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
-COPY_HARD_REG_SET (not_usable, bad_spill_regs);
-IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
-IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
-CLEAR_HARD_REG_SET (used_by_other_reload);
-for (k = 0; k < order; k++)
-{
-int other = reload_order[k];
-if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
-	for (j = 0; j < rld[other].nregs; j++)
-	  SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
-}
-for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-{
-#ifdef REG_ALLOC_ORDER
-unsigned int regno = reg_alloc_order[i];
-#else
-unsigned int regno = i;
-#endif
-if (! TEST_HARD_REG_BIT (not_usable, regno)
-	  && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
-	  && HARD_REGNO_MODE_OK (regno, rl->mode))
-	{
-	  int this_cost = spill_cost[regno];
-	  int ok = 1;
-	  unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
-	  for (j = 1; j < this_nregs; j++)
-	    {
-	      this_cost += spill_add_cost[regno + j];
-	      if ((TEST_HARD_REG_BIT (not_usable, regno + j))
-		  || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
-		ok = 0;
-	    }
-	  if (! ok)
-	    continue;
-	  if (ira_conflicts_p)
-	    {
-	      /* Ask IRA to find a better pseudo-register for
-		 spilling.  */
-	      for (n = j = 0; j < this_nregs; j++)
-		{
-		  int r = hard_regno_to_pseudo_regno[regno + j];
-		  if (r < 0)
-		    continue;
-		  if (n == 0 || regno_pseudo_regs[n - 1] != r)
-		    regno_pseudo_regs[n++] = r;
-		}
-	      regno_pseudo_regs[n++] = -1;
-	      if (best_reg < 0
-		  || ira_better_spill_reload_regno_p (regno_pseudo_regs,
-						      best_regno_pseudo_regs,
-						      rl->in, rl->out,
-						      chain->insn))
-		{
-		  best_reg = regno;
-		  for (j = 0;; j++)
-		    {
-		      best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
-		      if (regno_pseudo_regs[j] < 0)
-			break;
-		    }
-		}
-	      continue;
-	    }
-	  if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
-	    this_cost--;
-	  if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
-	    this_cost--;
-	  if (this_cost < best_cost
-	      /* Among registers with equal cost, prefer caller-saved ones, or
-		 use REG_ALLOC_ORDER if it is defined.  */
-	      || (this_cost == best_cost
-#ifdef REG_ALLOC_ORDER
-		  && (inv_reg_alloc_order[regno]
-		      < inv_reg_alloc_order[best_reg])
-#else
-		  && call_used_regs[regno]
-		  && ! call_used_regs[best_reg]
-#endif
-		  ))
-	    {
-	      best_reg = regno;
-	      best_cost = this_cost;
-	    }
-	}
-}
-if (best_reg == -1)
-return 0;
-if (dump_file)
-fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
-rl->nregs = hard_regno_nregs[best_reg][rl->mode];
-rl->regno = best_reg;
-EXECUTE_IF_SET_IN_REG_SET
-(&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
-{
-count_spilled_pseudo (best_reg, rl->nregs, j);
-}
-EXECUTE_IF_SET_IN_REG_SET
-(&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
-{
-count_spilled_pseudo (best_reg, rl->nregs, j);
-}
-for (i = 0; i < rl->nregs; i++)
-{
-gcc_assert (spill_cost[best_reg + i] == 0);
-gcc_assert (spill_add_cost[best_reg + i] == 0);
-gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
-SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
-}
-return 1;
-}
-/* Find more reload regs to satisfy the remaining need of an insn, which
-is given by CHAIN.
-Do it by ascending class number, since otherwise a reg
-might be spilled for a big class and might fail to count
-for a smaller class even though it belongs to that class.  */
-static void
-find_reload_regs (struct insn_chain *chain)
-{
-int i;
-/* In order to be certain of getting the registers we need,
-we must sort the reloads into order of increasing register class.
-Then our grabbing of reload registers will parallel the process
-that provided the reload registers.  */
-for (i = 0; i < chain->n_reloads; i++)
-{
-/* Show whether this reload already has a hard reg.  */
-if (chain->rld[i].reg_rtx)
-	{
-	  int regno = REGNO (chain->rld[i].reg_rtx);
-	  chain->rld[i].regno = regno;
-	  chain->rld[i].nregs
-	    = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
-	}
-else
-	chain->rld[i].regno = -1;
-reload_order[i] = i;
-}
-n_reloads = chain->n_reloads;
-memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
-CLEAR_HARD_REG_SET (used_spill_regs_local);
-if (dump_file)
-fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
-qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
-/* Compute the order of preference for hard registers to spill.  */
-order_regs_for_reload (chain);
-for (i = 0; i < n_reloads; i++)
-{
-int r = reload_order[i];
-/* Ignore reloads that got marked inoperative.  */
-if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
-	  && ! rld[r].optional
-	  && rld[r].regno == -1)
-	if (! find_reg (chain, i))
-	  {
-	    if (dump_file)
-	      fprintf (dump_file, "reload failure for reload %d\n", r);
-	    spill_failure (chain->insn, rld[r].rclass);
-	    failure = 1;
-	    return;
-	  }
-}
-COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
-IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
-memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
-}
-static void
-select_reload_regs (void)
-{
-struct insn_chain *chain;
-/* Try to satisfy the needs for each insn.  */
-for (chain = insns_need_reload; chain != 0;
-chain = chain->next_need_reload)
-find_reload_regs (chain);
-}
-/* Delete all insns that were inserted by emit_caller_save_insns during
-this iteration.  */
-static void
-delete_caller_save_insns (void)
-{
-struct insn_chain *c = reload_insn_chain;
-while (c != 0)
-{
-while (c != 0 && c->is_caller_save_insn)
-	{
-	  struct insn_chain *next = c->next;
-	  rtx insn = c->insn;
-	  if (c == reload_insn_chain)
-	    reload_insn_chain = next;
-	  delete_insn (insn);
-	  if (next)
-	    next->prev = c->prev;
-	  if (c->prev)
-	    c->prev->next = next;
-	  c->next = unused_insn_chains;
-	  unused_insn_chains = c;
-	  c = next;
-	}
-if (c != 0)
-	c = c->next;
-}
-}
-/* Handle the failure to find a register to spill.
-INSN should be one of the insns which needed this particular spill reg.  */
-static void
-spill_failure (rtx insn, enum reg_class rclass)
-{
-if (asm_noperands (PATTERN (insn)) >= 0)
-error_for_asm (insn, "can't find a register in class %qs while "
-		   "reloading %<asm%>",
-		   reg_class_names[rclass]);
-else
-{
-error ("unable to find a register to spill in class %qs",
-	     reg_class_names[rclass]);
-if (dump_file)
-	{
-	  fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
-	  debug_reload_to_stream (dump_file);
-	}
-fatal_insn ("this is the insn:", insn);
-}
-}
-/* Delete an unneeded INSN and any previous insns who sole purpose is loading
-data that is dead in INSN.  */
-static void
-delete_dead_insn (rtx insn)
-{
-rtx prev = prev_real_insn (insn);
-rtx prev_dest;
-/* If the previous insn sets a register that dies in our insn, delete it
-too.  */
-if (prev && GET_CODE (PATTERN (prev)) == SET
-&& (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
-&& reg_mentioned_p (prev_dest, PATTERN (insn))
-&& find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
-&& ! side_effects_p (SET_SRC (PATTERN (prev))))
-delete_dead_insn (prev);
-SET_INSN_DELETED (insn);
-}
-/* Modify the home of pseudo-reg I.
-The new home is present in reg_renumber[I].
-FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
-or it may be -1, meaning there is none or it is not relevant.
-This is used so that all pseudos spilled from a given hard reg
-can share one stack slot.  */
-static void
-alter_reg (int i, int from_reg, bool dont_share_p)
-{
-/* When outputting an inline function, this can happen
-for a reg that isn't actually used.  */
-if (regno_reg_rtx[i] == 0)
-return;
-/* If the reg got changed to a MEM at rtl-generation time,
-ignore it.  */
-if (!REG_P (regno_reg_rtx[i]))
-return;
-/* Modify the reg-rtx to contain the new hard reg
-number or else to contain its pseudo reg number.  */
-SET_REGNO (regno_reg_rtx[i],
-	     reg_renumber[i] >= 0 ? reg_renumber[i] : i);
-/* If we have a pseudo that is needed but has no hard reg or equivalent,
-allocate a stack slot for it.  */
-if (reg_renumber[i] < 0
-&& REG_N_REFS (i) > 0
-&& reg_equiv_constant[i] == 0
-&& (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
-&& reg_equiv_memory_loc[i] == 0)
-{
-rtx x = NULL_RTX;
-enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
-unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
-unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
-unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
-unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
-int adjust = 0;
-something_was_spilled = true;
-if (ira_conflicts_p)
-	{
-	  /* Mark the spill for IRA.  */
-	  SET_REGNO_REG_SET (&spilled_pseudos, i);
-	  if (!dont_share_p)
-	    x = ira_reuse_stack_slot (i, inherent_size, total_size);
-	}
-if (x)
-	;
-/* Each pseudo reg has an inherent size which comes from its own mode,
-	 and a total size which provides room for paradoxical subregs
-	 which refer to the pseudo reg in wider modes.
-	 We can use a slot already allocated if it provides both
-	 enough inherent space and enough total space.
-	 Otherwise, we allocate a new slot, making sure that it has no less
-	 inherent space, and no less total space, then the previous slot.  */
-else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
-	{
-	  rtx stack_slot;
-	  /* No known place to spill from => no slot to reuse.  */
-	  x = assign_stack_local (mode, total_size,
-				  min_align > inherent_align
-				  || total_size > inherent_size ? -1 : 0);
-	  stack_slot = x;
-	  /* Cancel the big-endian correction done in assign_stack_local.
-	     Get the address of the beginning of the slot.  This is so we
-	     can do a big-endian correction unconditionally below.  */
-	  if (BYTES_BIG_ENDIAN)
-	    {
-	      adjust = inherent_size - total_size;
-	      if (adjust)
-		stack_slot
-		  = adjust_address_nv (x, mode_for_size (total_size
-						         * BITS_PER_UNIT,
-						         MODE_INT, 1),
-				       adjust);
-	    }
-	  if (! dont_share_p && ira_conflicts_p)
-	    /* Inform IRA about allocation a new stack slot.  */
-	    ira_mark_new_stack_slot (stack_slot, i, total_size);
-	}
-/* Reuse a stack slot if possible.  */
-else if (spill_stack_slot[from_reg] != 0
-	       && spill_stack_slot_width[from_reg] >= total_size
-	       && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
-		   >= inherent_size)
-	       && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
-	x = spill_stack_slot[from_reg];
-/* Allocate a bigger slot.  */
-else
-	{
-	  /* Compute maximum size needed, both for inherent size
-	     and for total size.  */
-	  rtx stack_slot;
-	  if (spill_stack_slot[from_reg])
-	    {
-	      if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
-		  > inherent_size)
-		mode = GET_MODE (spill_stack_slot[from_reg]);
-	      if (spill_stack_slot_width[from_reg] > total_size)
-		total_size = spill_stack_slot_width[from_reg];
-	      if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
-		min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
-	    }
-	  /* Make a slot with that size.  */
-	  x = assign_stack_local (mode, total_size,
-				  min_align > inherent_align
-				  || total_size > inherent_size ? -1 : 0);
-	  stack_slot = x;
-	  /* Cancel the  big-endian correction done in assign_stack_local.
-	     Get the address of the beginning of the slot.  This is so we
-	     can do a big-endian correction unconditionally below.  */
-	  if (BYTES_BIG_ENDIAN)
-	    {
-	      adjust = GET_MODE_SIZE (mode) - total_size;
-	      if (adjust)
-		stack_slot
-		  = adjust_address_nv (x, mode_for_size (total_size
-							 * BITS_PER_UNIT,
-							 MODE_INT, 1),
-				       adjust);
-	    }
-	  spill_stack_slot[from_reg] = stack_slot;
-	  spill_stack_slot_width[from_reg] = total_size;
-	}
-/* On a big endian machine, the "address" of the slot
-	 is the address of the low part that fits its inherent mode.  */
-if (BYTES_BIG_ENDIAN && inherent_size < total_size)
-	adjust += (total_size - inherent_size);
-/* If we have any adjustment to make, or if the stack slot is the
-	 wrong mode, make a new stack slot.  */
-x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
-/* Set all of the memory attributes as appropriate for a spill.  */
-set_mem_attrs_for_spill (x);
-/* Save the stack slot for later.  */
-reg_equiv_memory_loc[i] = x;
-}
-}
-/* Mark the slots in regs_ever_live for the hard regs used by
-pseudo-reg number REGNO, accessed in MODE.  */
-static void
-mark_home_live_1 (int regno, enum machine_mode mode)
-{
-int i, lim;
-i = reg_renumber[regno];
-if (i < 0)
-return;
-lim = end_hard_regno (mode, i);
-while (i < lim)
-df_set_regs_ever_live(i++, true);
-}
-/* Mark the slots in regs_ever_live for the hard regs
-used by pseudo-reg number REGNO.  */
-void
-mark_home_live (int regno)
-{
-if (reg_renumber[regno] >= 0)
-mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
-}
-/* This function handles the tracking of elimination offsets around branches.
-X is a piece of RTL being scanned.
-INSN is the insn that it came from, if any.
-INITIAL_P is nonzero if we are to set the offset to be the initial
-offset and zero if we are setting the offset of the label to be the
-current offset.  */
-static void
-set_label_offsets (rtx x, rtx insn, int initial_p)
-{
-enum rtx_code code = GET_CODE (x);
-rtx tem;
-unsigned int i;
-struct elim_table *p;
-switch (code)
-{
-case LABEL_REF:
-if (LABEL_REF_NONLOCAL_P (x))
-	return;
-x = XEXP (x, 0);
-/* ... fall through ...  */
-case CODE_LABEL:
-/* If we know nothing about this label, set the desired offsets.  Note
-	 that this sets the offset at a label to be the offset before a label
-	 if we don't know anything about the label.  This is not correct for
-	 the label after a BARRIER, but is the best guess we can make.  If
-	 we guessed wrong, we will suppress an elimination that might have
-	 been possible had we been able to guess correctly.  */
-if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
-	{
-	  for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
-	    offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
-	      = (initial_p ? reg_eliminate[i].initial_offset
-		 : reg_eliminate[i].offset);
-	  offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
-	}
-/* Otherwise, if this is the definition of a label and it is
-	 preceded by a BARRIER, set our offsets to the known offset of
-	 that label.  */
-else if (x == insn
-	       && (tem = prev_nonnote_insn (insn)) != 0
-	       && BARRIER_P (tem))
-	set_offsets_for_label (insn);
-else
-	/* If neither of the above cases is true, compare each offset
-	   with those previously recorded and suppress any eliminations
-	   where the offsets disagree.  */
-	for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
-	  if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
-	      != (initial_p ? reg_eliminate[i].initial_offset
-		  : reg_eliminate[i].offset))
-	    reg_eliminate[i].can_eliminate = 0;
-return;
-case JUMP_INSN:
-set_label_offsets (PATTERN (insn), insn, initial_p);
-/* ... fall through ...  */
-case INSN:
-case CALL_INSN:
-/* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
-	 to indirectly and hence must have all eliminations at their
-	 initial offsets.  */
-for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
-	if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
-	  set_label_offsets (XEXP (tem, 0), insn, 1);
-return;
-case PARALLEL:
-case ADDR_VEC:
-case ADDR_DIFF_VEC:
-/* Each of the labels in the parallel or address vector must be
-	 at their initial offsets.  We want the first field for PARALLEL
-	 and ADDR_VEC and the second field for ADDR_DIFF_VEC.  */
-for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
-	set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
-			   insn, initial_p);
-return;
-case SET:
-/* We only care about setting PC.  If the source is not RETURN,
-	 IF_THEN_ELSE, or a label, disable any eliminations not at
-	 their initial offsets.  Similarly if any arm of the IF_THEN_ELSE
-	 isn't one of those possibilities.  For branches to a label,
-	 call ourselves recursively.
-	 Note that this can disable elimination unnecessarily when we have
-	 a non-local goto since it will look like a non-constant jump to
-	 someplace in the current function.  This isn't a significant
-	 problem since such jumps will normally be when all elimination
-	 pairs are back to their initial offsets.  */
-if (SET_DEST (x) != pc_rtx)
-	return;
-switch (GET_CODE (SET_SRC (x)))
-	{
-	case PC:
-	case RETURN:
-	  return;
-	case LABEL_REF:
-	  set_label_offsets (SET_SRC (x), insn, initial_p);
-	  return;
-	case IF_THEN_ELSE:
-	  tem = XEXP (SET_SRC (x), 1);
-	  if (GET_CODE (tem) == LABEL_REF)
-	    set_label_offsets (XEXP (tem, 0), insn, initial_p);
-	  else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
-	    break;
-	  tem = XEXP (SET_SRC (x), 2);
-	  if (GET_CODE (tem) == LABEL_REF)
-	    set_label_offsets (XEXP (tem, 0), insn, initial_p);
-	  else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
-	    break;
-	  return;
-	default:
-	  break;
-	}
-/* If we reach here, all eliminations must be at their initial
-	 offset because we are doing a jump to a variable address.  */
-for (p = reg_eliminate; p < &reg_eliminate[NUM_ELIMINABLE_REGS]; p++)
-	if (p->offset != p->initial_offset)
-	  p->can_eliminate = 0;
-break;
-default:
-break;
-}
-}
-/* Scan X and replace any eliminable registers (such as fp) with a
-replacement (such as sp), plus an offset.
-MEM_MODE is the mode of an enclosing MEM.  We need this to know how
-much to adjust a register for, e.g., PRE_DEC.  Also, if we are inside a
-MEM, we are allowed to replace a sum of a register and the constant zero
-with the register, which we cannot do outside a MEM.  In addition, we need
-to record the fact that a register is referenced outside a MEM.
-If INSN is an insn, it is the insn containing X.  If we replace a REG
-in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
-CLOBBER of the pseudo after INSN so find_equiv_regs will know that
-the REG is being modified.
-Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
-That's used when we eliminate in expressions stored in notes.
-This means, do not set ref_outside_mem even if the reference
-is outside of MEMs.
-REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
-replacements done assuming all offsets are at their initial values.  If
-they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
-encounter, return the actual location so that find_reloads will do
-the proper thing.  */
-static rtx
-eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
-		  bool may_use_invariant)
-{
-enum rtx_code code = GET_CODE (x);
-struct elim_table *ep;
-int regno;
-rtx new_rtx;
-int i, j;
-const char *fmt;
-int copied = 0;
-if (! current_function_decl)
-return x;
-switch (code)
-{
-case CONST_INT:
-case CONST_DOUBLE:
-case CONST_FIXED:
-case CONST_VECTOR:
-case CONST:
-case SYMBOL_REF:
-case CODE_LABEL:
-case PC:
-case CC0:
-case ASM_INPUT:
-case ADDR_VEC:
-case ADDR_DIFF_VEC:
-case RETURN:
-return x;
-case REG:
-regno = REGNO (x);
-/* First handle the case where we encounter a bare register that
-	 is eliminable.  Replace it with a PLUS.  */
-if (regno < FIRST_PSEUDO_REGISTER)
-	{
-	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
-	       ep++)
-	    if (ep->from_rtx == x && ep->can_eliminate)
-	      return plus_constant (ep->to_rtx, ep->previous_offset);
-	}
-else if (reg_renumber && reg_renumber[regno] < 0
-	       && reg_equiv_invariant && reg_equiv_invariant[regno])
-	{
-	  if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
-	    return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
-			             mem_mode, insn, true);
-	  /* There exists at least one use of REGNO that cannot be
-	     eliminated.  Prevent the defining insn from being deleted.  */
-	  reg_equiv_init[regno] = NULL_RTX;
-	  alter_reg (regno, -1, true);
-	}
-return x;
-/* You might think handling MINUS in a manner similar to PLUS is a
-good idea.  It is not.  It has been tried multiple times and every
-time the change has had to have been reverted.
-Other parts of reload know a PLUS is special (gen_reload for example)
-and require special code to handle code a reloaded PLUS operand.
-Also consider backends where the flags register is clobbered by a
-MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
-lea instruction comes to mind).  If we try to reload a MINUS, we
-may kill the flags register that was holding a useful value.
-So, please before trying to handle MINUS, consider reload as a
-whole instead of this little section as well as the backend issues.  */
-case PLUS:
-/* If this is the sum of an eliminable register and a constant, rework
-	 the sum.  */
-if (REG_P (XEXP (x, 0))
-	  && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
-	  && CONSTANT_P (XEXP (x, 1)))
-	{
-	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
-	       ep++)
-	    if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
-	      {
-		/* The only time we want to replace a PLUS with a REG (this
-		   occurs when the constant operand of the PLUS is the negative
-		   of the offset) is when we are inside a MEM.  We won't want
-		   to do so at other times because that would change the
-		   structure of the insn in a way that reload can't handle.
-		   We special-case the commonest situation in
-		   eliminate_regs_in_insn, so just replace a PLUS with a
-		   PLUS here, unless inside a MEM.  */
-		if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
-		    && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
-		  return ep->to_rtx;
-		else
-		  return gen_rtx_PLUS (Pmode, ep->to_rtx,
-				       plus_constant (XEXP (x, 1),
-						      ep->previous_offset));
-	      }
-	  /* If the register is not eliminable, we are done since the other
-	     operand is a constant.  */
-	  return x;
-	}
-/* If this is part of an address, we want to bring any constant to the
-	 outermost PLUS.  We will do this by doing register replacement in
-	 our operands and seeing if a constant shows up in one of them.
-	 Note that there is no risk of modifying the structure of the insn,
-	 since we only get called for its operands, thus we are either
-	 modifying the address inside a MEM, or something like an address
-	 operand of a load-address insn.  */
-{
-	rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
-	rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
-	if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
-	  {
-	    /* If one side is a PLUS and the other side is a pseudo that
-	       didn't get a hard register but has a reg_equiv_constant,
-	       we must replace the constant here since it may no longer
-	       be in the position of any operand.  */
-	    if (GET_CODE (new0) == PLUS && REG_P (new1)
-		&& REGNO (new1) >= FIRST_PSEUDO_REGISTER
-		&& reg_renumber[REGNO (new1)] < 0
-		&& reg_equiv_constant != 0
-		&& reg_equiv_constant[REGNO (new1)] != 0)
-	      new1 = reg_equiv_constant[REGNO (new1)];
-	    else if (GET_CODE (new1) == PLUS && REG_P (new0)
-		     && REGNO (new0) >= FIRST_PSEUDO_REGISTER
-		     && reg_renumber[REGNO (new0)] < 0
-		     && reg_equiv_constant[REGNO (new0)] != 0)
-	      new0 = reg_equiv_constant[REGNO (new0)];
-	    new_rtx = form_sum (GET_MODE (x), new0, new1);
-	    /* As above, if we are not inside a MEM we do not want to
-	       turn a PLUS into something else.  We might try to do so here
-	       for an addition of 0 if we aren't optimizing.  */
-	    if (! mem_mode && GET_CODE (new_rtx) != PLUS)
-	      return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
-	    else
-	      return new_rtx;
-	  }
-}
-return x;
-case MULT:
-/* If this is the product of an eliminable register and a
-	 constant, apply the distribute law and move the constant out
-	 so that we have (plus (mult ..) ..).  This is needed in order
-	 to keep load-address insns valid.   This case is pathological.
-	 We ignore the possibility of overflow here.  */
-if (REG_P (XEXP (x, 0))
-	  && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
-	  && CONST_INT_P (XEXP (x, 1)))
-	for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
-	     ep++)
-	  if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
-	    {
-	      if (! mem_mode
-		  /* Refs inside notes or in DEBUG_INSNs don't count for
-		     this purpose.  */
-		  && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
-				      || GET_CODE (insn) == INSN_LIST
-				      || DEBUG_INSN_P (insn))))
-		ep->ref_outside_mem = 1;
-	      return
-		plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
-			       ep->previous_offset * INTVAL (XEXP (x, 1)));
-	    }
-/* ... fall through ...  */
-case CALL:
-case COMPARE:
-/* See comments before PLUS about handling MINUS.  */
-case MINUS:
-case DIV:      case UDIV:
-case MOD:      case UMOD:
-case AND:      case IOR:      case XOR:
-case ROTATERT: case ROTATE:
-case ASHIFTRT: case LSHIFTRT: case ASHIFT:
-case NE:       case EQ:
-case GE:       case GT:       case GEU:    case GTU:
-case LE:       case LT:       case LEU:    case LTU:
-{
-	rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
-	rtx new1 = XEXP (x, 1)
-		   ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
-	if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
-	  return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
-}
-return x;
-case EXPR_LIST:
-/* If we have something in XEXP (x, 0), the usual case, eliminate it.  */
-if (XEXP (x, 0))
-	{
-	  new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
-	  if (new_rtx != XEXP (x, 0))
-	    {
-	      /* If this is a REG_DEAD note, it is not valid anymore.
-		 Using the eliminated version could result in creating a
-		 REG_DEAD note for the stack or frame pointer.  */
-	      if (REG_NOTE_KIND (x) == REG_DEAD)
-		return (XEXP (x, 1)
-			? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
-			: NULL_RTX);
-	      x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
-	    }
-	}
-/* ... fall through ...  */
-case INSN_LIST:
-/* Now do eliminations in the rest of the chain.  If this was
-	 an EXPR_LIST, this might result in allocating more memory than is
-	 strictly needed, but it simplifies the code.  */
-if (XEXP (x, 1))
-	{
-	  new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
-	  if (new_rtx != XEXP (x, 1))
-	    return
-	      gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
-	}
-return x;
-case PRE_INC:
-case POST_INC:
-case PRE_DEC:
-case POST_DEC:
-/* We do not support elimination of a register that is modified.
-	 elimination_effects has already make sure that this does not
-	 happen.  */
-return x;
-case PRE_MODIFY:
-case POST_MODIFY:
-/* We do not support elimination of a register that is modified.
-	 elimination_effects has already make sure that this does not
-	 happen.  The only remaining case we need to consider here is
-	 that the increment value may be an eliminable register.  */
-if (GET_CODE (XEXP (x, 1)) == PLUS
-	  && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
-	{
-	  rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
-				      insn, true);
-	  if (new_rtx != XEXP (XEXP (x, 1), 1))
-	    return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
-				   gen_rtx_PLUS (GET_MODE (x),
-						 XEXP (x, 0), new_rtx));
-	}
-return x;
-case STRICT_LOW_PART:
-case NEG:          case NOT:
-case SIGN_EXTEND:  case ZERO_EXTEND:
-case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
-case FLOAT:        case FIX:
-case UNSIGNED_FIX: case UNSIGNED_FLOAT:
-case ABS:
-case SQRT:
-case FFS:
-case CLZ:
-case CTZ:
-case POPCOUNT:
-case PARITY:
-case BSWAP:
-new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
-if (new_rtx != XEXP (x, 0))
-	return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
-return x;
-case SUBREG:
-/* Similar to above processing, but preserve SUBREG_BYTE.
-	 Convert (subreg (mem)) to (mem) if not paradoxical.
-	 Also, if we have a non-paradoxical (subreg (pseudo)) and the
-	 pseudo didn't get a hard reg, we must replace this with the
-	 eliminated version of the memory location because push_reload
-	 may do the replacement in certain circumstances.  */
-if (REG_P (SUBREG_REG (x))
-	  && (GET_MODE_SIZE (GET_MODE (x))
-	      <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
-	  && reg_equiv_memory_loc != 0
-	  && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
-	{
-	  new_rtx = SUBREG_REG (x);
-	}
-else
-	new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
-if (new_rtx != SUBREG_REG (x))
-	{
-	  int x_size = GET_MODE_SIZE (GET_MODE (x));
-	  int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
-	  if (MEM_P (new_rtx)
-	      && ((x_size < new_size
-#ifdef WORD_REGISTER_OPERATIONS
-		   /* On these machines, combine can create rtl of the form
-		      (set (subreg:m1 (reg:m2 R) 0) ...)
-		      where m1 < m2, and expects something interesting to
-		      happen to the entire word.  Moreover, it will use the
-		      (reg:m2 R) later, expecting all bits to be preserved.
-		      So if the number of words is the same, preserve the
-		      subreg so that push_reload can see it.  */
-		   && ! ((x_size - 1) / UNITS_PER_WORD
-			 == (new_size -1 ) / UNITS_PER_WORD)
-#endif
-		   )
-		  || x_size == new_size)
-	      )
-	    return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
-	  else
-	    return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
-	}
-return x;
-case MEM:
-/* Our only special processing is to pass the mode of the MEM to our
-	 recursive call and copy the flags.  While we are here, handle this
-	 case more efficiently.  */
-return
-	replace_equiv_address_nv (x,
-				  eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
-						    insn, true));
-case USE:
-/* Handle insn_list USE that a call to a pure function may generate.  */
-new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false);
-if (new_rtx != XEXP (x, 0))
-	return gen_rtx_USE (GET_MODE (x), new_rtx);
-return x;
-case CLOBBER:
-gcc_assert (insn && DEBUG_INSN_P (insn));
-break;
-case ASM_OPERANDS:
-case SET:
-gcc_unreachable ();
-default:
-break;
-}
-/* Process each of our operands recursively.  If any have changed, make a
-copy of the rtx.  */
-fmt = GET_RTX_FORMAT (code);
-for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
-{
-if (*fmt == 'e')
-	{
-	  new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
-	  if (new_rtx != XEXP (x, i) && ! copied)
-	    {
-	      x = shallow_copy_rtx (x);
-	      copied = 1;
-	    }
-	  XEXP (x, i) = new_rtx;
-	}
-else if (*fmt == 'E')
-	{
-	  int copied_vec = 0;
-	  for (j = 0; j < XVECLEN (x, i); j++)
-	    {
-	      new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
-	      if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
-		{
-		  rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
-					     XVEC (x, i)->elem);
-		  if (! copied)
-		    {
-		      x = shallow_copy_rtx (x);
-		      copied = 1;
-		    }
-		  XVEC (x, i) = new_v;
-		  copied_vec = 1;
-		}
-	      XVECEXP (x, i, j) = new_rtx;
-	    }
-	}
-}
-return x;
-}
-rtx
-eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
-{
-return eliminate_regs_1 (x, mem_mode, insn, false);
-}
-/* Scan rtx X for modifications of elimination target registers.  Update
-the table of eliminables to reflect the changed state.  MEM_MODE is
-the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM.  */
-static void
-elimination_effects (rtx x, enum machine_mode mem_mode)
-{
-enum rtx_code code = GET_CODE (x);
-struct elim_table *ep;
-int regno;
-int i, j;
-const char *fmt;
-switch (code)
-{
-case CONST_INT:
-case CONST_DOUBLE:
-case CONST_FIXED:
-case CONST_VECTOR:
-case CONST:
-case SYMBOL_REF:
-case CODE_LABEL:
-case PC:
-case CC0:
-case ASM_INPUT:
-case ADDR_VEC:
-case ADDR_DIFF_VEC:
-case RETURN:
-return;
-case REG:
-regno = REGNO (x);
-/* First handle the case where we encounter a bare register that
-	 is eliminable.  Replace it with a PLUS.  */
-if (regno < FIRST_PSEUDO_REGISTER)
-	{
-	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
-	       ep++)
-	    if (ep->from_rtx == x && ep->can_eliminate)
-	      {
-		if (! mem_mode)
-		  ep->ref_outside_mem = 1;
-		return;
-	      }
-	}
-else if (reg_renumber[regno] < 0 && reg_equiv_constant
-	       && reg_equiv_constant[regno]
-	       && ! function_invariant_p (reg_equiv_constant[regno]))
-	elimination_effects (reg_equiv_constant[regno], mem_mode);
-return;
-case PRE_INC:
-case POST_INC:
-case PRE_DEC:
-case POST_DEC:
-case POST_MODIFY:
-case PRE_MODIFY:
-/* If we modify the source of an elimination rule, disable it.  */
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-	if (ep->from_rtx == XEXP (x, 0))
-	  ep->can_eliminate = 0;
-/* If we modify the target of an elimination rule by adding a constant,
-	 update its offset.  If we modify the target in any other way, we'll
-	 have to disable the rule as well.  */
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-	if (ep->to_rtx == XEXP (x, 0))
-	  {
-	    int size = GET_MODE_SIZE (mem_mode);
-	    /* If more bytes than MEM_MODE are pushed, account for them.  */
-#ifdef PUSH_ROUNDING
-	    if (ep->to_rtx == stack_pointer_rtx)
-	      size = PUSH_ROUNDING (size);
-#endif
-	    if (code == PRE_DEC || code == POST_DEC)
-	      ep->offset += size;
-	    else if (code == PRE_INC || code == POST_INC)
-	      ep->offset -= size;
-	    else if (code == PRE_MODIFY || code == POST_MODIFY)
-	      {
-		if (GET_CODE (XEXP (x, 1)) == PLUS
-		    && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
-		    && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
-		  ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
-		else
-		  ep->can_eliminate = 0;
-	      }
-	  }
-/* These two aren't unary operators.  */
-if (code == POST_MODIFY || code == PRE_MODIFY)
-	break;
-/* Fall through to generic unary operation case.  */
-case STRICT_LOW_PART:
-case NEG:          case NOT:
-case SIGN_EXTEND:  case ZERO_EXTEND:
-case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
-case FLOAT:        case FIX:
-case UNSIGNED_FIX: case UNSIGNED_FLOAT:
-case ABS:
-case SQRT:
-case FFS:
-case CLZ:
-case CTZ:
-case POPCOUNT:
-case PARITY:
-case BSWAP:
-elimination_effects (XEXP (x, 0), mem_mode);
-return;
-case SUBREG:
-if (REG_P (SUBREG_REG (x))
-	  && (GET_MODE_SIZE (GET_MODE (x))
-	      <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
-	  && reg_equiv_memory_loc != 0
-	  && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
-	return;
-elimination_effects (SUBREG_REG (x), mem_mode);
-return;
-case USE:
-/* If using a register that is the source of an eliminate we still
-	 think can be performed, note it cannot be performed since we don't
-	 know how this register is used.  */
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-	if (ep->from_rtx == XEXP (x, 0))
-	  ep->can_eliminate = 0;
-elimination_effects (XEXP (x, 0), mem_mode);
-return;
-case CLOBBER:
-/* If clobbering a register that is the replacement register for an
-	 elimination we still think can be performed, note that it cannot
-	 be performed.  Otherwise, we need not be concerned about it.  */
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-	if (ep->to_rtx == XEXP (x, 0))
-	  ep->can_eliminate = 0;
-elimination_effects (XEXP (x, 0), mem_mode);
-return;
-case SET:
-/* Check for setting a register that we know about.  */
-if (REG_P (SET_DEST (x)))
-	{
-	  /* See if this is setting the replacement register for an
-	     elimination.
-	     If DEST is the hard frame pointer, we do nothing because we
-	     assume that all assignments to the frame pointer are for
-	     non-local gotos and are being done at a time when they are valid
-	     and do not disturb anything else.  Some machines want to
-	     eliminate a fake argument pointer (or even a fake frame pointer)
-	     with either the real frame or the stack pointer.  Assignments to
-	     the hard frame pointer must not prevent this elimination.  */
-	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
-	       ep++)
-	    if (ep->to_rtx == SET_DEST (x)
-		&& SET_DEST (x) != hard_frame_pointer_rtx)
-	      {
-		/* If it is being incremented, adjust the offset.  Otherwise,
-		   this elimination can't be done.  */
-		rtx src = SET_SRC (x);
-		if (GET_CODE (src) == PLUS
-		    && XEXP (src, 0) == SET_DEST (x)
-		    && CONST_INT_P (XEXP (src, 1)))
-		  ep->offset -= INTVAL (XEXP (src, 1));
-		else
-		  ep->can_eliminate = 0;
-	      }
-	}
-elimination_effects (SET_DEST (x), VOIDmode);
-elimination_effects (SET_SRC (x), VOIDmode);
-return;
-case MEM:
-/* Our only special processing is to pass the mode of the MEM to our
-	 recursive call.  */
-elimination_effects (XEXP (x, 0), GET_MODE (x));
-return;
-default:
-break;
-}
-fmt = GET_RTX_FORMAT (code);
-for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
-{
-if (*fmt == 'e')
-	elimination_effects (XEXP (x, i), mem_mode);
-else if (*fmt == 'E')
-	for (j = 0; j < XVECLEN (x, i); j++)
-	  elimination_effects (XVECEXP (x, i, j), mem_mode);
-}
-}
-/* Descend through rtx X and verify that no references to eliminable registers
-remain.  If any do remain, mark the involved register as not
-eliminable.  */
-static void
-check_eliminable_occurrences (rtx x)
-{
-const char *fmt;
-int i;
-enum rtx_code code;
-if (x == 0)
-return;
-code = GET_CODE (x);
-if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
-{
-struct elim_table *ep;
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-	if (ep->from_rtx == x)
-	  ep->can_eliminate = 0;
-return;
-}
-fmt = GET_RTX_FORMAT (code);
-for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
-{
-if (*fmt == 'e')
-	check_eliminable_occurrences (XEXP (x, i));
-else if (*fmt == 'E')
-	{
-	  int j;
-	  for (j = 0; j < XVECLEN (x, i); j++)
-	    check_eliminable_occurrences (XVECEXP (x, i, j));
-	}
-}
-}
-/* Scan INSN and eliminate all eliminable registers in it.
-If REPLACE is nonzero, do the replacement destructively.  Also
-delete the insn as dead it if it is setting an eliminable register.
-If REPLACE is zero, do all our allocations in reload_obstack.
-If no eliminations were done and this insn doesn't require any elimination
-processing (these are not identical conditions: it might be updating sp,
-but not referencing fp; this needs to be seen during reload_as_needed so
-that the offset between fp and sp can be taken into consideration), zero
-is returned.  Otherwise, 1 is returned.  */
-static int
-eliminate_regs_in_insn (rtx insn, int replace)
-{
-int icode = recog_memoized (insn);
-rtx old_body = PATTERN (insn);
-int insn_is_asm = asm_noperands (old_body) >= 0;
-rtx old_set = single_set (insn);
-rtx new_body;
-int val = 0;
-int i;
-rtx substed_operand[MAX_RECOG_OPERANDS];
-rtx orig_operand[MAX_RECOG_OPERANDS];
-struct elim_table *ep;
-rtx plus_src, plus_cst_src;
-if (! insn_is_asm && icode < 0)
-{
-gcc_assert (GET_CODE (PATTERN (insn)) == USE
-		  || GET_CODE (PATTERN (insn)) == CLOBBER
-		  || GET_CODE (PATTERN (insn)) == ADDR_VEC
-		  || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
-		  || GET_CODE (PATTERN (insn)) == ASM_INPUT
-		  || DEBUG_INSN_P (insn));
-if (DEBUG_INSN_P (insn))
-	INSN_VAR_LOCATION_LOC (insn)
-	  = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
-return 0;
-}
-if (old_set != 0 && REG_P (SET_DEST (old_set))
-&& REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
-{
-/* Check for setting an eliminable register.  */
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-	if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
-	  {
-#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
-	    /* If this is setting the frame pointer register to the
-	       hardware frame pointer register and this is an elimination
-	       that will be done (tested above), this insn is really
-	       adjusting the frame pointer downward to compensate for
-	       the adjustment done before a nonlocal goto.  */
-	    if (ep->from == FRAME_POINTER_REGNUM
-		&& ep->to == HARD_FRAME_POINTER_REGNUM)
-	      {
-		rtx base = SET_SRC (old_set);
-		rtx base_insn = insn;
-		HOST_WIDE_INT offset = 0;
-		while (base != ep->to_rtx)
-		  {
-		    rtx prev_insn, prev_set;
-		    if (GET_CODE (base) == PLUS
-		        && CONST_INT_P (XEXP (base, 1)))
-		      {
-		        offset += INTVAL (XEXP (base, 1));
-		        base = XEXP (base, 0);
-		      }
-		    else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
-			     && (prev_set = single_set (prev_insn)) != 0
-			     && rtx_equal_p (SET_DEST (prev_set), base))
-		      {
-		        base = SET_SRC (prev_set);
-		        base_insn = prev_insn;
-		      }
-		    else
-		      break;
-		  }
-		if (base == ep->to_rtx)
-		  {
-		    rtx src
-		      = plus_constant (ep->to_rtx, offset - ep->offset);
-		    new_body = old_body;
-		    if (! replace)
-		      {
-			new_body = copy_insn (old_body);
-			if (REG_NOTES (insn))
-			  REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
-		      }
-		    PATTERN (insn) = new_body;
-		    old_set = single_set (insn);
-		    /* First see if this insn remains valid when we
-		       make the change.  If not, keep the INSN_CODE
-		       the same and let reload fit it up.  */
-		    validate_change (insn, &SET_SRC (old_set), src, 1);
-		    validate_change (insn, &SET_DEST (old_set),
-				     ep->to_rtx, 1);
-		    if (! apply_change_group ())
-		      {
-			SET_SRC (old_set) = src;
-			SET_DEST (old_set) = ep->to_rtx;
-		      }
-		    val = 1;
-		    goto done;
-		  }
-	      }
-#endif
-	    /* In this case this insn isn't serving a useful purpose.  We
-	       will delete it in reload_as_needed once we know that this
-	       elimination is, in fact, being done.
-	       If REPLACE isn't set, we can't delete this insn, but needn't
-	       process it since it won't be used unless something changes.  */
-	    if (replace)
-	      {
-		delete_dead_insn (insn);
-		return 1;
-	      }
-	    val = 1;
-	    goto done;
-	  }
-}
-/* We allow one special case which happens to work on all machines we
-currently support: a single set with the source or a REG_EQUAL
-note being a PLUS of an eliminable register and a constant.  */
-plus_src = plus_cst_src = 0;
-if (old_set && REG_P (SET_DEST (old_set)))
-{
-if (GET_CODE (SET_SRC (old_set)) == PLUS)
-	plus_src = SET_SRC (old_set);
-/* First see if the source is of the form (plus (...) CST).  */
-if (plus_src
-	  && CONST_INT_P (XEXP (plus_src, 1)))
-	plus_cst_src = plus_src;
-else if (REG_P (SET_SRC (old_set))
-	       || plus_src)
-	{
-	  /* Otherwise, see if we have a REG_EQUAL note of the form
-	     (plus (...) CST).  */
-	  rtx links;
-	  for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
-	    {
-	      if ((REG_NOTE_KIND (links) == REG_EQUAL
-		   || REG_NOTE_KIND (links) == REG_EQUIV)
-		  && GET_CODE (XEXP (links, 0)) == PLUS
-		  && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
-		{
-		  plus_cst_src = XEXP (links, 0);
-		  break;
-		}
-	    }
-	}
-/* Check that the first operand of the PLUS is a hard reg or
-	 the lowpart subreg of one.  */
-if (plus_cst_src)
-	{
-	  rtx reg = XEXP (plus_cst_src, 0);
-	  if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
-	    reg = SUBREG_REG (reg);
-	  if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
-	    plus_cst_src = 0;
-	}
-}
-if (plus_cst_src)
-{
-rtx reg = XEXP (plus_cst_src, 0);
-HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
-if (GET_CODE (reg) == SUBREG)
-	reg = SUBREG_REG (reg);
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-	if (ep->from_rtx == reg && ep->can_eliminate)
-	  {
-	    rtx to_rtx = ep->to_rtx;
-	    offset += ep->offset;
-	    offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
-	    if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
-	      to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
-				    to_rtx);
-	    /* If we have a nonzero offset, and the source is already
-	       a simple REG, the following transformation would
-	       increase the cost of the insn by replacing a simple REG
-	       with (plus (reg sp) CST).  So try only when we already
-	       had a PLUS before.  */
-	    if (offset == 0 || plus_src)
-	      {
-		rtx new_src = plus_constant (to_rtx, offset);
-		new_body = old_body;
-		if (! replace)
-		  {
-		    new_body = copy_insn (old_body);
-		    if (REG_NOTES (insn))
-		      REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
-		  }
-		PATTERN (insn) = new_body;
-		old_set = single_set (insn);
-		/* First see if this insn remains valid when we make the
-		   change.  If not, try to replace the whole pattern with
-		   a simple set (this may help if the original insn was a
-		   PARALLEL that was only recognized as single_set due to
-		   REG_UNUSED notes).  If this isn't valid either, keep
-		   the INSN_CODE the same and let reload fix it up.  */
-		if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
-		  {
-		    rtx new_pat = gen_rtx_SET (VOIDmode,
-					       SET_DEST (old_set), new_src);
-		    if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
-		      SET_SRC (old_set) = new_src;
-		  }
-	      }
-	    else
-	      break;
-	    val = 1;
-	    /* This can't have an effect on elimination offsets, so skip right
-	       to the end.  */
-	    goto done;
-	  }
-}
-/* Determine the effects of this insn on elimination offsets.  */
-elimination_effects (old_body, VOIDmode);
-/* Eliminate all eliminable registers occurring in operands that
-can be handled by reload.  */
-extract_insn (insn);
-for (i = 0; i < recog_data.n_operands; i++)
-{
-orig_operand[i] = recog_data.operand[i];
-substed_operand[i] = recog_data.operand[i];
-/* For an asm statement, every operand is eliminable.  */
-if (insn_is_asm || insn_data[icode].operand[i].eliminable)
-	{
-	  bool is_set_src, in_plus;
-	  /* Check for setting a register that we know about.  */
-	  if (recog_data.operand_type[i] != OP_IN
-	      && REG_P (orig_operand[i]))
-	    {
-	      /* If we are assigning to a register that can be eliminated, it
-		 must be as part of a PARALLEL, since the code above handles
-		 single SETs.  We must indicate that we can no longer
-		 eliminate this reg.  */
-	      for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
-		   ep++)
-		if (ep->from_rtx == orig_operand[i])
-		  ep->can_eliminate = 0;
-	    }
-	  /* Companion to the above plus substitution, we can allow
-	     invariants as the source of a plain move.  */
-	  is_set_src = false;
-	  if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
-	    is_set_src = true;
-	  in_plus = false;
-	  if (plus_src
-	      && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
-		  || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
-	    in_plus = true;
-	  substed_operand[i]
-	    = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
-			        replace ? insn : NULL_RTX,
-				is_set_src || in_plus);
-	  if (substed_operand[i] != orig_operand[i])
-	    val = 1;
-	  /* Terminate the search in check_eliminable_occurrences at
-	     this point.  */
-	  *recog_data.operand_loc[i] = 0;
-	  /* If an output operand changed from a REG to a MEM and INSN is an
-	     insn, write a CLOBBER insn.  */
-	  if (recog_data.operand_type[i] != OP_IN
-	      && REG_P (orig_operand[i])
-	      && MEM_P (substed_operand[i])
-	      && replace)
-	    emit_insn_after (gen_clobber (orig_operand[i]), insn);
-	}
-}
-for (i = 0; i < recog_data.n_dups; i++)
-*recog_data.dup_loc[i]
-= *recog_data.operand_loc[(int) recog_data.dup_num[i]];
-/* If any eliminable remain, they aren't eliminable anymore.  */
-check_eliminable_occurrences (old_body);
-/* Substitute the operands; the new values are in the substed_operand
-array.  */
-for (i = 0; i < recog_data.n_operands; i++)
-*recog_data.operand_loc[i] = substed_operand[i];
-for (i = 0; i < recog_data.n_dups; i++)
-*recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
-/* If we are replacing a body that was a (set X (plus Y Z)), try to
-re-recognize the insn.  We do this in case we had a simple addition
-but now can do this as a load-address.  This saves an insn in this
-common case.
-If re-recognition fails, the old insn code number will still be used,
-and some register operands may have changed into PLUS expressions.
-These will be handled by find_reloads by loading them into a register
-again.  */
-if (val)
-{
-/* If we aren't replacing things permanently and we changed something,
-	 make another copy to ensure that all the RTL is new.  Otherwise
-	 things can go wrong if find_reload swaps commutative operands
-	 and one is inside RTL that has been copied while the other is not.  */
-new_body = old_body;
-if (! replace)
-	{
-	  new_body = copy_insn (old_body);
-	  if (REG_NOTES (insn))
-	    REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
-	}
-PATTERN (insn) = new_body;
-/* If we had a move insn but now we don't, rerecognize it.  This will
-	 cause spurious re-recognition if the old move had a PARALLEL since
-	 the new one still will, but we can't call single_set without
-	 having put NEW_BODY into the insn and the re-recognition won't
-	 hurt in this rare case.  */
-/* ??? Why this huge if statement - why don't we just rerecognize the
-	 thing always?  */
-if (! insn_is_asm
-	  && old_set != 0
-	  && ((REG_P (SET_SRC (old_set))
-	       && (GET_CODE (new_body) != SET
-		   || !REG_P (SET_SRC (new_body))))
-	      /* If this was a load from or store to memory, compare
-		 the MEM in recog_data.operand to the one in the insn.
-		 If they are not equal, then rerecognize the insn.  */
-	      || (old_set != 0
-		  && ((MEM_P (SET_SRC (old_set))
-		       && SET_SRC (old_set) != recog_data.operand[1])
-		      || (MEM_P (SET_DEST (old_set))
-			  && SET_DEST (old_set) != recog_data.operand[0])))
-	      /* If this was an add insn before, rerecognize.  */
-	      || GET_CODE (SET_SRC (old_set)) == PLUS))
-	{
-	  int new_icode = recog (PATTERN (insn), insn, 0);
-	  if (new_icode >= 0)
-	    INSN_CODE (insn) = new_icode;
-	}
-}
-/* Restore the old body.  If there were any changes to it, we made a copy
-of it while the changes were still in place, so we'll correctly return
-a modified insn below.  */
-if (! replace)
-{
-/* Restore the old body.  */
-for (i = 0; i < recog_data.n_operands; i++)
-	/* Restoring a top-level match_parallel would clobber the new_body
-	   we installed in the insn.  */
-	if (recog_data.operand_loc[i] != &PATTERN (insn))
-	  *recog_data.operand_loc[i] = orig_operand[i];
-for (i = 0; i < recog_data.n_dups; i++)
-	*recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
-}
-/* Update all elimination pairs to reflect the status after the current
-insn.  The changes we make were determined by the earlier call to
-elimination_effects.
-We also detect cases where register elimination cannot be done,
-namely, if a register would be both changed and referenced outside a MEM
-in the resulting insn since such an insn is often undefined and, even if
-not, we cannot know what meaning will be given to it.  Note that it is
-valid to have a register used in an address in an insn that changes it
-(presumably with a pre- or post-increment or decrement).
-If anything changes, return nonzero.  */
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-{
-if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
-	ep->can_eliminate = 0;
-ep->ref_outside_mem = 0;
-if (ep->previous_offset != ep->offset)
-	val = 1;
-}
-done:
-/* If we changed something, perform elimination in REG_NOTES.  This is
-needed even when REPLACE is zero because a REG_DEAD note might refer
-to a register that we eliminate and could cause a different number
-of spill registers to be needed in the final reload pass than in
-the pre-passes.  */
-if (val && REG_NOTES (insn) != 0)
-REG_NOTES (insn)
-= eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true);
-return val;
-}
-/* Loop through all elimination pairs.
-Recalculate the number not at initial offset.
-Compute the maximum offset (minimum offset if the stack does not
-grow downward) for each elimination pair.  */
-static void
-update_eliminable_offsets (void)
-{
-struct elim_table *ep;
-num_not_at_initial_offset = 0;
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-{
-ep->previous_offset = ep->offset;
-if (ep->can_eliminate && ep->offset != ep->initial_offset)
-	num_not_at_initial_offset++;
-}
-}
-/* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
-replacement we currently believe is valid, mark it as not eliminable if X
-modifies DEST in any way other than by adding a constant integer to it.
-If DEST is the frame pointer, we do nothing because we assume that
-all assignments to the hard frame pointer are nonlocal gotos and are being
-done at a time when they are valid and do not disturb anything else.
-Some machines want to eliminate a fake argument pointer with either the
-frame or stack pointer.  Assignments to the hard frame pointer must not
-prevent this elimination.
-Called via note_stores from reload before starting its passes to scan
-the insns of the function.  */
-static void
-mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
-{
-unsigned int i;
-/* A SUBREG of a hard register here is just changing its mode.  We should
-not see a SUBREG of an eliminable hard register, but check just in
-case.  */
-if (GET_CODE (dest) == SUBREG)
-dest = SUBREG_REG (dest);
-if (dest == hard_frame_pointer_rtx)
-return;
-for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
-if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
-	&& (GET_CODE (x) != SET
-	    || GET_CODE (SET_SRC (x)) != PLUS
-	    || XEXP (SET_SRC (x), 0) != dest
-	    || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
-{
-	reg_eliminate[i].can_eliminate_previous
-	  = reg_eliminate[i].can_eliminate = 0;
-	num_eliminable--;
-}
-}
-/* Verify that the initial elimination offsets did not change since the
-last call to set_initial_elim_offsets.  This is used to catch cases
-where something illegal happened during reload_as_needed that could
-cause incorrect code to be generated if we did not check for it.  */
-static bool
-verify_initial_elim_offsets (void)
-{
-HOST_WIDE_INT t;
-if (!num_eliminable)
-return true;
-#ifdef ELIMINABLE_REGS
-{
-struct elim_table *ep;
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-{
-INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
-if (t != ep->initial_offset)
-	 return false;
-}
-}
-#else
-INITIAL_FRAME_POINTER_OFFSET (t);
-if (t != reg_eliminate[0].initial_offset)
-return false;
-#endif
-return true;
-}
-/* Reset all offsets on eliminable registers to their initial values.  */
-static void
-set_initial_elim_offsets (void)
-{
-struct elim_table *ep = reg_eliminate;
-#ifdef ELIMINABLE_REGS
-for (; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-{
-INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
-ep->previous_offset = ep->offset = ep->initial_offset;
-}
-#else
-INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
-ep->previous_offset = ep->offset = ep->initial_offset;
-#endif
-num_not_at_initial_offset = 0;
-}
-/* Subroutine of set_initial_label_offsets called via for_each_eh_label.  */
-static void
-set_initial_eh_label_offset (rtx label)
-{
-set_label_offsets (label, NULL_RTX, 1);
-}
-/* Initialize the known label offsets.
-Set a known offset for each forced label to be at the initial offset
-of each elimination.  We do this because we assume that all
-computed jumps occur from a location where each elimination is
-at its initial offset.
-For all other labels, show that we don't know the offsets.  */
-static void
-set_initial_label_offsets (void)
-{
-rtx x;
-memset (offsets_known_at, 0, num_labels);
-for (x = forced_labels; x; x = XEXP (x, 1))
-if (XEXP (x, 0))
-set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
-for_each_eh_label (set_initial_eh_label_offset);
-}
-/* Set all elimination offsets to the known values for the code label given
-by INSN.  */
-static void
-set_offsets_for_label (rtx insn)
-{
-unsigned int i;
-int label_nr = CODE_LABEL_NUMBER (insn);
-struct elim_table *ep;
-num_not_at_initial_offset = 0;
-for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
-{
-ep->offset = ep->previous_offset
-		 = offsets_at[label_nr - first_label_num][i];
-if (ep->can_eliminate && ep->offset != ep->initial_offset)
-	num_not_at_initial_offset++;
-}
-}
-/* See if anything that happened changes which eliminations are valid.
-For example, on the SPARC, whether or not the frame pointer can
-be eliminated can depend on what registers have been used.  We need
-not check some conditions again (such as flag_omit_frame_pointer)
-since they can't have changed.  */
-static void
-update_eliminables (HARD_REG_SET *pset)
-{
-int previous_frame_pointer_needed = frame_pointer_needed;
-struct elim_table *ep;
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-if ((ep->from == HARD_FRAME_POINTER_REGNUM
-&& targetm.frame_pointer_required ())
-#ifdef ELIMINABLE_REGS
-	|| ! targetm.can_eliminate (ep->from, ep->to)
-#endif
-	)
-ep->can_eliminate = 0;
-/* Look for the case where we have discovered that we can't replace
-register A with register B and that means that we will now be
-trying to replace register A with register C.  This means we can
-no longer replace register C with register B and we need to disable
-such an elimination, if it exists.  This occurs often with A == ap,
-B == sp, and C == fp.  */
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-{
-struct elim_table *op;
-int new_to = -1;
-if (! ep->can_eliminate && ep->can_eliminate_previous)
-	{
-	  /* Find the current elimination for ep->from, if there is a
-	     new one.  */
-	  for (op = reg_eliminate;
-	       op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
-	    if (op->from == ep->from && op->can_eliminate)
-	      {
-		new_to = op->to;
-		break;
-	      }
-	  /* See if there is an elimination of NEW_TO -> EP->TO.  If so,
-	     disable it.  */
-	  for (op = reg_eliminate;
-	       op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
-	    if (op->from == new_to && op->to == ep->to)
-	      op->can_eliminate = 0;
-	}
-}
-/* See if any registers that we thought we could eliminate the previous
-time are no longer eliminable.  If so, something has changed and we
-must spill the register.  Also, recompute the number of eliminable
-registers and see if the frame pointer is needed; it is if there is
-no elimination of the frame pointer that we can perform.  */
-frame_pointer_needed = 1;
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-{
-if (ep->can_eliminate
-	  && ep->from == FRAME_POINTER_REGNUM
-	  && ep->to != HARD_FRAME_POINTER_REGNUM
-	  && (! SUPPORTS_STACK_ALIGNMENT
-	      || ! crtl->stack_realign_needed))
-	frame_pointer_needed = 0;
-if (! ep->can_eliminate && ep->can_eliminate_previous)
-	{
-	  ep->can_eliminate_previous = 0;
-	  SET_HARD_REG_BIT (*pset, ep->from);
-	  num_eliminable--;
-	}
-}
-/* If we didn't need a frame pointer last time, but we do now, spill
-the hard frame pointer.  */
-if (frame_pointer_needed && ! previous_frame_pointer_needed)
-SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
-}
-/* Return true if X is used as the target register of an elimination.  */
-bool
-elimination_target_reg_p (rtx x)
-{
-struct elim_table *ep;
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-if (ep->to_rtx == x && ep->can_eliminate)
-return true;
-return false;
-}
-/* Initialize the table of registers to eliminate.
-Pre-condition: global flag frame_pointer_needed has been set before
-calling this function.  */
-static void
-init_elim_table (void)
-{
-struct elim_table *ep;
-#ifdef ELIMINABLE_REGS
-const struct elim_table_1 *ep1;
-#endif
-if (!reg_eliminate)
-reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
-num_eliminable = 0;
-#ifdef ELIMINABLE_REGS
-for (ep = reg_eliminate, ep1 = reg_eliminate_1;
-ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
-{
-ep->from = ep1->from;
-ep->to = ep1->to;
-ep->can_eliminate = ep->can_eliminate_previous
-	= (targetm.can_eliminate (ep->from, ep->to)
-	   && ! (ep->to == STACK_POINTER_REGNUM
-		 && frame_pointer_needed
-		 && (! SUPPORTS_STACK_ALIGNMENT
-		     || ! stack_realign_fp)));
-}
-#else
-reg_eliminate[0].from = reg_eliminate_1[0].from;
-reg_eliminate[0].to = reg_eliminate_1[0].to;
-reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
-= ! frame_pointer_needed;
-#endif
-/* Count the number of eliminable registers and build the FROM and TO
-REG rtx's.  Note that code in gen_rtx_REG will cause, e.g.,
-gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
-We depend on this.  */
-for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
-{
-num_eliminable += ep->can_eliminate;
-ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
-ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
-}
 }
 /* Kick all pseudos out of hard register REGNO.
 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
 		 reusing reload regs from previous insns, or else output
 		 load insns to reload them.  Maybe output store insns too.
 		 Record the choices of reload reg in reload_reg_rtx.  */
 	      choose_reload_regs (chain);
-	      /* Merge any reloads that we didn't combine for fear of
-		 increasing the number of spill registers needed but now
-		 discover can be safely merged.  */
-	      if (targetm.small_register_classes_for_mode_p (VOIDmode))
-		merge_assigned_reloads (insn);
 	      /* Generate the insns to reload operands into or out of
 		 their reload regs.  */
 	      emit_reload_insns (chain);
 	      /* Substitute the chosen reload regs from reload_reg_rtx
 		 load and store insn that we just made for reloading
 		 and that we moved the structure into).  */
 	      subst_reloads (insn);
 	      /* Adjust the exception region notes for loads and stores.  */
-	      if (flag_non_call_exceptions && !CALL_P (insn))
+	      if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
 		fixup_eh_region_note (insn, prev, next);
 	      /* If this was an ASM, make sure that all the reload insns
 		 we have generated are valid.  If not, give an error
 		 and delete them.  */
 return 1;
 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
 return 1;
 if (GET_CODE (x) == PLUS
 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
-&& CONSTANT_P (XEXP (x, 1)))
+&& GET_CODE (XEXP (x, 1)) == CONST_INT)
 return 1;
 return 0;
 }
 /* Determine whether the reload reg X overlaps any rtx'es used for
 for reload R.  If it's valid, get an rtx for it.  Return nonzero if
 successful.  */
 static int
 set_reload_reg (int i, int r)
 {
-int regno;
+/* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
+parameter.  */
+int regno ATTRIBUTE_UNUSED;
 rtx reg = spill_reg_rtx[i];
 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
 spill_reg_rtx[i] = reg
 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
 /* If we want a single register and haven't yet found one,
 take any reg in the right class and not in use.
 If we want a consecutive group, here is where we look for it.
-We use two passes so we can first look for reload regs to
+We use three passes so we can first look for reload regs to
 reuse, which are already in use for other reloads in this insn,
-and only then use additional registers.
+and only then use additional registers which are not "bad", then
+finally any register.
 I think that maximizing reuse is needed to make sure we don't
 run out of reload regs.  Suppose we have three reloads, and
 reloads A and B can share regs.  These need two regs.
 Suppose A and B are given different regs.
 That leaves none for C.  */
-for (pass = 0; pass < 2; pass++)
+for (pass = 0; pass < 3; pass++)
 {
 /* I is the index in spill_regs.
 	 We advance it round-robin between insns to use all spill regs
 	 equally, so that inherited reloads have a chance
 	 of leapfrogging each other.  */
 					 regnum)
 		      && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
 					      regnum))))
 	    {
 	      int nr = hard_regno_nregs[regnum][rld[r].mode];
+	      /* During the second pass we want to avoid reload registers
+		 which are "bad" for this reload.  */
+	      if (pass == 1
+		  && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
+		continue;
 	      /* Avoid the problem where spilling a GENERAL_OR_FP_REG
 		 (on 68000) got us two FP regs.  If NR is 1,
 		 we would reject both of them.  */
 	      if (force_group)
 		nr = rld[r].nregs;
 	      if (nr == 1)
 		break;
 	    }
 	}
-/* If we found something on pass 1, omit pass 2.  */
+/* If we found something on the current pass, omit later passes.  */
 if (count < n_spills)
 	break;
 }
 /* We should have found a spill register by now.  */
 		      && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
 			  /* Even if we can't use this register as a reload
 			     register, we might use it for reload_override_in,
 			     if copying it to the desired class is cheap
 			     enough.  */
-			  || ((REGISTER_MOVE_COST (mode, last_class, rclass)
+			  || ((register_move_cost (mode, last_class, rclass)
-			       < MEMORY_MOVE_COST (mode, rclass, 1))
+			       < memory_move_cost (mode, rclass, true))
 			      && (secondary_reload_class (1, rclass, mode,
 							  last_reg)
 				  == NO_REGS)
 #ifdef SECONDARY_MEMORY_NEEDED
 			      && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
 		  || REG_P (rld[r].in)
 		  || MEM_P (rld[r].in))
 	      && (rld[r].nregs == max_group_size
 		  || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
 	    search_equiv = rld[r].in;
-	  /* If this is an output reload from a simple move insn, look
-	     if an equivalence for the input is available.  */
-	  else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
-	    {
-	      rtx set = single_set (insn);
-	      if (set
-		  && rtx_equal_p (rld[r].out, SET_DEST (set))
-		  && CONSTANT_P (SET_SRC (set)))
-		search_equiv = SET_SRC (set);
-	    }
 	  if (search_equiv)
 	    {
 	      rtx equiv
 		= find_equiv_reg (search_equiv, insn, rld[r].rclass,
 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
 			     rld[r].mode);
 reload_spill_index[r] = -1;
 }
-/* If the small_register_classes_for_mode_p target hook returns true for
-some machine modes, we may not have merged two reloads of the same item
-for fear that we might not have enough reload registers.  However,
-normally they will get the same reload register and hence actually need
-not be loaded twice.
-Here we check for the most common case of this phenomenon: when we have
-a number of reloads for the same object, each of which were allocated
-the same reload_reg_rtx, that reload_reg_rtx is not used for any other
-reload, and is not modified in the insn itself.  If we find such,
-merge all the reloads and set the resulting reload to RELOAD_OTHER.
-This will not increase the number of spill registers needed and will
-prevent redundant code.  */
-static void
-merge_assigned_reloads (rtx insn)
-{
-int i, j;
-/* Scan all the reloads looking for ones that only load values and
-are not already RELOAD_OTHER and ones whose reload_reg_rtx are
-assigned and not modified by INSN.  */
-for (i = 0; i < n_reloads; i++)
-{
-int conflicting_input = 0;
-int max_input_address_opnum = -1;
-int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
-if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
-	  || rld[i].out != 0 || rld[i].reg_rtx == 0
-	  || reg_set_p (rld[i].reg_rtx, insn))
-	continue;
-/* Look at all other reloads.  Ensure that the only use of this
-	 reload_reg_rtx is in a reload that just loads the same value
-	 as we do.  Note that any secondary reloads must be of the identical
-	 class since the values, modes, and result registers are the
-	 same, so we need not do anything with any secondary reloads.  */
-for (j = 0; j < n_reloads; j++)
-	{
-	  if (i == j || rld[j].reg_rtx == 0
-	      || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
-					    rld[i].reg_rtx))
-	    continue;
-	  if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
-	      && rld[j].opnum > max_input_address_opnum)
-	    max_input_address_opnum = rld[j].opnum;
-	  /* If the reload regs aren't exactly the same (e.g, different modes)
-	     or if the values are different, we can't merge this reload.
-	     But if it is an input reload, we might still merge
-	     RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads.  */
-	  if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
-	      || rld[j].out != 0 || rld[j].in == 0
-	      || ! rtx_equal_p (rld[i].in, rld[j].in))
-	    {
-	      if (rld[j].when_needed != RELOAD_FOR_INPUT
-		  || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
-		       || rld[i].opnum > rld[j].opnum)
-		      && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
-		break;
-	      conflicting_input = 1;
-	      if (min_conflicting_input_opnum > rld[j].opnum)
-		min_conflicting_input_opnum = rld[j].opnum;
-	    }
-	}
-/* If all is OK, merge the reloads.  Only set this to RELOAD_OTHER if
-	 we, in fact, found any matching reloads.  */
-if (j == n_reloads
-	  && max_input_address_opnum <= min_conflicting_input_opnum)
-	{
-	  gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
-	  for (j = 0; j < n_reloads; j++)
-	    if (i != j && rld[j].reg_rtx != 0
-		&& rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
-		&& (! conflicting_input
-		    || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
-		    || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
-	      {
-		rld[i].when_needed = RELOAD_OTHER;
-		rld[j].in = 0;
-		reload_spill_index[j] = -1;
-		transfer_replacements (i, j);
-	      }
-	  /* If this is now RELOAD_OTHER, look for any reloads that
-	     load parts of this operand and set them to
-	     RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
-	     RELOAD_OTHER for outputs.  Note that this test is
-	     equivalent to looking for reloads for this operand
-	     number.
-	     We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
-	     it may share registers with a RELOAD_FOR_INPUT, so we can
-	     not change it to RELOAD_FOR_OTHER_ADDRESS.  We should
-	     never need to, since we do not modify RELOAD_FOR_OUTPUT.
-	     It is possible that the RELOAD_FOR_OPERAND_ADDRESS
-	     instruction is assigned the same register as the earlier
-	     RELOAD_FOR_OTHER_ADDRESS instruction.  Merging these two
-	     instructions will cause the RELOAD_FOR_OTHER_ADDRESS
-	     instruction to be deleted later on.  */
-	  if (rld[i].when_needed == RELOAD_OTHER)
-	    for (j = 0; j < n_reloads; j++)
-	      if (rld[j].in != 0
-		  && rld[j].when_needed != RELOAD_OTHER
-		  && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
-		  && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
-		  && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
-		  && (! conflicting_input
-		      || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
-		      || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
-		  && reg_overlap_mentioned_for_reload_p (rld[j].in,
-							 rld[i].in))
-		{
-		  int k;
-		  rld[j].when_needed
-		    = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
-			|| rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
-		       ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
-		  /* Check to see if we accidentally converted two
-		     reloads that use the same reload register with
-		     different inputs to the same type.  If so, the
-		     resulting code won't work.  */
-		  if (rld[j].reg_rtx)
-		    for (k = 0; k < j; k++)
-		      gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
-				  || rld[k].when_needed != rld[j].when_needed
-				  || !rtx_equal_p (rld[k].reg_rtx,
-						   rld[j].reg_rtx)
-				  || rtx_equal_p (rld[k].in,
-						  rld[j].in));
-		}
-	}
-}
-}
 /* These arrays are filled by emit_reload_insns and its subroutines.  */
 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
 static rtx other_input_address_reload_insns = 0;
 static rtx other_input_reload_insns = 0;
 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
 	  secondary_reload_info sri, sri2;
 	  enum reg_class new_class, new_t_class;
 	  sri.icode = CODE_FOR_nothing;
 	  sri.prev_sri = NULL;
-	  new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
+	  new_class
-						mode, &sri);
+	    = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
+							 rl->rclass, mode,
+							 &sri);
 	  if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
 	    second_reload_reg = 0;
 	  else if (new_class == NO_REGS)
 	    {
 	    gcc_unreachable ();
 	  else
 	    {
 	      sri2.icode = CODE_FOR_nothing;
 	      sri2.prev_sri = &sri;
-	      new_t_class = targetm.secondary_reload (1, real_oldequiv,
+	      new_t_class
-						      new_class, mode, &sri);
+		= (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
+							     new_class, mode,
+							     &sri);
 	      if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
 		{
 		  if (reload_adjust_reg_for_temp (&second_reload_reg,
 						  third_reload_reg,
 						  new_class, mode))
 	      && ((reg_equiv_memory_loc
 		   [REGNO (SUBREG_REG (oldequiv))] != 0)
 		  || (reg_equiv_constant
 		      [REGNO (SUBREG_REG (oldequiv))] != 0)))
 	  || (CONSTANT_P (oldequiv)
-	      && (PREFERRED_RELOAD_CLASS (oldequiv,
+	      && (targetm.preferred_reload_class (oldequiv,
-					  REGNO_REG_CLASS (REGNO (reloadreg)))
+						  REGNO_REG_CLASS (REGNO (reloadreg)))
 		  == NO_REGS)))
 	real_oldequiv = rl->in;
 gen_reload (reloadreg, real_oldequiv, rl->opnum,
 		  rl->when_needed);
 }
-if (flag_non_call_exceptions)
+if (cfun->can_throw_non_call_exceptions)
 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
 /* End this sequence.  */
 *where = get_insns ();
 end_sequence ();
 other_output_reload_insns[rl->opnum] = get_insns ();
 }
 else
 output_reload_insns[rl->opnum] = get_insns ();
-if (flag_non_call_exceptions)
+if (cfun->can_throw_non_call_exceptions)
 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
 end_sequence ();
 }
 	      CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
 	  /* Maybe the spill reg contains a copy of reload_out.  */
 	  if (rld[r].out != 0
 	      && (REG_P (rld[r].out)
-#ifdef AUTO_INC_DEC
+		  || (rld[r].out_reg
-		  || ! rld[r].out_reg
+		      ? REG_P (rld[r].out_reg)
-#endif
+		      /* The reload value is an auto-modification of
-		  || REG_P (rld[r].out_reg)))
+			 some kind.  For PRE_INC, POST_INC, PRE_DEC
+			 and POST_DEC, we record an equivalence
+			 between the reload register and the operand
+			 on the optimistic assumption that we can make
+			 the equivalence hold.  reload_as_needed must
+			 then either make it hold or invalidate the
+			 equivalence.
+			 PRE_MODIFY and POST_MODIFY addresses are reloaded
+			 somewhat differently, and allowing them here leads
+			 to problems.  */
+		      : (GET_CODE (rld[r].out) != POST_MODIFY
+			 && GET_CODE (rld[r].out) != PRE_MODIFY))))
 	    {
 	      rtx reg;
 	      enum machine_mode mode;
 	      int regno, nregs;
 	 If there is another way to do this for a specific machine, a
 	 DEFINE_PEEPHOLE should be specified that recognizes the sequence
 	 we emit below.  */
-code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
+code = (int) optab_handler (add_optab, GET_MODE (out));
 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
 	  || (REG_P (op1)
 	      && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
 	  || (code != CODE_FOR_nothing
 	{
 	  set_unique_reg_note (insn, REG_EQUIV, in);
 	  return insn;
 	}
-fatal_insn ("Failure trying to reload:", set);
+fatal_insn ("failure trying to reload:", set);
 }
 /* If IN is a simple operand, use gen_move_insn.  */
 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
 {
 tem = emit_insn (gen_move_insn (out, in));
 int k;
 int n_occurrences;
 int n_inherited = 0;
 rtx i1;
 rtx substed;
+unsigned regno;
+int nregs;
 /* It is possible that this reload has been only used to set another reload
 we eliminated earlier and thus deleted this instruction too.  */
 if (INSN_DELETED_P (output_reload_insn))
 return;
 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
 }
 if (n_occurrences > n_inherited)
 return;
+regno = REGNO (reg);
+if (regno >= FIRST_PSEUDO_REGISTER)
+nregs = 1;
+else
+nregs = hard_regno_nregs[regno][GET_MODE (reg)];
 /* If the pseudo-reg we are reloading is no longer referenced
 anywhere between the store into it and here,
 and we're within the same basic block, then the value can only
 pass through the reload reg and end up here.
 Otherwise, give up--return.  */
 i1 != insn; i1 = NEXT_INSN (i1))
 {
 if (NOTE_INSN_BASIC_BLOCK_P (i1))
 	return;
 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
-	  && reg_mentioned_p (reg, PATTERN (i1)))
+	  && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
 	{
 	  /* If this is USE in front of INSN, we only have to check that
 	     there are no more references than accounted for by inheritance.  */
 	  while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
 	    {
 	      /* If this is a pre-increment and we have incremented the value
 		 where it lives, copy the incremented value to RELOADREG to
 		 be used as an address.  */
 	      if (! post)
-		emit_insn (gen_move_insn (reloadreg, incloc));
+		add_insn = emit_insn (gen_move_insn (reloadreg, incloc));
 	      return add_insn;
 	    }
 	}
 delete_insns_since (last);
 	      stop = NEXT_INSN (BB_END (bb));
 	      BB_END (bb) = insn;
 	      insn = NEXT_INSN (insn);
-	      FOR_EACH_EDGE (e, ei, bb->succs)
+	      e = find_fallthru_edge (bb->succs);
-		if (e->flags & EDGE_FALLTHRU)
-		  break;
 	      while (insn && insn != stop)
 		{
 		  next = NEXT_INSN (insn);
 		  if (INSN_P (insn))
 	    purge_dead_edges (bb);
 	}
 }
 /* We've possibly turned single trapping insn into multiple ones.  */
-if (flag_non_call_exceptions)
+if (cfun->can_throw_non_call_exceptions)
 {
 sbitmap blocks;
 blocks = sbitmap_alloc (last_basic_block);
 sbitmap_ones (blocks);
 find_many_sub_basic_blocks (blocks);

Mercurial > hg > CbC > CbC_gcc

comparison gcc/reload1.c @ 67:f6334be47118