--- a/gcc/config/arm/fa526.md	Sun Aug 21 07:07:55 2011 +0900
+++ b/gcc/config/arm/fa526.md	Fri Oct 27 22:46:09 2017 +0900
@@ -1,5 +1,5 @@
 ;; Faraday FA526 Pipeline Description
-;; Copyright (C) 2010 Free Software Foundation, Inc.
+;; Copyright (C) 2010-2017 Free Software Foundation, Inc.
 ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description.
 
 ;; This file is part of GCC.
@@ -54,7 +54,7 @@
 
 ;; ALU instructions require two cycles to execute, and use the ALU
 ;; pipeline in each of the three stages.  The results are available
-;; after the execute stage stage has finished.
+;; after the execute stage has finished.
 ;;
 ;; If the destination register is the PC, the pipelines are stalled
 ;; for several cycles.  That case is not modeled here.
@@ -62,12 +62,24 @@
 ;; ALU operations
 (define_insn_reservation "526_alu_op" 1
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "alu"))
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_sreg,alus_sreg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg,\
+                       mov_imm,mov_reg,mvn_imm,mvn_reg,\
+                       mrs,multiple,no_insn"))
  "fa526_core")
 
 (define_insn_reservation "526_alu_shift_op" 2
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "alu_shift,alu_shift_reg"))
+      (eq_attr "type" "extend,\
+                       alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm,\
+                       alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
+                       mov_shift,mov_shift_reg,\
+                       mvn_shift,mvn_shift_reg"))
  "fa526_core")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -76,12 +88,12 @@
 
 (define_insn_reservation "526_mult1" 2
  (and (eq_attr "tune" "fa526")
-      (eq_attr "insn" "smlalxy,smulxy,smlaxy,smlalxy"))
+      (eq_attr "type" "smlalxy,smulxy,smlaxy,smlalxy"))
  "fa526_core")
 
 (define_insn_reservation "526_mult2" 5
  (and (eq_attr "tune" "fa526")
-      (eq_attr "insn" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\
+      (eq_attr "type" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\
                        umlals,smulls,smlals,smlawx"))
  "fa526_core*4")
 
@@ -96,42 +108,42 @@
 
 (define_insn_reservation "526_load1_op" 3
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "load1,load_byte"))
+      (eq_attr "type" "load_4,load_byte"))
  "fa526_core")
 
 (define_insn_reservation "526_load2_op" 4
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "load2"))
+      (eq_attr "type" "load_8"))
  "fa526_core*2")
 
 (define_insn_reservation "526_load3_op" 5
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "load3"))
+      (eq_attr "type" "load_12"))
  "fa526_core*3")
 
 (define_insn_reservation "526_load4_op" 6
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "load4"))
+      (eq_attr "type" "load_16"))
  "fa526_core*4")
 
 (define_insn_reservation "526_store1_op" 0
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "store1"))
+      (eq_attr "type" "store_4"))
  "fa526_core")
 
 (define_insn_reservation "526_store2_op" 1
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "store2"))
+      (eq_attr "type" "store_8"))
  "fa526_core*2")
 
 (define_insn_reservation "526_store3_op" 2
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "store3"))
+      (eq_attr "type" "store_12"))
  "fa526_core*3")
 
 (define_insn_reservation "526_store4_op" 3
  (and (eq_attr "tune" "fa526")
-      (eq_attr "type" "store4"))
+      (eq_attr "type" "store_16"))
  "fa526_core*4")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;